qcacmn: Add delayed register write support in HAL
In case the bus is in low power mode, the register writes (followed by a memory barrier) may take a long time (~4ms). This can cause the caller to block till the PCIe write is completed. Thus, even though PCI writes are posted, it can still block the caller. Hence, in case the bus is in low power mode (not in M0), or not in high throughput scenarios, queue the register write in a workqueue. The register write will happen in the delayed work context. In other cases, i.e ,when the bus is not in low power mode or in high thoughput scenarios, do the register writes in caller context. Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e CRs-Fixed: 2602029
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@@ -334,6 +334,7 @@ const int dp_stats_mapping_table[][STATS_TYPE_MAX] = {
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{TXRX_FW_STATS_INVALID, TXRX_PDEV_CFG_PARAMS},
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{TXRX_FW_STATS_INVALID, TXRX_SOC_INTERRUPT_STATS},
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{TXRX_FW_STATS_INVALID, TXRX_SOC_FSE_STATS},
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{TXRX_FW_STATS_INVALID, TXRX_HAL_REG_WRITE_STATS},
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};
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/* MCL specific functions */
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@@ -7604,6 +7605,7 @@ static void dp_txrx_stats_help(void)
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dp_info(" 29 -- Host Soc cfg param Statistics");
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dp_info(" 30 -- Host pdev cfg param Statistics");
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dp_info(" 31 -- Host FISA stats");
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dp_info(" 32 -- Host Register Work stats");
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}
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/**
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@@ -7663,11 +7665,17 @@ dp_print_host_stats(struct dp_vdev *vdev,
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break;
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case TXRX_NAPI_STATS:
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dp_print_napi_stats(pdev->soc);
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break;
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case TXRX_SOC_INTERRUPT_STATS:
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dp_print_soc_interrupt_stats(pdev->soc);
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break;
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case TXRX_SOC_FSE_STATS:
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dp_rx_dump_fisa_table(pdev->soc);
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break;
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case TXRX_HAL_REG_WRITE_STATS:
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hal_dump_reg_write_stats(pdev->soc->hal_soc);
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hal_dump_reg_write_srng_stats(pdev->soc->hal_soc);
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break;
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default:
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dp_info("Wrong Input For TxRx Host Stats");
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dp_txrx_stats_help();
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@@ -9098,6 +9106,7 @@ static QDF_STATUS dp_txrx_dump_stats(struct cdp_soc_t *psoc, uint16_t value,
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case CDP_TXRX_PATH_STATS:
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dp_txrx_path_stats(soc);
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dp_print_soc_interrupt_stats(soc);
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hal_dump_reg_write_stats(soc->hal_soc);
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break;
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case CDP_RX_RING_STATS:
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