qcacmn: Add delayed register write support in HAL

In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.

Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.

Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029

dp/inc/cdp_txrx_cmn_struct.h

@@ -269,6 +269,7 @@ enum htt_cmn_dbg_stats_type {
  * @TXRX_PDEV_CFG_PARAMS: Print pdev cfg params info
  * @TXRX_NAPI_STATS: Print NAPI scheduling statistics
  * @TXRX_SOC_INTERRUPT_STATS: Print soc interrupt stats
+ * @TXRX_HAL_REG_WRITE_STATS: Hal Reg Write stats
  */
 enum cdp_host_txrx_stats {
 	TXRX_HOST_STATS_INVALID  = -1,
@@ -286,6 +287,7 @@ enum cdp_host_txrx_stats {
 	TXRX_NAPI_STATS       = 11,
 	TXRX_SOC_INTERRUPT_STATS = 12,
 	TXRX_SOC_FSE_STATS = 13,
+	TXRX_HAL_REG_WRITE_STATS = 14,
 	TXRX_HOST_STATS_MAX,
 };