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msm: camera: isp: Implement the global clear only once

Fix the implementation where global clear command is
getting applied redundantly for more than once in a
for loop.

CRs-Fixed: 2880438
Change-Id: I0ff4b120eb7458bfc9978d5c6916d21d8db35e16
Signed-off-by: Jigar Agrawal <[email protected]>
Jigar Agrawal 4 年之前
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共有 1 个文件被更改,包括 12 次插入11 次删除
  1. 12 11
      drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c

+ 12 - 11
drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c

@@ -471,13 +471,12 @@ int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle)
 		cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
 		cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
 			controller->mem_base +
 			controller->mem_base +
 			irq_register->clear_reg_offset);
 			irq_register->clear_reg_offset);
-
-		if (controller->global_clear_offset)
-			cam_io_w_mb(
-				controller->global_clear_bitmask,
-				controller->mem_base +
-				controller->global_clear_offset);
 	}
 	}
+
+	if (controller->global_clear_offset)
+		cam_io_w_mb(controller->global_clear_bitmask,
+			controller->mem_base + controller->global_clear_offset);
+
 	if (need_lock)
 	if (need_lock)
 		spin_unlock_irqrestore(&controller->lock, flags);
 		spin_unlock_irqrestore(&controller->lock, flags);
 
 
@@ -810,11 +809,6 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
 			irq_register->top_half_enable_mask[priority] &=
 			irq_register->top_half_enable_mask[priority] &=
 								~irq_mask[i];
 								~irq_mask[i];
 			evt_handler->evt_bit_mask_arr[i] &= ~irq_mask[i];
 			evt_handler->evt_bit_mask_arr[i] &= ~irq_mask[i];
-
-			if (controller->global_clear_offset)
-				cam_io_w_mb(controller->global_clear_bitmask,
-					controller->mem_base +
-					controller->global_clear_offset);
 		}
 		}
 
 
 		cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
 		cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
@@ -822,6 +816,13 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
 			controller->irq_register_arr[i].mask_reg_offset);
 			controller->irq_register_arr[i].mask_reg_offset);
 	}
 	}
 
 
+	if (!enable) {
+		if (controller->global_clear_offset)
+			cam_io_w_mb(controller->global_clear_bitmask,
+				controller->mem_base +
+				controller->global_clear_offset);
+	}
+
 	if (need_lock)
 	if (need_lock)
 		spin_unlock_irqrestore(&controller->lock, flags);
 		spin_unlock_irqrestore(&controller->lock, flags);