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@@ -471,13 +471,12 @@ int cam_irq_controller_disable_irq(void *irq_controller, uint32_t handle)
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cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
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controller->mem_base +
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irq_register->clear_reg_offset);
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-
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- if (controller->global_clear_offset)
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- cam_io_w_mb(
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- controller->global_clear_bitmask,
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- controller->mem_base +
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- controller->global_clear_offset);
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}
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+
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+ if (controller->global_clear_offset)
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+ cam_io_w_mb(controller->global_clear_bitmask,
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+ controller->mem_base + controller->global_clear_offset);
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+
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if (need_lock)
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spin_unlock_irqrestore(&controller->lock, flags);
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@@ -810,11 +809,6 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
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irq_register->top_half_enable_mask[priority] &=
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~irq_mask[i];
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evt_handler->evt_bit_mask_arr[i] &= ~irq_mask[i];
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-
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- if (controller->global_clear_offset)
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- cam_io_w_mb(controller->global_clear_bitmask,
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- controller->mem_base +
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- controller->global_clear_offset);
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}
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cam_io_w_mb(evt_handler->evt_bit_mask_arr[i],
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@@ -822,6 +816,13 @@ int cam_irq_controller_update_irq(void *irq_controller, uint32_t handle,
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controller->irq_register_arr[i].mask_reg_offset);
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}
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+ if (!enable) {
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+ if (controller->global_clear_offset)
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+ cam_io_w_mb(controller->global_clear_bitmask,
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+ controller->mem_base +
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+ controller->global_clear_offset);
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+ }
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+
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if (need_lock)
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spin_unlock_irqrestore(&controller->lock, flags);
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