qcacmn: Fix tlv parsing for rx_evm details tlv
Fixed tlv parsing for rx_evm and rx_antenna for QCN9224. Change-Id: I9a24a0231289018e73c4dfa3c4f0dd1c79d6f84b CRs-Fixed: 3485292
This commit is contained in:

committed by
Rahul Choudhary

parent
1ba9e267e0
commit
ade262ccac
@@ -190,7 +190,11 @@
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#define CDP_SNR_UPDATE_AVG(x, y) x = CDP_SNR_AVG((x), CDP_SNR_IN((y)))
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#define CDP_SNR_UPDATE_AVG(x, y) x = CDP_SNR_AVG((x), CDP_SNR_IN((y)))
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/*Max SU EVM count */
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/*Max SU EVM count */
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#ifdef QCA_MONITOR_2_0_SUPPORT
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#define DP_RX_MAX_SU_EVM_COUNT 256
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#else
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#define DP_RX_MAX_SU_EVM_COUNT 32
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#define DP_RX_MAX_SU_EVM_COUNT 32
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#endif
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#define WDI_EVENT_BASE 0x100
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#define WDI_EVENT_BASE 0x100
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@@ -348,9 +348,9 @@ void
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dp_rx_populate_su_evm_details(struct hal_rx_ppdu_info *ppdu_info,
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dp_rx_populate_su_evm_details(struct hal_rx_ppdu_info *ppdu_info,
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struct cdp_rx_indication_ppdu *cdp_rx_ppdu)
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struct cdp_rx_indication_ppdu *cdp_rx_ppdu)
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{
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{
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uint8_t pilot_evm;
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uint16_t pilot_evm;
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uint8_t nss_count;
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uint16_t nss_count;
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uint8_t pilot_count;
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uint16_t pilot_count;
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nss_count = ppdu_info->evm_info.nss_count;
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nss_count = ppdu_info->evm_info.nss_count;
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pilot_count = ppdu_info->evm_info.pilot_count;
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pilot_count = ppdu_info->evm_info.pilot_count;
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@@ -191,7 +191,11 @@
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#define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16
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#define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16
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/* Max pilot count */
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/* Max pilot count */
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#ifdef QCA_MONITOR_2_0_SUPPORT
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#define HAL_RX_MAX_SU_EVM_COUNT 256
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#else
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#define HAL_RX_MAX_SU_EVM_COUNT 32
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#define HAL_RX_MAX_SU_EVM_COUNT 32
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#endif
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#define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C
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#define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C
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#define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\
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#define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\
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@@ -253,50 +253,64 @@ uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc)
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}
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}
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#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
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#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
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#define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \
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#define HAL_RX_EVM_DEMF_SEGMENT_SIZE 128
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(ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \
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#define HAL_RX_EVM_DEMF_MAX_STREAMS 2
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PHYRX_OTHER_RECEIVE_INFO, \
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#define HAL_RX_SU_EVM_MEMBER_LEN 4
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SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM)
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static inline void
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static inline void
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hal_rx_update_su_evm_info(void *rx_tlv,
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hal_rx_update_su_evm_info(void *rx_tlv,
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void *ppdu_info_hdl)
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void *ppdu_info_hdl)
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{
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{
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uint32_t nss_count, pilot_count;
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uint16_t istream = 0, ipilot = 0;
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uint8_t pilot_shift = 0;
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uint8_t *pilot_ptr = NULL;
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uint16_t segment = 0;
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struct hal_rx_ppdu_info *ppdu_info =
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struct hal_rx_ppdu_info *ppdu_info =
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(struct hal_rx_ppdu_info *)ppdu_info_hdl;
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(struct hal_rx_ppdu_info *)ppdu_info_hdl;
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nss_count = ppdu_info->evm_info.nss_count;
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pilot_count = ppdu_info->evm_info.pilot_count;
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0);
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if (nss_count * pilot_count > HAL_RX_MAX_SU_EVM_COUNT)
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1);
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return;
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2);
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3);
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/* move rx_tlv by 4 to skip no_of_data_sym, nss_cnt and pilot_cnt */
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4);
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rx_tlv = (uint8_t *)rx_tlv + HAL_RX_SU_EVM_MEMBER_LEN;
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5);
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6);
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/* EVM values = number_of_streams * number_of_pilots
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7);
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* each EVM value is 8 bits, So, each variable acc_linear_evm_x_y
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8);
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* is (32 bits) will contain 4 EVM values.
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9);
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* For ex:
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10);
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* acc_linear_evm_0_0 : <Pilot0, stream0>, <Pilot0, stream1>,
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11);
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* <Pilot1, stream0>, <Pilot1, stream1>
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12);
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* .....
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13);
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* acc_linear_evm_1_15 : <Pilot62, stream0>, <Pilot62, stream1>,
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14);
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* <Pilot63, stream0>, <Pilot63, stream1> ...
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15);
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*/
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16);
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17);
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for (istream = 0; istream < nss_count; istream++) {
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18);
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segment = HAL_RX_EVM_DEMF_SEGMENT_SIZE * (istream / HAL_RX_EVM_DEMF_MAX_STREAMS);
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19);
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pilot_ptr = (uint8_t *)rx_tlv + segment;
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20);
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for (ipilot = 0; ipilot < pilot_count; ipilot++) {
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21);
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/* In case there is one stream in Demf segment,
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22);
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* pilots are one after the other
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23);
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*/
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24);
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if (nss_count == 1 ||
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25);
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((nss_count == HAL_RX_EVM_DEMF_MAX_STREAMS + 1) &&
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26);
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(istream == HAL_RX_EVM_DEMF_MAX_STREAMS)))
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27);
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pilot_shift = ipilot;
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28);
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/* In case there are more than one stream in DemF
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29);
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* segment, pilot 0 of all streams come one after the
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30);
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* other before pilot 1
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HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31);
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*/
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else
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pilot_shift = (ipilot * HAL_RX_EVM_DEMF_MAX_STREAMS)
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+ (istream % HAL_RX_EVM_DEMF_MAX_STREAMS);
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ppdu_info->evm_info.pilot_evm[segment + pilot_shift] =
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*(pilot_ptr + pilot_shift);
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}
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}
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}
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}
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/**
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/**
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@@ -310,11 +324,16 @@ static inline
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void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
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void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
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void *ppdu_info_hdl)
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void *ppdu_info_hdl)
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{
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{
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uint32_t tlv_tag, tlv_len;
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uint32_t tlv_len, tlv_tag;
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void *rx_tlv;
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void *rx_tlv;
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
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tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
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rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
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rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
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if (!tlv_len)
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return;
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tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv);
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tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv);
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tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv);
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tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv);
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@@ -323,21 +342,24 @@ void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
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switch (tlv_tag) {
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switch (tlv_tag) {
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case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E:
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case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E:
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/* Skip TLV length to get TLV content */
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/* Skip TLV length to get TLV content */
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rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE;
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rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE;
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ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
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ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
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PHYRX_OTHER_RECEIVE_INFO,
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PHYRX_OTHER_RECEIVE_INFO,
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SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS);
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EVM_DETAILS_NUMBER_OF_DATA_SYM);
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ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
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ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
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PHYRX_OTHER_RECEIVE_INFO,
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PHYRX_OTHER_RECEIVE_INFO,
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SU_EVM_DETAILS_0_PILOT_COUNT);
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EVM_DETAILS_NUMBER_OF_PILOTS);
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ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
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ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
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PHYRX_OTHER_RECEIVE_INFO,
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PHYRX_OTHER_RECEIVE_INFO,
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SU_EVM_DETAILS_0_NSS_COUNT);
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EVM_DETAILS_NUMBER_OF_STREAMS);
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hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
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hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
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break;
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break;
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default:
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QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG,
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"%s unhandled TLV type: %d, TLV len:%d",
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__func__, tlv_tag, tlv_len);
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break;
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}
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}
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}
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}
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@@ -1,6 +1,6 @@
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/*
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/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* any purpose with or without fee is hereby granted, provided that the
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@@ -38,7 +38,7 @@
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#include "hal_api_mon.h"
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#include "hal_api_mon.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
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#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
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#include "phyrx_other_receive_info_su_evm_details.h"
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#include "phyrx_other_receive_info_evm_details.h"
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#endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */
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#endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
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