qcacmn: Fix tlv parsing for rx_evm details tlv

Fixed tlv parsing for rx_evm and rx_antenna
for QCN9224.

Change-Id: I9a24a0231289018e73c4dfa3c4f0dd1c79d6f84b
CRs-Fixed: 3485292
This commit is contained in:
Sushant Butta
2023-05-02 16:23:43 +05:30
committed by Rahul Choudhary
parent 1ba9e267e0
commit ade262ccac
5 changed files with 78 additions and 48 deletions

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@@ -190,7 +190,11 @@
#define CDP_SNR_UPDATE_AVG(x, y) x = CDP_SNR_AVG((x), CDP_SNR_IN((y))) #define CDP_SNR_UPDATE_AVG(x, y) x = CDP_SNR_AVG((x), CDP_SNR_IN((y)))
/*Max SU EVM count */ /*Max SU EVM count */
#ifdef QCA_MONITOR_2_0_SUPPORT
#define DP_RX_MAX_SU_EVM_COUNT 256
#else
#define DP_RX_MAX_SU_EVM_COUNT 32 #define DP_RX_MAX_SU_EVM_COUNT 32
#endif
#define WDI_EVENT_BASE 0x100 #define WDI_EVENT_BASE 0x100

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@@ -348,9 +348,9 @@ void
dp_rx_populate_su_evm_details(struct hal_rx_ppdu_info *ppdu_info, dp_rx_populate_su_evm_details(struct hal_rx_ppdu_info *ppdu_info,
struct cdp_rx_indication_ppdu *cdp_rx_ppdu) struct cdp_rx_indication_ppdu *cdp_rx_ppdu)
{ {
uint8_t pilot_evm; uint16_t pilot_evm;
uint8_t nss_count; uint16_t nss_count;
uint8_t pilot_count; uint16_t pilot_count;
nss_count = ppdu_info->evm_info.nss_count; nss_count = ppdu_info->evm_info.nss_count;
pilot_count = ppdu_info->evm_info.pilot_count; pilot_count = ppdu_info->evm_info.pilot_count;

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@@ -191,7 +191,11 @@
#define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16 #define HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER 16
/* Max pilot count */ /* Max pilot count */
#ifdef QCA_MONITOR_2_0_SUPPORT
#define HAL_RX_MAX_SU_EVM_COUNT 256
#else
#define HAL_RX_MAX_SU_EVM_COUNT 32 #define HAL_RX_MAX_SU_EVM_COUNT 32
#endif
#define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C #define HAL_RX_FRAMECTRL_TYPE_MASK 0x0C
#define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\ #define HAL_RX_GET_FRAME_CTRL_TYPE(fc)\

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@@ -253,50 +253,64 @@ uint8_t hal_rx_wbm_err_msdu_continuation_get_9224(void *wbm_desc)
} }
#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
#define HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, evm, pilot) \ #define HAL_RX_EVM_DEMF_SEGMENT_SIZE 128
(ppdu_info)->evm_info.pilot_evm[pilot] = HAL_RX_GET(rx_tlv, \ #define HAL_RX_EVM_DEMF_MAX_STREAMS 2
PHYRX_OTHER_RECEIVE_INFO, \ #define HAL_RX_SU_EVM_MEMBER_LEN 4
SU_EVM_DETAILS_##evm##_PILOT_##pilot##_EVM)
static inline void static inline void
hal_rx_update_su_evm_info(void *rx_tlv, hal_rx_update_su_evm_info(void *rx_tlv,
void *ppdu_info_hdl) void *ppdu_info_hdl)
{ {
uint32_t nss_count, pilot_count;
uint16_t istream = 0, ipilot = 0;
uint8_t pilot_shift = 0;
uint8_t *pilot_ptr = NULL;
uint16_t segment = 0;
struct hal_rx_ppdu_info *ppdu_info = struct hal_rx_ppdu_info *ppdu_info =
(struct hal_rx_ppdu_info *)ppdu_info_hdl; (struct hal_rx_ppdu_info *)ppdu_info_hdl;
nss_count = ppdu_info->evm_info.nss_count;
pilot_count = ppdu_info->evm_info.pilot_count;
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 1, 0); if (nss_count * pilot_count > HAL_RX_MAX_SU_EVM_COUNT)
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 2, 1); return;
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 3, 2);
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 4, 3); /* move rx_tlv by 4 to skip no_of_data_sym, nss_cnt and pilot_cnt */
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 5, 4); rx_tlv = (uint8_t *)rx_tlv + HAL_RX_SU_EVM_MEMBER_LEN;
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 6, 5);
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 7, 6); /* EVM values = number_of_streams * number_of_pilots
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 8, 7); * each EVM value is 8 bits, So, each variable acc_linear_evm_x_y
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 9, 8); * is (32 bits) will contain 4 EVM values.
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 10, 9); * For ex:
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 11, 10); * acc_linear_evm_0_0 : <Pilot0, stream0>, <Pilot0, stream1>,
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 12, 11); * <Pilot1, stream0>, <Pilot1, stream1>
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 13, 12); * .....
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 14, 13); * acc_linear_evm_1_15 : <Pilot62, stream0>, <Pilot62, stream1>,
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 15, 14); * <Pilot63, stream0>, <Pilot63, stream1> ...
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 16, 15); */
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 17, 16);
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 18, 17); for (istream = 0; istream < nss_count; istream++) {
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 19, 18); segment = HAL_RX_EVM_DEMF_SEGMENT_SIZE * (istream / HAL_RX_EVM_DEMF_MAX_STREAMS);
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 20, 19); pilot_ptr = (uint8_t *)rx_tlv + segment;
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 21, 20); for (ipilot = 0; ipilot < pilot_count; ipilot++) {
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 22, 21); /* In case there is one stream in Demf segment,
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 23, 22); * pilots are one after the other
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 24, 23); */
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 25, 24); if (nss_count == 1 ||
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 26, 25); ((nss_count == HAL_RX_EVM_DEMF_MAX_STREAMS + 1) &&
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 27, 26); (istream == HAL_RX_EVM_DEMF_MAX_STREAMS)))
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 28, 27); pilot_shift = ipilot;
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 29, 28); /* In case there are more than one stream in DemF
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 30, 29); * segment, pilot 0 of all streams come one after the
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 31, 30); * other before pilot 1
HAL_RX_UPDATE_SU_EVM_INFO(rx_tlv, ppdu_info, 32, 31); */
else
pilot_shift = (ipilot * HAL_RX_EVM_DEMF_MAX_STREAMS)
+ (istream % HAL_RX_EVM_DEMF_MAX_STREAMS);
ppdu_info->evm_info.pilot_evm[segment + pilot_shift] =
*(pilot_ptr + pilot_shift);
}
}
} }
/** /**
@@ -310,11 +324,16 @@ static inline
void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr, void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
void *ppdu_info_hdl) void *ppdu_info_hdl)
{ {
uint32_t tlv_tag, tlv_len; uint32_t tlv_len, tlv_tag;
void *rx_tlv; void *rx_tlv;
struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
if (!tlv_len)
return;
tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv); tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv);
tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv); tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv);
@@ -323,21 +342,24 @@ void hal_rx_proc_phyrx_other_receive_info_tlv_9224(void *rx_tlv_hdr,
switch (tlv_tag) { switch (tlv_tag) {
case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E: case WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E:
/* Skip TLV length to get TLV content */ /* Skip TLV length to get TLV content */
rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE; rx_tlv = (uint8_t *)rx_tlv + HAL_RX_TLV64_HDR_SIZE;
ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv, ppdu_info->evm_info.number_of_symbols = HAL_RX_GET(rx_tlv,
PHYRX_OTHER_RECEIVE_INFO, PHYRX_OTHER_RECEIVE_INFO,
SU_EVM_DETAILS_0_NUMBER_OF_SYMBOLS); EVM_DETAILS_NUMBER_OF_DATA_SYM);
ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv, ppdu_info->evm_info.pilot_count = HAL_RX_GET(rx_tlv,
PHYRX_OTHER_RECEIVE_INFO, PHYRX_OTHER_RECEIVE_INFO,
SU_EVM_DETAILS_0_PILOT_COUNT); EVM_DETAILS_NUMBER_OF_PILOTS);
ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv, ppdu_info->evm_info.nss_count = HAL_RX_GET(rx_tlv,
PHYRX_OTHER_RECEIVE_INFO, PHYRX_OTHER_RECEIVE_INFO,
SU_EVM_DETAILS_0_NSS_COUNT); EVM_DETAILS_NUMBER_OF_STREAMS);
hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl); hal_rx_update_su_evm_info(rx_tlv, ppdu_info_hdl);
break; break;
default:
QDF_TRACE(QDF_MODULE_ID_HAL, QDF_TRACE_LEVEL_DEBUG,
"%s unhandled TLV type: %d, TLV len:%d",
__func__, tlv_tag, tlv_len);
break;
} }
} }

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@@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2021 The Linux Foundation. All rights reserved. * Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* *
* Permission to use, copy, modify, and/or distribute this software for * Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the * any purpose with or without fee is hereby granted, provided that the
@@ -38,7 +38,7 @@
#include "hal_api_mon.h" #include "hal_api_mon.h"
#include "phyrx_other_receive_info_ru_details.h" #include "phyrx_other_receive_info_ru_details.h"
#if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574)) #if (defined(WLAN_SA_API_ENABLE)) && (defined(QCA_WIFI_QCA9574))
#include "phyrx_other_receive_info_su_evm_details.h" #include "phyrx_other_receive_info_evm_details.h"
#endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */ #endif /* WLAN_SA_API_ENABLE && QCA_WIFI_QCA9574 */
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \ #define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \