qcacld-3.0: Add multi pages prealloc support for HIF layer
The IOVA for the buffers that are attached to the direct link receive copy engine need to be contiguous for optimal memory mapping on ADSP. Fix is to add multi pages prealloc support for HIF layer and add a pool entry to multi pages prealloc for direct link receive copy engine. Change-Id: Ieb253bd3c1b6550e4c1c63cd587993891ac817f2 CRs-Fixed: 3497689
This commit is contained in:

committed by
Rahul Choudhary

parent
dc308d506f
commit
ad66c99ef1
@@ -344,8 +344,11 @@ static struct dp_consistent_prealloc g_dp_consistent_allocs[] = {
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#define NON_CACHEABLE 0
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#define CACHEABLE 1
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#define TX_DIRECT_LINK_CE_BUF_PAGES 4
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#define TX_DIRECT_LINK_BUF_PAGES 190
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#define DIRECT_LINK_CE_RX_BUF_SIZE 256
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#define DIRECT_LINK_DEFAULT_BUF_SZ 2048
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#define TX_DIRECT_LINK_BUF_NUM 380
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#define TX_DIRECT_LINK_CE_BUF_NUM 8
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#define RX_DIRECT_LINK_CE_BUF_NUM 30
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static struct dp_multi_page_prealloc g_dp_multi_page_allocs[] = {
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/* 4 TX DESC pools */
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@@ -413,10 +416,12 @@ static struct dp_multi_page_prealloc g_dp_multi_page_allocs[] = {
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0, NON_CACHEABLE, { 0 } },
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#endif
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#ifdef FEATURE_DIRECT_LINK
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{QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE, qdf_page_size,
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TX_DIRECT_LINK_CE_BUF_PAGES, 0, NON_CACHEABLE, { 0 } },
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{QDF_DP_TX_DIRECT_LINK_BUF_TYPE, qdf_page_size,
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TX_DIRECT_LINK_BUF_PAGES, 0, NON_CACHEABLE, { 0 } },
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{QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE, DIRECT_LINK_DEFAULT_BUF_SZ,
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TX_DIRECT_LINK_CE_BUF_NUM, 0, NON_CACHEABLE, { 0 } },
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{QDF_DP_TX_DIRECT_LINK_BUF_TYPE, DIRECT_LINK_DEFAULT_BUF_SZ,
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TX_DIRECT_LINK_BUF_NUM, 0, NON_CACHEABLE, { 0 } },
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{QDF_DP_RX_DIRECT_LINK_CE_BUF_TYPE, DIRECT_LINK_CE_RX_BUF_SIZE,
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RX_DIRECT_LINK_CE_BUF_NUM, 0, NON_CACHEABLE, { 0 } },
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#endif
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};
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@@ -214,7 +214,8 @@ dp_wfds_req_mem_msg(struct dp_direct_link_wfds_context *dl_wfds)
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&buf_size);
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qdf_assert(dma_addr);
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info->mem_arena_page_info[i].num_entries_per_page = 1;
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info->mem_arena_page_info[i].num_entries_per_page =
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qdf_page_size / buf_size;
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info->mem_arena_page_info[i].page_dma_addr_len =
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num_pages;
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while (num_pages--) {
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@@ -408,22 +409,14 @@ dp_wfds_alloc_mem_arena(struct dp_direct_link_wfds_context *dl_wfds,
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{
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qdf_device_t qdf_ctx = dl_wfds->direct_link_ctx->dp_ctx->qdf_dev;
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uint32_t desc_type;
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uint32_t elem_per_page;
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uint32_t num_pages;
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desc_type = dp_wfds_get_desc_type_from_mem_arena(mem_arena);
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if (desc_type != QDF_DP_DESC_TYPE_MAX) {
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elem_per_page = qdf_page_size / entry_size;
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num_pages = num_entries / elem_per_page;
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if (num_entries % elem_per_page)
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num_pages++;
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dp_prealloc_get_multi_pages(desc_type, qdf_page_size,
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num_pages,
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if (desc_type != QDF_DP_DESC_TYPE_MAX)
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dp_prealloc_get_multi_pages(desc_type, entry_size,
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num_entries,
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&dl_wfds->mem_arena_pages[mem_arena],
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false);
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}
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if (!dl_wfds->mem_arena_pages[mem_arena].num_pages)
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qdf_mem_multi_pages_alloc(qdf_ctx,
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@@ -1330,6 +1330,32 @@ void *ucfg_dp_prealloc_get_consistent_mem_unaligned(qdf_size_t size,
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* Return: None
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*/
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void ucfg_dp_prealloc_put_consistent_mem_unaligned(void *va_unaligned);
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/**
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* ucfg_dp_prealloc_get_multi_pages() - gets pre-alloc DP multi-pages memory
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* @desc_type: descriptor type
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* @elem_size: single element size
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* @elem_num: total number of elements should be allocated
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* @pages: multi page information storage
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* @cacheable: coherent memory or cacheable memory
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*
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* Return: None
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*/
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void ucfg_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size,
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uint16_t elem_num,
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struct qdf_mem_multi_page_t *pages,
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bool cacheable);
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/**
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* ucfg_dp_prealloc_put_multi_pages() - puts back pre-alloc DP multi-pages
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* memory
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* @desc_type: descriptor type
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* @pages: multi page information storage
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*
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* Return: None
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*/
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void ucfg_dp_prealloc_put_multi_pages(uint32_t desc_type,
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struct qdf_mem_multi_page_t *pages);
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#endif
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#ifdef FEATURE_DIRECT_LINK
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@@ -2349,6 +2349,21 @@ void ucfg_dp_prealloc_put_consistent_mem_unaligned(void *va_unaligned)
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{
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dp_prealloc_put_consistent_mem_unaligned(va_unaligned);
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}
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void ucfg_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size,
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uint16_t elem_num,
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struct qdf_mem_multi_page_t *pages,
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bool cacheable)
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{
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dp_prealloc_get_multi_pages(desc_type, elem_size, elem_num, pages,
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cacheable);
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}
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void ucfg_dp_prealloc_put_multi_pages(uint32_t desc_type,
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struct qdf_mem_multi_page_t *pages)
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{
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dp_prealloc_put_multi_pages(desc_type, pages);
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}
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#endif
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#if defined(WLAN_SUPPORT_RX_FISA)
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@@ -137,6 +137,39 @@ void hdd_put_consistent_mem_unaligned(void *vaddr)
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ucfg_dp_prealloc_put_consistent_mem_unaligned(vaddr);
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}
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/**
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* hdd_dp_prealloc_get_multi_pages() - gets pre-alloc DP multi-pages memory
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* @desc_type: descriptor type
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* @elem_size: single element size
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* @elem_num: total number of elements should be allocated
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* @pages: multi page information storage
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* @cacheable: coherent memory or cacheable memory
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*
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* Return: None
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*/
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static
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void hdd_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size,
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uint16_t elem_num,
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struct qdf_mem_multi_page_t *pages,
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bool cacheable)
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{
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ucfg_dp_prealloc_get_multi_pages(desc_type, elem_size, elem_num, pages,
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cacheable);
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}
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/**
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* hdd_dp_prealloc_put_multi_pages() - puts back pre-alloc DP multi-pages memory
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* @desc_type: descriptor type
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* @pages: multi page information storage
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*
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* Return: None
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*/
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static
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void hdd_dp_prealloc_put_multi_pages(uint32_t desc_type,
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struct qdf_mem_multi_page_t *pages)
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{
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ucfg_dp_prealloc_put_multi_pages(desc_type, pages);
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}
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#else
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static
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void *hdd_get_consistent_mem_unaligned(size_t size,
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@@ -153,6 +186,20 @@ void hdd_put_consistent_mem_unaligned(void *vaddr)
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{
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hdd_err_rl("prealloc not support!");
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}
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static inline
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void hdd_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size,
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uint16_t elem_num,
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struct qdf_mem_multi_page_t *pages,
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bool cacheable)
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{
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}
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static inline
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void hdd_dp_prealloc_put_multi_pages(uint32_t desc_type,
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struct qdf_mem_multi_page_t *pages)
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{
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}
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#endif
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/**
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@@ -266,6 +313,10 @@ static void hdd_hif_init_driver_state_callbacks(void *data,
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hdd_get_consistent_mem_unaligned;
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cbk->prealloc_put_consistent_mem_unaligned =
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hdd_put_consistent_mem_unaligned;
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cbk->prealloc_get_multi_pages =
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hdd_dp_prealloc_get_multi_pages;
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cbk->prealloc_put_multi_pages =
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hdd_dp_prealloc_put_multi_pages;
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}
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#ifdef HIF_DETECTION_LATENCY_ENABLE
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