From ad66c99ef1c5e7bff9d85a40efb26eb3a86a69b2 Mon Sep 17 00:00:00 2001 From: Yeshwanth Sriram Guntuka Date: Thu, 18 May 2023 17:26:36 +0530 Subject: [PATCH] qcacld-3.0: Add multi pages prealloc support for HIF layer The IOVA for the buffers that are attached to the direct link receive copy engine need to be contiguous for optimal memory mapping on ADSP. Fix is to add multi pages prealloc support for HIF layer and add a pool entry to multi pages prealloc for direct link receive copy engine. Change-Id: Ieb253bd3c1b6550e4c1c63cd587993891ac817f2 CRs-Fixed: 3497689 --- components/dp/core/src/wlan_dp_prealloc.c | 17 ++++--- components/dp/core/src/wlan_dp_wfds.c | 17 ++----- .../dp/dispatcher/inc/wlan_dp_ucfg_api.h | 26 ++++++++++ .../dp/dispatcher/src/wlan_dp_ucfg_api.c | 15 ++++++ core/hdd/src/wlan_hdd_driver_ops.c | 51 +++++++++++++++++++ 5 files changed, 108 insertions(+), 18 deletions(-) diff --git a/components/dp/core/src/wlan_dp_prealloc.c b/components/dp/core/src/wlan_dp_prealloc.c index d1963eeb68..e05526108e 100644 --- a/components/dp/core/src/wlan_dp_prealloc.c +++ b/components/dp/core/src/wlan_dp_prealloc.c @@ -344,8 +344,11 @@ static struct dp_consistent_prealloc g_dp_consistent_allocs[] = { #define NON_CACHEABLE 0 #define CACHEABLE 1 -#define TX_DIRECT_LINK_CE_BUF_PAGES 4 -#define TX_DIRECT_LINK_BUF_PAGES 190 +#define DIRECT_LINK_CE_RX_BUF_SIZE 256 +#define DIRECT_LINK_DEFAULT_BUF_SZ 2048 +#define TX_DIRECT_LINK_BUF_NUM 380 +#define TX_DIRECT_LINK_CE_BUF_NUM 8 +#define RX_DIRECT_LINK_CE_BUF_NUM 30 static struct dp_multi_page_prealloc g_dp_multi_page_allocs[] = { /* 4 TX DESC pools */ @@ -413,10 +416,12 @@ static struct dp_multi_page_prealloc g_dp_multi_page_allocs[] = { 0, NON_CACHEABLE, { 0 } }, #endif #ifdef FEATURE_DIRECT_LINK - {QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE, qdf_page_size, - TX_DIRECT_LINK_CE_BUF_PAGES, 0, NON_CACHEABLE, { 0 } }, - {QDF_DP_TX_DIRECT_LINK_BUF_TYPE, qdf_page_size, - TX_DIRECT_LINK_BUF_PAGES, 0, NON_CACHEABLE, { 0 } }, + {QDF_DP_TX_DIRECT_LINK_CE_BUF_TYPE, DIRECT_LINK_DEFAULT_BUF_SZ, + TX_DIRECT_LINK_CE_BUF_NUM, 0, NON_CACHEABLE, { 0 } }, + {QDF_DP_TX_DIRECT_LINK_BUF_TYPE, DIRECT_LINK_DEFAULT_BUF_SZ, + TX_DIRECT_LINK_BUF_NUM, 0, NON_CACHEABLE, { 0 } }, + {QDF_DP_RX_DIRECT_LINK_CE_BUF_TYPE, DIRECT_LINK_CE_RX_BUF_SIZE, + RX_DIRECT_LINK_CE_BUF_NUM, 0, NON_CACHEABLE, { 0 } }, #endif }; diff --git a/components/dp/core/src/wlan_dp_wfds.c b/components/dp/core/src/wlan_dp_wfds.c index 921eda688c..06a31d44e2 100644 --- a/components/dp/core/src/wlan_dp_wfds.c +++ b/components/dp/core/src/wlan_dp_wfds.c @@ -214,7 +214,8 @@ dp_wfds_req_mem_msg(struct dp_direct_link_wfds_context *dl_wfds) &buf_size); qdf_assert(dma_addr); - info->mem_arena_page_info[i].num_entries_per_page = 1; + info->mem_arena_page_info[i].num_entries_per_page = + qdf_page_size / buf_size; info->mem_arena_page_info[i].page_dma_addr_len = num_pages; while (num_pages--) { @@ -408,22 +409,14 @@ dp_wfds_alloc_mem_arena(struct dp_direct_link_wfds_context *dl_wfds, { qdf_device_t qdf_ctx = dl_wfds->direct_link_ctx->dp_ctx->qdf_dev; uint32_t desc_type; - uint32_t elem_per_page; - uint32_t num_pages; desc_type = dp_wfds_get_desc_type_from_mem_arena(mem_arena); - if (desc_type != QDF_DP_DESC_TYPE_MAX) { - elem_per_page = qdf_page_size / entry_size; - num_pages = num_entries / elem_per_page; - if (num_entries % elem_per_page) - num_pages++; - - dp_prealloc_get_multi_pages(desc_type, qdf_page_size, - num_pages, + if (desc_type != QDF_DP_DESC_TYPE_MAX) + dp_prealloc_get_multi_pages(desc_type, entry_size, + num_entries, &dl_wfds->mem_arena_pages[mem_arena], false); - } if (!dl_wfds->mem_arena_pages[mem_arena].num_pages) qdf_mem_multi_pages_alloc(qdf_ctx, diff --git a/components/dp/dispatcher/inc/wlan_dp_ucfg_api.h b/components/dp/dispatcher/inc/wlan_dp_ucfg_api.h index a77271d299..faef9665a8 100644 --- a/components/dp/dispatcher/inc/wlan_dp_ucfg_api.h +++ b/components/dp/dispatcher/inc/wlan_dp_ucfg_api.h @@ -1330,6 +1330,32 @@ void *ucfg_dp_prealloc_get_consistent_mem_unaligned(qdf_size_t size, * Return: None */ void ucfg_dp_prealloc_put_consistent_mem_unaligned(void *va_unaligned); + +/** + * ucfg_dp_prealloc_get_multi_pages() - gets pre-alloc DP multi-pages memory + * @desc_type: descriptor type + * @elem_size: single element size + * @elem_num: total number of elements should be allocated + * @pages: multi page information storage + * @cacheable: coherent memory or cacheable memory + * + * Return: None + */ +void ucfg_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size, + uint16_t elem_num, + struct qdf_mem_multi_page_t *pages, + bool cacheable); + +/** + * ucfg_dp_prealloc_put_multi_pages() - puts back pre-alloc DP multi-pages + * memory + * @desc_type: descriptor type + * @pages: multi page information storage + * + * Return: None + */ +void ucfg_dp_prealloc_put_multi_pages(uint32_t desc_type, + struct qdf_mem_multi_page_t *pages); #endif #ifdef FEATURE_DIRECT_LINK diff --git a/components/dp/dispatcher/src/wlan_dp_ucfg_api.c b/components/dp/dispatcher/src/wlan_dp_ucfg_api.c index 942f74644c..9e13276f77 100644 --- a/components/dp/dispatcher/src/wlan_dp_ucfg_api.c +++ b/components/dp/dispatcher/src/wlan_dp_ucfg_api.c @@ -2349,6 +2349,21 @@ void ucfg_dp_prealloc_put_consistent_mem_unaligned(void *va_unaligned) { dp_prealloc_put_consistent_mem_unaligned(va_unaligned); } + +void ucfg_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size, + uint16_t elem_num, + struct qdf_mem_multi_page_t *pages, + bool cacheable) +{ + dp_prealloc_get_multi_pages(desc_type, elem_size, elem_num, pages, + cacheable); +} + +void ucfg_dp_prealloc_put_multi_pages(uint32_t desc_type, + struct qdf_mem_multi_page_t *pages) +{ + dp_prealloc_put_multi_pages(desc_type, pages); +} #endif #if defined(WLAN_SUPPORT_RX_FISA) diff --git a/core/hdd/src/wlan_hdd_driver_ops.c b/core/hdd/src/wlan_hdd_driver_ops.c index 4d9ac58350..dbb2115710 100644 --- a/core/hdd/src/wlan_hdd_driver_ops.c +++ b/core/hdd/src/wlan_hdd_driver_ops.c @@ -137,6 +137,39 @@ void hdd_put_consistent_mem_unaligned(void *vaddr) ucfg_dp_prealloc_put_consistent_mem_unaligned(vaddr); } +/** + * hdd_dp_prealloc_get_multi_pages() - gets pre-alloc DP multi-pages memory + * @desc_type: descriptor type + * @elem_size: single element size + * @elem_num: total number of elements should be allocated + * @pages: multi page information storage + * @cacheable: coherent memory or cacheable memory + * + * Return: None + */ +static +void hdd_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size, + uint16_t elem_num, + struct qdf_mem_multi_page_t *pages, + bool cacheable) +{ + ucfg_dp_prealloc_get_multi_pages(desc_type, elem_size, elem_num, pages, + cacheable); +} + +/** + * hdd_dp_prealloc_put_multi_pages() - puts back pre-alloc DP multi-pages memory + * @desc_type: descriptor type + * @pages: multi page information storage + * + * Return: None + */ +static +void hdd_dp_prealloc_put_multi_pages(uint32_t desc_type, + struct qdf_mem_multi_page_t *pages) +{ + ucfg_dp_prealloc_put_multi_pages(desc_type, pages); +} #else static void *hdd_get_consistent_mem_unaligned(size_t size, @@ -153,6 +186,20 @@ void hdd_put_consistent_mem_unaligned(void *vaddr) { hdd_err_rl("prealloc not support!"); } + +static inline +void hdd_dp_prealloc_get_multi_pages(uint32_t desc_type, qdf_size_t elem_size, + uint16_t elem_num, + struct qdf_mem_multi_page_t *pages, + bool cacheable) +{ +} + +static inline +void hdd_dp_prealloc_put_multi_pages(uint32_t desc_type, + struct qdf_mem_multi_page_t *pages) +{ +} #endif /** @@ -266,6 +313,10 @@ static void hdd_hif_init_driver_state_callbacks(void *data, hdd_get_consistent_mem_unaligned; cbk->prealloc_put_consistent_mem_unaligned = hdd_put_consistent_mem_unaligned; + cbk->prealloc_get_multi_pages = + hdd_dp_prealloc_get_multi_pages; + cbk->prealloc_put_multi_pages = + hdd_dp_prealloc_put_multi_pages; } #ifdef HIF_DETECTION_LATENCY_ENABLE