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@@ -200,10 +200,17 @@ static void _dce_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
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u32 common_mode, bool ich_reset,
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struct sde_hw_pingpong *hw_dsc_pp,
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enum sde_3d_blend_mode mode_3d,
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- bool disable_merge_3d, bool enable)
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+ bool disable_merge_3d, bool enable,
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+ bool half_panel_partial_update)
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{
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if (!enable) {
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- if (hw_dsc_pp && hw_dsc_pp->ops.disable_dsc)
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+ /*
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+ * avoid disabling dsc encoder in pp-block as it is
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+ * not double-buffered and is not required to be disabled
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+ * for half panel updates
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+ */
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+ if (hw_dsc_pp && hw_dsc_pp->ops.disable_dsc
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+ && !half_panel_partial_update)
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hw_dsc_pp->ops.disable_dsc(hw_dsc_pp);
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if (hw_dsc && hw_dsc->ops.dsc_disable)
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@@ -342,7 +349,8 @@ static int _dce_dsc_setup_single(struct sde_encoder_virt *sde_enc,
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index, active, merge_3d, disable_merge_3d);
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_dce_dsc_pipe_cfg(hw_dsc, hw_pp, dsc, dsc_common_mode, ich_res,
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- hw_dsc_pp, mode_3d, disable_merge_3d, active);
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+ hw_dsc_pp, mode_3d, disable_merge_3d, active,
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+ half_panel_partial_update);
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memset(&cfg, 0, sizeof(cfg));
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cfg.dsc[cfg.dsc_count++] = hw_dsc->idx;
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@@ -717,7 +725,7 @@ static void _dce_dsc_disable(struct sde_encoder_virt *sde_enc)
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_dce_dsc_pipe_cfg(hw_dsc, hw_pp, NULL,
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0, 0, hw_dsc_pp,
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- BLEND_3D_NONE, false, false);
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+ BLEND_3D_NONE, false, false, false);
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if (hw_dsc) {
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sde_enc->dirty_dsc_ids[i] = hw_dsc->idx;
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