msm: camera: isp: Add VFE debug info

Print status of  VFE debug registers info in case of error.

CRs-Fixed: 2830502
Change-Id: I616ebd90e1d7b648221248571ca35112d7b4f35b
Signed-off-by: Gaurav Jindal <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 
@@ -11,6 +11,265 @@
 #include "cam_vfe_bus_ver3.h"
 #include "cam_irq_controller.h"
 
+static struct cam_vfe_top_ver4_module_desc vfe_pp_mod_desc[] = {
+	{
+		.id = 0,
+		.desc = "CLC_DEMUX",
+	},
+	{
+		.id = 1,
+		.desc = "CLC_CHANNEL_GAIN",
+	},
+	{
+		.id = 2,
+		.desc = "CLC_BPC_PDPC",
+	},
+	{
+		.id = 3,
+		.desc = "CLC_BINCORRECT",
+	},
+	{
+		.id = 4,
+		.desc = "CLC_COMPDECOMP",
+	},
+	{
+		.id = 5,
+		.desc = "CLC_LSC",
+	},
+	{
+		.id = 6,
+		.desc = "CLC_WB_GAIN",
+	},
+	{
+		.id = 7,
+		.desc = "CLC_GIC",
+	},
+	{
+		.id = 8,
+		.desc = "CLC_BPC_ABF",
+	},
+	{
+		.id = 9,
+		.desc = "CLC_BLS",
+	},
+	{
+		.id = 10,
+		.desc = "CLC_BAYER_GTM",
+	},
+	{
+		.id = 11,
+		.desc = "CLC_BAYER_LTM",
+	},
+	{
+		.id = 12,
+		.desc = "CLC_LCAC",
+	},
+	{
+		.id = 13,
+		.desc = "CLC_DEMOSAIC",
+	},
+	{
+		.id = 14,
+		.desc = "CLC_COLOR_CORRECT",
+	},
+	{
+		.id = 15,
+		.desc = "CLC_GTM",
+	},
+	{
+		.id = 16,
+		.desc = "CLC_GLUT",
+	},
+	{
+		.id = 17,
+		.desc = "CLC_COLOR_TRANSFORM",
+	},
+	{
+		.id = 18,
+		.desc = "CLC_UVG",
+	},
+	{
+		.id = 19,
+		.desc = "CLC_PREPROCESSOR",
+	},
+	{
+		.id = 20,
+		.desc = "CLC_CHROMA_UP",
+	},
+	{
+		.id = 21,
+		.desc = "CLC_SPARSE_PD_EXT",
+	},
+	{
+		.id = 22,
+		.desc = "CLC_LCR",
+	},
+	{
+		.id = 23,
+		.desc = "CLC_COMPDECOMP_HVX_TX",
+	},
+	{
+		.id = 24,
+		.desc = "CLC_COMPDECOMP_HVX_RX",
+	},
+	{
+		.id = 25,
+		.desc = "CLC_GTM_FD_OUT",
+	},
+	{
+		.id = 26,
+		.desc = "CLC_CROP_RND_CLAMP_PIXEL_RAW_OUT",
+	},
+	{
+		.id = 27,
+		.desc = "CLC_DOWNSCALE_MN_Y_FD_OUT",
+	},
+	{
+		.id = 28,
+		.desc = "CLC_DOWNSCALE_MN_C_FD_OUT",
+	},
+	{
+		.id = 29,
+		.desc = "CLC_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_FD_OUT",
+	},
+	{
+		.id = 30,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_FD_OUT",
+	},
+	{
+		.id = 31,
+		.desc = "CLC_DOWNSCALE_MN_Y_DISP_OUT",
+	},
+	{
+		.id = 32,
+		.desc = "CLC_DOWNSCALE_MN_C_DISP_OUT",
+	},
+	{
+		.id = 33,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_DISP_OUT",
+	},
+	{
+		.id = 34,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_DISP_OUT",
+	},
+	{
+		.id = 35,
+		.desc = "CLC_DOWNSCALE_4TO1_Y_DISP_DS4_OUT",
+	},
+	{
+		.id = 36,
+		.desc = "CLC_DOWNSCALE_4TO1_C_DISP_DS4_OUT",
+	},
+	{
+		.id = 37,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS4_OUT",
+	},
+	{
+		.id = 38,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS4_OUT",
+	},
+	{
+		.id = 39,
+		.desc = "CLC_DOWNSCALE_4TO1_Y_DISP_DS16_OUT",
+	},
+	{
+		.id = 40,
+		.desc = "CLC_DOWNSCALE_4TO1_C_DISP_DS16_OUT",
+	},
+	{
+		.id = 41,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS16_OUT",
+	},
+	{
+		.id = 42,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS16_OUT",
+	},
+	{
+		.id = 43,
+		.desc = "CLC_DOWNSCALE_MN_Y_VID_OUT",
+	},
+	{
+		.id = 44,
+		.desc = "CLC_DOWNSCALE_MN_C_VID_OUT",
+	},
+	{
+		.id = 45,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_VID_OUT",
+	},
+	{
+		.id = 46,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_VID_OUT",
+	},
+	{
+		.id = 47,
+		.desc = "CLC_DSX_Y_VID_OUT",
+	},
+	{
+		.id = 48,
+		.desc = "CLC_DSX_C_VID_OUT",
+	},
+	{
+		.id = 49,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DSX_Y_VID_OUT",
+	},
+	{
+		.id = 50,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DSX_C_VID_OUT",
+	},
+	{
+		.id = 51,
+		.desc = "CLC_DOWNSCALE_4TO1_Y_VID_DS16_OUT",
+	},
+	{
+		.id = 52,
+		.desc = "CLC_DOWNSCALE_4TO1_C_VID_DS16_OUT",
+	},
+	{
+		.id = 53,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_VID_DS16_OUT",
+	},
+	{
+		.id = 54,
+		.desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_VID_DS16_OUT",
+	},
+	{
+		.id = 55,
+		.desc = "CLC_STATS_AEC_BE",
+	},
+	{
+		.id = 56,
+		.desc = "CLC_STATS_AEC_BHIST",
+	},
+	{
+		.id = 57,
+		.desc = "CLC_STATS_BHIST",
+	},
+	{
+		.id = 58,
+		.desc = "CLC_STATS_TINTLESS_BG",
+	},
+	{
+		.id = 59,
+		.desc = "CLC_STATS_AWB_BG",
+	},
+	{
+		.id = 60,
+		.desc = "CLC_STATS_BFW",
+	},
+	{
+		.id = 61,
+		.desc = "CLC_STATS_BAF",
+	},
+	{
+		.id = 62,
+		.desc = "CLC_STATS_RS",
+	},
+	{
+		.id = 63,
+		.desc = "CLC_STATS_IHIST",
+	},
+};
+
 static struct cam_irq_register_set vfe680_top_irq_reg_set[3] = {
 	{
 		.mask_reg_offset   = 0x00000034,
@@ -64,7 +323,8 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe680_top_common_reg = {
 	.epoch0_pattern_cfg       = 0x00000094,
 	.epoch1_pattern_cfg       = 0x00000098,
 	.epoch_height_cfg         = 0x0000009C,
-	.bus_overflow_status      = 0x0000AA68,
+	.bus_violation_status     = 0x00000C64,
+	.bus_overflow_status      = 0x00000C68,
 	.top_debug_cfg            = 0x000000FC,
 	.top_debug_0              = 0x000000A0,
 	.top_debug_1              = 0x000000A4,
@@ -90,9 +350,10 @@ static struct cam_vfe_ver4_path_reg_data vfe_common_reg_data = {
 	.epoch0_irq_mask                 = 0x10000,
 	.epoch1_irq_mask                 = 0x20000,
 	.eof_irq_mask                    = 0x00000002,
-	.error_irq_mask                 = 0x7F050,
+	.error_irq_mask                  = 0x7F050,
 	.enable_diagnostic_hw            = 0x1,
 	.top_debug_cfg_en                = 3,
+	.pp_violation_mask               = 0x10,
 };
 
 static struct cam_vfe_ver4_path_reg_data vfe680_vfe_full_rdi_reg_data[3] = {
@@ -151,6 +412,7 @@ static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
 	.vfe_full_hw_info = {
 		.common_reg     = &vfe680_top_common_reg,
 		.reg_data       = &vfe_common_reg_data,
+		.module_desc    = vfe_pp_mod_desc,
 	},
 	.pdlib_hw_info = {
 		.common_reg     = &vfe680_top_common_reg,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -32,7 +32,8 @@ struct cam_vfe_mux_ver4_data {
 	struct cam_vfe_top_ver4_reg_offset_common   *common_reg;
 	struct cam_hw_soc_info                      *soc_info;
 	struct cam_vfe_top_common_cfg                cam_common_cfg;
-	struct cam_vfe_ver4_path_reg_data      *reg_data;
+	struct cam_vfe_ver4_path_reg_data           *reg_data;
+	struct cam_vfe_top_ver4_module_desc         *module_desc;
 
 	cam_hw_mgr_event_cb_func             event_cb;
 	void                                *priv;
@@ -508,6 +509,84 @@ int cam_vfe_top_ver4_release(void *device_priv,
 	return 0;
 }
 
+static void cam_vfe_top_ver4_print_debug_reg_status(
+	struct cam_vfe_mux_ver4_data            *mux_data,
+	uint32_t                                *irq_status)
+{
+	uint32_t val0, val1, val2, val3;
+
+	val0 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_0);
+	val1 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_1);
+	val2 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_2);
+	val3 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_3);
+
+	CAM_INFO(CAM_ISP,
+		"status_0: 0x%x status_1: 0x%x status_2: 0x%x status_3: 0x%x",
+		val0, val1, val2, val3);
+
+	val0 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_4);
+	val1 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_5);
+	val2 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_6);
+	val3 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_7);
+
+	CAM_INFO(CAM_ISP,
+		"status_4: 0x%x status_5: 0x%x status_6: 0x%x status_7: 0x%x",
+		val0, val1, val2, val3);
+
+	val0 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_8);
+	val1 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_9);
+	val2 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_10);
+	val3 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_11);
+	CAM_INFO(CAM_ISP,
+		"status_8: 0x%x status_9: 0x%x status_10: 0x%x status_11: 0x%x",
+		val0, val1, val2, val3);
+
+	val0 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_12);
+	val1 = cam_io_r(mux_data->mem_base +
+		mux_data->common_reg->top_debug_13);
+	CAM_INFO(CAM_ISP, "status_12: 0x%x status_13: 0x%x",
+		val0, val1);
+
+	if (irq_status[CAM_IFE_IRQ_CAMIF_REG_STATUS0] &&
+		mux_data->reg_data->pp_violation_mask) {
+
+		val0 =  cam_io_r(mux_data->mem_base +
+				mux_data->common_reg->violation_status),
+
+		CAM_ERR(CAM_ISP, "VFE[%u] PP Violation status 0x%x",
+		     mux_data->hw_intf->hw_idx, val0);
+
+		if (mux_data->module_desc)
+			CAM_ERR(CAM_ISP, "VFE[%u] PP Violation Module[%u] %s",
+				mux_data->hw_intf->hw_idx,
+				mux_data->module_desc[val0].id,
+				mux_data->module_desc[val0].desc);
+	}
+
+	CAM_ERR(CAM_ISP, "VFE[%u] Bus overflow status 0x%x",
+		mux_data->hw_intf->hw_idx,
+		cam_io_r(mux_data->mem_base +
+			mux_data->common_reg->bus_overflow_status));
+
+	CAM_ERR(CAM_ISP, "VFE[%u] Bus  Violation status 0x%x",
+		mux_data->hw_intf->hw_idx,
+		cam_io_r(mux_data->mem_base +
+			mux_data->common_reg->bus_violation_status));
+}
+
 int cam_vfe_top_ver4_start(void *device_priv,
 	void *start_args, uint32_t arg_size)
 {
@@ -895,6 +974,8 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 		if (vfe_priv->event_cb)
 			vfe_priv->event_cb(vfe_priv->priv,
 				CAM_ISP_HW_EVENT_ERROR, (void *)&evt_info);
+		cam_vfe_top_ver4_print_debug_reg_status(vfe_priv,
+			irq_status);
 
 		ret = CAM_VFE_IRQ_STATUS_ERR;
 	}
@@ -1237,6 +1318,7 @@ int cam_vfe_res_init(
 	vfe_priv->soc_info    = soc_info;
 	vfe_priv->vfe_irq_controller = vfe_irq_controller;
 	vfe_priv->is_pixel_path = (vfe_res->res_id == CAM_ISP_HW_VFE_IN_CAMIF);
+	vfe_priv->module_desc   = hw_info->module_desc;
 
 	vfe_res->init                = NULL;
 	vfe_res->deinit              = NULL;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_VFE_TOP_VER4_H_
@@ -60,6 +60,7 @@ struct cam_vfe_top_ver4_reg_offset_common {
 	uint32_t stats_throttle_cfg_0;
 	uint32_t stats_throttle_cfg_1;
 	uint32_t stats_throttle_cfg_2;
+	uint32_t bus_violation_status;
 	uint32_t bus_overflow_status;
 	uint32_t irq_sub_pattern_cfg;
 	uint32_t epoch0_pattern_cfg;
@@ -94,13 +95,17 @@ struct cam_vfe_top_common_cfg {
 	uint32_t     ihist_src_sel;
 };
 
+struct cam_vfe_top_ver4_module_desc {
+	uint32_t id;
+	uint8_t *desc;
+};
+
 struct cam_vfe_ver4_path_hw_info {
 	struct cam_vfe_top_ver4_reg_offset_common  *common_reg;
 	struct cam_vfe_ver4_path_reg_data          *reg_data;
+	struct cam_vfe_top_ver4_module_desc        *module_desc;
 };
 
-
-
 struct cam_vfe_top_ver4_hw_info {
 	struct cam_vfe_top_ver4_reg_offset_common  *common_reg;
 	struct cam_vfe_ver4_path_hw_info            vfe_full_hw_info;
@@ -124,6 +129,7 @@ struct cam_vfe_ver4_path_reg_data {
 	uint32_t     error_irq_mask;
 	uint32_t     enable_diagnostic_hw;
 	uint32_t     top_debug_cfg_en;
+	uint32_t     pp_violation_mask;
 };