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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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*/
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@@ -11,6 +11,265 @@
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#include "cam_vfe_bus_ver3.h"
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#include "cam_irq_controller.h"
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+static struct cam_vfe_top_ver4_module_desc vfe_pp_mod_desc[] = {
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+ {
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+ .id = 0,
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+ .desc = "CLC_DEMUX",
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+ },
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+ {
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+ .id = 1,
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+ .desc = "CLC_CHANNEL_GAIN",
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+ },
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+ {
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+ .id = 2,
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+ .desc = "CLC_BPC_PDPC",
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+ },
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+ {
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+ .id = 3,
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+ .desc = "CLC_BINCORRECT",
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+ },
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+ {
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+ .id = 4,
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+ .desc = "CLC_COMPDECOMP",
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+ },
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+ {
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+ .id = 5,
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+ .desc = "CLC_LSC",
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+ },
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+ {
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+ .id = 6,
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+ .desc = "CLC_WB_GAIN",
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+ },
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+ {
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+ .id = 7,
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+ .desc = "CLC_GIC",
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+ },
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+ {
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+ .id = 8,
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+ .desc = "CLC_BPC_ABF",
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+ },
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+ {
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+ .id = 9,
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+ .desc = "CLC_BLS",
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+ },
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+ {
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+ .id = 10,
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+ .desc = "CLC_BAYER_GTM",
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+ },
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+ {
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+ .id = 11,
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+ .desc = "CLC_BAYER_LTM",
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+ },
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+ {
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+ .id = 12,
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+ .desc = "CLC_LCAC",
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+ },
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+ {
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+ .id = 13,
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+ .desc = "CLC_DEMOSAIC",
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+ },
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+ {
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+ .id = 14,
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+ .desc = "CLC_COLOR_CORRECT",
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+ },
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+ {
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+ .id = 15,
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+ .desc = "CLC_GTM",
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+ },
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+ {
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+ .id = 16,
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+ .desc = "CLC_GLUT",
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+ },
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+ {
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+ .id = 17,
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+ .desc = "CLC_COLOR_TRANSFORM",
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+ },
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+ {
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+ .id = 18,
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+ .desc = "CLC_UVG",
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+ },
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+ {
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+ .id = 19,
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+ .desc = "CLC_PREPROCESSOR",
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+ },
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+ {
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+ .id = 20,
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+ .desc = "CLC_CHROMA_UP",
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+ },
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+ {
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+ .id = 21,
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+ .desc = "CLC_SPARSE_PD_EXT",
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+ },
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+ {
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+ .id = 22,
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+ .desc = "CLC_LCR",
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+ },
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+ {
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+ .id = 23,
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+ .desc = "CLC_COMPDECOMP_HVX_TX",
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+ },
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+ {
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+ .id = 24,
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+ .desc = "CLC_COMPDECOMP_HVX_RX",
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+ },
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+ {
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+ .id = 25,
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+ .desc = "CLC_GTM_FD_OUT",
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+ },
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+ {
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+ .id = 26,
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+ .desc = "CLC_CROP_RND_CLAMP_PIXEL_RAW_OUT",
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+ },
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+ {
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+ .id = 27,
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+ .desc = "CLC_DOWNSCALE_MN_Y_FD_OUT",
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+ },
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+ {
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+ .id = 28,
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+ .desc = "CLC_DOWNSCALE_MN_C_FD_OUT",
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+ },
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+ {
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+ .id = 29,
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+ .desc = "CLC_CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_FD_OUT",
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+ },
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+ {
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+ .id = 30,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_FD_OUT",
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+ },
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+ {
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+ .id = 31,
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+ .desc = "CLC_DOWNSCALE_MN_Y_DISP_OUT",
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+ },
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+ {
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+ .id = 32,
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+ .desc = "CLC_DOWNSCALE_MN_C_DISP_OUT",
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+ },
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+ {
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+ .id = 33,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_DISP_OUT",
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+ },
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+ {
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+ .id = 34,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_DISP_OUT",
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+ },
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+ {
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+ .id = 35,
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+ .desc = "CLC_DOWNSCALE_4TO1_Y_DISP_DS4_OUT",
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+ },
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+ {
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+ .id = 36,
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+ .desc = "CLC_DOWNSCALE_4TO1_C_DISP_DS4_OUT",
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+ },
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+ {
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+ .id = 37,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS4_OUT",
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+ },
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+ {
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+ .id = 38,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS4_OUT",
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+ },
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+ {
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+ .id = 39,
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+ .desc = "CLC_DOWNSCALE_4TO1_Y_DISP_DS16_OUT",
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+ },
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+ {
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+ .id = 40,
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+ .desc = "CLC_DOWNSCALE_4TO1_C_DISP_DS16_OUT",
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+ },
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+ {
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+ .id = 41,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_DISP_DS16_OUT",
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+ },
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+ {
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+ .id = 42,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_DISP_DS16_OUT",
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+ },
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+ {
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+ .id = 43,
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+ .desc = "CLC_DOWNSCALE_MN_Y_VID_OUT",
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+ },
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+ {
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+ .id = 44,
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+ .desc = "CLC_DOWNSCALE_MN_C_VID_OUT",
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+ },
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+ {
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+ .id = 45,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_Y_VID_OUT",
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+ },
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+ {
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+ .id = 46,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_MN_C_VID_OUT",
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+ },
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+ {
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+ .id = 47,
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+ .desc = "CLC_DSX_Y_VID_OUT",
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+ },
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+ {
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+ .id = 48,
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+ .desc = "CLC_DSX_C_VID_OUT",
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+ },
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+ {
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+ .id = 49,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DSX_Y_VID_OUT",
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+ },
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+ {
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+ .id = 50,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DSX_C_VID_OUT",
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+ },
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+ {
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+ .id = 51,
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+ .desc = "CLC_DOWNSCALE_4TO1_Y_VID_DS16_OUT",
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+ },
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+ {
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+ .id = 52,
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+ .desc = "CLC_DOWNSCALE_4TO1_C_VID_DS16_OUT",
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+ },
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+ {
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+ .id = 53,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_Y_VID_DS16_OUT",
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+ },
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+ {
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+ .id = 54,
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+ .desc = "CLC_CROP_RND_CLAMP_POST_DOWNSCALE_4TO1_C_VID_DS16_OUT",
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+ },
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+ {
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+ .id = 55,
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+ .desc = "CLC_STATS_AEC_BE",
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+ },
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+ {
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+ .id = 56,
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+ .desc = "CLC_STATS_AEC_BHIST",
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+ },
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+ {
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+ .id = 57,
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+ .desc = "CLC_STATS_BHIST",
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+ },
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+ {
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+ .id = 58,
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+ .desc = "CLC_STATS_TINTLESS_BG",
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+ },
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+ {
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+ .id = 59,
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+ .desc = "CLC_STATS_AWB_BG",
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+ },
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+ {
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+ .id = 60,
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+ .desc = "CLC_STATS_BFW",
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+ },
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+ {
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+ .id = 61,
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+ .desc = "CLC_STATS_BAF",
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+ },
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+ {
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+ .id = 62,
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+ .desc = "CLC_STATS_RS",
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+ },
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+ {
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+ .id = 63,
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+ .desc = "CLC_STATS_IHIST",
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+ },
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+};
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+
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static struct cam_irq_register_set vfe680_top_irq_reg_set[3] = {
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{
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.mask_reg_offset = 0x00000034,
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@@ -64,7 +323,8 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe680_top_common_reg = {
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.epoch0_pattern_cfg = 0x00000094,
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.epoch1_pattern_cfg = 0x00000098,
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.epoch_height_cfg = 0x0000009C,
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- .bus_overflow_status = 0x0000AA68,
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+ .bus_violation_status = 0x00000C64,
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+ .bus_overflow_status = 0x00000C68,
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.top_debug_cfg = 0x000000FC,
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.top_debug_0 = 0x000000A0,
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.top_debug_1 = 0x000000A4,
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@@ -90,9 +350,10 @@ static struct cam_vfe_ver4_path_reg_data vfe_common_reg_data = {
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.epoch0_irq_mask = 0x10000,
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.epoch1_irq_mask = 0x20000,
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.eof_irq_mask = 0x00000002,
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- .error_irq_mask = 0x7F050,
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+ .error_irq_mask = 0x7F050,
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.enable_diagnostic_hw = 0x1,
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.top_debug_cfg_en = 3,
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+ .pp_violation_mask = 0x10,
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};
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static struct cam_vfe_ver4_path_reg_data vfe680_vfe_full_rdi_reg_data[3] = {
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@@ -151,6 +412,7 @@ static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
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.vfe_full_hw_info = {
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.common_reg = &vfe680_top_common_reg,
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.reg_data = &vfe_common_reg_data,
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+ .module_desc = vfe_pp_mod_desc,
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},
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.pdlib_hw_info = {
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.common_reg = &vfe680_top_common_reg,
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