samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: sde: report intf interrupt status during underrun

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Add the INTF interrupt status register value to the underrun
line count event log to assist in debugging these issues.

Change-Id: I847cb12f8b4565d5f04667e0abda5d051a6194b2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This commit is contained in:
Steve Cohen
2020-07-29 22:14:04 -04:00
parent d767013a10
commit a4be27ac7e
3 changed files with 21 additions and 1 deletions
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8
msm/sde/sde_encoder_phys_vid.c
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@@ -1198,6 +1198,7 @@ static u32 sde_encoder_phys_vid_get_underrun_line_count(
struct sde_encoder_phys *phys_enc) struct sde_encoder_phys *phys_enc)
{ {
u32 underrun_linecount = 0xebadebad; u32 underrun_linecount = 0xebadebad;
u32 intf_intr_status = 0xebadebad;
struct intf_status intf_status = {0}; struct intf_status intf_status = {0};
if (!phys_enc) if (!phys_enc)
@@ -1215,8 +1216,13 @@ static u32 sde_encoder_phys_vid_get_underrun_line_count(
phys_enc->hw_intf->ops.get_underrun_line_count( phys_enc->hw_intf->ops.get_underrun_line_count(
phys_enc->hw_intf); phys_enc->hw_intf);
if (phys_enc->hw_intf->ops.get_intr_status)
intf_intr_status = phys_enc->hw_intf->ops.get_intr_status(
phys_enc->hw_intf);
SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount, SDE_EVT32(DRMID(phys_enc->parent), underrun_linecount,
intf_status.frame_count, intf_status.line_count); intf_status.frame_count, intf_status.line_count,
intf_intr_status);
return underrun_linecount; return underrun_linecount;
} }

9
msm/sde/sde_hw_intf.c
View File

@@ -531,6 +531,14 @@ static u32 sde_hw_intf_get_underrun_line_count(struct sde_hw_intf *intf)
0xebadebad; 0xebadebad;
} }
static u32 sde_hw_intf_get_intr_status(struct sde_hw_intf *intf)
{
if (!intf)
return -EINVAL;
return SDE_REG_READ(&intf->hw, INTF_INTR_STATUS);
}
static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf, static int sde_hw_intf_setup_te_config(struct sde_hw_intf *intf,
struct sde_hw_tear_check *te) struct sde_hw_tear_check *te)
{ {
@@ -783,6 +791,7 @@ static void _setup_intf_ops(struct sde_hw_intf_ops *ops,
ops->collect_misr = sde_hw_intf_collect_misr; ops->collect_misr = sde_hw_intf_collect_misr;
ops->get_line_count = sde_hw_intf_get_line_count; ops->get_line_count = sde_hw_intf_get_line_count;
ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count; ops->get_underrun_line_count = sde_hw_intf_get_underrun_line_count;
ops->get_intr_status = sde_hw_intf_get_intr_status;
ops->avr_setup = sde_hw_intf_avr_setup; ops->avr_setup = sde_hw_intf_avr_setup;
ops->avr_trigger = sde_hw_intf_avr_trigger; ops->avr_trigger = sde_hw_intf_avr_trigger;
ops->avr_ctrl = sde_hw_intf_avr_ctrl; ops->avr_ctrl = sde_hw_intf_avr_ctrl;

5
msm/sde/sde_hw_intf.h
View File

@@ -206,6 +206,11 @@ struct sde_hw_intf_ops {
* Enable processing of 2 pixels per clock * Enable processing of 2 pixels per clock
*/ */
void (*enable_wide_bus)(struct sde_hw_intf *intf, bool enable); void (*enable_wide_bus)(struct sde_hw_intf *intf, bool enable);
/**
* Get the INTF interrupt status
*/
u32 (*get_intr_status)(struct sde_hw_intf *intf);
}; };
struct sde_hw_intf { struct sde_hw_intf {