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Revert "asoc: lpass-cdc: Do not update VA clk muxsel register"

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This reverts commit 57fa62e292.

Change-Id: I1afb0d2f7495d3b30fc99bb4391eda094921fa89
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang
2021-05-26 17:52:21 -07:00
parent dbbe46ef46
commit a108d5c2bb
1 changed files with 18 additions and 38 deletions
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56
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
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@@ -232,13 +232,11 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
if (enable) { if (enable) {
if (priv->clk_cnt[clk_id] == 0) { if (priv->clk_cnt[clk_id] == 0) {
if (clk_id != VA_CORE_CLK) { ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, default_clk_id,
true); true);
if (ret < 0) if (ret < 0)
goto done; goto done;
}
ret = clk_prepare_enable(priv->clk[clk_id]); ret = clk_prepare_enable(priv->clk[clk_id]);
if (ret < 0) { if (ret < 0) {
@@ -246,22 +244,14 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id); __func__, clk_id);
goto err_clk; goto err_clk;
} }
/* if (priv->dev_up_gfmux) {
* Temp SW workaround to address a glitch issue of iowrite32(0x1, clk_muxsel);
* VA GFMux instance responsible for switching from muxsel = ioread32(clk_muxsel);
* TX MCLK to VA MCLK. This configuration would be taken trace_printk("%s: muxsel value after enable: %d\n",
* care in DSP itself __func__, muxsel);
*/
if (clk_id != VA_CORE_CLK) {
if (priv->dev_up_gfmux) {
iowrite32(0x1, clk_muxsel);
muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after enable: %d\n",
__func__, muxsel);
}
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
false);
} }
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
false);
} }
priv->clk_cnt[clk_id]++; priv->clk_cnt[clk_id]++;
} else { } else {
@@ -273,34 +263,24 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
} }
priv->clk_cnt[clk_id]--; priv->clk_cnt[clk_id]--;
if (priv->clk_cnt[clk_id] == 0) { if (priv->clk_cnt[clk_id] == 0) {
/* ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
* Temp SW workaround to address a glitch issue
* of VA GFMux instance responsible for
* switching from TX MCLK to VA MCLK.
* This configuration would be taken
* care in DSP itself.
*/
if (clk_id != VA_CORE_CLK) {
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, true); default_clk_id, true);
if (!ret && priv->dev_up_gfmux) { if (!ret && priv->dev_up_gfmux) {
iowrite32(0x0, clk_muxsel); iowrite32(0x0, clk_muxsel);
muxsel = ioread32(clk_muxsel); muxsel = ioread32(clk_muxsel);
trace_printk("%s: muxsel value after disable: %d\n", trace_printk("%s: muxsel value after disable: %d\n",
__func__, muxsel); __func__, muxsel);
}
} }
clk_disable_unprepare(priv->clk[clk_id]); clk_disable_unprepare(priv->clk[clk_id]);
if (clk_id != VA_CORE_CLK && !ret) if (!ret)
lpass_cdc_clk_rsc_mux0_clk_request(priv, lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, false); default_clk_id, false);
} }
} }
return ret; return ret;
err_clk: err_clk:
if (clk_id != VA_CORE_CLK) lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
done: done:
return ret; return ret;
} }