video: driver: Add HFI and internal buffer changes for AV1 DRAP
Add changes for AV1 DRAP (Delayed Random Access Point) handling: 1) Add config in kalama database to control DRAP and the HFI property to set DRAP config. 2) Update buffer calculations: - When DRAP is disabled, COMV buffer must be allocated and PERSIST buffer must be allocated with total_ref_count = 0 - When DRAP is enabled, COMV buffer must not be allocated - it is part of PERSIST buffer. Persist buffer must be allocated with the max_width, max_height and total_ref_count configured for DRAP. Change-Id: I2d2e8fd3f63ea8f9fc2845acd0b4e16ba4776a6b Signed-off-by: Mihir Ganu <quic_mganu@quicinc.com>
This commit is contained in:
@@ -1484,6 +1484,11 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
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0,
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0,
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HFI_PROP_AV1_SUPER_BLOCK_ENABLED},
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HFI_PROP_AV1_SUPER_BLOCK_ENABLED},
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{DRAP, DEC, AV1,
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0, S32_MAX, 1, 0,
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0,
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HFI_PROP_AV1_DRAP_CONFIG},
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{META_BITSTREAM_RESOLUTION, DEC, AV1,
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{META_BITSTREAM_RESOLUTION, DEC, AV1,
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V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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1, V4L2_MPEG_MSM_VIDC_DISABLE,
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@@ -880,6 +880,17 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
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#define AV1D_LCU_MIN_SIZE_PELS 64
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#define AV1D_LCU_MIN_SIZE_PELS 64
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#define AV1D_MAX_TILE_COLS 64
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#define AV1D_MAX_TILE_COLS 64
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#define HFI_BUFFER_COMV_AV1D(_size, frame_width, frame_height, \
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_yuv_bufcount_min) \
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do { \
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_size = 2 * HFI_ALIGN(MAX(((frame_width + 63) / 64) * \
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((frame_height + 63) / 64) * 512, \
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((frame_width + 127) / 128) * \
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((frame_height + 127) / 128) * 2816), \
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VENUS_DMA_ALIGNMENT); \
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_size *= _yuv_bufcount_min; \
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} while (0)
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#define SIZE_AV1D_LB_FE_TOP_DATA(frame_width, frame_height) \
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#define SIZE_AV1D_LB_FE_TOP_DATA(frame_width, frame_height) \
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(HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * ((16 * 10) >> 3) + \
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(HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) * ((16 * 10) >> 3) + \
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HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * ((16 * 6) >> 3) * 2)
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HFI_ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 * ((16 * 6) >> 3) * 2)
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@@ -1135,15 +1146,18 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
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(((8192 + 127) / 128) * ((4352 + 127) / 128) * \
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(((8192 + 127) / 128) * ((4352 + 127) / 128) * \
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AV1D_SIZE_BSE_COL_MV_128x128))
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AV1D_SIZE_BSE_COL_MV_128x128))
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#define HFI_BUFFER_PERSIST_AV1D(_size) \
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#define HFI_BUFFER_PERSIST_AV1D(_size, max_width, max_height, total_ref_count) \
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do \
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do \
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{ \
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{ \
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_size = HFI_ALIGN(SIZE_AV1D_SEQUENCE_HEADER * 2 + \
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HFI_U32 comv_size; \
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SIZE_AV1D_METADATA + \
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HFI_BUFFER_COMV_AV1D(comv_size, max_width, max_height, total_ref_count); \
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_size = \
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HFI_ALIGN((SIZE_AV1D_SEQUENCE_HEADER * 2 + \
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SIZE_AV1D_METADATA + \
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AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) + \
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AV1D_NUM_HW_PIC_BUF * (SIZE_AV1D_TILE_OFFSET + SIZE_AV1D_QM) + \
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AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER + \
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AV1D_NUM_FRAME_HEADERS * (SIZE_AV1D_FRAME_HEADER + \
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2 * SIZE_AV1D_PROB_TABLE) + \
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2 * SIZE_AV1D_PROB_TABLE) + \
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AV1D_NUM_HW_PIC_BUF * 2 * SIZE_AV1D_COL_MV, VENUS_DMA_ALIGNMENT); \
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comv_size), VENUS_DMA_ALIGNMENT); \
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} while (0)
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} while (0)
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#define HFI_BUFFER_BITSTREAM_ENC(size, frame_width, frame_height, \
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#define HFI_BUFFER_BITSTREAM_ENC(size, frame_width, frame_height, \
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@@ -69,7 +69,7 @@ static u32 msm_vidc_decoder_comv_size_iris3(struct msm_vidc_inst* inst)
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{
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{
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u32 size = 0;
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u32 size = 0;
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u32 width, height, out_min_count, vpp_delay;
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u32 width, height, out_min_count, vpp_delay;
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struct v4l2_format* f;
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struct v4l2_format *f;
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if (!inst || !inst->core) {
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if (!inst || !inst->core) {
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d_vpr_e("%s: invalid params\n", __func__);
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d_vpr_e("%s: invalid params\n", __func__);
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@@ -86,10 +86,21 @@ static u32 msm_vidc_decoder_comv_size_iris3(struct msm_vidc_inst* inst)
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out_min_count = inst->buffers.output.min_count;
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out_min_count = inst->buffers.output.min_count;
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out_min_count = max(vpp_delay + 1, out_min_count);
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out_min_count = max(vpp_delay + 1, out_min_count);
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if (inst->codec == MSM_VIDC_H264)
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if (inst->codec == MSM_VIDC_H264) {
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HFI_BUFFER_COMV_H264D(size, width, height, out_min_count);
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HFI_BUFFER_COMV_H264D(size, width, height, out_min_count);
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else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
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} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
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HFI_BUFFER_COMV_H265D(size, width, height, out_min_count);
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HFI_BUFFER_COMV_H265D(size, width, height, out_min_count);
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} else if (inst->codec == MSM_VIDC_AV1) {
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/*
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* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
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* should not be allocated separately.
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* When DRAP is disabled, COMV buffer must be allocated.
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*/
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if (inst->capabilities->cap[DRAP].value)
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size = 0;
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else
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HFI_BUFFER_COMV_AV1D(size, width, height, out_min_count);
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}
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i_vpr_l(inst, "%s: size %d\n", __func__, size);
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i_vpr_l(inst, "%s: size %d\n", __func__, size);
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return size;
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return size;
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@@ -195,14 +206,28 @@ static u32 msm_vidc_decoder_persist_size_iris3(struct msm_vidc_inst *inst)
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return size;
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return size;
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}
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}
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if (inst->codec == MSM_VIDC_H264)
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if (inst->codec == MSM_VIDC_H264) {
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HFI_BUFFER_PERSIST_H264D(size);
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HFI_BUFFER_PERSIST_H264D(size);
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else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC)
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} else if (inst->codec == MSM_VIDC_HEVC || inst->codec == MSM_VIDC_HEIC) {
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HFI_BUFFER_PERSIST_H265D(size);
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HFI_BUFFER_PERSIST_H265D(size);
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else if (inst->codec == MSM_VIDC_VP9)
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} else if (inst->codec == MSM_VIDC_VP9) {
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HFI_BUFFER_PERSIST_VP9D(size);
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HFI_BUFFER_PERSIST_VP9D(size);
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else if (inst->codec == MSM_VIDC_AV1)
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} else if (inst->codec == MSM_VIDC_AV1) {
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HFI_BUFFER_PERSIST_AV1D(size);
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/*
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* When DRAP is enabled, COMV buffer is part of PERSIST buffer and
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* should not be allocated separately. PERSIST buffer should include
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* COMV buffer calculated with width, height, refcount.
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* When DRAP is disabled, COMV buffer should not be included in PERSIST
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* buffer.
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*/
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if (inst->capabilities->cap[DRAP].value)
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HFI_BUFFER_PERSIST_AV1D(size,
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inst->capabilities->cap[FRAME_WIDTH].max,
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inst->capabilities->cap[FRAME_HEIGHT].max, 16);
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else
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HFI_BUFFER_PERSIST_AV1D(size, 0, 0, 0);
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}
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i_vpr_l(inst, "%s: size %d\n", __func__, size);
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i_vpr_l(inst, "%s: size %d\n", __func__, size);
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return size;
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return size;
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}
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}
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@@ -540,6 +540,8 @@ enum hfi_nal_length_field_type {
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#define HFI_PROP_OPB_ENABLE 0x03000184
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#define HFI_PROP_OPB_ENABLE 0x03000184
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#define HFI_PROP_AV1_DRAP_CONFIG 0x03000189
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#define HFI_PROP_END 0x03FFFFFF
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#define HFI_PROP_END 0x03FFFFFF
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#define HFI_SESSION_ERROR_BEGIN 0x04000000
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#define HFI_SESSION_ERROR_BEGIN 0x04000000
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@@ -556,6 +558,8 @@ enum hfi_nal_length_field_type {
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#define HFI_ERROR_BUFFER_NOT_SET 0x04000006
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#define HFI_ERROR_BUFFER_NOT_SET 0x04000006
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#define HFI_ERROR_DRAP_CONFIG_EXCEED 0x04000007
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#define HFI_SESSION_ERROR_END 0x04FFFFFF
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#define HFI_SESSION_ERROR_END 0x04FFFFFF
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#define HFI_SYSTEM_ERROR_BEGIN 0x05000000
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#define HFI_SYSTEM_ERROR_BEGIN 0x05000000
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@@ -458,6 +458,7 @@ enum msm_vidc_inst_capability_type {
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DPB_LIST,
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DPB_LIST,
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FILM_GRAIN,
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FILM_GRAIN,
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SUPER_BLOCK,
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SUPER_BLOCK,
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DRAP,
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ALL_INTRA,
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ALL_INTRA,
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INPUT_METADATA_FD,
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INPUT_METADATA_FD,
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META_BITSTREAM_RESOLUTION,
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META_BITSTREAM_RESOLUTION,
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@@ -886,6 +886,32 @@ static int msm_vdec_set_av1_operating_point(struct msm_vidc_inst *inst,
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return rc;
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return rc;
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}
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}
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static int msm_vdec_set_av1_drap_config(struct msm_vidc_inst *inst,
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enum msm_vidc_port_type port)
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{
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int rc = 0;
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u32 drap_config;
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if (inst->codec != MSM_VIDC_AV1)
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return 0;
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drap_config = inst->capabilities->cap[DRAP].value;
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i_vpr_h(inst, "%s: drap_config: %u\n", __func__, drap_config);
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rc = venus_hfi_session_property(inst,
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HFI_PROP_AV1_DRAP_CONFIG,
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HFI_HOST_FLAGS_NONE,
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get_hfi_port(inst, port),
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HFI_PAYLOAD_U32,
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&drap_config,
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sizeof(u32));
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if (rc) {
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i_vpr_e(inst, "%s: set property failed\n", __func__);
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return rc;
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}
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return rc;
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}
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static int msm_vdec_set_input_properties(struct msm_vidc_inst *inst)
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static int msm_vdec_set_input_properties(struct msm_vidc_inst *inst)
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{
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{
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int rc = 0;
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int rc = 0;
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@@ -935,6 +961,10 @@ static int msm_vdec_set_input_properties(struct msm_vidc_inst *inst)
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if (rc)
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if (rc)
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return rc;
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return rc;
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rc = msm_vdec_set_av1_drap_config(inst, INPUT_PORT);
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if (rc)
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return rc;
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return rc;
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return rc;
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}
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}
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@@ -187,7 +187,8 @@ u32 msm_vidc_internal_buffer_count(struct msm_vidc_inst *inst,
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buffer_type == MSM_VIDC_BUF_NON_COMV) {
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buffer_type == MSM_VIDC_BUF_NON_COMV) {
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if (inst->codec == MSM_VIDC_H264 ||
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if (inst->codec == MSM_VIDC_H264 ||
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inst->codec == MSM_VIDC_HEVC ||
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inst->codec == MSM_VIDC_HEVC ||
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inst->codec == MSM_VIDC_HEIC)
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inst->codec == MSM_VIDC_HEIC ||
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inst->codec == MSM_VIDC_AV1)
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count = 1;
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count = 1;
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else
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else
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count = 0;
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count = 0;
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@@ -175,6 +175,7 @@ static const struct msm_vidc_cap_name cap_name_arr[] = {
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{DPB_LIST, "DPB_LIST" },
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{DPB_LIST, "DPB_LIST" },
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{FILM_GRAIN, "FILM_GRAIN" },
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{FILM_GRAIN, "FILM_GRAIN" },
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{SUPER_BLOCK, "SUPER_BLOCK" },
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{SUPER_BLOCK, "SUPER_BLOCK" },
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{DRAP, "DRAP" },
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{ALL_INTRA, "ALL_INTRA" },
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{ALL_INTRA, "ALL_INTRA" },
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{INPUT_METADATA_FD, "INPUT_METADATA_FD" },
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{INPUT_METADATA_FD, "INPUT_METADATA_FD" },
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{META_BITSTREAM_RESOLUTION, "META_BITSTREAM_RESOLUTION" },
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{META_BITSTREAM_RESOLUTION, "META_BITSTREAM_RESOLUTION" },
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