ipa: update hw stats to IPAv5

Adapt to removal of uni dimensional registers and replace
in bi dimensional registers due to increase in IPA pipes
number

Change-Id: Icf8e858d275744d30ffcc09ab6147de52b9ab148
Signed-off-by: Amir Levy <[email protected]>

drivers/platform/msm/ipa/ipa_v3/ipa_i.h

@@ -2955,8 +2955,8 @@ int ipa3_wigig_init_i(void);
 #define IPA_STATS_MAX_PIPE_BIT 32
 
 struct ipa_teth_stats_endpoints {
-	u32 prod_mask;
-	u32 dst_ep_mask[IPA_STATS_MAX_PIPE_BIT];
+	u32 prod_mask[IPA5_PIPE_REG_NUM];
+	u32 dst_ep_mask[IPA5_PIPES_NUM][IPA5_PIPE_REG_NUM];
 };
 
 int ipa_hw_stats_init(void);
@@ -2965,7 +2965,7 @@ int ipa_init_flt_rt_stats(void);
 
 int ipa_debugfs_init_stats(struct dentry *parent);
 
-int ipa_init_quota_stats(u32 pipe_bitmask);
+int ipa_init_quota_stats(u32 *pipe_bitmask);
 
 int ipa_get_quota_stats(struct ipa_quota_stats_all *out);
 
@@ -2975,7 +2975,7 @@ int ipa_reset_all_quota_stats(void);
 
 int ipa_drop_stats_init(void);
 
-int ipa_init_drop_stats(u32 pipe_bitmask);
+int ipa_init_drop_stats(u32 *pipe_bitmask);
 
 int ipa_get_drop_stats(struct ipa_drop_stats_all *out);
 

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal.h

@@ -698,4 +698,19 @@ int ipahal_init(enum ipa_hw_type ipa_hw_type, void __iomem *base,
 void ipahal_destroy(void);
 void ipahal_free_dma_mem(struct ipa_mem_buffer *mem);
 
+/*
+* ipahal_test_ep_bit() - return true if a ep bit is set
+*/
+bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num);
+
+/*
+* ipahal_get_ep_bit() - get ep bit set in the right offset
+*/
+u32 ipahal_get_ep_bit(u32 ep_num);
+
+/*
+* ipahal_get_ep_reg_idx() - get ep reg index according to ep num
+*/
+u32 ipahal_get_ep_reg_idx(u32 ep_num);
+
 #endif /* _IPAHAL_H_ */

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.c

@@ -34,7 +34,31 @@ static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_quota(
 	struct ipahal_stats_init_pyld *pyld;
 	struct ipahal_stats_init_quota *in =
 		(struct ipahal_stats_init_quota *)params;
-	int entries = _count_ones(in->enabled_bitmask);
+	int entries = _count_ones(in->enabled_bitmask[0]);
+
+	IPAHAL_DBG_LOW("entries = %d\n", entries);
+	pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) +
+		entries * sizeof(struct ipahal_stats_quota_hw), is_atomic_ctx);
+	if (!pyld) {
+		IPAHAL_ERR("no mem\n");
+		return NULL;
+	}
+
+	pyld->len = entries * sizeof(struct ipahal_stats_quota_hw);
+	return pyld;
+}
+
+static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_quota_v5_0(
+	void *params, bool is_atomic_ctx)
+{
+	struct ipahal_stats_init_pyld *pyld;
+	struct ipahal_stats_init_quota *in =
+		(struct ipahal_stats_init_quota *)params;
+	int i;
+	int entries = 0;
+
+	for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++)
+		entries += _count_ones(in->enabled_bitmask[i]);
 
 	IPAHAL_DBG_LOW("entries = %d\n", entries);
 	pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) +
@@ -53,7 +77,24 @@ static int ipahal_get_offset_quota(void *params,
 {
 	struct ipahal_stats_get_offset_quota *in =
 		(struct ipahal_stats_get_offset_quota *)params;
-	int entries = _count_ones(in->init.enabled_bitmask);
+	int entries = _count_ones(in->init.enabled_bitmask[0]);
+
+	IPAHAL_DBG_LOW("\n");
+	out->offset = 0;
+	out->size = entries * sizeof(struct ipahal_stats_quota_hw);
+
+	return 0;
+}
+
+static int ipahal_get_offset_quota_v5_0(void *params,
+	struct ipahal_stats_offset *out)
+{
+	struct ipahal_stats_get_offset_quota *in =
+		(struct ipahal_stats_get_offset_quota *)params;
+	int i, entries = 0;
+
+	for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++)
+		entries += _count_ones(in->init.enabled_bitmask[i]);
 
 	IPAHAL_DBG_LOW("\n");
 	out->offset = 0;
@@ -77,7 +118,40 @@ static int ipahal_parse_stats_quota(void *init_params, void *raw_stats,
 	memset(out, 0, sizeof(*out));
 	IPAHAL_DBG_LOW("\n");
 	for (i = 0; i < IPAHAL_MAX_PIPES; i++) {
-		if (init->enabled_bitmask & (1 << i)) {
+		if (init->enabled_bitmask[0] & (1 << i)) {
+			IPAHAL_DBG_LOW("pipe %d stat_idx %d\n", i, stat_idx);
+			out->stats[i].num_ipv4_bytes =
+				raw_hw[stat_idx].num_ipv4_bytes;
+			out->stats[i].num_ipv4_pkts =
+				raw_hw[stat_idx].num_ipv4_pkts;
+			out->stats[i].num_ipv6_pkts =
+				raw_hw[stat_idx].num_ipv6_pkts;
+			out->stats[i].num_ipv6_bytes =
+				raw_hw[stat_idx].num_ipv6_bytes;
+			stat_idx++;
+		}
+	}
+
+	return 0;
+}
+
+static int ipahal_parse_stats_quota_v5_0(void *init_params, void *raw_stats,
+	void *parsed_stats)
+{
+	struct ipahal_stats_init_quota *init =
+		(struct ipahal_stats_init_quota *)init_params;
+	struct ipahal_stats_quota_hw *raw_hw =
+		(struct ipahal_stats_quota_hw *)raw_stats;
+	struct ipahal_stats_quota_all *out =
+		(struct ipahal_stats_quota_all *)parsed_stats;
+	int stat_idx = 0;
+	int i, reg_idx;
+
+	memset(out, 0, sizeof(*out));
+	IPAHAL_DBG_LOW("\n");
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		reg_idx = ipahal_get_ep_reg_idx(i);
+		if (init->enabled_bitmask[reg_idx] & ipahal_get_ep_bit(i)) {
 			IPAHAL_DBG_LOW("pipe %d stat_idx %d\n", i, stat_idx);
 			out->stats[i].num_ipv4_bytes =
 				raw_hw[stat_idx].num_ipv4_bytes;
@@ -100,20 +174,20 @@ static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering(
 	struct ipahal_stats_init_pyld *pyld;
 	struct ipahal_stats_init_tethering *in =
 		(struct ipahal_stats_init_tethering *)params;
-	int hdr_entries = _count_ones(in->prod_bitmask);
+	int hdr_entries = _count_ones(in->prod_bitmask[0]);
 	int entries = 0;
 	int i;
 	void *pyld_ptr;
 	u32 incremental_offset;
 
 	IPAHAL_DBG_LOW("prod entries = %d\n", hdr_entries);
-	for (i = 0; i < sizeof(in->prod_bitmask) * 8; i++) {
-		if (in->prod_bitmask & (1 << i)) {
-			if (in->cons_bitmask[i] == 0) {
+	for (i = 0; i < sizeof(in->prod_bitmask[0]) * 8; i++) {
+		if (in->prod_bitmask[0] & (1 << i)) {
+			if (in->cons_bitmask[i][0] == 0) {
 				IPAHAL_ERR("no cons bitmask for prod %d\n", i);
 				return NULL;
 			}
-			entries += _count_ones(in->cons_bitmask[i]);
+			entries += _count_ones(in->cons_bitmask[i][0]);
 		}
 	}
 	IPAHAL_DBG_LOW("sum all entries = %d\n", entries);
@@ -132,16 +206,108 @@ static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering(
 	incremental_offset =
 		(hdr_entries * sizeof(struct ipahal_stats_tethering_hdr_hw))
 			/ 8;
-	for (i = 0; i < sizeof(in->prod_bitmask) * 8; i++) {
-		if (in->prod_bitmask & (1 << i)) {
+	for (i = 0; i < sizeof(in->prod_bitmask[0]) * 8; i++) {
+		if (in->prod_bitmask[0] & (1 << i)) {
 			struct ipahal_stats_tethering_hdr_hw *hdr = pyld_ptr;
 
-			hdr->dst_mask = in->cons_bitmask[i];
+			hdr->dst_mask = in->cons_bitmask[i][0];
 			hdr->offset = incremental_offset;
 			IPAHAL_DBG_LOW("hdr->dst_mask=0x%x\n", hdr->dst_mask);
 			IPAHAL_DBG_LOW("hdr->offset=0x%x\n", hdr->offset);
 			/* add the stats entry */
-			incremental_offset += _count_ones(in->cons_bitmask[i]) *
+			incremental_offset += _count_ones(
+				in->cons_bitmask[i][0]) *
+				sizeof(struct ipahal_stats_tethering_hw) / 8;
+			pyld_ptr += sizeof(*hdr);
+		}
+	}
+
+	return pyld;
+}
+
+static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_tethering_v5_0(
+	void *params, bool is_atomic_ctx)
+{
+	struct ipahal_stats_init_pyld *pyld;
+	struct ipahal_stats_init_tethering *in =
+		(struct ipahal_stats_init_tethering *)params;
+	int hdr_entries;
+	int entries = 0;
+	int i, j, reg_idx;
+	void *pyld_ptr;
+	u32 incremental_offset;
+
+	for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++) {
+		hdr_entries = _count_ones(in->prod_bitmask[i]);
+	}
+
+	IPAHAL_DBG_LOW("prod entries = %d\n", hdr_entries);
+	reg_idx = 0;
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) {
+			reg_idx++;
+		}
+		if (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i)) {
+			bool has_cons = false;
+
+			for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) {
+				if (in->cons_bitmask[i][j]) {
+					has_cons = true;
+					entries +=
+						_count_ones(in->cons_bitmask[i][j]);
+				}
+			}
+			if (!has_cons) {
+				IPAHAL_ERR("no cons bitmask for prod %d\n", i);
+				return NULL;
+			}
+		}
+	}
+	IPAHAL_DBG_LOW("sum all entries = %d\n", entries);
+
+	pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) +
+		hdr_entries *
+		sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) +
+		entries * sizeof(struct ipahal_stats_tethering_hw),
+		is_atomic_ctx);
+	if (!pyld)
+		return NULL;
+
+	pyld->len = hdr_entries *
+		sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw) +
+		entries * sizeof(struct ipahal_stats_tethering_hw);
+
+	pyld_ptr = pyld->data;
+
+	/*
+	 * Note that the address of the offset in the RAM line is of RAM line
+	 *(8-byte address) and not like the address in the “BASE” register,
+	 * which is a byte address
+	 */
+	incremental_offset =
+		(hdr_entries *
+			sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw))
+		/ 8;
+
+	reg_idx = 0;
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		if (in->prod_bitmask[reg_idx] & ipahal_get_ep_bit(i)) {
+			struct ipahal_stats_tethering_hdr_v5_0_hw *hdr =
+				pyld_ptr;
+
+			if (i > 0 && !(i % IPAHAL_MAX_PIPES_PER_REG)) {
+				reg_idx++;
+			}
+			hdr->dst_mask1 = in->cons_bitmask[i][0];
+			hdr->dst_mask1 = in->cons_bitmask[i][1];
+			hdr->offset = incremental_offset;
+			IPAHAL_DBG_LOW("hdr->dst_mask=0x[%X][%X]\n",
+				hdr->dst_mask1, hdr->dst_mask2);
+			IPAHAL_DBG_LOW("hdr->offset=0x%x\n", hdr->offset);
+			/* add the stats entry */
+			incremental_offset +=
+				(_count_ones(in->cons_bitmask[i][0]) +
+				_count_ones(in->cons_bitmask[i][1])) *
 				sizeof(struct ipahal_stats_tethering_hw) / 8;
 			pyld_ptr += sizeof(*hdr);
 		}
@@ -158,25 +324,65 @@ static int ipahal_get_offset_tethering(void *params,
 	int entries = 0;
 	int i;
 
-	for (i = 0; i < sizeof(in->init.prod_bitmask) * 8; i++) {
-		if (in->init.prod_bitmask & (1 << i)) {
-			if (in->init.cons_bitmask[i] == 0) {
+	for (i = 0; i < sizeof(in->init.prod_bitmask[0]) * 8; i++) {
+		if (in->init.prod_bitmask[0] & (1 << i)) {
+			if (in->init.cons_bitmask[i][0] == 0) {
 				IPAHAL_ERR("no cons bitmask for prod %d\n", i);
 				return -EPERM;
 			}
-			entries += _count_ones(in->init.cons_bitmask[i]);
+			entries += _count_ones(in->init.cons_bitmask[i][0]);
 		}
 	}
 	IPAHAL_DBG_LOW("sum all entries = %d\n", entries);
 
 	/* skip the header */
-	out->offset = _count_ones(in->init.prod_bitmask) *
+	out->offset = _count_ones(in->init.prod_bitmask[0]) *
 		sizeof(struct ipahal_stats_tethering_hdr_hw);
 	out->size = entries * sizeof(struct ipahal_stats_tethering_hw);
 
 	return 0;
 }
 
+static int ipahal_get_offset_tethering_v5_0(void *params,
+	struct ipahal_stats_offset *out)
+{
+	struct ipahal_stats_get_offset_tethering *in =
+		(struct ipahal_stats_get_offset_tethering *)params;
+	int entries = 0;
+	int i, j, reg_idx;
+
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		reg_idx = ipahal_get_ep_reg_idx(i);
+
+		if (in->init.prod_bitmask[reg_idx] & ipahal_get_ep_bit(i)) {
+			bool has_cons = false;
+
+			for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++) {
+				if (in->init.cons_bitmask[i][j]) {
+					has_cons = true;
+					entries +=_count_ones(
+						in->init.cons_bitmask[i][j]);
+				}
+			}
+			if (!has_cons) {
+				IPAHAL_ERR("no cons bitmask for prod %d\n", i);
+				return -EPERM;
+			}
+		}
+	}
+	IPAHAL_DBG_LOW("sum all entries = %d\n", entries);
+
+	/* skip the header */
+	out->offset = 0;
+	for (j = 0; j < IPAHAL_IPA5_PIPE_REG_NUM; j++)
+		out->offset += _count_ones(in->init.prod_bitmask[j]) *
+		sizeof(struct ipahal_stats_tethering_hdr_v5_0_hw);
+
+	out->size = entries * sizeof(struct ipahal_stats_tethering_hw);
+
+	return 0;
+}
+
 static int ipahal_parse_stats_tethering(void *init_params, void *raw_stats,
 	void *parsed_stats)
 {
@@ -193,8 +399,57 @@ static int ipahal_parse_stats_tethering(void *init_params, void *raw_stats,
 	IPAHAL_DBG_LOW("\n");
 	for (i = 0; i < IPAHAL_MAX_PIPES; i++) {
 		for (j = 0; j < IPAHAL_MAX_PIPES; j++) {
-			if ((init->prod_bitmask & (1 << i)) &&
-			    init->cons_bitmask[i] & (1 << j)) {
+			if ((init->prod_bitmask[0] & (1 << i)) &&
+			    init->cons_bitmask[i][0] & (1 << j)) {
+				IPAHAL_DBG_LOW("prod %d cons %d\n", i, j);
+				IPAHAL_DBG_LOW("stat_idx %d\n", stat_idx);
+				out->stats[i][j].num_ipv4_bytes =
+					raw_hw[stat_idx].num_ipv4_bytes;
+				IPAHAL_DBG_LOW("num_ipv4_bytes %lld\n",
+					out->stats[i][j].num_ipv4_bytes);
+				out->stats[i][j].num_ipv4_pkts =
+					raw_hw[stat_idx].num_ipv4_pkts;
+				IPAHAL_DBG_LOW("num_ipv4_pkts %lld\n",
+					out->stats[i][j].num_ipv4_pkts);
+				out->stats[i][j].num_ipv6_pkts =
+					raw_hw[stat_idx].num_ipv6_pkts;
+				IPAHAL_DBG_LOW("num_ipv6_pkts %lld\n",
+					out->stats[i][j].num_ipv6_pkts);
+				out->stats[i][j].num_ipv6_bytes =
+					raw_hw[stat_idx].num_ipv6_bytes;
+				IPAHAL_DBG_LOW("num_ipv6_bytes %lld\n",
+					out->stats[i][j].num_ipv6_bytes);
+				stat_idx++;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int ipahal_parse_stats_tethering_v5_0(void *init_params, void *raw_stats,
+	void *parsed_stats)
+{
+	struct ipahal_stats_init_tethering *init =
+		(struct ipahal_stats_init_tethering *)init_params;
+	struct ipahal_stats_tethering_hw *raw_hw =
+		(struct ipahal_stats_tethering_hw *)raw_stats;
+	struct ipahal_stats_tethering_all *out =
+		(struct ipahal_stats_tethering_all *)parsed_stats;
+	int i, j;
+	int stat_idx = 0;
+	int prod_idx, cons_idx;
+
+	memset(out, 0, sizeof(*out));
+	IPAHAL_DBG_LOW("\n");
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		prod_idx = ipahal_get_ep_reg_idx(i);
+		for (j = 0; j < IPAHAL_IPA5_PIPES_NUM; j++) {
+			cons_idx = ipahal_get_ep_reg_idx(j);
+			if ((init->prod_bitmask[prod_idx] &
+				ipahal_get_ep_bit(i)) &&
+				init->cons_bitmask[i][cons_idx] &
+				ipahal_get_ep_bit(j)) {
 				IPAHAL_DBG_LOW("prod %d cons %d\n", i, j);
 				IPAHAL_DBG_LOW("stat_idx %d\n", stat_idx);
 				out->stats[i][j].num_ipv4_bytes =
@@ -427,8 +682,30 @@ static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_drop(
 	struct ipahal_stats_init_pyld *pyld;
 	struct ipahal_stats_init_drop *in =
 		(struct ipahal_stats_init_drop *)params;
-	int entries = _count_ones(in->enabled_bitmask);
+	int entries = _count_ones(in->enabled_bitmask[0]);
+
+	IPAHAL_DBG_LOW("entries = %d\n", entries);
+	pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) +
+		entries * sizeof(struct ipahal_stats_drop_hw), is_atomic_ctx);
+	if (!pyld)
+		return NULL;
+
+	pyld->len = entries * sizeof(struct ipahal_stats_drop_hw);
+
+	return pyld;
+}
+
+static struct ipahal_stats_init_pyld *ipahal_generate_init_pyld_drop_v5_0(
+	void *params, bool is_atomic_ctx)
+{
+	struct ipahal_stats_init_pyld *pyld;
+	struct ipahal_stats_init_drop *in =
+		(struct ipahal_stats_init_drop *)params;
+	int entries = 0;
+	int i;
 
+	for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++)
+		entries += _count_ones(in->enabled_bitmask[i]);
 	IPAHAL_DBG_LOW("entries = %d\n", entries);
 	pyld = IPAHAL_MEM_ALLOC(sizeof(*pyld) +
 		entries * sizeof(struct ipahal_stats_drop_hw), is_atomic_ctx);
@@ -445,7 +722,7 @@ static int ipahal_get_offset_drop(void *params,
 {
 	struct ipahal_stats_get_offset_drop *in =
 		(struct ipahal_stats_get_offset_drop *)params;
-	int entries = _count_ones(in->init.enabled_bitmask);
+	int entries = _count_ones(in->init.enabled_bitmask[0]);
 
 	IPAHAL_DBG_LOW("\n");
 	out->offset = 0;
@@ -454,6 +731,24 @@ static int ipahal_get_offset_drop(void *params,
 	return 0;
 }
 
+static int ipahal_get_offset_drop_v5_0(void *params,
+	struct ipahal_stats_offset *out)
+{
+	struct ipahal_stats_get_offset_drop *in =
+		(struct ipahal_stats_get_offset_drop *)params;
+	int entries = 0;
+	int i;
+
+	for (i = 0; i < IPAHAL_IPA5_PIPE_REG_NUM; i++)
+		entries += _count_ones(in->init.enabled_bitmask[i]);
+	IPAHAL_DBG_LOW("entries %d\n", entries);
+
+	out->offset = 0;
+	out->size = entries * sizeof(struct ipahal_stats_drop_hw);
+
+	return 0;
+}
+
 static int ipahal_parse_stats_drop(void *init_params, void *raw_stats,
 	void *parsed_stats)
 {
@@ -469,7 +764,35 @@ static int ipahal_parse_stats_drop(void *init_params, void *raw_stats,
 	memset(out, 0, sizeof(*out));
 	IPAHAL_DBG_LOW("\n");
 	for (i = 0; i < IPAHAL_MAX_PIPES; i++) {
-		if (init->enabled_bitmask & (1 << i)) {
+		if (init->enabled_bitmask[0] & (1 << i)) {
+			out->stats[i].drop_byte_cnt =
+				raw_hw[stat_idx].drop_byte_cnt;
+			out->stats[i].drop_packet_cnt =
+				raw_hw[stat_idx].drop_packet_cnt;
+			stat_idx++;
+		}
+	}
+
+	return 0;
+}
+
+static int ipahal_parse_stats_drop_v5_0(void *init_params, void *raw_stats,
+	void *parsed_stats)
+{
+	struct ipahal_stats_init_drop *init =
+		(struct ipahal_stats_init_drop *)init_params;
+	struct ipahal_stats_drop_hw *raw_hw =
+		(struct ipahal_stats_drop_hw *)raw_stats;
+	struct ipahal_stats_drop_all *out =
+		(struct ipahal_stats_drop_all *)parsed_stats;
+	int stat_idx = 0;
+	int i, reg_idx;
+
+	memset(out, 0, sizeof(*out));
+	IPAHAL_DBG_LOW("\n");
+	for (i = 0; i < IPAHAL_IPA5_PIPES_NUM; i++) {
+		reg_idx = ipahal_get_ep_reg_idx(i);
+		if (init->enabled_bitmask[reg_idx] & ipahal_get_ep_bit(i)) {
 			out->stats[i].drop_byte_cnt =
 				raw_hw[stat_idx].drop_byte_cnt;
 			out->stats[i].drop_packet_cnt =
@@ -504,6 +827,8 @@ static struct ipahal_hw_stats_obj
 		ipahal_get_offset_drop,
 		ipahal_parse_stats_drop
 	},
+
+	/* IPAv4_5 */
 	[IPA_HW_v4_5][IPAHAL_HW_STATS_QUOTA] = {
 		ipahal_generate_init_pyld_quota,
 		ipahal_get_offset_quota,
@@ -524,6 +849,23 @@ static struct ipahal_hw_stats_obj
 		ipahal_get_offset_drop,
 		ipahal_parse_stats_drop
 	},
+
+	/* IPAv5_0 */
+	[IPA_HW_v5_0][IPAHAL_HW_STATS_TETHERING] = {
+	ipahal_generate_init_pyld_tethering_v5_0,
+	ipahal_get_offset_tethering_v5_0,
+	ipahal_parse_stats_tethering_v5_0
+	},
+	[IPA_HW_v5_0][IPAHAL_HW_STATS_QUOTA] = {
+	ipahal_generate_init_pyld_quota_v5_0,
+	ipahal_get_offset_quota_v5_0,
+	ipahal_parse_stats_quota_v5_0
+	},
+	[IPA_HW_v5_0][IPAHAL_HW_STATS_DROP] = {
+	ipahal_generate_init_pyld_drop_v5_0,
+	ipahal_get_offset_drop_v5_0,
+	ipahal_parse_stats_drop_v5_0
+	},
 };
 
 int ipahal_hw_stats_init(enum ipa_hw_type ipa_hw_type)

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats.h

@@ -9,6 +9,9 @@
 #include <linux/ipa.h>
 
 #define IPAHAL_MAX_PIPES 32
+#define IPAHAL_MAX_PIPES_PER_REG 32
+#define IPAHAL_IPA5_PIPES_NUM 36
+#define IPAHAL_IPA5_PIPE_REG_NUM 2
 #define IPAHAL_MAX_RULE_ID_32 (1024 / 32) /* 10 bits of rule id */
 
 enum ipahal_hw_stats_type {
@@ -45,7 +48,7 @@ struct ipahal_stats_offset {
  * @enabled_bitmask: bit mask of pipes to be monitored
  */
 struct ipahal_stats_init_quota {
-	u32 enabled_bitmask;
+	u32 enabled_bitmask[IPAHAL_IPA5_PIPE_REG_NUM];
 };
 
 /*
@@ -75,7 +78,7 @@ struct ipahal_stats_quota {
  * @stats: array of statistics per pipe
  */
 struct ipahal_stats_quota_all {
-	struct ipahal_stats_quota stats[IPAHAL_MAX_PIPES];
+	struct ipahal_stats_quota stats[IPAHAL_IPA5_PIPES_NUM];
 };
 
 /*
@@ -84,8 +87,8 @@ struct ipahal_stats_quota_all {
  * @cons_bitmask: bit mask of consumer pipes to be monitored per producer
  */
 struct ipahal_stats_init_tethering {
-	u32 prod_bitmask;
-	u32 cons_bitmask[IPAHAL_MAX_PIPES];
+	u32 prod_bitmask[IPAHAL_IPA5_PIPE_REG_NUM];
+	u32 cons_bitmask[IPAHAL_IPA5_PIPES_NUM][IPAHAL_IPA5_PIPE_REG_NUM];
 };
 
 /*
@@ -117,7 +120,7 @@ struct ipahal_stats_tethering {
  */
 struct ipahal_stats_tethering_all {
 	struct ipahal_stats_tethering
-		stats[IPAHAL_MAX_PIPES][IPAHAL_MAX_PIPES];
+		stats[IPAHAL_IPA5_PIPES_NUM][IPAHAL_IPA5_PIPES_NUM];
 };
 
 /*
@@ -178,7 +181,7 @@ struct ipahal_stats_get_offset_flt_rt_v4_5 {
  * @enabled_bitmask: bit mask of pipes to be monitored
  */
 struct ipahal_stats_init_drop {
-	u32 enabled_bitmask;
+	u32 enabled_bitmask[IPAHAL_IPA5_PIPE_REG_NUM];
 };
 
 /*
@@ -204,7 +207,7 @@ struct ipahal_stats_drop {
  * @stats: array of statistics per pipes
  */
 struct ipahal_stats_drop_all {
-	struct ipahal_stats_drop stats[IPAHAL_MAX_PIPES];
+	struct ipahal_stats_drop stats[IPAHAL_IPA5_PIPES_NUM];
 };
 
 /*

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_hw_stats_i.h

@@ -22,6 +22,13 @@ struct ipahal_stats_tethering_hdr_hw {
 	u64 offset:32;
 };
 
+struct ipahal_stats_tethering_hdr_v5_0_hw {
+	u64 dst_mask1;
+	u64 dst_mask2;
+	u64 offset : 32;
+	u64 reserved : 32;
+};
+
 struct ipahal_stats_tethering_hw {
 	u64 num_ipv4_bytes;
 	u64 num_ipv4_pkts:32;

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.c

@@ -152,6 +152,8 @@ static const char *ipareg_name_to_str[IPA_REG_MAX] = {
 	__stringify(IPA_SUSPEND_IRQ_INFO_EE_n_REG_k),
 	__stringify(IPA_SUSPEND_IRQ_CLR_EE_n_REG_k),
 	__stringify(IPA_SUSPEND_IRQ_EN_EE_n_REG_k),
+	__stringify(IPA_STAT_TETHERING_MASK_EE_n_REG_k),
+	__stringify(IPA_STAT_DROP_CNT_MASK_EE_n_REG_k),
 };
 
 static void ipareg_construct_dummy(enum ipahal_reg_name reg,
@@ -4096,6 +4098,9 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = {
 	[IPA_HW_v5_0][IPA_STAT_TETHERING_MASK_n] = {
 		ipareg_construct_dummy, ipareg_parse_dummy,
 		-1, 0x4, 0, 0, 0, 0},
+	[IPA_HW_v5_0][IPA_STAT_TETHERING_MASK_EE_n_REG_k] = {
+		ipareg_construct_dummy, ipareg_parse_dummy,
+		0x00000750, 0x4, 0, 0, 0, 0x8},
 	[IPA_HW_v5_0][IPA_STAT_FILTER_IPV4_BASE] = {
 		ipareg_construct_dummy, ipareg_parse_dummy,
 		0x00000700, 0, 0, 0, 0, 0},
@@ -4114,6 +4119,9 @@ static struct ipahal_reg_obj ipahal_reg_objs[IPA_HW_MAX][IPA_REG_MAX] = {
 	[IPA_HW_v5_0][IPA_STAT_DROP_CNT_MASK_n] = {
 		ipareg_construct_dummy, ipareg_parse_dummy,
 		-1, 0x4, 0, 0, 1, 0},
+	[IPA_HW_v5_0][IPA_STAT_DROP_CNT_MASK_EE_n_REG_k] = {
+		ipareg_construct_dummy, ipareg_parse_dummy,
+		0x00000790 , 0x4, 0, 0, 1, 0x8},
 	[IPA_HW_v5_0][IPA_ENDP_INIT_CTRL_n] = {
 		ipareg_construct_endp_init_ctrl_n_v4_0, ipareg_parse_dummy,
 		0x00001000, 0x80, 0, 30, 1, 0},
@@ -4659,9 +4667,9 @@ u32 ipahal_get_ep_reg_offset(enum ipahal_reg_name reg, u32 ep_num)
 /*
 * Get the offset of a ep n register according to ep index and n
 */
-u32 ipahal_get_ep_reg_n_offset(enum ipahal_reg_name reg, u32 n, u32 ep_num)
+u32 ipahal_get_reg_nk_offset(enum ipahal_reg_name reg, u32 n, u32 k)
 {
-	return ipahal_get_reg_mn_ofst(reg, IPA_BIT_MAP_CELL_NUM(ep_num), n);
+	return ipahal_get_reg_mn_ofst(reg, k, n);
 }
 
 u32 ipahal_get_reg_base(void)

drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_reg.h

@@ -149,6 +149,8 @@ enum ipahal_reg_name {
 	IPA_SUSPEND_IRQ_INFO_EE_n_REG_k,
 	IPA_SUSPEND_IRQ_CLR_EE_n_REG_k,
 	IPA_SUSPEND_IRQ_EN_EE_n_REG_k,
+	IPA_STAT_TETHERING_MASK_EE_n_REG_k,
+	IPA_STAT_DROP_CNT_MASK_EE_n_REG_k,
 	IPA_REG_MAX,
 };
 
@@ -803,21 +805,6 @@ static inline u32 ipahal_read_reg(enum ipahal_reg_name reg)
  */
 u32 ipahal_read_ep_reg(enum ipahal_reg_name reg, u32 ep_num);
 
-/*
- * ipahal_test_ep_bit() - return true if a ep bit is set
- */
-bool ipahal_test_ep_bit(u32 reg_val, u32 ep_num);
-
-/*
- * ipahal_get_ep_bit() - get ep bit set in the right offset
- */
-u32 ipahal_get_ep_bit(u32 ep_num);
-
-/*
- * ipahal_get_ep_reg_idx() - get ep reg index according to ep num
- */
-u32 ipahal_get_ep_reg_idx(u32 ep_num);
-
 /*
  * ipahal_write_reg() - Write to reg a raw value
  */
@@ -860,9 +847,9 @@ void ipahal_write_ep_reg_n(enum ipahal_reg_name reg, u32 n, u32 ep_num, u32 val)
 u32 ipahal_get_reg_mn_ofst(enum ipahal_reg_name reg, u32 m, u32 n);
 
 /*
-* Get the offset of a ep n register according to ep index and n
+* Get the offset of a n,k register
 */
-u32 ipahal_get_ep_reg_n_offset(enum ipahal_reg_name reg, u32 n, u32 ep_num);
+u32 ipahal_get_reg_nk_offset(enum ipahal_reg_name reg, u32 n, u32 l);
 
 /*
  * Get the offset of a n parameterized register