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soc: swr: update interval high register

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Update interval high register.

Change-Id: I7c56ba801545f14607796977a976e535cf9da6ca
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang
2020-04-01 14:44:47 +08:00
committed by Gerrit - the friendly Code Review server
parent 848466a9cc
commit 96262c74ed
2 changed files with 9 additions and 1 deletions
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8
soc/swr-mstr-ctrl.c
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@@ -1275,10 +1275,16 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK(mport->sinterval,
val[len++] = SWR_REG_VAL_PACK(mport->sinterval & 0xFF,
port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK((mport->sinterval >> 8)& 0xFF,
port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
bank));
/* Assumption: If different channels in the same port
* on master is enabled for different slaves, then each
* slave offset should be configured differently.