soc: swr: update interval high register

Update interval high register.

Change-Id: I7c56ba801545f14607796977a976e535cf9da6ca
Signed-off-by: Meng Wang <[email protected]>

soc/swr-mstr-ctrl.c

@@ -1275,10 +1275,16 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
 								bank));
 
 			reg[len] = SWRM_CMD_FIFO_WR_CMD;
-			val[len++] = SWR_REG_VAL_PACK(mport->sinterval,
+			val[len++] = SWR_REG_VAL_PACK(mport->sinterval & 0xFF,
 					port_req->dev_num, 0x00,
 					SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
 								bank));
+
+			reg[len] = SWRM_CMD_FIFO_WR_CMD;
+			val[len++] = SWR_REG_VAL_PACK((mport->sinterval >> 8)& 0xFF,
+					port_req->dev_num, 0x00,
+					SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
+								bank));
 			/* Assumption: If different channels in the same port
 			 * on master is enabled for different slaves, then each
 			 * slave offset should be configured differently.

soc/swrm_registers.h

@@ -232,6 +232,8 @@
 						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x122 + \
 						 SWRS_DP_REG_OFFSET(n, m))
+#define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x123 + \
+						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x124 + \
 						 SWRS_DP_REG_OFFSET(n, m))
 #define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m)	(SWRS_BASE_ADDRESS + 0x125 + \