fw-api: Add 6490 R52 HW header file changes

Add 6490 R52 HW header file changes.

Change-Id: Iceac787a5905823fb01eaf3531f187406424ef33
CRs-Fixed: 2513249

hw/qca6490/v1/HALcomdef.h

@@ -113,11 +113,12 @@ SIDE EFFECTS
   ** macroized to access memory directly
   */
 
-  #define inp(port)         (*((volatile dword *) (port)))
+  #define inp(port)         (*((volatile byte *) (port)))
+
   #define inpw(port)        (*((volatile word *) (port)))
   #define inpdw(port)       (*((volatile dword *)(port)))
 
-  #define outp(port, val)   (*((volatile dword *) (port)) = ((dword) (val)))
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
   #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
   #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
 

hw/qca6490/v1/wcss_seq_hwiobase.h

@@ -73,6 +73,19 @@
 #define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET                       0x004b0000
 #define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET                 0x00500000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET                     0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET             0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET  0x005cf000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET     0x005cf400
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET     0x005c0000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET      0x005c0200
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x005c5000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET         0x005d1000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x005c7000
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005cb000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET             0x005d4000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET         0x005d4000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET    0x005d4240
@@ -106,6 +119,7 @@
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00
+#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET    0x005da000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET              0x005dc000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET       0x005dc000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800
@@ -165,7 +179,6 @@
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400
-#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET     0x005f2500
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x005f25c0
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x005f26c0
@@ -177,9 +190,7 @@
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x005f28c0
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x005f2900
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x005f299c
-#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET  0x005f2c00
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000
-#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_MEM_OFFSET    0x005f6000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400
 #define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x005f8800
@@ -220,6 +231,19 @@
 #define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET                    0x00780000
 #define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET                     0x007b0000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_OFFSET                     0x007c0000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET             0x007c0000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET  0x007cf000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET     0x007cf400
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x007cf800
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x007cfc00
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET     0x007c0000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET      0x007c0200
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x007c5000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET         0x007d1000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x007c7000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x007c9b00
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x007c7000
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x007cb000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET             0x007d4000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET         0x007d4000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET    0x007d4240
@@ -253,6 +277,7 @@
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x007d71c0
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x007d7280
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x007d7c00
+#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET    0x007da000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET              0x007dc000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET       0x007dc000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x007de800
@@ -312,7 +337,6 @@
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400
-#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET     0x007f2500
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x007f25c0
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x007f26c0
@@ -324,9 +348,7 @@
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x007f28c0
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x007f2900
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x007f299c
-#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET  0x007f2c00
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000
-#define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_MEM_OFFSET    0x007f6000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400
 #define SEQ_WCSS_PHYB_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x007f8800
@@ -508,6 +530,19 @@
 #define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x001b0000
 #define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET                  0x00200000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET                      0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET              0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET   0x002cf000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET      0x002cf400
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET  0x002cfc00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET      0x002c0000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET       0x002c0200
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x002c5000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET          0x002d1000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x002c7000
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x002cb000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET              0x002d4000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET          0x002d4000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET     0x002d4240
@@ -541,6 +576,7 @@
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x002d71c0
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x002d7280
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00
+#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET     0x002da000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET               0x002dc000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET        0x002dc000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002de800
@@ -600,7 +636,6 @@
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x002f1300
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x002f2000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x002f2400
-#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET      0x002f2500
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x002f2580
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x002f25c0
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x002f26c0
@@ -612,9 +647,7 @@
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x002f28c0
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x002f2900
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x002f299c
-#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET   0x002f2c00
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x002f4000
-#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_MEM_OFFSET     0x002f6000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET  0x002f8000
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x002f8400
 #define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x002f8800
@@ -640,6 +673,19 @@
 // Instance Relative Offsets from Block rfa_from_wsi
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
+#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET                              0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET                   0x0000f000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET                      0x0000f400
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET              0x0000f800
+#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET                  0x0000fc00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET                      0x00000000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TRC_OFFSET                       0x00000200
+#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_LTE_REG_OFFSET              0x00005000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET                          0x00011000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET          0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000
+#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET                              0x00014000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET                          0x00014000
 #define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET                     0x00014240
@@ -673,6 +719,7 @@
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET                 0x000171c0
 #define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET                 0x00017280
 #define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET               0x00017c00
+#define SEQ_RFA_FROM_WSI_RFA_CMN_PMU_TEST_OFFSET                     0x0001a000
 #define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET                               0x0001c000
 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET                        0x0001c000
 #define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET          0x0001e800
@@ -732,7 +779,6 @@
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET                0x00031300
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET                 0x00032000
 #define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET               0x00032400
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_OFFSET                      0x00032500
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET                 0x00032580
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET  0x000325c0
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET            0x000326c0
@@ -744,9 +790,7 @@
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET  0x000328c0
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET     0x00032900
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET        0x0003299c
-#define SEQ_RFA_FROM_WSI_RFA_WL_WL_CAL_CORE_OFFSET                   0x00032c00
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET                 0x00034000
-#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_MEM_OFFSET                     0x00036000
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET                  0x00038000
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET                0x00038400
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_5G_CH1_OFFSET                0x00038800
@@ -768,6 +812,33 @@
 #define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET                 0x0003c000
 
 
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_soc
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET                                0x0000f000
+#define SEQ_RFA_SOC_AO_TLMM_OFFSET                                   0x0000f400
+#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET                           0x0000f800
+#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET                               0x0000fc00
+#define SEQ_RFA_SOC_HZ_TLMM_OFFSET                                   0x00000000
+#define SEQ_RFA_SOC_HZ_TRC_OFFSET                                    0x00000200
+#define SEQ_RFA_SOC_HZ_COEX_LTE_REG_OFFSET                           0x00005000
+#define SEQ_RFA_SOC_PMU_OFFSET                                       0x00011000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET                       0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET    0x00007000
+#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET   0x0000b000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block security_control_bt
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET      0x00002b00
+#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET            0x00000000
+#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET           0x00004000
+
+
 ///////////////////////////////////////////////////////////////////////////////////////////////
 // Instance Relative Offsets from Block rfa_cmn
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -804,6 +875,7 @@
 #define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET                              0x000031c0
 #define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET                              0x00003280
 #define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET                            0x00003c00
+#define SEQ_RFA_CMN_PMU_TEST_OFFSET                                  0x00006000
 
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -873,7 +945,6 @@
 #define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET                             0x00011300
 #define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET                              0x00012000
 #define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET                            0x00012400
-#define SEQ_RFA_WL_RBIST_RX_OFFSET                                   0x00012500
 #define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET                              0x00012580
 #define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET               0x000125c0
 #define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET                         0x000126c0
@@ -885,9 +956,7 @@
 #define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET               0x000128c0
 #define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET                  0x00012900
 #define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET                     0x0001299c
-#define SEQ_RFA_WL_WL_CAL_CORE_OFFSET                                0x00012c00
 #define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET                              0x00014000
-#define SEQ_RFA_WL_RBIST_MEM_OFFSET                                  0x00016000
 #define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET                               0x00018000
 #define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET                             0x00018400
 #define SEQ_RFA_WL_WL_TXBB_5G_CH1_OFFSET                             0x00018800
@@ -933,6 +1002,19 @@
 #define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET                   0x00180000
 #define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET                    0x001b0000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_OFFSET                    0x001c0000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET            0x001c0000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x001cf000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET    0x001cf400
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x001cf800
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x001cfc00
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET    0x001c0000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET     0x001c0200
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x001c5000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET        0x001d1000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x001c7000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x001c9b00
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x001c7000
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001cb000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET            0x001d4000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET        0x001d4000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET   0x001d4240
@@ -966,6 +1048,7 @@
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00
+#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_CMN_PMU_TEST_OFFSET   0x001da000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET             0x001dc000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET      0x001dc000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800
@@ -1025,7 +1108,6 @@
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400
-#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET    0x001f2500
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0
@@ -1037,9 +1119,7 @@
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c
-#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x001f2c00
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000
-#define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_MEM_OFFSET   0x001f6000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
 #define SEQ_WFAX_TOP_B_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_5G_CH1_OFFSET 0x001f8800

hw/qca6490/v1/wcss_version.h

@@ -16,4 +16,4 @@
  * PERFORMANCE OF THIS SOFTWARE.
  */
 
-#define WCSS_VERSION 1050
+#define WCSS_VERSION 1052