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qcacmn: hal API changes for wcn6450

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Add generic HAL APIs changes for Rhine architecture under
hal/wifi3.0/rh/ which are generic across Rhine chipsets.

Add wcn6450 specific HAL API changes under hal/wifi3.0/wcn6450.

Change-Id: I0964e0f610faa402c00fb68e4c6e901a92f6d7a7
CRs-Fixed: 3383304
This commit is contained in:
Venkateswara Naralasetty
2022-12-28 21:21:04 +05:30
committed by Madan Koyyalamudi
parent bd07dadb15
commit 87fdda9166
9 changed files with 6620 additions and 0 deletions
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10
hal/wifi3.0/hal_generic_api.h
View File

@@ -589,6 +589,16 @@ static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc)
REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER); REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER);
#endif #endif
} }
#else
static inline
void hal_srng_src_hw_init_generic(struct hal_soc *hal,
struct hal_srng *srng, bool idle_check,
uint32_t idx) {}
static inline
void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
struct hal_srng *srng, bool idle_check,
uint32_t idx) {}
#endif #endif
#ifdef FEATURE_DIRECT_LINK #ifdef FEATURE_DIRECT_LINK

32
hal/wifi3.0/rh/hal_rh_api.h Normal file
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@@ -0,0 +1,32 @@
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_RH_API_H_
#define _HAL_RH_API_H_
#include "hal_internal.h"
/**
* hal_hw_txrx_default_ops_attach_rh(): Add default ops for RH chips
* @soc: hal_soc handle
*
* Return: None
*/
void hal_hw_txrx_default_ops_attach_rh(struct hal_soc *soc);
#endif /* _HAL_RH_API_H_ */

908
hal/wifi3.0/rh/hal_rh_generic_api.c Normal file
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@@ -0,0 +1,908 @@
/*
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_rh_api.h"
#include "hal_rx.h"
#include "hal_rh_rx.h"
#include "hal_tx.h"
#include <hal_api_mon.h>
static uint32_t hal_get_reo_qdesc_size_rh(uint32_t ba_window_size,
int tid)
{
return 0;
}
static uint16_t hal_get_rx_max_ba_window_rh(int tid)
{
return 0;
}
static void hal_set_link_desc_addr_rh(void *desc, uint32_t cookie,
qdf_dma_addr_t link_desc_paddr,
uint8_t bm_id)
{
}
static void hal_tx_init_data_ring_rh(hal_soc_handle_t hal_soc_hdl,
hal_ring_handle_t hal_ring_hdl)
{
}
static void hal_get_ba_aging_timeout_rh(hal_soc_handle_t hal_soc_hdl,
uint8_t ac, uint32_t *value)
{
}
static void hal_set_ba_aging_timeout_rh(hal_soc_handle_t hal_soc_hdl,
uint8_t ac, uint32_t value)
{
}
static uint32_t hal_get_reo_reg_base_offset_rh(void)
{
return 0;
}
static void hal_rx_reo_buf_paddr_get_rh(hal_ring_desc_t rx_desc,
struct hal_buf_info *buf_info)
{
}
static void
hal_rx_msdu_link_desc_set_rh(hal_soc_handle_t hal_soc_hdl,
void *src_srng_desc,
hal_buff_addrinfo_t buf_addr_info,
uint8_t bm_action)
{
}
static
void hal_rx_buf_cookie_rbm_get_rh(uint32_t *buf_addr_info_hdl,
hal_buf_info_t buf_info_hdl)
{
}
static uint8_t hal_rx_ret_buf_manager_get_rh(hal_ring_desc_t ring_desc)
{
return 0;
}
static uint32_t hal_rx_get_reo_error_code_rh(hal_ring_desc_t rx_desc)
{
return 0;
}
static uint32_t
hal_gen_reo_remap_val_generic_rh(enum hal_reo_remap_reg remap_reg,
uint8_t *ix0_map)
{
return 0;
}
static void hal_rx_mpdu_desc_info_get_rh(void *desc_addr,
void *mpdu_desc_info_hdl)
{
}
static uint8_t hal_rx_err_status_get_rh(hal_ring_desc_t rx_desc)
{
return 0;
}
static uint8_t hal_rx_reo_buf_type_get_rh(hal_ring_desc_t rx_desc)
{
return 0;
}
static uint32_t hal_rx_wbm_err_src_get_rh(hal_ring_desc_t ring_desc)
{
return 0;
}
static void
hal_rx_wbm_rel_buf_paddr_get_rh(hal_ring_desc_t rx_desc,
struct hal_buf_info *buf_info)
{
}
static int hal_reo_send_cmd_rh(hal_soc_handle_t hal_soc_hdl,
hal_ring_handle_t hal_ring_hdl,
enum hal_reo_cmd_type cmd,
void *params)
{
return 0;
}
static void
hal_reo_qdesc_setup_rh(hal_soc_handle_t hal_soc_hdl, int tid,
uint32_t ba_window_size,
uint32_t start_seq, void *hw_qdesc_vaddr,
qdf_dma_addr_t hw_qdesc_paddr,
int pn_type, uint8_t vdev_stats_id)
{
}
static inline uint32_t
hal_rx_msdu_reo_dst_ind_get_rh(hal_soc_handle_t hal_soc_hdl,
void *msdu_link_desc)
{
return 0;
}
static inline void
hal_msdu_desc_info_set_rh(hal_soc_handle_t hal_soc_hdl,
void *msdu_desc, uint32_t dst_ind,
uint32_t nbuf_len)
{
}
static inline void
hal_mpdu_desc_info_set_rh(hal_soc_handle_t hal_soc_hdl, void *ent_desc,
void *mpdu_desc, uint32_t seq_no)
{
}
static QDF_STATUS hal_reo_status_update_rh(hal_soc_handle_t hal_soc_hdl,
hal_ring_desc_t reo_desc,
void *st_handle,
uint32_t tlv, int *num_ref)
{
return QDF_STATUS_SUCCESS;
}
static uint8_t hal_get_tlv_hdr_size_rh(void)
{
return sizeof(struct tlv_32_hdr);
}
static inline
uint8_t *hal_get_reo_ent_desc_qdesc_addr_rh(uint8_t *desc)
{
return 0;
}
static inline
void hal_set_reo_ent_desc_reo_dest_ind_rh(uint8_t *desc,
uint32_t dst_ind)
{
}
static uint64_t hal_rx_get_qdesc_addr_rh(uint8_t *dst_ring_desc,
uint8_t *buf)
{
return 0;
}
static uint8_t hal_get_idle_link_bm_id_rh(uint8_t chip_id)
{
return 0;
}
/*
* hal_rx_msdu_is_wlan_mcast_generic_rh(): Check if the buffer is for multicast
* address
* @nbuf: Network buffer
*
* Returns: flag to indicate whether the nbuf has MC/BC address
*/
static uint32_t hal_rx_msdu_is_wlan_mcast_generic_rh(qdf_nbuf_t nbuf)
{
uint8_t *buf = qdf_nbuf_data(nbuf);
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
return rx_attn->mcast_bcast;
}
/**
* hal_rx_tlv_decap_format_get_rh() - Get packet decap format from the TLV
* @hw_desc_addr: rx tlv desc
*
* Return: pkt decap format
*/
static uint32_t hal_rx_tlv_decap_format_get_rh(void *hw_desc_addr)
{
struct rx_msdu_start *rx_msdu_start;
struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
}
/**
* hal_rx_dump_pkt_tlvs_rh(): API to print all member elements of
* RX TLVs
* @hal_soc_hdl: HAL SOC handle
* @buf: pointer the pkt buffer
* @dbg_level: log level
*
* Return: void
*/
static void hal_rx_dump_pkt_tlvs_rh(hal_soc_handle_t hal_soc_hdl,
uint8_t *buf, uint8_t dbg_level)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
struct rx_mpdu_start *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
}
/**
* hal_rx_tlv_get_offload_info_rh() - Get the offload info from TLV
* @rx_tlv: RX tlv start address in buffer
* @offload_info: Buffer to store the offload info
*
* Return: 0 on success, -EINVAL on failure.
*/
static int
hal_rx_tlv_get_offload_info_rh(uint8_t *rx_tlv,
struct hal_offload_info *offload_info)
{
offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv);
offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv);
offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv);
offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv);
if (offload_info->tcp_proto) {
offload_info->tcp_pure_ack =
HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv);
offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv);
offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv);
offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv);
offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv);
}
return 0;
}
/*
* hal_rx_attn_phy_ppdu_id_get_rh(): get phy_ppdu_id value
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: phy_ppdu_id
*/
static uint16_t hal_rx_attn_phy_ppdu_id_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint16_t phy_ppdu_id;
phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
return phy_ppdu_id;
}
/**
* hal_rx_msdu_start_msdu_len_get_rh(): API to get the MSDU length
* from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
*
* Return: msdu length
*/
static uint32_t hal_rx_msdu_start_msdu_len_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t msdu_len;
msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
return msdu_len;
}
/**
* hal_rx_get_proto_params_rh() - Get l4 proto values from TLV
* @buf: rx tlv address
* @proto_params: Buffer to store proto parameters
*
* Return: 0 on success.
*/
static int hal_rx_get_proto_params_rh(uint8_t *buf, void *proto_params)
{
struct hal_proto_params *param =
(struct hal_proto_params *)proto_params;
param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf);
param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf);
param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf);
return 0;
}
/**
* hal_rx_get_l3_l4_offsets_rh() - Get l3/l4 header offset from TLV
* @buf: rx tlv start address
* @l3_hdr_offset: buffer to store l3 offset
* @l4_hdr_offset: buffer to store l4 offset
*
* Return: 0 on success.
*/
static int hal_rx_get_l3_l4_offsets_rh(uint8_t *buf, uint32_t *l3_hdr_offset,
uint32_t *l4_hdr_offset)
{
*l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf);
*l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf);
return 0;
}
/**
* hal_rx_tlv_get_pn_num_rh() - Get packet number from RX TLV
* @buf: rx tlv address
* @pn_num: buffer to store packet number
*
* Return: None
*/
static inline void hal_rx_tlv_get_pn_num_rh(uint8_t *buf, uint64_t *pn_num)
{
struct rx_pkt_tlvs *rx_pkt_tlv =
(struct rx_pkt_tlvs *)buf;
struct rx_mpdu_info *rx_mpdu_info_details =
&rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
pn_num[0] = rx_mpdu_info_details->pn_31_0;
pn_num[0] |=
((uint64_t)rx_mpdu_info_details->pn_63_32 << 32);
pn_num[1] = rx_mpdu_info_details->pn_95_64;
pn_num[1] |=
((uint64_t)rx_mpdu_info_details->pn_127_96 << 32);
}
#ifdef NO_RX_PKT_HDR_TLV
/**
* hal_rx_pkt_hdr_get_rh() - Get rx packet header start address.
* @buf: packet start address
*
* Return: packet data start address.
*/
static inline uint8_t *hal_rx_pkt_hdr_get_rh(uint8_t *buf)
{
return buf + RX_PKT_TLVS_LEN;
}
#else
static inline uint8_t *hal_rx_pkt_hdr_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
}
#endif
/**
* hal_rx_priv_info_set_in_tlv_rh(): Save the private info to
* the reserved bytes of rx_tlv_hdr
* @buf: start of rx_tlv_hdr
* @priv_data: hal_wbm_err_desc_info structure
* @len: length of the private data
* Return: void
*/
static inline void
hal_rx_priv_info_set_in_tlv_rh(uint8_t *buf, uint8_t *priv_data,
uint32_t len)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
RX_PADDING0_BYTES : len;
qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len);
}
/**
* hal_rx_priv_info_get_from_tlv_rh(): retrieve the private data from
* the reserved bytes of rx_tlv_hdr.
* @buf: start of rx_tlv_hdr
* @priv_data: hal_wbm_err_desc_info structure
* @len: length of the private data
* Return: void
*/
static inline void
hal_rx_priv_info_get_from_tlv_rh(uint8_t *buf, uint8_t *priv_data,
uint32_t len)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
uint32_t copy_len = (len > RX_PADDING0_BYTES) ?
RX_PADDING0_BYTES : len;
qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len);
}
/**
* hal_rx_get_tlv_size_generic_rh() - Get rx packet tlv size
* @rx_pkt_tlv_size: TLV size for regular RX packets
* @rx_mon_pkt_tlv_size: TLV size for monitor mode packets
*
* Return: size of rx pkt tlv before the actual data
*/
static void hal_rx_get_tlv_size_generic_rh(uint16_t *rx_pkt_tlv_size,
uint16_t *rx_mon_pkt_tlv_size)
{
*rx_pkt_tlv_size = RX_PKT_TLVS_LEN;
*rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV;
}
/*
* hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
* rxdma ring entry.
* @rxdma_entry: descriptor entry
* @paddr: physical address of nbuf data pointer.
* @cookie: SW cookie used as a index to SW rx desc.
* @manager: who owns the nbuf (host, NSS, etc...).
*
*/
static void
hal_rxdma_buff_addr_info_set_rh(void *rxdma_entry, qdf_dma_addr_t paddr,
uint32_t cookie, uint8_t manager)
{
uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
}
/**
* hal_rx_tlv_csum_err_get_rh() - Get IP and tcp-udp checksum fail flag
* @rx_tlv_hdr: start address of rx_tlv_hdr
* @ip_csum_err: buffer to return ip_csum_fail flag
* @tcp_udp_csum_err: placeholder to return tcp-udp checksum fail flag
*
* Return: None
*/
static inline void
hal_rx_tlv_csum_err_get_rh(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err,
uint32_t *tcp_udp_csum_err)
{
*ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr);
*tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr);
}
static void
hal_rx_tlv_get_pkt_capture_flags_rh(uint8_t *rx_tlv_pkt_hdr,
struct hal_rx_pkt_capture_flags *flags)
{
struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr;
struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn;
struct rx_mpdu_start *mpdu_start =
&rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start;
struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end;
struct rx_msdu_start *msdu_start =
&rx_tlv_hdr->msdu_start_tlv.rx_msdu_start;
flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type;
flags->fcs_err = mpdu_end->fcs_err;
flags->fragment_flag = rx_attn->fragment_flag;
flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
flags->tsft = msdu_start->ppdu_start_timestamp;
}
static inline bool
hal_rx_mpdu_info_ampdu_flag_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_start *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
bool ampdu_flag;
ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
return ampdu_flag;
}
static
uint32_t hal_rx_tlv_mpdu_len_err_get_rh(void *hw_desc_addr)
{
struct rx_attention *rx_attn;
struct rx_mon_pkt_tlvs *rx_desc =
(struct rx_mon_pkt_tlvs *)hw_desc_addr;
rx_attn = &rx_desc->attn_tlv.rx_attn;
return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR);
}
static
uint32_t hal_rx_tlv_mpdu_fcs_err_get_rh(void *hw_desc_addr)
{
struct rx_attention *rx_attn;
struct rx_mon_pkt_tlvs *rx_desc =
(struct rx_mon_pkt_tlvs *)hw_desc_addr;
rx_attn = &rx_desc->attn_tlv.rx_attn;
return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR);
}
#ifdef NO_RX_PKT_HDR_TLV
static uint8_t *hal_rx_desc_get_80211_hdr_rh(void *hw_desc_addr)
{
uint8_t *rx_pkt_hdr;
struct rx_mon_pkt_tlvs *rx_desc =
(struct rx_mon_pkt_tlvs *)hw_desc_addr;
rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
return rx_pkt_hdr;
}
#else
static uint8_t *hal_rx_desc_get_80211_hdr_rh(void *hw_desc_addr)
{
uint8_t *rx_pkt_hdr;
struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
return rx_pkt_hdr;
}
#endif
static uint32_t hal_rx_hw_desc_mpdu_user_id_rh(void *hw_desc_addr)
{
struct rx_mon_pkt_tlvs *rx_desc =
(struct rx_mon_pkt_tlvs *)hw_desc_addr;
uint32_t user_id;
user_id = HAL_RX_GET_USER_TLV32_USERID(
&rx_desc->mpdu_start_tlv);
return user_id;
}
/**
* hal_rx_msdu_start_msdu_len_set_rh(): API to set the MSDU length
* from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* @len: msdu length
*
* Return: none
*/
static inline void
hal_rx_msdu_start_msdu_len_set_rh(uint8_t *buf, uint32_t len)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
void *wrd1;
wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
*(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
*(uint32_t *)wrd1 |= len;
}
/*
* hal_rx_tlv_bw_get_rh(): API to get the Bandwidth
* Interval from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(bw)
*/
static inline uint32_t hal_rx_tlv_bw_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t bw;
bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
return bw;
}
/*
* hal_rx_tlv_get_freq_rh(): API to get the frequency of operating channel
* from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(frequency)
*/
static inline uint32_t
hal_rx_tlv_get_freq_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t freq;
freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
return freq;
}
/**
* hal_rx_tlv_sgi_get_rh(): API to get the Short Guard
* Interval from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(sgi)
*/
static inline uint32_t
hal_rx_tlv_sgi_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t sgi;
sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
return sgi;
}
/**
* hal_rx_tlv_rate_mcs_get_rh(): API to get the MCS rate
* from rx_msdu_start TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(rate_mcs)
*/
static inline uint32_t
hal_rx_tlv_rate_mcs_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t rate_mcs;
rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
return rate_mcs;
}
/*
* hal_rx_tlv_get_pkt_type_rh(): API to get the pkt type
* from rx_msdu_start
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(pkt type)
*/
static inline uint32_t hal_rx_tlv_get_pkt_type_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_start *msdu_start =
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
uint32_t pkt_type;
pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
return pkt_type;
}
/**
* hal_rx_tlv_mic_err_get_rh(): API to get the MIC ERR
* from rx_mpdu_end TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(mic_err)
*/
static inline uint32_t
hal_rx_tlv_mic_err_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_end *mpdu_end =
&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
uint32_t mic_err;
mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
return mic_err;
}
/**
* hal_rx_tlv_decrypt_err_get_rh(): API to get the Decrypt ERR
* from rx_mpdu_end TLV
*
* @buf: pointer to the start of RX PKT TLV headers
* Return: uint32_t(decrypt_err)
*/
static inline uint32_t
hal_rx_tlv_decrypt_err_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_end *mpdu_end =
&pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
uint32_t decrypt_err;
decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
return decrypt_err;
}
/*
* hal_rx_tlv_first_mpdu_get_rh(): get fist_mpdu bit from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* reutm: uint32_t(first_msdu)
*/
static inline uint32_t
hal_rx_tlv_first_mpdu_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint32_t first_mpdu;
first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
return first_mpdu;
}
/*
* hal_rx_msdu_get_keyid_rh(): API to get the key id if the decrypted packet
* from rx_msdu_end
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(key id)
*/
static inline uint8_t
hal_rx_msdu_get_keyid_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
uint32_t keyid_octet;
keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
return keyid_octet & 0x3;
}
/*
* hal_rx_tlv_get_is_decrypted_rh(): API to get the decrypt status of the
* packet from rx_attention
*
* @buf: pointer to the start of RX PKT TLV header
* Return: uint32_t(decryt status)
*/
static inline uint32_t
hal_rx_tlv_get_is_decrypted_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint32_t is_decrypt = 0;
uint32_t decrypt_status;
decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
if (!decrypt_status)
is_decrypt = 1;
return is_decrypt;
}
/**
* hal_hw_txrx_default_ops_attach_rh() - Attach the default hal ops for
* Rh arch chipsets.
* @hal_soc: HAL soc handle
*
* Return: None
*/
void hal_hw_txrx_default_ops_attach_rh(struct hal_soc *hal_soc)
{
hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_rh;
hal_soc->ops->hal_get_rx_max_ba_window =
hal_get_rx_max_ba_window_rh;
hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_rh;
hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_rh;
hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_rh;
hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_rh;
hal_soc->ops->hal_get_reo_reg_base_offset =
hal_get_reo_reg_base_offset_rh;
hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_rh;
hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
hal_rx_msdu_is_wlan_mcast_generic_rh;
hal_soc->ops->hal_rx_tlv_decap_format_get =
hal_rx_tlv_decap_format_get_rh;
hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_rh;
hal_soc->ops->hal_rx_tlv_get_offload_info =
hal_rx_tlv_get_offload_info_rh;
hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
hal_rx_attn_phy_ppdu_id_get_rh;
hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_rh;
hal_soc->ops->hal_rx_tlv_msdu_len_get =
hal_rx_msdu_start_msdu_len_get_rh;
hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_rh;
hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_rh;
hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_rh;
hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_rh;
hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_rh;
hal_soc->ops->hal_rx_ret_buf_manager_get =
hal_rx_ret_buf_manager_get_rh;
hal_soc->ops->hal_rxdma_buff_addr_info_set =
hal_rxdma_buff_addr_info_set_rh;
hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_rh;
hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_rh;
hal_soc->ops->hal_gen_reo_remap_val =
hal_gen_reo_remap_val_generic_rh;
hal_soc->ops->hal_rx_tlv_csum_err_get =
hal_rx_tlv_csum_err_get_rh;
hal_soc->ops->hal_rx_mpdu_desc_info_get =
hal_rx_mpdu_desc_info_get_rh;
hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_rh;
hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_rh;
hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_rh;
hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_rh;
hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get =
hal_rx_wbm_rel_buf_paddr_get_rh;
hal_soc->ops->hal_rx_priv_info_set_in_tlv =
hal_rx_priv_info_set_in_tlv_rh;
hal_soc->ops->hal_rx_priv_info_get_from_tlv =
hal_rx_priv_info_get_from_tlv_rh;
hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
hal_rx_mpdu_info_ampdu_flag_get_rh;
hal_soc->ops->hal_rx_tlv_mpdu_len_err_get =
hal_rx_tlv_mpdu_len_err_get_rh;
hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get =
hal_rx_tlv_mpdu_fcs_err_get_rh;
hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_rh;
hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
hal_rx_tlv_get_pkt_capture_flags_rh;
hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_rh;
hal_soc->ops->hal_rx_hw_desc_mpdu_user_id =
hal_rx_hw_desc_mpdu_user_id_rh;
hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_rh;
hal_soc->ops->hal_rx_tlv_msdu_len_set =
hal_rx_msdu_start_msdu_len_set_rh;
hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_rh;
hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_rh;
hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_rh;
hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_rh;
hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_rh;
hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_rh;
hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_rh;
hal_soc->ops->hal_rx_tlv_decrypt_err_get =
hal_rx_tlv_decrypt_err_get_rh;
hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_rh;
hal_soc->ops->hal_rx_tlv_get_is_decrypted =
hal_rx_tlv_get_is_decrypted_rh;
hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_rh;
hal_soc->ops->hal_rx_msdu_reo_dst_ind_get =
hal_rx_msdu_reo_dst_ind_get_rh;
hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_rh;
hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_rh;
hal_soc->ops->hal_reo_status_update = hal_reo_status_update_rh;
hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_rh;
hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
hal_get_reo_ent_desc_qdesc_addr_rh;
hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_rh;
hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind =
hal_set_reo_ent_desc_reo_dest_ind_rh;
hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_rh;
}

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hal/wifi3.0/rh/hal_rh_generic_api.h Normal file
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/*
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_RH_RX_H_
#define _HAL_RH_RX_H_
#include <hal_rx.h>
/*
* macro to set the cookie into the rxdma ring entry
*/
#define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
((*(((unsigned int *)buff_addr_info) + \
(BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
((*(((unsigned int *)buff_addr_info) + \
(BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
/*
* macro to set the manager into the rxdma ring entry
*/
#define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
((*(((unsigned int *)buff_addr_info) + \
(BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
((*(((unsigned int *)buff_addr_info) + \
(BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
/*
* NOTE: None of the following _GET macros need a right
* shift by the corresponding _LSB. This is because, they are
* finally taken and "OR'ed" into a single word again.
*/
#define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
#define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
#define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
#define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
#define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
#define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
/*
* Structures & Macros to obtain fields from the TLV's in the Rx packet
* pre-header.
*/
/*
* Every Rx packet starts at an offset from the top of the buffer.
* If the host hasn't subscribed to any specific TLV, there is
* still space reserved for the following TLV's from the start of
* the buffer:
* -- RX ATTENTION
* -- RX MPDU START
* -- RX MSDU START
* -- RX MSDU END
* -- RX MPDU END
* -- RX PACKET HEADER (802.11)
* If the host subscribes to any of the TLV's above, that TLV
* if populated by the HW
*/
#define NUM_DWORDS_TAG 1
/* By default the packet header TLV is 128 bytes */
#define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
#define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
(NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
#define RX_PKT_OFFSET_WORDS \
( \
NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
)
#define RX_PKT_OFFSET_BYTES \
(RX_PKT_OFFSET_WORDS << 2)
#define RX_PKT_HDR_TLV_LEN 120
/*
* Each RX descriptor TLV is preceded by 1 DWORD "tag"
*/
struct rx_attention_tlv {
uint32_t tag;
struct rx_attention rx_attn;
};
struct rx_mpdu_start_tlv {
uint32_t tag;
struct rx_mpdu_start rx_mpdu_start;
};
struct rx_msdu_start_tlv {
uint32_t tag;
struct rx_msdu_start rx_msdu_start;
};
struct rx_msdu_end_tlv {
uint32_t tag;
struct rx_msdu_end rx_msdu_end;
};
struct rx_mpdu_end_tlv {
uint32_t tag;
struct rx_mpdu_end rx_mpdu_end;
};
struct rx_pkt_hdr_tlv {
uint32_t tag; /* 4 B */
uint32_t phy_ppdu_id; /* 4 B */
char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
};
/* rx_pkt_tlvs structure should be used to process Data buffers, monitor status
* buffers, monitor destination buffers and monitor descriptor buffers.
*/
#ifdef RXDMA_OPTIMIZATION
/*
* The RX_PADDING_BYTES is required so that the TLV's don't
* spread across the 128 byte boundary
* RXDMA optimization requires:
* 1) MSDU_END & ATTENTION TLV's follow in that order
* 2) TLV's don't span across 128 byte lines
* 3) Rx Buffer is nicely aligned on the 128 byte boundary
*/
#define RX_PADDING0_BYTES 4
#define RX_PADDING1_BYTES 16
struct rx_pkt_tlvs {
struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
struct rx_attention_tlv attn_tlv; /* 16 bytes */
struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
#ifndef NO_RX_PKT_HDR_TLV
struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
#endif
};
#else /* RXDMA_OPTIMIZATION */
struct rx_pkt_tlvs {
struct rx_attention_tlv attn_tlv;
struct rx_mpdu_start_tlv mpdu_start_tlv;
struct rx_msdu_start_tlv msdu_start_tlv;
struct rx_msdu_end_tlv msdu_end_tlv;
struct rx_mpdu_end_tlv mpdu_end_tlv;
struct rx_pkt_hdr_tlv pkt_hdr_tlv;
};
#endif /* RXDMA_OPTIMIZATION */
/* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */
#ifdef RXDMA_OPTIMIZATION
struct rx_mon_pkt_tlvs {
struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
struct rx_attention_tlv attn_tlv; /* 16 bytes */
struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
};
#else /* RXDMA_OPTIMIZATION */
struct rx_mon_pkt_tlvs {
struct rx_attention_tlv attn_tlv;
struct rx_mpdu_start_tlv mpdu_start_tlv;
struct rx_msdu_start_tlv msdu_start_tlv;
struct rx_msdu_end_tlv msdu_end_tlv;
struct rx_mpdu_end_tlv mpdu_end_tlv;
struct rx_pkt_hdr_tlv pkt_hdr_tlv;
};
#endif
#define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs)
#define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs)
#define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV
#define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
#define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
RX_PKT_TLV_OFFSET(mpdu_start_tlv)
#define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
#define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
RX_PKT_TLV_OFFSET(msdu_start_tlv)
#define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
#define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
#define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
/**
* hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
*
* @rx_buf_start: Pointer to data buffer field
*
* Returns: pointer to rx_pkt_tlvs
*/
static inline
struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
{
return (struct rx_pkt_tlvs *)rx_buf_start;
}
/**
* hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
*
* @pkt_tlvs: Pointer to pkt_tlvs
* Returns: pointer to rx_mpdu_info structure
*/
static inline
struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
{
return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
}
/**
* hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info
* from the reserved bytes of rx_tlv_hdr.
* @buf: start of rx_tlv_hdr
* @buf_info: hal_rx_mon_dest_buf_info structure
*
* Return: void
*/
static inline void hal_rx_mon_dest_get_buffer_info_from_tlv(
uint8_t *buf,
struct hal_rx_mon_dest_buf_info *buf_info)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0,
sizeof(struct hal_rx_mon_dest_buf_info));
}
/*
* Get msdu_done bit from the RX_ATTENTION TLV
*/
#define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
RX_ATTENTION_2_MSDU_DONE_MASK, \
RX_ATTENTION_2_MSDU_DONE_LSB))
#define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
RX_ATTENTION_1_FIRST_MPDU_MASK, \
RX_ATTENTION_1_FIRST_MPDU_LSB))
#define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
/*
* hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: tcp_udp_cksum_fail
*/
static inline bool
hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint8_t tcp_udp_cksum_fail;
tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
return !!tcp_udp_cksum_fail;
}
#define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
/*
* hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
* from rx attention
* @buf: pointer to rx_pkt_tlvs
*
* Return: ip_cksum_fail
*/
static inline bool
hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint8_t ip_cksum_fail;
ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
return !!ip_cksum_fail;
}
#define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
RX_ATTENTION_0_PHY_PPDU_ID_LSB))
#define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
RX_ATTENTION_1_CCE_MATCH_MASK, \
RX_ATTENTION_1_CCE_MATCH_LSB))
/*
* hal_rx_msdu_cce_match_get_rh(): get CCE match bit
* from rx attention
* @buf: pointer to rx_pkt_tlvs
* Return: CCE match value
*/
static inline bool
hal_rx_msdu_cce_match_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint8_t cce_match_val;
cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
return !!cce_match_val;
}
/*
* Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
*/
#define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
RX_MPDU_INFO_8_PEER_META_DATA_LSB))
static inline uint32_t
hal_rx_mpdu_peer_meta_data_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_mpdu_start *mpdu_start =
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
uint32_t peer_meta_data;
peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
return peer_meta_data;
}
#define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
/*
* LRO information needed from the TLVs
*/
#define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
#define HAL_RX_TLV_GET_TCP_ACK(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
#define HAL_RX_TLV_GET_TCP_SEQ(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
#define HAL_RX_TLV_GET_TCP_WIN(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
RX_MSDU_END_9_WINDOW_SIZE_MASK, \
RX_MSDU_END_9_WINDOW_SIZE_LSB))
#define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
#define HAL_RX_TLV_GET_TCP_PROTO(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
RX_MSDU_START_2_TCP_PROTO_MASK, \
RX_MSDU_START_2_TCP_PROTO_LSB))
#define HAL_RX_TLV_GET_UDP_PROTO(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_2_UDP_PROTO_OFFSET)), \
RX_MSDU_START_2_UDP_PROTO_MASK, \
RX_MSDU_START_2_UDP_PROTO_LSB))
#define HAL_RX_TLV_GET_IPV6(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
RX_MSDU_START_2_IPV6_PROTO_MASK, \
RX_MSDU_START_2_IPV6_PROTO_LSB))
#define HAL_RX_TLV_GET_IP_OFFSET(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
RX_MSDU_START_1_L3_OFFSET_MASK, \
RX_MSDU_START_1_L3_OFFSET_LSB))
#define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
RX_MSDU_START_1_L4_OFFSET_MASK, \
RX_MSDU_START_1_L4_OFFSET_LSB))
#define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_start_tlv.rx_msdu_start), \
RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
#define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
RX_MSDU_START_1_MSDU_LENGTH_MASK, \
RX_MSDU_START_1_MSDU_LENGTH_LSB))
#define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
#define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_SGI_OFFSET)), \
RX_MSDU_START_5_SGI_MASK, \
RX_MSDU_START_5_SGI_LSB))
#define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_RATE_MCS_OFFSET)), \
RX_MSDU_START_5_RATE_MCS_MASK, \
RX_MSDU_START_5_RATE_MCS_LSB))
#define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
/*
* Get key index from RX_MSDU_END
*/
#define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
RX_MSDU_END_2_KEY_ID_OCTET_LSB))
#define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
RX_MSDU_START_5_USER_RSSI_OFFSET)), \
RX_MSDU_START_5_USER_RSSI_MASK, \
RX_MSDU_START_5_USER_RSSI_LSB))
#define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
#define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
RX_MSDU_START_5_PKT_TYPE_MASK, \
RX_MSDU_START_5_PKT_TYPE_LSB))
#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
/*******************************************************************************
* RX ERROR APIS
******************************************************************************/
#define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
#define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
/**
* hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
* humman readable format.
* @rx_attn: pointer the rx_attention TLV in pkt.
* @dbg_level: log level.
*
* Return: void
*/
static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
uint8_t dbg_level)
{
hal_verbose_debug("rx_attention tlv (1/2) - "
"rxpcu_mpdu_filter_in_category: %x "
"sw_frame_group_id: %x "
"reserved_0: %x "
"phy_ppdu_id: %x "
"first_mpdu : %x "
"reserved_1a: %x "
"mcast_bcast: %x "
"ast_index_not_found: %x "
"ast_index_timeout: %x "
"power_mgmt: %x "
"non_qos: %x "
"null_data: %x "
"mgmt_type: %x "
"ctrl_type: %x "
"more_data: %x "
"eosp: %x "
"a_msdu_error: %x "
"fragment_flag: %x "
"order: %x "
"cce_match: %x "
"overflow_err: %x "
"msdu_length_err: %x "
"tcp_udp_chksum_fail: %x "
"ip_chksum_fail: %x "
"sa_idx_invalid: %x "
"da_idx_invalid: %x "
"reserved_1b: %x "
"rx_in_tx_decrypt_byp: %x ",
rx_attn->rxpcu_mpdu_filter_in_category,
rx_attn->sw_frame_group_id,
rx_attn->reserved_0,
rx_attn->phy_ppdu_id,
rx_attn->first_mpdu,
rx_attn->reserved_1a,
rx_attn->mcast_bcast,
rx_attn->ast_index_not_found,
rx_attn->ast_index_timeout,
rx_attn->power_mgmt,
rx_attn->non_qos,
rx_attn->null_data,
rx_attn->mgmt_type,
rx_attn->ctrl_type,
rx_attn->more_data,
rx_attn->eosp,
rx_attn->a_msdu_error,
rx_attn->fragment_flag,
rx_attn->order,
rx_attn->cce_match,
rx_attn->overflow_err,
rx_attn->msdu_length_err,
rx_attn->tcp_udp_chksum_fail,
rx_attn->ip_chksum_fail,
rx_attn->sa_idx_invalid,
rx_attn->da_idx_invalid,
rx_attn->reserved_1b,
rx_attn->rx_in_tx_decrypt_byp);
hal_verbose_debug("rx_attention tlv (2/2) - "
"encrypt_required: %x "
"directed: %x "
"buffer_fragment: %x "
"mpdu_length_err: %x "
"tkip_mic_err: %x "
"decrypt_err: %x "
"unencrypted_frame_err: %x "
"fcs_err: %x "
"flow_idx_timeout: %x "
"flow_idx_invalid: %x "
"wifi_parser_error: %x "
"amsdu_parser_error: %x "
"sa_idx_timeout: %x "
"da_idx_timeout: %x "
"msdu_limit_error: %x "
"da_is_valid: %x "
"da_is_mcbc: %x "
"sa_is_valid: %x "
"decrypt_status_code: %x "
"rx_bitmap_not_updated: %x "
"reserved_2: %x "
"msdu_done: %x ",
rx_attn->encrypt_required,
rx_attn->directed,
rx_attn->buffer_fragment,
rx_attn->mpdu_length_err,
rx_attn->tkip_mic_err,
rx_attn->decrypt_err,
rx_attn->unencrypted_frame_err,
rx_attn->fcs_err,
rx_attn->flow_idx_timeout,
rx_attn->flow_idx_invalid,
rx_attn->wifi_parser_error,
rx_attn->amsdu_parser_error,
rx_attn->sa_idx_timeout,
rx_attn->da_idx_timeout,
rx_attn->msdu_limit_error,
rx_attn->da_is_valid,
rx_attn->da_is_mcbc,
rx_attn->sa_is_valid,
rx_attn->decrypt_status_code,
rx_attn->rx_bitmap_not_updated,
rx_attn->reserved_2,
rx_attn->msdu_done);
}
/**
* hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
* human readable format.
* @mpdu_end: pointer the mpdu_end TLV in pkt.
* @dbg_level: log level.
*
* Return: void
*/
static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
uint8_t dbg_level)
{
hal_verbose_debug("rx_mpdu_end tlv - "
"rxpcu_mpdu_filter_in_category: %x "
"sw_frame_group_id: %x "
"phy_ppdu_id: %x "
"unsup_ktype_short_frame: %x "
"rx_in_tx_decrypt_byp: %x "
"overflow_err: %x "
"mpdu_length_err: %x "
"tkip_mic_err: %x "
"decrypt_err: %x "
"unencrypted_frame_err: %x "
"pn_fields_contain_valid_info: %x "
"fcs_err: %x "
"msdu_length_err: %x "
"rxdma0_destination_ring: %x "
"rxdma1_destination_ring: %x "
"decrypt_status_code: %x "
"rx_bitmap_not_updated: %x ",
mpdu_end->rxpcu_mpdu_filter_in_category,
mpdu_end->sw_frame_group_id,
mpdu_end->phy_ppdu_id,
mpdu_end->unsup_ktype_short_frame,
mpdu_end->rx_in_tx_decrypt_byp,
mpdu_end->overflow_err,
mpdu_end->mpdu_length_err,
mpdu_end->tkip_mic_err,
mpdu_end->decrypt_err,
mpdu_end->unencrypted_frame_err,
mpdu_end->pn_fields_contain_valid_info,
mpdu_end->fcs_err,
mpdu_end->msdu_length_err,
mpdu_end->rxdma0_destination_ring,
mpdu_end->rxdma1_destination_ring,
mpdu_end->decrypt_status_code,
mpdu_end->rx_bitmap_not_updated);
}
#ifdef NO_RX_PKT_HDR_TLV
static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
uint8_t dbg_level)
{
}
#else
/**
* hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
* @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
* @dbg_level: log level.
*
* Return: void
*/
static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
uint8_t dbg_level)
{
struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv"
"\n---------------\nphy_ppdu_id %d ",
pkt_hdr_tlv->phy_ppdu_id);
hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
}
#endif
#define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
/**
* hal_rx_attn_msdu_done_get_rh() - Get msdi done flag from RX TLV
* @buf: RX tlv address
*
* Return: msdu done flag
*/
static inline uint32_t hal_rx_attn_msdu_done_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
uint32_t msdu_done;
msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
return msdu_done;
}
#define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
(HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
/**
* hal_rx_msdu_flags_get_rh() - Get msdu flags from ring desc
* @msdu_desc_info_hdl: msdu desc info handle
*
* Return: msdu flags
*/
static inline
uint32_t hal_rx_msdu_flags_get_rh(rx_msdu_desc_info_t msdu_desc_info_hdl)
{
struct rx_msdu_desc_info *msdu_desc_info =
(struct rx_msdu_desc_info *)msdu_desc_info_hdl;
return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
}
#define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \
RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \
RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB))
/**
* hal_rx_attn_msdu_len_err_get_rh(): Get msdu_len_err value from
* rx attention tlvs
* @buf: pointer to rx pkt tlvs hdr
*
* Return: msdu_len_err value
*/
static inline uint32_t
hal_rx_attn_msdu_len_err_get_rh(uint8_t *buf)
{
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn);
}
#endif /* _HAL_RH_RX_H_ */

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/*
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_RH_TX_H_
#define _HAL_RH_TX_H_
/*---------------------------------------------------------------------------
* Function declarations and documentation
* ---------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------
* TCL Descriptor accessor APIs
* ---------------------------------------------------------------------------
*/
/**
* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
* @hal_soc_hdl: HAL SOC handle
* @desc: Handle to Tx Descriptor
* @paddr: Physical Address
* @pool_id: Return Buffer Manager ID
* @desc_id: Descriptor ID
* @type: 0 - Address points to a MSDU buffer
* 1 - Address points to MSDU extension descriptor
*
* Return: void
*/
static inline
void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc,
dma_addr_t paddr,
uint8_t pool_id, uint32_t desc_id,
uint8_t type)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id,
desc_id, type);
}
/**
* hal_tx_desc_set_lmac_id - Set the lmac_id value
* @hal_soc_hdl: HAL SOC handle
* @desc: Handle to Tx Descriptor
* @lmac_id: mac Id to ast matching
* b00 – mac 0
* b01 – mac 1
* b10 – mac 2
* b11 – all macs (legacy HK way)
*
* Return: void
*/
static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl,
void *desc, uint8_t lmac_id)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
}
/**
* hal_tx_desc_set_search_type - Set the search type value
* @hal_soc_hdl: HAL SOC handle
* @desc: Handle to Tx Descriptor
* @search_type: search type
* 0 – Normal search
* 1 – Index based address search
* 2 – Index based flow search
*
* Return: void
*/
static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl,
void *desc,
uint8_t search_type)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type);
}
/**
* hal_tx_desc_set_search_index - Set the search index value
* @hal_soc_hdl: HAL SOC handle
* @desc: Handle to Tx Descriptor
* @search_index: The index that will be used for index based address or
* flow search. The field is valid when 'search_type' is
* 1 0r 2
*
* Return: void
*/
static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl,
void *desc,
uint32_t search_index)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index);
}
/**
* hal_tx_desc_set_cache_set_num - Set the cache-set-num value
* @hal_soc_hdl: HAL SOC handle
* @desc: Handle to Tx Descriptor
* @cache_num: Cache set number that should be used to cache the index
* based search results, for address and flow search.
* This value should be equal to LSB four bits of the hash value
* of match data, in case of search index points to an entry
* which may be used in content based search also. The value can
* be anything when the entry pointed by search index will not be
* used for content based search.
*
* Return: void
*/
static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl,
void *desc,
uint8_t cache_num)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num);
}
/**
* hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
* @desc: Handle to Tx Descriptor
* @data_length: MSDU length in case of direct descriptor.
* Length of link extension descriptor in case of Link extension
* descriptor.Includes the length of Metadata
* Return: None
*/
static inline void hal_tx_desc_set_buf_length(void *desc,
uint16_t data_length)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |=
HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length);
}
/**
* hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor
* @desc: Handle to Tx Descriptor
* @offset: Packet offset from Metadata in case of direct buffer descriptor.
*
* Return: void
*/
static inline void hal_tx_desc_set_buf_offset(void *desc,
uint8_t offset)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |=
HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset);
}
/**
* hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor
* @desc: Handle to Tx Descriptor
* @encap_type: Encapsulation that HW will perform
*
* Return: void
*
*/
static inline void hal_tx_desc_set_encap_type(void *desc,
enum hal_tx_encap_type encap_type)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |=
HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type);
}
/**
* hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor
* @desc: Handle to Tx Descriptor
* @type: Encrypt Type
*
* Return: void
*/
static inline void hal_tx_desc_set_encrypt_type(void *desc,
enum hal_tx_encrypt_type type)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |=
HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type);
}
/**
* hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags
* @desc: Handle to Tx Descriptor
* @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable
*
* Return: void
*/
static inline void hal_tx_desc_set_addr_search_flags(void *desc,
uint8_t flags)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |=
HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1));
HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |=
HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1));
}
/**
* hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags
* Tx Descriptor for MSDU_buffer type
* @desc: Handle to Tx Descriptor
* @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits)
*
* Return: void
*/
static inline void hal_tx_desc_set_l4_checksum_en(void *desc,
uint8_t en)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
(HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) |
HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) |
HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) |
HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en));
}
/**
* hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in
* Tx Descriptor for MSDU_buffer type
* @desc: Handle to Tx Descriptor
* @en: ipv4 checksum enable flags
*
* Return: void
*/
static inline void hal_tx_desc_set_l3_checksum_en(void *desc,
uint8_t en)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |=
HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en);
}
/**
* hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor
* @desc:Handle to Tx Descriptor
* @metadata: Metadata to be sent to Firmware
*
* Return: void
*/
static inline void hal_tx_desc_set_fw_metadata(void *desc,
uint16_t metadata)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |=
HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata);
}
/**
* hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor.
* @desc:Handle to Tx Descriptor
* @to_fw: if set, Forward packet to FW along with classification result
*
* Return: void
*/
static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |=
HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw);
}
/**
* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
* @hal_soc_hdl: hal soc handle
* @desc: Handle to Tx Descriptor
* @en: For raw WiFi frames, this indicates transmission to a mesh STA,
* enabling the interpretation of the 'Mesh Control Present' bit
* (bit 8) of QoS Control (otherwise this bit is ignored),
* For native WiFi frames, this indicates that a 'Mesh Control' field
* is present between the header and the LLC.
*
* Return: void
*/
static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl,
void *desc, uint8_t en)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en);
}
/**
* hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in
* frame) to be used for Tx Frame
* @desc: Handle to Tx Descriptor
* @hlos_tid: HLOS TID
*
* Return: void
*/
static inline void hal_tx_desc_set_hlos_tid(void *desc,
uint8_t hlos_tid)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |=
HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid);
HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |=
HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1);
}
/**
* hal_tx_desc_clear - Clear the HW descriptor entry
* @hw_desc: Hardware descriptor to be cleared
*
* Return: void
*/
static inline void hal_tx_desc_clear(void *hw_desc)
{
qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr),
HAL_TX_DESC_LEN_BYTES, 0);
}
/**
* hal_tx_desc_sync - Commit the descriptor to Hardware
* @hal_tx_desc_cached: Cached descriptor that software maintains
* @hw_desc: Hardware descriptor to be updated
*/
static inline void hal_tx_desc_sync(void *hal_tx_desc_cached,
void *hw_desc)
{
qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)),
hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES);
}
#endif /* _HAL_RH_TX_H_ */

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hal/wifi3.0/wcn6450/hal_wcn6450.c
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hal/wifi3.0/wcn6450/hal_wcn6450_rx.h Normal file
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/*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_6450_RX_H_
#define _HAL_6450_RX_H_
#include "qdf_util.h"
#include "qdf_types.h"
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "tcl_data_cmd.h"
#include "phyrx_rssi_legacy.h"
#include "rx_msdu_start.h"
#include "tlv_tag_def.h"
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"
#include "phyrx_other_receive_info_ru_details.h"
#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \
RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB))
#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \
RX_MSDU_END_10_DA_IS_MCBC_MASK, \
RX_MSDU_END_10_DA_IS_MCBC_LSB))
#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \
RX_MSDU_END_10_SA_IS_VALID_MASK, \
RX_MSDU_END_10_SA_IS_VALID_LSB))
#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_11_SA_IDX_OFFSET)), \
RX_MSDU_END_11_SA_IDX_MASK, \
RX_MSDU_END_11_SA_IDX_LSB))
#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \
RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \
RX_MSDU_END_10_L3_HEADER_PADDING_LSB))
#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \
RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \
RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB))
#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_3_PN_31_0_OFFSET)), \
RX_MPDU_INFO_3_PN_31_0_MASK, \
RX_MPDU_INFO_3_PN_31_0_LSB))
#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_4_PN_63_32_OFFSET)), \
RX_MPDU_INFO_4_PN_63_32_MASK, \
RX_MPDU_INFO_4_PN_63_32_LSB))
#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_5_PN_95_64_OFFSET)), \
RX_MPDU_INFO_5_PN_95_64_MASK, \
RX_MPDU_INFO_5_PN_95_64_LSB))
#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_6_PN_127_96_OFFSET)), \
RX_MPDU_INFO_6_PN_127_96_MASK, \
RX_MPDU_INFO_6_PN_127_96_LSB))
#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \
RX_MSDU_END_10_FIRST_MSDU_MASK, \
RX_MSDU_END_10_FIRST_MSDU_LSB))
#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \
RX_MSDU_END_10_DA_IS_VALID_MASK, \
RX_MSDU_END_10_DA_IS_VALID_LSB))
#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_LAST_MSDU_OFFSET)), \
RX_MSDU_END_10_LAST_MSDU_MASK, \
RX_MSDU_END_10_LAST_MSDU_LSB))
#define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \
RX_MPDU_INFO_10_SW_PEER_ID_MASK, \
RX_MPDU_INFO_10_SW_PEER_ID_LSB))
#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_TO_DS_OFFSET)), \
RX_MPDU_INFO_11_TO_DS_MASK, \
RX_MPDU_INFO_11_TO_DS_LSB))
#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_FR_DS_OFFSET)), \
RX_MPDU_INFO_11_FR_DS_MASK, \
RX_MPDU_INFO_11_FR_DS_LSB))
#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \
RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \
RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB))
#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \
RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \
RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB))
#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \
RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \
RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB))
#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \
RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \
RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB))
#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \
RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \
RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB))
#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \
RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \
RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB))
#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \
RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \
RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB))
#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \
RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \
RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB))
#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \
RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \
RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB))
#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \
RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \
RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB))
#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \
RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB))
#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \
RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB))
#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \
RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \
RX_MSDU_END_14_SA_SW_PEER_ID_LSB))
#define HAL_RX_GET_FC_VALID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID)
#define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS)
#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID)
#define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID)
#define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY)
#define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID)
#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID)
#define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID)
#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
((struct rx_msdu_desc_info *) \
_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET))
#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
((struct rx_msdu_details *) \
_OFFSET_TO_BYTE_PTR((link_desc),\
RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
#define HAL_RX_MSDU_END_REO_DEST_IND_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET)), \
RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK, \
RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_12_FLOW_IDX_OFFSET)), \
RX_MSDU_END_12_FLOW_IDX_MASK, \
RX_MSDU_END_12_FLOW_IDX_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \
RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \
RX_MSDU_END_10_FLOW_IDX_INVALID_LSB))
#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \
RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB))
#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_13_FSE_METADATA_OFFSET)), \
RX_MSDU_END_13_FSE_METADATA_MASK, \
RX_MSDU_END_13_FSE_METADATA_LSB))
#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_14_CCE_METADATA_OFFSET)), \
RX_MSDU_END_14_CCE_METADATA_MASK, \
RX_MSDU_END_14_CCE_METADATA_LSB))
#define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \
RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \
RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB))
#define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \
(_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \
RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \
RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB))
#define HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET)), \
RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK, \
RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB))
#define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET)), \
RX_MSDU_END_15_AGGREGATION_COUNT_MASK, \
RX_MSDU_END_15_AGGREGATION_COUNT_LSB))
#define HAL_RX_TLV_GET_FISA_TIMEOUT(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_15_FISA_TIMEOUT_OFFSET)), \
RX_MSDU_END_15_FISA_TIMEOUT_MASK, \
RX_MSDU_END_15_FISA_TIMEOUT_LSB))
#define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET)), \
RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK, \
RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB))
#define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf) \
(_HAL_MS( \
(*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
msdu_end_tlv.rx_msdu_end), \
RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET)), \
RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK, \
RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB))
#if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
static inline
void hal_rx_get_bb_info_6450(void *rx_tlv,
void *ppdu_info_hdl)
{
struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
ppdu_info->cfr_info.bb_captured_channel =
HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL);
ppdu_info->cfr_info.bb_captured_timeout =
HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT);
ppdu_info->cfr_info.bb_captured_reason =
HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON);
}
static inline
void hal_rx_get_rtt_info_6450(void *rx_tlv,
void *ppdu_info_hdl)
{
struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
ppdu_info->cfr_info.rx_location_info_valid =
HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS,
RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID);
ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RTT_CHE_BUFFER_POINTER_LOW32);
ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RTT_CHE_BUFFER_POINTER_HIGH8);
ppdu_info->cfr_info.chan_capture_status =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RESERVED_8);
ppdu_info->cfr_info.rx_start_ts =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RX_START_TS);
ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RTT_CFO_MEASUREMENT);
ppdu_info->cfr_info.agc_gain_info0 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_1_RX_PKT_END_DETAILS,
PHY_TIMESTAMP_1_LOWER_32);
ppdu_info->cfr_info.agc_gain_info1 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_2_RX_PKT_END_DETAILS,
PHY_TIMESTAMP_1_UPPER_32);
ppdu_info->cfr_info.agc_gain_info2 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_3_RX_PKT_END_DETAILS,
PHY_TIMESTAMP_2_LOWER_32);
ppdu_info->cfr_info.agc_gain_info3 =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_4_RX_PKT_END_DETAILS,
PHY_TIMESTAMP_2_UPPER_32);
ppdu_info->cfr_info.mcs_rate =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RTT_MCS_RATE);
ppdu_info->cfr_info.gi_type =
HAL_RX_GET(rx_tlv,
PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS,
RTT_GI_TYPE);
}
#endif
#endif

66
hal/wifi3.0/wcn6450/hal_wcn6450_tx.h Normal file
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/*
* Copyright (c) 2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _HAL_6450_TX_H_
#define _HAL_6450_TX_H_
#include "tcl_data_cmd.h"
#include "phyrx_rssi_legacy.h"
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"
/**
* hal_tx_desc_set_lmac_id_6450 - Set the lmac_id value
* @desc: Handle to Tx Descriptor
* @lmac_id: mac Id to ast matching
* b00 – mac 0
* b01 – mac 1
* b10 – mac 2
* b11 – all macs (legacy HK way)
*
* Return: void
*/
static void hal_tx_desc_set_lmac_id_6450(void *desc, uint8_t lmac_id)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
}
/**
* hal_tx_desc_set_mesh_en_6450 - Set mesh_enable flag in Tx descriptor
* @desc: Handle to Tx Descriptor
* @en: For raw WiFi frames, this indicates transmission to a mesh STA,
* enabling the interpretation of the 'Mesh Control Present' bit
* (bit 8) of QoS Control (otherwise this bit is ignored),
* For native WiFi frames, this indicates that a 'Mesh Control' field
* is present between the header and the LLC.
*
* Return: void
*/
static inline
void hal_tx_desc_set_mesh_en_6450(void *desc, uint8_t en)
{
HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |=
HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en);
}
#endif