diff --git a/hal/wifi3.0/hal_generic_api.h b/hal/wifi3.0/hal_generic_api.h index 6e2a0c91f0..eec4249ecc 100644 --- a/hal/wifi3.0/hal_generic_api.h +++ b/hal/wifi3.0/hal_generic_api.h @@ -589,6 +589,16 @@ static inline void hal_srng_hw_reg_offset_init_generic(struct hal_soc *hal_soc) REG_OFFSET(SRC, CONSUMER_PREFETCH_TIMER); #endif } +#else +static inline +void hal_srng_src_hw_init_generic(struct hal_soc *hal, + struct hal_srng *srng, bool idle_check, + uint32_t idx) {} + +static inline +void hal_srng_dst_hw_init_generic(struct hal_soc *hal, + struct hal_srng *srng, bool idle_check, + uint32_t idx) {} #endif #ifdef FEATURE_DIRECT_LINK diff --git a/hal/wifi3.0/rh/hal_rh_api.h b/hal/wifi3.0/rh/hal_rh_api.h new file mode 100644 index 0000000000..7daaeeba58 --- /dev/null +++ b/hal/wifi3.0/rh/hal_rh_api.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_RH_API_H_ +#define _HAL_RH_API_H_ + +#include "hal_internal.h" + +/** + * hal_hw_txrx_default_ops_attach_rh(): Add default ops for RH chips + * @soc: hal_soc handle + * + * Return: None + */ +void hal_hw_txrx_default_ops_attach_rh(struct hal_soc *soc); + +#endif /* _HAL_RH_API_H_ */ diff --git a/hal/wifi3.0/rh/hal_rh_generic_api.c b/hal/wifi3.0/rh/hal_rh_generic_api.c new file mode 100644 index 0000000000..7789dbafc6 --- /dev/null +++ b/hal/wifi3.0/rh/hal_rh_generic_api.c @@ -0,0 +1,908 @@ +/* + * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#include "hal_rh_api.h" +#include "hal_rx.h" +#include "hal_rh_rx.h" +#include "hal_tx.h" +#include + +static uint32_t hal_get_reo_qdesc_size_rh(uint32_t ba_window_size, + int tid) +{ + return 0; +} + +static uint16_t hal_get_rx_max_ba_window_rh(int tid) +{ + return 0; +} + +static void hal_set_link_desc_addr_rh(void *desc, uint32_t cookie, + qdf_dma_addr_t link_desc_paddr, + uint8_t bm_id) +{ +} + +static void hal_tx_init_data_ring_rh(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl) +{ +} + +static void hal_get_ba_aging_timeout_rh(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t *value) +{ +} + +static void hal_set_ba_aging_timeout_rh(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t value) +{ +} + +static uint32_t hal_get_reo_reg_base_offset_rh(void) +{ + return 0; +} + +static void hal_rx_reo_buf_paddr_get_rh(hal_ring_desc_t rx_desc, + struct hal_buf_info *buf_info) +{ +} + +static void +hal_rx_msdu_link_desc_set_rh(hal_soc_handle_t hal_soc_hdl, + void *src_srng_desc, + hal_buff_addrinfo_t buf_addr_info, + uint8_t bm_action) +{ +} + +static +void hal_rx_buf_cookie_rbm_get_rh(uint32_t *buf_addr_info_hdl, + hal_buf_info_t buf_info_hdl) +{ +} + +static uint8_t hal_rx_ret_buf_manager_get_rh(hal_ring_desc_t ring_desc) +{ + return 0; +} + +static uint32_t hal_rx_get_reo_error_code_rh(hal_ring_desc_t rx_desc) +{ + return 0; +} + +static uint32_t +hal_gen_reo_remap_val_generic_rh(enum hal_reo_remap_reg remap_reg, + uint8_t *ix0_map) +{ + return 0; +} + +static void hal_rx_mpdu_desc_info_get_rh(void *desc_addr, + void *mpdu_desc_info_hdl) +{ +} + +static uint8_t hal_rx_err_status_get_rh(hal_ring_desc_t rx_desc) +{ + return 0; +} + +static uint8_t hal_rx_reo_buf_type_get_rh(hal_ring_desc_t rx_desc) +{ + return 0; +} + +static uint32_t hal_rx_wbm_err_src_get_rh(hal_ring_desc_t ring_desc) +{ + return 0; +} + +static void +hal_rx_wbm_rel_buf_paddr_get_rh(hal_ring_desc_t rx_desc, + struct hal_buf_info *buf_info) +{ +} + +static int hal_reo_send_cmd_rh(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + enum hal_reo_cmd_type cmd, + void *params) +{ + return 0; +} + +static void +hal_reo_qdesc_setup_rh(hal_soc_handle_t hal_soc_hdl, int tid, + uint32_t ba_window_size, + uint32_t start_seq, void *hw_qdesc_vaddr, + qdf_dma_addr_t hw_qdesc_paddr, + int pn_type, uint8_t vdev_stats_id) +{ +} + +static inline uint32_t +hal_rx_msdu_reo_dst_ind_get_rh(hal_soc_handle_t hal_soc_hdl, + void *msdu_link_desc) +{ + return 0; +} + +static inline void +hal_msdu_desc_info_set_rh(hal_soc_handle_t hal_soc_hdl, + void *msdu_desc, uint32_t dst_ind, + uint32_t nbuf_len) +{ +} + +static inline void +hal_mpdu_desc_info_set_rh(hal_soc_handle_t hal_soc_hdl, void *ent_desc, + void *mpdu_desc, uint32_t seq_no) +{ +} + +static QDF_STATUS hal_reo_status_update_rh(hal_soc_handle_t hal_soc_hdl, + hal_ring_desc_t reo_desc, + void *st_handle, + uint32_t tlv, int *num_ref) +{ + return QDF_STATUS_SUCCESS; +} + +static uint8_t hal_get_tlv_hdr_size_rh(void) +{ + return sizeof(struct tlv_32_hdr); +} + +static inline +uint8_t *hal_get_reo_ent_desc_qdesc_addr_rh(uint8_t *desc) +{ + return 0; +} + +static inline +void hal_set_reo_ent_desc_reo_dest_ind_rh(uint8_t *desc, + uint32_t dst_ind) +{ +} + +static uint64_t hal_rx_get_qdesc_addr_rh(uint8_t *dst_ring_desc, + uint8_t *buf) +{ + return 0; +} + +static uint8_t hal_get_idle_link_bm_id_rh(uint8_t chip_id) +{ + return 0; +} +/* + * hal_rx_msdu_is_wlan_mcast_generic_rh(): Check if the buffer is for multicast + * address + * @nbuf: Network buffer + * + * Returns: flag to indicate whether the nbuf has MC/BC address + */ +static uint32_t hal_rx_msdu_is_wlan_mcast_generic_rh(qdf_nbuf_t nbuf) +{ + uint8_t *buf = qdf_nbuf_data(nbuf); + + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + + return rx_attn->mcast_bcast; +} + +/** + * hal_rx_tlv_decap_format_get_rh() - Get packet decap format from the TLV + * @hw_desc_addr: rx tlv desc + * + * Return: pkt decap format + */ +static uint32_t hal_rx_tlv_decap_format_get_rh(void *hw_desc_addr) +{ + struct rx_msdu_start *rx_msdu_start; + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; + + rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; + + return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); +} + +/** + * hal_rx_dump_pkt_tlvs_rh(): API to print all member elements of + * RX TLVs + * @hal_soc_hdl: HAL SOC handle + * @buf: pointer the pkt buffer + * @dbg_level: log level + * + * Return: void + */ +static void hal_rx_dump_pkt_tlvs_rh(hal_soc_handle_t hal_soc_hdl, + uint8_t *buf, uint8_t dbg_level) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level); + hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc); + hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level); + hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level); + hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level); + hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level); +} + +/** + * hal_rx_tlv_get_offload_info_rh() - Get the offload info from TLV + * @rx_tlv: RX tlv start address in buffer + * @offload_info: Buffer to store the offload info + * + * Return: 0 on success, -EINVAL on failure. + */ +static int +hal_rx_tlv_get_offload_info_rh(uint8_t *rx_tlv, + struct hal_offload_info *offload_info) +{ + offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); + offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); + offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); + offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); + + if (offload_info->tcp_proto) { + offload_info->tcp_pure_ack = + HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); + offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); + offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); + offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); + offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); + } + return 0; +} + +/* + * hal_rx_attn_phy_ppdu_id_get_rh(): get phy_ppdu_id value + * from rx attention + * @buf: pointer to rx_pkt_tlvs + * + * Return: phy_ppdu_id + */ +static uint16_t hal_rx_attn_phy_ppdu_id_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint16_t phy_ppdu_id; + + phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); + + return phy_ppdu_id; +} + +/** + * hal_rx_msdu_start_msdu_len_get_rh(): API to get the MSDU length + * from rx_msdu_start TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: msdu length + */ +static uint32_t hal_rx_msdu_start_msdu_len_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t msdu_len; + + msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); + + return msdu_len; +} + +/** + * hal_rx_get_proto_params_rh() - Get l4 proto values from TLV + * @buf: rx tlv address + * @proto_params: Buffer to store proto parameters + * + * Return: 0 on success. + */ +static int hal_rx_get_proto_params_rh(uint8_t *buf, void *proto_params) +{ + struct hal_proto_params *param = + (struct hal_proto_params *)proto_params; + + param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf); + param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); + param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); + + return 0; +} + +/** + * hal_rx_get_l3_l4_offsets_rh() - Get l3/l4 header offset from TLV + * @buf: rx tlv start address + * @l3_hdr_offset: buffer to store l3 offset + * @l4_hdr_offset: buffer to store l4 offset + * + * Return: 0 on success. + */ +static int hal_rx_get_l3_l4_offsets_rh(uint8_t *buf, uint32_t *l3_hdr_offset, + uint32_t *l4_hdr_offset) +{ + *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); + *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); + + return 0; +} + +/** + * hal_rx_tlv_get_pn_num_rh() - Get packet number from RX TLV + * @buf: rx tlv address + * @pn_num: buffer to store packet number + * + * Return: None + */ +static inline void hal_rx_tlv_get_pn_num_rh(uint8_t *buf, uint64_t *pn_num) +{ + struct rx_pkt_tlvs *rx_pkt_tlv = + (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_info *rx_mpdu_info_details = + &rx_pkt_tlv->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; + + pn_num[0] = rx_mpdu_info_details->pn_31_0; + pn_num[0] |= + ((uint64_t)rx_mpdu_info_details->pn_63_32 << 32); + pn_num[1] = rx_mpdu_info_details->pn_95_64; + pn_num[1] |= + ((uint64_t)rx_mpdu_info_details->pn_127_96 << 32); +} + +#ifdef NO_RX_PKT_HDR_TLV +/** + * hal_rx_pkt_hdr_get_rh() - Get rx packet header start address. + * @buf: packet start address + * + * Return: packet data start address. + */ +static inline uint8_t *hal_rx_pkt_hdr_get_rh(uint8_t *buf) +{ + return buf + RX_PKT_TLVS_LEN; +} +#else +static inline uint8_t *hal_rx_pkt_hdr_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + + return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; +} +#endif + +/** + * hal_rx_priv_info_set_in_tlv_rh(): Save the private info to + * the reserved bytes of rx_tlv_hdr + * @buf: start of rx_tlv_hdr + * @priv_data: hal_wbm_err_desc_info structure + * @len: length of the private data + * Return: void + */ +static inline void +hal_rx_priv_info_set_in_tlv_rh(uint8_t *buf, uint8_t *priv_data, + uint32_t len) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + uint32_t copy_len = (len > RX_PADDING0_BYTES) ? + RX_PADDING0_BYTES : len; + + qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); +} + +/** + * hal_rx_priv_info_get_from_tlv_rh(): retrieve the private data from + * the reserved bytes of rx_tlv_hdr. + * @buf: start of rx_tlv_hdr + * @priv_data: hal_wbm_err_desc_info structure + * @len: length of the private data + * Return: void + */ +static inline void +hal_rx_priv_info_get_from_tlv_rh(uint8_t *buf, uint8_t *priv_data, + uint32_t len) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + uint32_t copy_len = (len > RX_PADDING0_BYTES) ? + RX_PADDING0_BYTES : len; + + qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); +} + +/** + * hal_rx_get_tlv_size_generic_rh() - Get rx packet tlv size + * @rx_pkt_tlv_size: TLV size for regular RX packets + * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets + * + * Return: size of rx pkt tlv before the actual data + */ +static void hal_rx_get_tlv_size_generic_rh(uint16_t *rx_pkt_tlv_size, + uint16_t *rx_mon_pkt_tlv_size) +{ + *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; + *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; +} + +/* + * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the + * rxdma ring entry. + * @rxdma_entry: descriptor entry + * @paddr: physical address of nbuf data pointer. + * @cookie: SW cookie used as a index to SW rx desc. + * @manager: who owns the nbuf (host, NSS, etc...). + * + */ +static void +hal_rxdma_buff_addr_info_set_rh(void *rxdma_entry, qdf_dma_addr_t paddr, + uint32_t cookie, uint8_t manager) +{ + uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); + uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; + + HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); + HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); + HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); + HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); +} + +/** + * hal_rx_tlv_csum_err_get_rh() - Get IP and tcp-udp checksum fail flag + * @rx_tlv_hdr: start address of rx_tlv_hdr + * @ip_csum_err: buffer to return ip_csum_fail flag + * @tcp_udp_csum_err: placeholder to return tcp-udp checksum fail flag + * + * Return: None + */ +static inline void +hal_rx_tlv_csum_err_get_rh(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, + uint32_t *tcp_udp_csum_err) +{ + *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); + *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); +} + +static void +hal_rx_tlv_get_pkt_capture_flags_rh(uint8_t *rx_tlv_pkt_hdr, + struct hal_rx_pkt_capture_flags *flags) +{ + struct rx_pkt_tlvs *rx_tlv_hdr = (struct rx_pkt_tlvs *)rx_tlv_pkt_hdr; + struct rx_attention *rx_attn = &rx_tlv_hdr->attn_tlv.rx_attn; + struct rx_mpdu_start *mpdu_start = + &rx_tlv_hdr->mpdu_start_tlv.rx_mpdu_start; + struct rx_mpdu_end *mpdu_end = &rx_tlv_hdr->mpdu_end_tlv.rx_mpdu_end; + struct rx_msdu_start *msdu_start = + &rx_tlv_hdr->msdu_start_tlv.rx_msdu_start; + + flags->encrypt_type = mpdu_start->rx_mpdu_info_details.encrypt_type; + flags->fcs_err = mpdu_end->fcs_err; + flags->fragment_flag = rx_attn->fragment_flag; + flags->chan_freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); + flags->rssi_comb = HAL_RX_MSDU_START_RSSI_GET(msdu_start); + flags->tsft = msdu_start->ppdu_start_timestamp; +} + +static inline bool +hal_rx_mpdu_info_ampdu_flag_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + bool ampdu_flag; + + ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info); + + return ampdu_flag; +} + +static +uint32_t hal_rx_tlv_mpdu_len_err_get_rh(void *hw_desc_addr) +{ + struct rx_attention *rx_attn; + struct rx_mon_pkt_tlvs *rx_desc = + (struct rx_mon_pkt_tlvs *)hw_desc_addr; + + rx_attn = &rx_desc->attn_tlv.rx_attn; + + return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); +} + +static +uint32_t hal_rx_tlv_mpdu_fcs_err_get_rh(void *hw_desc_addr) +{ + struct rx_attention *rx_attn; + struct rx_mon_pkt_tlvs *rx_desc = + (struct rx_mon_pkt_tlvs *)hw_desc_addr; + + rx_attn = &rx_desc->attn_tlv.rx_attn; + + return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); +} + +#ifdef NO_RX_PKT_HDR_TLV +static uint8_t *hal_rx_desc_get_80211_hdr_rh(void *hw_desc_addr) +{ + uint8_t *rx_pkt_hdr; + struct rx_mon_pkt_tlvs *rx_desc = + (struct rx_mon_pkt_tlvs *)hw_desc_addr; + + rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; + + return rx_pkt_hdr; +} +#else +static uint8_t *hal_rx_desc_get_80211_hdr_rh(void *hw_desc_addr) +{ + uint8_t *rx_pkt_hdr; + + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; + + rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; + + return rx_pkt_hdr; +} +#endif + +static uint32_t hal_rx_hw_desc_mpdu_user_id_rh(void *hw_desc_addr) +{ + struct rx_mon_pkt_tlvs *rx_desc = + (struct rx_mon_pkt_tlvs *)hw_desc_addr; + uint32_t user_id; + + user_id = HAL_RX_GET_USER_TLV32_USERID( + &rx_desc->mpdu_start_tlv); + + return user_id; +} + +/** + * hal_rx_msdu_start_msdu_len_set_rh(): API to set the MSDU length + * from rx_msdu_start TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * @len: msdu length + * + * Return: none + */ +static inline void +hal_rx_msdu_start_msdu_len_set_rh(uint8_t *buf, uint32_t len) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + void *wrd1; + + wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; + *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); + *(uint32_t *)wrd1 |= len; +} + +/* + * hal_rx_tlv_bw_get_rh(): API to get the Bandwidth + * Interval from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(bw) + */ +static inline uint32_t hal_rx_tlv_bw_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t bw; + + bw = HAL_RX_MSDU_START_BW_GET(msdu_start); + + return bw; +} + +/* + * hal_rx_tlv_get_freq_rh(): API to get the frequency of operating channel + * from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(frequency) + */ +static inline uint32_t +hal_rx_tlv_get_freq_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t freq; + + freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); + + return freq; +} + +/** + * hal_rx_tlv_sgi_get_rh(): API to get the Short Guard + * Interval from rx_msdu_start TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: uint32_t(sgi) + */ +static inline uint32_t +hal_rx_tlv_sgi_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t sgi; + + sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); + + return sgi; +} + +/** + * hal_rx_tlv_rate_mcs_get_rh(): API to get the MCS rate + * from rx_msdu_start TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: uint32_t(rate_mcs) + */ +static inline uint32_t +hal_rx_tlv_rate_mcs_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t rate_mcs; + + rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); + + return rate_mcs; +} + +/* + * hal_rx_tlv_get_pkt_type_rh(): API to get the pkt type + * from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(pkt type) + */ + +static inline uint32_t hal_rx_tlv_get_pkt_type_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t pkt_type; + + pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); + + return pkt_type; +} + +/** + * hal_rx_tlv_mic_err_get_rh(): API to get the MIC ERR + * from rx_mpdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: uint32_t(mic_err) + */ +static inline uint32_t +hal_rx_tlv_mic_err_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_end *mpdu_end = + &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; + uint32_t mic_err; + + mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end); + + return mic_err; +} + +/** + * hal_rx_tlv_decrypt_err_get_rh(): API to get the Decrypt ERR + * from rx_mpdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: uint32_t(decrypt_err) + */ +static inline uint32_t +hal_rx_tlv_decrypt_err_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_end *mpdu_end = + &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end; + uint32_t decrypt_err; + + decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end); + + return decrypt_err; +} + +/* + * hal_rx_tlv_first_mpdu_get_rh(): get fist_mpdu bit from rx attention + * @buf: pointer to rx_pkt_tlvs + * + * reutm: uint32_t(first_msdu) + */ +static inline uint32_t +hal_rx_tlv_first_mpdu_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint32_t first_mpdu; + + first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); + + return first_mpdu; +} + +/* + * hal_rx_msdu_get_keyid_rh(): API to get the key id if the decrypted packet + * from rx_msdu_end + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(key id) + */ +static inline uint8_t +hal_rx_msdu_get_keyid_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint32_t keyid_octet; + + keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); + + return keyid_octet & 0x3; +} + +/* + * hal_rx_tlv_get_is_decrypted_rh(): API to get the decrypt status of the + * packet from rx_attention + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(decryt status) + */ +static inline uint32_t +hal_rx_tlv_get_is_decrypted_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint32_t is_decrypt = 0; + uint32_t decrypt_status; + + decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); + + if (!decrypt_status) + is_decrypt = 1; + + return is_decrypt; +} + +/** + * hal_hw_txrx_default_ops_attach_rh() - Attach the default hal ops for + * Rh arch chipsets. + * @hal_soc: HAL soc handle + * + * Return: None + */ +void hal_hw_txrx_default_ops_attach_rh(struct hal_soc *hal_soc) +{ + hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_rh; + hal_soc->ops->hal_get_rx_max_ba_window = + hal_get_rx_max_ba_window_rh; + hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_rh; + hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_rh; + hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_rh; + hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_rh; + hal_soc->ops->hal_get_reo_reg_base_offset = + hal_get_reo_reg_base_offset_rh; + hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_rh; + hal_soc->ops->hal_rx_msdu_is_wlan_mcast = + hal_rx_msdu_is_wlan_mcast_generic_rh; + hal_soc->ops->hal_rx_tlv_decap_format_get = + hal_rx_tlv_decap_format_get_rh; + hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_rh; + hal_soc->ops->hal_rx_tlv_get_offload_info = + hal_rx_tlv_get_offload_info_rh; + hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = + hal_rx_attn_phy_ppdu_id_get_rh; + hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_rh; + hal_soc->ops->hal_rx_tlv_msdu_len_get = + hal_rx_msdu_start_msdu_len_get_rh; + hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_rh; + hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_rh; + + hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_rh; + hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_rh; + hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_rh; + hal_soc->ops->hal_rx_ret_buf_manager_get = + hal_rx_ret_buf_manager_get_rh; + hal_soc->ops->hal_rxdma_buff_addr_info_set = + hal_rxdma_buff_addr_info_set_rh; + hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_rh; + hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_rh; + hal_soc->ops->hal_gen_reo_remap_val = + hal_gen_reo_remap_val_generic_rh; + hal_soc->ops->hal_rx_tlv_csum_err_get = + hal_rx_tlv_csum_err_get_rh; + hal_soc->ops->hal_rx_mpdu_desc_info_get = + hal_rx_mpdu_desc_info_get_rh; + hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_rh; + hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_rh; + hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_rh; + hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_rh; + hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get = + hal_rx_wbm_rel_buf_paddr_get_rh; + hal_soc->ops->hal_rx_priv_info_set_in_tlv = + hal_rx_priv_info_set_in_tlv_rh; + hal_soc->ops->hal_rx_priv_info_get_from_tlv = + hal_rx_priv_info_get_from_tlv_rh; + hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = + hal_rx_mpdu_info_ampdu_flag_get_rh; + hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = + hal_rx_tlv_mpdu_len_err_get_rh; + hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = + hal_rx_tlv_mpdu_fcs_err_get_rh; + hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_rh; + hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = + hal_rx_tlv_get_pkt_capture_flags_rh; + hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_rh; + hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = + hal_rx_hw_desc_mpdu_user_id_rh; + hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_rh; + hal_soc->ops->hal_rx_tlv_msdu_len_set = + hal_rx_msdu_start_msdu_len_set_rh; + hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_rh; + hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_rh; + hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_rh; + hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_rh; + hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_rh; + hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_rh; + hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_rh; + hal_soc->ops->hal_rx_tlv_decrypt_err_get = + hal_rx_tlv_decrypt_err_get_rh; + hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_rh; + hal_soc->ops->hal_rx_tlv_get_is_decrypted = + hal_rx_tlv_get_is_decrypted_rh; + hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_rh; + hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = + hal_rx_msdu_reo_dst_ind_get_rh; + hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_rh; + hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_rh; + hal_soc->ops->hal_reo_status_update = hal_reo_status_update_rh; + hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_rh; + hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = + hal_get_reo_ent_desc_qdesc_addr_rh; + hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_rh; + hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = + hal_set_reo_ent_desc_reo_dest_ind_rh; + hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_rh; +} diff --git a/hal/wifi3.0/rh/hal_rh_generic_api.h b/hal/wifi3.0/rh/hal_rh_generic_api.h new file mode 100644 index 0000000000..e74e58f6f8 --- /dev/null +++ b/hal/wifi3.0/rh/hal_rh_generic_api.h @@ -0,0 +1,2151 @@ +/* + * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_RH_GENERIC_API_H_ +#define _HAL_RH_GENERIC_API_H_ + +#include "hal_tx.h" +#include "hal_rh_tx.h" +#include "hal_rh_rx.h" + +#ifdef QCA_UNDECODED_METADATA_SUPPORT +static inline void +hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info){ + switch (hal->target_type) { + case TARGET_TYPE_QCN9000: + ppdu_info->rx_status.phyrx_abort = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, + PHYRX_ABORT_REQUEST_INFO_VALID); + ppdu_info->rx_status.phyrx_abort_reason = + HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_11, + PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON); + break; + default: + break; + } +} + +static inline void +hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *ht_sig_info) +{ + ppdu_info->rx_status.ht_length = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_0, LENGTH); + ppdu_info->rx_status.smoothing = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, SMOOTHING); + ppdu_info->rx_status.not_sounding = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, NOT_SOUNDING); + ppdu_info->rx_status.aggregation = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, AGGREGATION); + ppdu_info->rx_status.ht_stbc = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, STBC); + ppdu_info->rx_status.ht_crc = + HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, CRC); +} + +static inline void +hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *l_sig_a_info) +{ + ppdu_info->rx_status.l_sig_length = + HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, LENGTH); + ppdu_info->rx_status.l_sig_a_parity = + HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PARITY); + ppdu_info->rx_status.l_sig_a_pkt_type = + HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, PKT_TYPE); + ppdu_info->rx_status.l_sig_a_implicit_sounding = + HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, + CAPTURED_IMPLICIT_SOUNDING); +} + +static inline void +hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *vht_sig_a_info) +{ + ppdu_info->rx_status.vht_no_txop_ps = + HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, + TXOP_PS_NOT_ALLOWED); + ppdu_info->rx_status.vht_crc = + HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, CRC); +} + +static inline void +hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *he_sig_a_su_info) { + ppdu_info->rx_status.he_crc = + HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, CRC); +} + +static inline void +hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *he_sig_a_mu_dl_info) { + ppdu_info->rx_status.he_crc = + HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, CRC); +} +#else +static inline void +hal_rx_get_phyrx_abort(struct hal_soc *hal, void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info) +{ +} + +static inline void +hal_rx_get_ht_sig_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *ht_sig_info) +{ +} + +static inline void +hal_rx_get_l_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *l_sig_a_info) +{ +} + +static inline void +hal_rx_get_vht_sig_a_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *vht_sig_a_info) +{ +} + +static inline void +hal_rx_get_crc_he_sig_a_su_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *he_sig_a_su_info) +{ +} + +static inline void +hal_rx_get_crc_he_sig_a_mu_dl_info(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *he_sig_a_mu_dl_info) +{ +} +#endif /* QCA_UNDECODED_METADATA_SUPPORT */ + +/** + * hal_tx_desc_set_buf_addr_generic_rh - Fill Buffer Address information + * in Tx Descriptor + * @desc: Handle to Tx Descriptor + * @paddr: Physical Address + * @rbm_id: Return Buffer Manager ID + * @desc_id: Descriptor ID + * @type: 0 - Address points to a MSDU buffer + * 1 - Address points to MSDU extension descriptor + * + * Return: void + */ +static inline void +hal_tx_desc_set_buf_addr_generic_rh(void *desc, dma_addr_t paddr, + uint8_t rbm_id, uint32_t desc_id, + uint8_t type) +{ + /* Set buffer_addr_info.buffer_addr_31_0 */ + HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_0, + BUFFER_ADDR_INFO_BUF_ADDR_INFO) = + HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr); + + /* Set buffer_addr_info.buffer_addr_39_32 */ + HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, + BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= + HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, + (((uint64_t)paddr) >> 32)); + + /* Set buffer_addr_info.return_buffer_manager = rbm id */ + HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, + BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= + HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, + RETURN_BUFFER_MANAGER, rbm_id); + + /* Set buffer_addr_info.sw_buffer_cookie = desc_id */ + HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_1, + BUFFER_ADDR_INFO_BUF_ADDR_INFO) |= + HAL_TX_SM(UNIFIED_BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, + desc_id); + + /* Set Buffer or Ext Descriptor Type */ + HAL_SET_FLD(desc, UNIFIED_TCL_DATA_CMD_2, + BUF_OR_EXT_DESC_TYPE) |= + HAL_TX_SM(UNIFIED_TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type); +} + +#if defined(QCA_WIFI_QCA6290_11AX_MU_UL) && defined(QCA_WIFI_QCA6290_11AX) +/** + * hal_rx_handle_other_tlvs() - handle special TLVs like MU_UL + * @tlv_tag: Taf of the TLVs + * @rx_tlv: the pointer to the TLVs + * @ppdu_info: pointer to ppdu_info + * + * Return: true if the tlv is handled, false if not + */ +static inline bool +hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info) +{ + uint32_t value; + + switch (tlv_tag) { + case WIFIPHYRX_HE_SIG_A_MU_UL_E: + { + uint8_t *he_sig_a_mu_ul_info = + (uint8_t *)rx_tlv + + HAL_RX_OFFSET(PHYRX_HE_SIG_A_MU_UL_0, + HE_SIG_A_MU_UL_INFO_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS); + ppdu_info->rx_status.he_flags = 1; + + value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, + FORMAT_INDICATION); + if (value == 0) { + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; + } else { + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_SU_FORMAT_TYPE; + } + + /* data1 */ + ppdu_info->rx_status.he_data1 |= + QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | + QDF_MON_STATUS_HE_DL_UL_KNOWN | + QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; + + /* data2 */ + ppdu_info->rx_status.he_data2 |= + QDF_MON_STATUS_TXOP_KNOWN; + + /*data3*/ + value = HAL_RX_GET(he_sig_a_mu_ul_info, + HE_SIG_A_MU_UL_INFO_0, BSS_COLOR_ID); + ppdu_info->rx_status.he_data3 = value; + /* 1 for UL and 0 for DL */ + value = 1; + value = value << QDF_MON_STATUS_DL_UL_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + /*data4*/ + value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_0, + SPATIAL_REUSE); + ppdu_info->rx_status.he_data4 = value; + + /*data5*/ + value = HAL_RX_GET(he_sig_a_mu_ul_info, + HE_SIG_A_MU_UL_INFO_0, TRANSMIT_BW); + ppdu_info->rx_status.he_data5 = value; + ppdu_info->rx_status.bw = value; + + /*data6*/ + value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO_1, + TXOP_DURATION); + value = value << QDF_MON_STATUS_TXOP_SHIFT; + ppdu_info->rx_status.he_data6 |= value; + return true; + } + default: + return false; + } +} +#else +static inline bool +hal_rx_handle_other_tlvs(uint32_t tlv_tag, void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info) +{ + return false; +} +#endif /* QCA_WIFI_QCA6290_11AX_MU_UL && QCA_WIFI_QCA6290_11AX */ + +#if defined(RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET) && \ +defined(RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) + +static inline void +hal_rx_handle_mu_ul_info(void *rx_tlv, + struct mon_rx_user_status *mon_rx_user_status) +{ + mon_rx_user_status->mu_ul_user_v0_word0 = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_11, + SW_RESPONSE_REFERENCE_PTR); + + mon_rx_user_status->mu_ul_user_v0_word1 = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_22, + SW_RESPONSE_REFERENCE_PTR_EXT); +} + +static inline void +hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, + struct mon_rx_user_status *mon_rx_user_status) +{ + uint32_t mpdu_ok_byte_count; + uint32_t mpdu_err_byte_count; + + mpdu_ok_byte_count = HAL_RX_GET(rx_tlv, + RX_PPDU_END_USER_STATS_17, + MPDU_OK_BYTE_COUNT); + mpdu_err_byte_count = HAL_RX_GET(rx_tlv, + RX_PPDU_END_USER_STATS_19, + MPDU_ERR_BYTE_COUNT); + + mon_rx_user_status->mpdu_ok_byte_count = mpdu_ok_byte_count; + mon_rx_user_status->mpdu_err_byte_count = mpdu_err_byte_count; +} +#else +static inline void +hal_rx_handle_mu_ul_info(void *rx_tlv, + struct mon_rx_user_status *mon_rx_user_status) +{ +} + +static inline void +hal_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, + struct mon_rx_user_status *mon_rx_user_status) +{ + struct hal_rx_ppdu_info *ppdu_info = + (struct hal_rx_ppdu_info *)ppduinfo; + + /* HKV1: doesn't support mpdu byte count */ + mon_rx_user_status->mpdu_ok_byte_count = ppdu_info->rx_status.ppdu_len; + mon_rx_user_status->mpdu_err_byte_count = 0; +} +#endif + +static inline void +hal_rx_populate_mu_user_info(void *rx_tlv, void *ppduinfo, uint32_t user_id, + struct mon_rx_user_status *mon_rx_user_status) +{ + struct mon_rx_info *mon_rx_info; + struct mon_rx_user_info *mon_rx_user_info; + struct hal_rx_ppdu_info *ppdu_info = + (struct hal_rx_ppdu_info *)ppduinfo; + + mon_rx_info = &ppdu_info->rx_info; + mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; + mon_rx_user_info->qos_control_info_valid = + mon_rx_info->qos_control_info_valid; + mon_rx_user_info->qos_control = mon_rx_info->qos_control; + + mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; + mon_rx_user_status->tid = ppdu_info->rx_status.tid; + mon_rx_user_status->tcp_msdu_count = + ppdu_info->rx_status.tcp_msdu_count; + mon_rx_user_status->udp_msdu_count = + ppdu_info->rx_status.udp_msdu_count; + mon_rx_user_status->other_msdu_count = + ppdu_info->rx_status.other_msdu_count; + mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; + mon_rx_user_status->frame_control_info_valid = + ppdu_info->rx_status.frame_control_info_valid; + mon_rx_user_status->data_sequence_control_info_valid = + ppdu_info->rx_status.data_sequence_control_info_valid; + mon_rx_user_status->first_data_seq_ctrl = + ppdu_info->rx_status.first_data_seq_ctrl; + mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; + mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; + mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; + mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; + mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; + mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; + + mon_rx_user_status->mpdu_cnt_fcs_ok = + ppdu_info->com_info.mpdu_cnt_fcs_ok; + mon_rx_user_status->mpdu_cnt_fcs_err = + ppdu_info->com_info.mpdu_cnt_fcs_err; + qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, + &ppdu_info->com_info.mpdu_fcs_ok_bitmap, + HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * + sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); + + hal_rx_populate_byte_count(rx_tlv, ppdu_info, mon_rx_user_status); +} + +#define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, word_1, word_2, \ + ppdu_info, rssi_info_tlv) \ + { \ + ppdu_info->rx_status.rssi_chain[chain][0] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ + RSSI_PRI20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][1] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ + RSSI_EXT20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][2] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ + RSSI_EXT40_LOW20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][3] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_1,\ + RSSI_EXT40_HIGH20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][4] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ + RSSI_EXT80_LOW20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][5] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ + RSSI_EXT80_LOW_HIGH20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][6] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ + RSSI_EXT80_HIGH_LOW20_CHAIN##chain); \ + ppdu_info->rx_status.rssi_chain[chain][7] = \ + HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO_##word_2,\ + RSSI_EXT80_HIGH20_CHAIN##chain); \ + } \ + +#define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ + {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, 0, 1, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, 2, 3, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, 4, 5, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, 6, 7, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(4, 8, 9, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(5, 10, 11, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(6, 12, 13, ppdu_info, rssi_info_tlv) \ + HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(7, 14, 15, ppdu_info, rssi_info_tlv)} \ + +static inline uint32_t +hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, + uint8_t *rssi_info_tlv) +{ + HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) + return 0; +} + +#ifdef WLAN_TX_PKT_CAPTURE_ENH +static inline void +hal_get_qos_control(void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info) +{ + ppdu_info->rx_info.qos_control_info_valid = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, + QOS_CONTROL_INFO_VALID); + + if (ppdu_info->rx_info.qos_control_info_valid) + ppdu_info->rx_info.qos_control = + HAL_RX_GET(rx_tlv, + RX_PPDU_END_USER_STATS_5, + QOS_CONTROL_FIELD); +} + +static inline void +hal_get_mac_addr1(uint8_t *rx_mpdu_start, + struct hal_rx_ppdu_info *ppdu_info) +{ + if ((ppdu_info->sw_frame_group_id + == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || + (ppdu_info->sw_frame_group_id == + HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { + ppdu_info->rx_info.mac_addr1_valid = + HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start); + + *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_15, + MAC_ADDR_AD1_31_0); + if (ppdu_info->sw_frame_group_id == + HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { + *(uint32_t *)&ppdu_info->rx_info.mac_addr1[4] = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_16, + MAC_ADDR_AD1_47_32); + } + } +} +#else +static inline void +hal_get_qos_control(void *rx_tlv, + struct hal_rx_ppdu_info *ppdu_info) +{ +} + +static inline void +hal_get_mac_addr1(uint8_t *rx_mpdu_start, + struct hal_rx_ppdu_info *ppdu_info) +{ +} +#endif + +#ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS +static inline void +hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, + struct hal_rx_ppdu_info *ppdu_info) +{ + uint16_t frame_ctrl; + uint8_t fc_type; + + if (HAL_RX_GET_FC_VALID(rx_mpdu_start)) { + frame_ctrl = HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_14, + MPDU_FRAME_CONTROL_FIELD); + fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); + if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) + ppdu_info->frm_type_info.rx_mgmt_cnt++; + else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) + ppdu_info->frm_type_info.rx_ctrl_cnt++; + else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) + ppdu_info->frm_type_info.rx_data_cnt++; + } +} +#else +static inline void +hal_update_frame_type_cnt(uint8_t *rx_mpdu_start, + struct hal_rx_ppdu_info *ppdu_info) +{ +} +#endif + +/** + * hal_rx_status_get_tlv_info_generic_rh() - process receive info TLV + * @rx_tlv_hdr: pointer to TLV header + * @ppduinfo: pointer to ppdu_info + * @hal_soc_hdl: HAL SOC handle + * @nbuf: pkt buffer + * + * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv + */ +static inline uint32_t +hal_rx_status_get_tlv_info_generic_rh(void *rx_tlv_hdr, void *ppduinfo, + hal_soc_handle_t hal_soc_hdl, + qdf_nbuf_t nbuf) +{ + struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; + uint32_t tlv_tag, user_id, tlv_len, value; + uint8_t group_id = 0; + uint8_t he_dcm = 0; + uint8_t he_stbc = 0; + uint16_t he_gi = 0; + uint16_t he_ltf = 0; + void *rx_tlv; + bool unhandled = false; + struct mon_rx_user_status *mon_rx_user_status; + struct hal_rx_ppdu_info *ppdu_info = + (struct hal_rx_ppdu_info *)ppduinfo; + + tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); + user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); + tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); + + rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; + + qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + rx_tlv, tlv_len); + + switch (tlv_tag) { + case WIFIRX_PPDU_START_E: + { + if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == + HAL_RX_GET(rx_tlv, RX_PPDU_START_0, PHY_PPDU_ID))) + hal_err("Matching ppdu_id(%u) detected", + ppdu_info->com_info.last_ppdu_id); + + /* Reset ppdu_info before processing the ppdu */ + qdf_mem_zero(ppdu_info, + sizeof(struct hal_rx_ppdu_info)); + + ppdu_info->com_info.last_ppdu_id = + ppdu_info->com_info.ppdu_id = + HAL_RX_GET(rx_tlv, RX_PPDU_START_0, + PHY_PPDU_ID); + + /* channel number is set in PHY meta data */ + ppdu_info->rx_status.chan_num = + (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, + SW_PHY_META_DATA) & 0x0000FFFF); + ppdu_info->rx_status.chan_freq = + (HAL_RX_GET(rx_tlv, RX_PPDU_START_1, + SW_PHY_META_DATA) & 0xFFFF0000) >> 16; + if (ppdu_info->rx_status.chan_num) { + ppdu_info->rx_status.chan_freq = + hal_rx_radiotap_num_to_freq( + ppdu_info->rx_status.chan_num, + ppdu_info->rx_status.chan_freq); + } + ppdu_info->com_info.ppdu_timestamp = + HAL_RX_GET(rx_tlv, RX_PPDU_START_2, + PPDU_START_TIMESTAMP); + ppdu_info->rx_status.ppdu_timestamp = + ppdu_info->com_info.ppdu_timestamp; + ppdu_info->rx_state = HAL_RX_MON_PPDU_START; + + break; + } + + case WIFIRX_PPDU_START_USER_INFO_E: + break; + + case WIFIRX_PPDU_END_E: + dp_nofl_debug("[%s][%d] ppdu_end_e len=%d", + __func__, __LINE__, tlv_len); + /* This is followed by sub-TLVs of PPDU_END */ + ppdu_info->rx_state = HAL_RX_MON_PPDU_END; + break; + + case WIFIPHYRX_PKT_END_E: + hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); + break; + + case WIFIRXPCU_PPDU_END_INFO_E: + ppdu_info->rx_status.rx_antenna = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_2, RX_ANTENNA); + ppdu_info->rx_status.tsft = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_1, + WB_TIMESTAMP_UPPER_32); + ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_0, + WB_TIMESTAMP_LOWER_32); + ppdu_info->rx_status.duration = + HAL_RX_GET(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, + RX_PPDU_DURATION); + hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); + hal_rx_get_phyrx_abort(hal, rx_tlv, ppdu_info); + break; + + /* + * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. + * for MU, based on num users we see this tlv that many times. + */ + case WIFIRX_PPDU_END_USER_STATS_E: + { + unsigned long tid = 0; + uint16_t seq = 0; + + ppdu_info->rx_status.ast_index = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_4, + AST_INDEX); + + tid = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_12, + RECEIVED_QOS_DATA_TID_BITMAP); + ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, + sizeof(tid) * 8); + + if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) + ppdu_info->rx_status.tid = HAL_TID_INVALID; + + ppdu_info->rx_status.tcp_msdu_count = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, + TCP_MSDU_COUNT) + + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, + TCP_ACK_MSDU_COUNT); + ppdu_info->rx_status.udp_msdu_count = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_9, + UDP_MSDU_COUNT); + ppdu_info->rx_status.other_msdu_count = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_10, + OTHER_MSDU_COUNT); + + if (ppdu_info->sw_frame_group_id + != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { + ppdu_info->rx_status.frame_control_info_valid = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, + FRAME_CONTROL_INFO_VALID); + + if (ppdu_info->rx_status.frame_control_info_valid) + ppdu_info->rx_status.frame_control = + HAL_RX_GET(rx_tlv, + RX_PPDU_END_USER_STATS_4, + FRAME_CONTROL_FIELD); + + hal_get_qos_control(rx_tlv, ppdu_info); + } + + ppdu_info->rx_status.data_sequence_control_info_valid = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, + DATA_SEQUENCE_CONTROL_INFO_VALID); + + seq = HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_5, + FIRST_DATA_SEQ_CTRL); + if (ppdu_info->rx_status.data_sequence_control_info_valid) + ppdu_info->rx_status.first_data_seq_ctrl = seq; + + ppdu_info->rx_status.preamble_type = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, + HT_CONTROL_FIELD_PKT_TYPE); + switch (ppdu_info->rx_status.preamble_type) { + case HAL_RX_PKT_TYPE_11N: + ppdu_info->rx_status.ht_flags = 1; + ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; + break; + case HAL_RX_PKT_TYPE_11AC: + ppdu_info->rx_status.vht_flags = 1; + break; + case HAL_RX_PKT_TYPE_11AX: + ppdu_info->rx_status.he_flags = 1; + break; + default: + break; + } + + ppdu_info->com_info.mpdu_cnt_fcs_ok = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_3, + MPDU_CNT_FCS_OK); + ppdu_info->com_info.mpdu_cnt_fcs_err = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_2, + MPDU_CNT_FCS_ERR); + if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | + ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) + ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; + else + ppdu_info->rx_status.rs_flags &= + (~IEEE80211_AMPDU_FLAG); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_7, + FCS_OK_BITMAP_31_0); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_8, + FCS_OK_BITMAP_63_32); + + if (user_id < HAL_MAX_UL_MU_USERS) { + mon_rx_user_status = + &ppdu_info->rx_user_status[user_id]; + + hal_rx_handle_mu_ul_info(rx_tlv, mon_rx_user_status); + + ppdu_info->com_info.num_users++; + + hal_rx_populate_mu_user_info(rx_tlv, ppdu_info, + user_id, + mon_rx_user_status); + } + break; + } + + case WIFIRX_PPDU_END_USER_STATS_EXT_E: + ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_1, + FCS_OK_BITMAP_95_64); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_2, + FCS_OK_BITMAP_127_96); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_3, + FCS_OK_BITMAP_159_128); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_4, + FCS_OK_BITMAP_191_160); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_5, + FCS_OK_BITMAP_223_192); + + ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = + HAL_RX_GET(rx_tlv, RX_PPDU_END_USER_STATS_EXT_6, + FCS_OK_BITMAP_255_224); + break; + + case WIFIRX_PPDU_END_STATUS_DONE_E: + return HAL_TLV_STATUS_PPDU_DONE; + + case WIFIDUMMY_E: + return HAL_TLV_STATUS_BUF_DONE; + + case WIFIPHYRX_HT_SIG_E: + { + uint8_t *ht_sig_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, + HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); + value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO_1, + FEC_CODING); + ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? + 1 : 0; + ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, + HT_SIG_INFO_0, MCS); + ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; + ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, + HT_SIG_INFO_0, CBW); + ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, + HT_SIG_INFO_1, SHORT_GI); + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; + ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> + HT_SIG_SU_NSS_SHIFT) + 1; + ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); + hal_rx_get_ht_sig_info(ppdu_info, ht_sig_info); + break; + } + + case WIFIPHYRX_L_SIG_B_E: + { + uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, + L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); + + value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO_0, RATE); + ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); + switch (value) { + case 1: + ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; + break; + case 2: + ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; + break; + case 3: + ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; + break; + case 4: + ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; + break; + case 5: + ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; + break; + case 6: + ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; + break; + case 7: + ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; + break; + default: + break; + } + ppdu_info->rx_status.cck_flag = 1; + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; + break; + } + + case WIFIPHYRX_L_SIG_A_E: + { + uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, + L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); + + value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO_0, RATE); + ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); + switch (value) { + case 8: + ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; + break; + case 9: + ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; + break; + case 10: + ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; + break; + case 11: + ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; + break; + case 12: + ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; + break; + case 13: + ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; + break; + case 14: + ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; + break; + case 15: + ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; + ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; + break; + default: + break; + } + ppdu_info->rx_status.ofdm_flag = 1; + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; + hal_rx_get_l_sig_a_info(ppdu_info, l_sig_a_info); + break; + } + + case WIFIPHYRX_VHT_SIG_A_E: + { + uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, + VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); + + value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_1, + SU_MU_CODING); + ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? + 1 : 0; + group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO_0, + GROUP_ID); + ppdu_info->rx_status.vht_flag_values5 = group_id; + ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_1, MCS); + ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_1, GI_SETTING); + + switch (hal->target_type) { + case TARGET_TYPE_QCA8074: + case TARGET_TYPE_QCA8074V2: + case TARGET_TYPE_QCA6018: + case TARGET_TYPE_QCA5018: + case TARGET_TYPE_QCN9000: + case TARGET_TYPE_QCN6122: +#ifdef QCA_WIFI_QCA6390 + case TARGET_TYPE_QCA6390: +#endif + case TARGET_TYPE_QCA6490: + ppdu_info->rx_status.is_stbc = + HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_0, STBC); + value = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_0, N_STS); + value = value & VHT_SIG_SU_NSS_MASK; + if (ppdu_info->rx_status.is_stbc && (value > 0)) + value = ((value + 1) >> 1) - 1; + ppdu_info->rx_status.nss = + ((value & VHT_SIG_SU_NSS_MASK) + 1); + + break; + case TARGET_TYPE_QCA6290: +#if !defined(QCA_WIFI_QCA6290_11AX) + ppdu_info->rx_status.is_stbc = + HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_0, STBC); + value = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_0, N_STS); + value = value & VHT_SIG_SU_NSS_MASK; + if (ppdu_info->rx_status.is_stbc && (value > 0)) + value = ((value + 1) >> 1) - 1; + ppdu_info->rx_status.nss = + ((value & VHT_SIG_SU_NSS_MASK) + 1); +#else + ppdu_info->rx_status.nss = 0; +#endif + break; + case TARGET_TYPE_QCA6750: + ppdu_info->rx_status.nss = 0; + break; + default: + break; + } + ppdu_info->rx_status.vht_flag_values3[0] = + (((ppdu_info->rx_status.mcs) << 4) + | ppdu_info->rx_status.nss); + ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_0, BANDWIDTH); + ppdu_info->rx_status.vht_flag_values2 = + ppdu_info->rx_status.bw; + ppdu_info->rx_status.vht_flag_values4 = + HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_1, SU_MU_CODING); + + ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, + VHT_SIG_A_INFO_1, BEAMFORMED); + if (group_id == 0 || group_id == 63) + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; + else + ppdu_info->rx_status.reception_type = + HAL_RX_TYPE_MU_MIMO; + + hal_rx_get_vht_sig_a_info(ppdu_info, vht_sig_a_info); + break; + } + case WIFIPHYRX_HE_SIG_A_SU_E: + { + uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, + HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); + ppdu_info->rx_status.he_flags = 1; + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, + FORMAT_INDICATION); + if (value == 0) { + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; + } else { + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_SU_FORMAT_TYPE; + } + + /* data1 */ + ppdu_info->rx_status.he_data1 |= + QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | + QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | + QDF_MON_STATUS_HE_DL_UL_KNOWN | + QDF_MON_STATUS_HE_MCS_KNOWN | + QDF_MON_STATUS_HE_DCM_KNOWN | + QDF_MON_STATUS_HE_CODING_KNOWN | + QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | + QDF_MON_STATUS_HE_STBC_KNOWN | + QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | + QDF_MON_STATUS_HE_DOPPLER_KNOWN; + + /* data2 */ + ppdu_info->rx_status.he_data2 = + QDF_MON_STATUS_HE_GI_KNOWN; + ppdu_info->rx_status.he_data2 |= + QDF_MON_STATUS_TXBF_KNOWN | + QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | + QDF_MON_STATUS_TXOP_KNOWN | + QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | + QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | + QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; + + /* data3 */ + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, BSS_COLOR_ID); + ppdu_info->rx_status.he_data3 = value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, BEAM_CHANGE); + value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, DL_UL_FLAG); + value = value << QDF_MON_STATUS_DL_UL_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, TRANSMIT_MCS); + ppdu_info->rx_status.mcs = value; + value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, DCM); + he_dcm = value; + value = value << QDF_MON_STATUS_DCM_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_1, CODING); + ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? + 1 : 0; + value = value << QDF_MON_STATUS_CODING_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_1, + LDPC_EXTRA_SYMBOL); + value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_1, STBC); + he_stbc = value; + value = value << QDF_MON_STATUS_STBC_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + /* data4 */ + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, + SPATIAL_REUSE); + ppdu_info->rx_status.he_data4 = value; + + /* data5 */ + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, TRANSMIT_BW); + ppdu_info->rx_status.he_data5 = value; + ppdu_info->rx_status.bw = value; + value = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_0, CP_LTF_SIZE); + switch (value) { + case 0: + he_gi = HE_GI_0_8; + he_ltf = HE_LTF_1_X; + break; + case 1: + he_gi = HE_GI_0_8; + he_ltf = HE_LTF_2_X; + break; + case 2: + he_gi = HE_GI_1_6; + he_ltf = HE_LTF_2_X; + break; + case 3: + if (he_dcm && he_stbc) { + he_gi = HE_GI_0_8; + he_ltf = HE_LTF_4_X; + } else { + he_gi = HE_GI_3_2; + he_ltf = HE_LTF_4_X; + } + break; + } + ppdu_info->rx_status.sgi = he_gi; + ppdu_info->rx_status.ltf_size = he_ltf; + hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); + value = he_gi << QDF_MON_STATUS_GI_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); + value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, + PACKET_EXTENSION_A_FACTOR); + value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, TXBF); + value = value << QDF_MON_STATUS_TXBF_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, + PACKET_EXTENSION_PE_DISAMBIGUITY); + value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + /* data6 */ + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_0, NSTS); + value++; + ppdu_info->rx_status.nss = value; + ppdu_info->rx_status.he_data6 = value; + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, + DOPPLER_INDICATION); + value = value << QDF_MON_STATUS_DOPPLER_SHIFT; + ppdu_info->rx_status.he_data6 |= value; + value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO_1, + TXOP_DURATION); + value = value << QDF_MON_STATUS_TXOP_SHIFT; + ppdu_info->rx_status.he_data6 |= value; + + ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, + HE_SIG_A_SU_INFO_1, TXBF); + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; + hal_rx_get_crc_he_sig_a_su_info(ppdu_info, he_sig_a_su_info); + break; + } + case WIFIPHYRX_HE_SIG_A_MU_DL_E: + { + uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, + HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); + + ppdu_info->rx_status.he_mu_flags = 1; + + /* HE Flags */ + /*data1*/ + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_MU_FORMAT_TYPE; + ppdu_info->rx_status.he_data1 |= + QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | + QDF_MON_STATUS_HE_DL_UL_KNOWN | + QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | + QDF_MON_STATUS_HE_STBC_KNOWN | + QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | + QDF_MON_STATUS_HE_DOPPLER_KNOWN; + + /* data2 */ + ppdu_info->rx_status.he_data2 = + QDF_MON_STATUS_HE_GI_KNOWN; + ppdu_info->rx_status.he_data2 |= + QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | + QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | + QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | + QDF_MON_STATUS_TXOP_KNOWN | + QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; + + /*data3*/ + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, BSS_COLOR_ID); + ppdu_info->rx_status.he_data3 = value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, DL_UL_FLAG); + value = value << QDF_MON_STATUS_DL_UL_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_1, + LDPC_EXTRA_SYMBOL); + value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_1, STBC); + he_stbc = value; + value = value << QDF_MON_STATUS_STBC_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + /*data4*/ + value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, + SPATIAL_REUSE); + ppdu_info->rx_status.he_data4 = value; + + /*data5*/ + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); + ppdu_info->rx_status.he_data5 = value; + ppdu_info->rx_status.bw = value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, CP_LTF_SIZE); + switch (value) { + case 0: + he_gi = HE_GI_0_8; + he_ltf = HE_LTF_4_X; + break; + case 1: + he_gi = HE_GI_0_8; + he_ltf = HE_LTF_2_X; + break; + case 2: + he_gi = HE_GI_1_6; + he_ltf = HE_LTF_2_X; + break; + case 3: + he_gi = HE_GI_3_2; + he_ltf = HE_LTF_4_X; + break; + } + ppdu_info->rx_status.sgi = he_gi; + ppdu_info->rx_status.ltf_size = he_ltf; + hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); + value = he_gi << QDF_MON_STATUS_GI_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_1, NUM_LTF_SYMBOLS); + value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, + PACKET_EXTENSION_A_FACTOR); + value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, + PACKET_EXTENSION_PE_DISAMBIGUITY); + value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + /*data6*/ + value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_0, + DOPPLER_INDICATION); + value = value << QDF_MON_STATUS_DOPPLER_SHIFT; + ppdu_info->rx_status.he_data6 |= value; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO_1, + TXOP_DURATION); + value = value << QDF_MON_STATUS_TXOP_SHIFT; + ppdu_info->rx_status.he_data6 |= value; + + /* HE-MU Flags */ + /* HE-MU-flags1 */ + ppdu_info->rx_status.he_flags1 = + QDF_MON_STATUS_SIG_B_MCS_KNOWN | + QDF_MON_STATUS_SIG_B_DCM_KNOWN | + QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | + QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | + QDF_MON_STATUS_RU_0_KNOWN; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, MCS_OF_SIG_B); + ppdu_info->rx_status.he_flags1 |= value; + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, DCM_OF_SIG_B); + value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; + ppdu_info->rx_status.he_flags1 |= value; + + /* HE-MU-flags2 */ + ppdu_info->rx_status.he_flags2 = + QDF_MON_STATUS_BW_KNOWN; + + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, TRANSMIT_BW); + ppdu_info->rx_status.he_flags2 |= value; + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, COMP_MODE_SIG_B); + value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; + ppdu_info->rx_status.he_flags2 |= value; + value = HAL_RX_GET(he_sig_a_mu_dl_info, + HE_SIG_A_MU_DL_INFO_0, NUM_SIG_B_SYMBOLS); + value = value - 1; + value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; + ppdu_info->rx_status.he_flags2 |= value; + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; + hal_rx_get_crc_he_sig_a_mu_dl_info(ppdu_info, + he_sig_a_mu_dl_info); + break; + } + case WIFIPHYRX_HE_SIG_B1_MU_E: + { + uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, + HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); + + ppdu_info->rx_status.he_sig_b_common_known |= + QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; + /* TODO: Check on the availability of other fields in + * sig_b_common + */ + + value = HAL_RX_GET(he_sig_b1_mu_info, + HE_SIG_B1_MU_INFO_0, RU_ALLOCATION); + ppdu_info->rx_status.he_RU[0] = value; + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; + break; + } + case WIFIPHYRX_HE_SIG_B2_MU_E: + { + uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, + HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); + /* + * Not all "HE" fields can be updated from + * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E + * to populate rest of the "HE" fields for MU scenarios. + */ + + /* HE-data1 */ + ppdu_info->rx_status.he_data1 |= + QDF_MON_STATUS_HE_MCS_KNOWN | + QDF_MON_STATUS_HE_CODING_KNOWN; + + /* HE-data2 */ + + /* HE-data3 */ + value = HAL_RX_GET(he_sig_b2_mu_info, + HE_SIG_B2_MU_INFO_0, STA_MCS); + ppdu_info->rx_status.mcs = value; + value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_b2_mu_info, + HE_SIG_B2_MU_INFO_0, STA_CODING); + value = value << QDF_MON_STATUS_CODING_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + /* HE-data4 */ + value = HAL_RX_GET(he_sig_b2_mu_info, + HE_SIG_B2_MU_INFO_0, STA_ID); + value = value << QDF_MON_STATUS_STA_ID_SHIFT; + ppdu_info->rx_status.he_data4 |= value; + + /* HE-data5 */ + + /* HE-data6 */ + value = HAL_RX_GET(he_sig_b2_mu_info, + HE_SIG_B2_MU_INFO_0, NSTS); + /* value n indicates n+1 spatial streams */ + value++; + ppdu_info->rx_status.nss = value; + ppdu_info->rx_status.he_data6 |= value; + + break; + } + case WIFIPHYRX_HE_SIG_B2_OFDMA_E: + { + uint8_t *he_sig_b2_ofdma_info = + (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, + HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); + + /* + * Not all "HE" fields can be updated from + * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E + * to populate rest of "HE" fields for MU OFDMA scenarios. + */ + + /* HE-data1 */ + ppdu_info->rx_status.he_data1 |= + QDF_MON_STATUS_HE_MCS_KNOWN | + QDF_MON_STATUS_HE_DCM_KNOWN | + QDF_MON_STATUS_HE_CODING_KNOWN; + + /* HE-data2 */ + ppdu_info->rx_status.he_data2 |= + QDF_MON_STATUS_TXBF_KNOWN; + + /* HE-data3 */ + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, STA_MCS); + ppdu_info->rx_status.mcs = value; + value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, STA_DCM); + he_dcm = value; + value = value << QDF_MON_STATUS_DCM_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, STA_CODING); + value = value << QDF_MON_STATUS_CODING_SHIFT; + ppdu_info->rx_status.he_data3 |= value; + + /* HE-data4 */ + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, STA_ID); + value = value << QDF_MON_STATUS_STA_ID_SHIFT; + ppdu_info->rx_status.he_data4 |= value; + + /* HE-data5 */ + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, TXBF); + value = value << QDF_MON_STATUS_TXBF_SHIFT; + ppdu_info->rx_status.he_data5 |= value; + + /* HE-data6 */ + value = HAL_RX_GET(he_sig_b2_ofdma_info, + HE_SIG_B2_OFDMA_INFO_0, NSTS); + /* value n indicates n+1 spatial streams */ + value++; + ppdu_info->rx_status.nss = value; + ppdu_info->rx_status.he_data6 |= value; + ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; + break; + } + case WIFIPHYRX_RSSI_LEGACY_E: + { + uint8_t reception_type; + int8_t rssi_value; + uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + + HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, + RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); + + ppdu_info->rx_status.rssi_comb = HAL_RX_GET(rx_tlv, + PHYRX_RSSI_LEGACY_35, RSSI_COMB); + ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); + ppdu_info->rx_status.he_re = 0; + + reception_type = HAL_RX_GET(rx_tlv, + PHYRX_RSSI_LEGACY_0, + RECEPTION_TYPE); + switch (reception_type) { + case QDF_RECEPTION_TYPE_ULOFMDA: + ppdu_info->rx_status.reception_type = + HAL_RX_TYPE_MU_OFDMA; + ppdu_info->rx_status.ulofdma_flag = 1; + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; + break; + case QDF_RECEPTION_TYPE_ULMIMO: + ppdu_info->rx_status.reception_type = + HAL_RX_TYPE_MU_MIMO; + ppdu_info->rx_status.he_data1 = + QDF_MON_STATUS_HE_MU_FORMAT_TYPE; + break; + default: + ppdu_info->rx_status.reception_type = + HAL_RX_TYPE_SU; + break; + } + hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_0, RSSI_PRI20_CHAIN0); + ppdu_info->rx_status.rssi[0] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN0: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_2, RSSI_PRI20_CHAIN1); + ppdu_info->rx_status.rssi[1] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN1: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_4, RSSI_PRI20_CHAIN2); + ppdu_info->rx_status.rssi[2] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN2: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_6, RSSI_PRI20_CHAIN3); + ppdu_info->rx_status.rssi[3] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN3: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_8, RSSI_PRI20_CHAIN4); + ppdu_info->rx_status.rssi[4] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN4: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_10, + RSSI_PRI20_CHAIN5); + ppdu_info->rx_status.rssi[5] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN5: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_12, + RSSI_PRI20_CHAIN6); + ppdu_info->rx_status.rssi[6] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN6: %d\n", rssi_value); + + rssi_value = HAL_RX_GET(rssi_info_tlv, + RECEIVE_RSSI_INFO_14, + RSSI_PRI20_CHAIN7); + ppdu_info->rx_status.rssi[7] = rssi_value; + dp_nofl_debug("RSSI_PRI20_CHAIN7: %d\n", rssi_value); + break; + } + case WIFIPHYRX_OTHER_RECEIVE_INFO_E: + hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, + ppdu_info); + break; + case WIFIRX_HEADER_E: + { + struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; + + if (ppdu_info->fcs_ok_cnt >= + HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { + hal_err("Number of MPDUs(%d) per status buff exceeded", + ppdu_info->fcs_ok_cnt); + break; + } + + /* Update first_msdu_payload for every mpdu and increment + * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV + */ + ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = + rx_tlv; + ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; + ppdu_info->msdu_info.first_msdu_payload = rx_tlv; + ppdu_info->msdu_info.payload_len = tlv_len; + ppdu_info->user_id = user_id; + ppdu_info->hdr_len = tlv_len; + ppdu_info->data = rx_tlv; + ppdu_info->data += 4; + + /* for every RX_HEADER TLV increment mpdu_cnt */ + com_info->mpdu_cnt++; + return HAL_TLV_STATUS_HEADER; + } + case WIFIRX_MPDU_START_E: + { + uint8_t *rx_mpdu_start = (uint8_t *)rx_tlv; + uint32_t ppdu_id = HAL_RX_GET_PPDU_ID(rx_mpdu_start); + uint8_t filter_category = 0; + + hal_update_frame_type_cnt(rx_mpdu_start, ppdu_info); + + ppdu_info->nac_info.fc_valid = + HAL_RX_GET_FC_VALID(rx_mpdu_start); + + ppdu_info->nac_info.to_ds_flag = + HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start); + + ppdu_info->nac_info.frame_control = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_14, + MPDU_FRAME_CONTROL_FIELD); + + ppdu_info->sw_frame_group_id = + HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start); + + ppdu_info->rx_user_status[user_id].sw_peer_id = + HAL_RX_GET_SW_PEER_ID(rx_mpdu_start); + + if (ppdu_info->sw_frame_group_id == + HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { + ppdu_info->rx_status.frame_control_info_valid = + ppdu_info->nac_info.fc_valid; + ppdu_info->rx_status.frame_control = + ppdu_info->nac_info.frame_control; + } + + hal_get_mac_addr1(rx_mpdu_start, + ppdu_info); + + ppdu_info->nac_info.mac_addr2_valid = + HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start); + + *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_16, + MAC_ADDR_AD2_15_0); + + *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_17, + MAC_ADDR_AD2_47_16); + + if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { + ppdu_info->rx_status.prev_ppdu_id = ppdu_id; + ppdu_info->rx_status.ppdu_len = + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, + MPDU_LENGTH); + } else { + ppdu_info->rx_status.ppdu_len += + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_13, + MPDU_LENGTH); + } + + filter_category = + HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start); + + if (filter_category == 0) + ppdu_info->rx_status.rxpcu_filter_pass = 1; + else if (filter_category == 1) + ppdu_info->rx_status.monitor_direct_used = 1; + + ppdu_info->nac_info.mcast_bcast = + HAL_RX_GET(rx_mpdu_start, + RX_MPDU_INFO_13, + MCAST_BCAST); + break; + } + case WIFIRX_MPDU_END_E: + ppdu_info->user_id = user_id; + ppdu_info->fcs_err = + HAL_RX_GET(rx_tlv, RX_MPDU_END_1, + FCS_ERR); + return HAL_TLV_STATUS_MPDU_END; + case WIFIRX_MSDU_END_E: + if (user_id < HAL_MAX_UL_MU_USERS) { + ppdu_info->rx_msdu_info[user_id].cce_metadata = + HAL_RX_MSDU_END_CCE_METADATA_GET(rx_tlv); + ppdu_info->rx_msdu_info[user_id].fse_metadata = + HAL_RX_MSDU_END_FSE_METADATA_GET(rx_tlv); + ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = + HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(rx_tlv); + ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = + HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(rx_tlv); + ppdu_info->rx_msdu_info[user_id].flow_idx = + HAL_RX_MSDU_END_FLOW_IDX_GET(rx_tlv); + } + return HAL_TLV_STATUS_MSDU_END; + case 0: + return HAL_TLV_STATUS_PPDU_DONE; + + default: + if (hal_rx_handle_other_tlvs(tlv_tag, rx_tlv, ppdu_info)) + unhandled = false; + else + unhandled = true; + break; + } + + if (!unhandled) + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + "%s TLV type: %d, TLV len:%d %s", + __func__, tlv_tag, tlv_len, + unhandled == true ? "unhandled" : ""); + + qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + rx_tlv, tlv_len); + + return HAL_TLV_STATUS_PPDU_NOT_DONE; +} + +/** + * hal_rx_dump_mpdu_start_tlv_generic_rh: dump RX mpdu_start TLV in structured + * human readable format. + * @mpdustart: pointer the rx_attention TLV in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static inline void hal_rx_dump_mpdu_start_tlv_generic_rh(void *mpdustart, + uint8_t dbg_level) +{ + struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart; + struct rx_mpdu_info *mpdu_info = + (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details; + + hal_verbose_debug( + "rx_mpdu_start tlv (1/5) - " + "rxpcu_mpdu_filter_in_category: %x " + "sw_frame_group_id: %x " + "ndp_frame: %x " + "phy_err: %x " + "phy_err_during_mpdu_header: %x " + "protocol_version_err: %x " + "ast_based_lookup_valid: %x " + "phy_ppdu_id: %x " + "ast_index: %x " + "sw_peer_id: %x " + "mpdu_frame_control_valid: %x " + "mpdu_duration_valid: %x " + "mac_addr_ad1_valid: %x " + "mac_addr_ad2_valid: %x " + "mac_addr_ad3_valid: %x " + "mac_addr_ad4_valid: %x " + "mpdu_sequence_control_valid: %x " + "mpdu_qos_control_valid: %x " + "mpdu_ht_control_valid: %x " + "frame_encryption_info_valid: %x ", + mpdu_info->rxpcu_mpdu_filter_in_category, + mpdu_info->sw_frame_group_id, + mpdu_info->ndp_frame, + mpdu_info->phy_err, + mpdu_info->phy_err_during_mpdu_header, + mpdu_info->protocol_version_err, + mpdu_info->ast_based_lookup_valid, + mpdu_info->phy_ppdu_id, + mpdu_info->ast_index, + mpdu_info->sw_peer_id, + mpdu_info->mpdu_frame_control_valid, + mpdu_info->mpdu_duration_valid, + mpdu_info->mac_addr_ad1_valid, + mpdu_info->mac_addr_ad2_valid, + mpdu_info->mac_addr_ad3_valid, + mpdu_info->mac_addr_ad4_valid, + mpdu_info->mpdu_sequence_control_valid, + mpdu_info->mpdu_qos_control_valid, + mpdu_info->mpdu_ht_control_valid, + mpdu_info->frame_encryption_info_valid); + + hal_verbose_debug( + "rx_mpdu_start tlv (2/5) - " + "fr_ds: %x " + "to_ds: %x " + "encrypted: %x " + "mpdu_retry: %x " + "mpdu_sequence_number: %x " + "epd_en: %x " + "all_frames_shall_be_encrypted: %x " + "encrypt_type: %x " + "bssid_hit: %x " + "bssid_number: %x " + "tid: %x " + "pn_31_0: %x " + "pn_63_32: %x " + "pn_95_64: %x " + "pn_127_96: %x " + "peer_meta_data: %x " + "rxpt_classify_info.reo_destination_indication: %x " + "rxpt_classify_info.use_flow_id_toeplitz_clfy: %x " + "rx_reo_queue_desc_addr_31_0: %x ", + mpdu_info->fr_ds, + mpdu_info->to_ds, + mpdu_info->encrypted, + mpdu_info->mpdu_retry, + mpdu_info->mpdu_sequence_number, + mpdu_info->epd_en, + mpdu_info->all_frames_shall_be_encrypted, + mpdu_info->encrypt_type, + mpdu_info->bssid_hit, + mpdu_info->bssid_number, + mpdu_info->tid, + mpdu_info->pn_31_0, + mpdu_info->pn_63_32, + mpdu_info->pn_95_64, + mpdu_info->pn_127_96, + mpdu_info->peer_meta_data, + mpdu_info->rxpt_classify_info_details.reo_destination_indication, + mpdu_info->rxpt_classify_info_details.use_flow_id_toeplitz_clfy, + mpdu_info->rx_reo_queue_desc_addr_31_0); + + hal_verbose_debug( + "rx_mpdu_start tlv (3/5) - " + "rx_reo_queue_desc_addr_39_32: %x " + "receive_queue_number: %x " + "pre_delim_err_warning: %x " + "first_delim_err: %x " + "key_id_octet: %x " + "new_peer_entry: %x " + "decrypt_needed: %x " + "decap_type: %x " + "rx_insert_vlan_c_tag_padding: %x " + "rx_insert_vlan_s_tag_padding: %x " + "strip_vlan_c_tag_decap: %x " + "strip_vlan_s_tag_decap: %x " + "pre_delim_count: %x " + "ampdu_flag: %x " + "bar_frame: %x " + "mpdu_length: %x " + "first_mpdu: %x " + "mcast_bcast: %x " + "ast_index_not_found: %x " + "ast_index_timeout: %x ", + mpdu_info->rx_reo_queue_desc_addr_39_32, + mpdu_info->receive_queue_number, + mpdu_info->pre_delim_err_warning, + mpdu_info->first_delim_err, + mpdu_info->key_id_octet, + mpdu_info->new_peer_entry, + mpdu_info->decrypt_needed, + mpdu_info->decap_type, + mpdu_info->rx_insert_vlan_c_tag_padding, + mpdu_info->rx_insert_vlan_s_tag_padding, + mpdu_info->strip_vlan_c_tag_decap, + mpdu_info->strip_vlan_s_tag_decap, + mpdu_info->pre_delim_count, + mpdu_info->ampdu_flag, + mpdu_info->bar_frame, + mpdu_info->mpdu_length, + mpdu_info->first_mpdu, + mpdu_info->mcast_bcast, + mpdu_info->ast_index_not_found, + mpdu_info->ast_index_timeout); + + hal_verbose_debug( + "rx_mpdu_start tlv (4/5) - " + "power_mgmt: %x " + "non_qos: %x " + "null_data: %x " + "mgmt_type: %x " + "ctrl_type: %x " + "more_data: %x " + "eosp: %x " + "fragment_flag: %x " + "order: %x " + "u_apsd_trigger: %x " + "encrypt_required: %x " + "directed: %x " + "mpdu_frame_control_field: %x " + "mpdu_duration_field: %x " + "mac_addr_ad1_31_0: %x " + "mac_addr_ad1_47_32: %x " + "mac_addr_ad2_15_0: %x " + "mac_addr_ad2_47_16: %x " + "mac_addr_ad3_31_0: %x " + "mac_addr_ad3_47_32: %x ", + mpdu_info->power_mgmt, + mpdu_info->non_qos, + mpdu_info->null_data, + mpdu_info->mgmt_type, + mpdu_info->ctrl_type, + mpdu_info->more_data, + mpdu_info->eosp, + mpdu_info->fragment_flag, + mpdu_info->order, + mpdu_info->u_apsd_trigger, + mpdu_info->encrypt_required, + mpdu_info->directed, + mpdu_info->mpdu_frame_control_field, + mpdu_info->mpdu_duration_field, + mpdu_info->mac_addr_ad1_31_0, + mpdu_info->mac_addr_ad1_47_32, + mpdu_info->mac_addr_ad2_15_0, + mpdu_info->mac_addr_ad2_47_16, + mpdu_info->mac_addr_ad3_31_0, + mpdu_info->mac_addr_ad3_47_32); + + hal_verbose_debug( + "rx_mpdu_start tlv (5/5) - " + "mpdu_sequence_control_field: %x " + "mac_addr_ad4_31_0: %x " + "mac_addr_ad4_47_32: %x " + "mpdu_qos_control_field: %x " + "mpdu_ht_control_field: %x ", + mpdu_info->mpdu_sequence_control_field, + mpdu_info->mac_addr_ad4_31_0, + mpdu_info->mac_addr_ad4_47_32, + mpdu_info->mpdu_qos_control_field, + mpdu_info->mpdu_ht_control_field); +} + +static void +hal_tx_set_pcp_tid_map_generic_rh(struct hal_soc *soc, uint8_t *map) +{ +} + +static void +hal_tx_update_pcp_tid_generic_rh(struct hal_soc *soc, + uint8_t pcp, uint8_t tid) +{ +} + +static void +hal_tx_update_tidmap_prty_generic_rh(struct hal_soc *soc, uint8_t value) +{ +} + +/** + * hal_rx_msdu_packet_metadata_get_generic_rh(): API to get the + * msdu information from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * @pkt_msdu_metadata: pointer to the msdu metadata + */ +static void +hal_rx_msdu_packet_metadata_get_generic_rh(uint8_t *buf, + void *pkt_msdu_metadata) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + struct hal_rx_msdu_metadata *msdu_metadata = + (struct hal_rx_msdu_metadata *)pkt_msdu_metadata; + + msdu_metadata->l3_hdr_pad = + HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); + msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); + msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); + msdu_metadata->sa_sw_peer_id = + HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); +} + +/** + * hal_rx_msdu_end_offset_get_generic(): API to get the + * msdu_end structure offset rx_pkt_tlv structure + * + * NOTE: API returns offset of msdu_end TLV from structure + * rx_pkt_tlvs + */ +static uint32_t hal_rx_msdu_end_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(msdu_end_tlv); +} + +/** + * hal_rx_attn_offset_get_generic(): API to get the + * msdu_end structure offset rx_pkt_tlv structure + * + * NOTE: API returns offset of attn TLV from structure + * rx_pkt_tlvs + */ +static uint32_t hal_rx_attn_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(attn_tlv); +} + +/** + * hal_rx_msdu_start_offset_get_generic(): API to get the + * msdu_start structure offset rx_pkt_tlv structure + * + * NOTE: API returns offset of attn TLV from structure + * rx_pkt_tlvs + */ +static uint32_t hal_rx_msdu_start_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(msdu_start_tlv); +} + +/** + * hal_rx_mpdu_start_offset_get_generic(): API to get the + * mpdu_start structure offset rx_pkt_tlv structure + * + * NOTE: API returns offset of attn TLV from structure + * rx_pkt_tlvs + */ +static uint32_t hal_rx_mpdu_start_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(mpdu_start_tlv); +} + +/** + * hal_rx_mpdu_end_offset_get_generic(): API to get the + * mpdu_end structure offset rx_pkt_tlv structure + * + * NOTE: API returns offset of attn TLV from structure + * rx_pkt_tlvs + */ +static uint32_t hal_rx_mpdu_end_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(mpdu_end_tlv); +} + +#ifndef NO_RX_PKT_HDR_TLV +static uint32_t hal_rx_pkt_tlv_offset_get_generic(void) +{ + return RX_PKT_TLV_OFFSET(pkt_hdr_tlv); +} +#endif + +#ifdef TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET +/** + * hal_tx_desc_set_search_type_generic_rh - Set the search type value + * @desc: Handle to Tx Descriptor + * @search_type: search type + * 0 – Normal search + * 1 – Index based address search + * 2 – Index based flow search + * + * Return: void + */ +static inline +void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_2, SEARCH_TYPE) |= + HAL_TX_SM(TCL_DATA_CMD_2, SEARCH_TYPE, search_type); +} +#else +static inline +void hal_tx_desc_set_search_type_generic_rh(void *desc, uint8_t search_type) +{ +} + +#endif + +#ifdef TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET +/** + * hal_tx_desc_set_search_index_generic_rh - Set the search index value + * @desc: Handle to Tx Descriptor + * @search_index: The index that will be used for index based address or + * flow search. The field is valid when 'search_type' is + * 1 0r 2 + * + * Return: void + */ +static inline +void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_5, SEARCH_INDEX) |= + HAL_TX_SM(TCL_DATA_CMD_5, SEARCH_INDEX, search_index); +} +#else +static inline +void hal_tx_desc_set_search_index_generic_rh(void *desc, uint32_t search_index) +{ +} +#endif + +#ifdef TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET +/** + * hal_tx_desc_set_cache_set_num_generic_rh - Set the cache-set-num value + * @desc: Handle to Tx Descriptor + * @cache_num: Cache set number that should be used to cache the index + * based search results, for address and flow search. + * This value should be equal to LSB four bits of the hash value + * of match data, in case of search index points to an entry + * which may be used in content based search also. The value can + * be anything when the entry pointed by search index will not be + * used for content based search. + * + * Return: void + */ +static inline +void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_5, CACHE_SET_NUM) |= + HAL_TX_SM(TCL_DATA_CMD_5, CACHE_SET_NUM, cache_num); +} +#else +static inline +void hal_tx_desc_set_cache_set_num_generic_rh(void *desc, uint8_t cache_num) +{ +} +#endif + +#ifdef WLAN_SUPPORT_RX_FISA +/** + * hal_rx_flow_get_tuple_info_rh() - Setup a flow search entry in HW FST + * @rx_fst: Pointer to the Rx Flow Search Table + * @hal_hash: HAL 5 tuple hash + * @flow_tuple_info: 5-tuple info of the flow returned to the caller + * + * Return: Success/Failure + */ +static void * +hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash, + uint8_t *flow_tuple_info) +{ + struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; + void *hal_fse = NULL; + struct hal_flow_tuple_info *tuple_info + = (struct hal_flow_tuple_info *)flow_tuple_info; + + hal_fse = (uint8_t *)fst->base_vaddr + + (hal_hash * HAL_RX_FST_ENTRY_SIZE); + + if (!hal_fse || !tuple_info) + return NULL; + + if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) + return NULL; + + tuple_info->src_ip_127_96 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_0, + SRC_IP_127_96)); + tuple_info->src_ip_95_64 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_1, + SRC_IP_95_64)); + tuple_info->src_ip_63_32 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_2, + SRC_IP_63_32)); + tuple_info->src_ip_31_0 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_3, + SRC_IP_31_0)); + tuple_info->dest_ip_127_96 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_4, + DEST_IP_127_96)); + tuple_info->dest_ip_95_64 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_5, + DEST_IP_95_64)); + tuple_info->dest_ip_63_32 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_6, + DEST_IP_63_32)); + tuple_info->dest_ip_31_0 = + qdf_ntohl(HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_7, + DEST_IP_31_0)); + tuple_info->dest_port = HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_8, + DEST_PORT); + tuple_info->src_port = HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_8, + SRC_PORT); + tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, + RX_FLOW_SEARCH_ENTRY_9, + L4_PROTOCOL); + + return hal_fse; +} + +/** + * hal_rx_flow_delete_entry_rh() - Setup a flow search entry in HW FST + * @rx_fst: Pointer to the Rx Flow Search Table + * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST + * + * Return: Success/Failure + */ +static QDF_STATUS +hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse) +{ + uint8_t *fse = (uint8_t *)hal_rx_fse; + + if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID)) + return QDF_STATUS_E_NOENT; + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); + + return QDF_STATUS_SUCCESS; +} + +/** + * hal_rx_fst_get_fse_size_rh() - Retrieve the size of each entry + * + * Return: size of each entry/flow in Rx FST + */ +static inline uint32_t +hal_rx_fst_get_fse_size_rh(void) +{ + return HAL_RX_FST_ENTRY_SIZE; +} +#else +static inline void * +hal_rx_flow_get_tuple_info_rh(uint8_t *rx_fst, uint32_t hal_hash, + uint8_t *flow_tuple_info) +{ + return NULL; +} + +static inline QDF_STATUS +hal_rx_flow_delete_entry_rh(uint8_t *rx_fst, void *hal_rx_fse) +{ + return QDF_STATUS_SUCCESS; +} + +static inline uint32_t +hal_rx_fst_get_fse_size_rh(void) +{ + return 0; +} +#endif /* WLAN_SUPPORT_RX_FISA */ + +/** + * hal_rx_get_frame_ctrl_field_rh(): Function to retrieve frame control field + * + * @buf: Network buffer + * + * Returns: rx more fragment bit + */ +static uint16_t hal_rx_get_frame_ctrl_field_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + uint16_t frame_ctrl = 0; + + frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); + + return frame_ctrl; +} +#endif /* _HAL_RH_GENERIC_API_H_ */ diff --git a/hal/wifi3.0/rh/hal_rh_rx.h b/hal/wifi3.0/rh/hal_rh_rx.h new file mode 100644 index 0000000000..044342ac31 --- /dev/null +++ b/hal/wifi3.0/rh/hal_rh_rx.h @@ -0,0 +1,838 @@ +/* + * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_RH_RX_H_ +#define _HAL_RH_RX_H_ + +#include + +/* + * macro to set the cookie into the rxdma ring entry + */ +#define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \ + ((*(((unsigned int *)buff_addr_info) + \ + (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \ + ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \ + ((*(((unsigned int *)buff_addr_info) + \ + (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \ + ((cookie) << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \ + BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK) + +/* + * macro to set the manager into the rxdma ring entry + */ +#define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \ + ((*(((unsigned int *)buff_addr_info) + \ + (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \ + ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \ + ((*(((unsigned int *)buff_addr_info) + \ + (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \ + ((manager) << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \ + BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK) + +/* + * NOTE: None of the following _GET macros need a right + * shift by the corresponding _LSB. This is because, they are + * finally taken and "OR'ed" into a single word again. + */ + +#define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK) + +#define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK) + +#define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK) + +#define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK) + +#define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK) + +#define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \ + ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \ + RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \ + RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK) + +/* + * Structures & Macros to obtain fields from the TLV's in the Rx packet + * pre-header. + */ + +/* + * Every Rx packet starts at an offset from the top of the buffer. + * If the host hasn't subscribed to any specific TLV, there is + * still space reserved for the following TLV's from the start of + * the buffer: + * -- RX ATTENTION + * -- RX MPDU START + * -- RX MSDU START + * -- RX MSDU END + * -- RX MPDU END + * -- RX PACKET HEADER (802.11) + * If the host subscribes to any of the TLV's above, that TLV + * if populated by the HW + */ + +#define NUM_DWORDS_TAG 1 + +/* By default the packet header TLV is 128 bytes */ +#define NUM_OF_BYTES_RX_802_11_HDR_TLV 128 +#define NUM_OF_DWORDS_RX_802_11_HDR_TLV \ + (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2) + +#define RX_PKT_OFFSET_WORDS \ + ( \ + NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \ + NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \ + NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \ + NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \ + NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \ + NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \ + ) + +#define RX_PKT_OFFSET_BYTES \ + (RX_PKT_OFFSET_WORDS << 2) + +#define RX_PKT_HDR_TLV_LEN 120 + +/* + * Each RX descriptor TLV is preceded by 1 DWORD "tag" + */ +struct rx_attention_tlv { + uint32_t tag; + struct rx_attention rx_attn; +}; + +struct rx_mpdu_start_tlv { + uint32_t tag; + struct rx_mpdu_start rx_mpdu_start; +}; + +struct rx_msdu_start_tlv { + uint32_t tag; + struct rx_msdu_start rx_msdu_start; +}; + +struct rx_msdu_end_tlv { + uint32_t tag; + struct rx_msdu_end rx_msdu_end; +}; + +struct rx_mpdu_end_tlv { + uint32_t tag; + struct rx_mpdu_end rx_mpdu_end; +}; + +struct rx_pkt_hdr_tlv { + uint32_t tag; /* 4 B */ + uint32_t phy_ppdu_id; /* 4 B */ + char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */ +}; + +/* rx_pkt_tlvs structure should be used to process Data buffers, monitor status + * buffers, monitor destination buffers and monitor descriptor buffers. + */ +#ifdef RXDMA_OPTIMIZATION +/* + * The RX_PADDING_BYTES is required so that the TLV's don't + * spread across the 128 byte boundary + * RXDMA optimization requires: + * 1) MSDU_END & ATTENTION TLV's follow in that order + * 2) TLV's don't span across 128 byte lines + * 3) Rx Buffer is nicely aligned on the 128 byte boundary + */ +#define RX_PADDING0_BYTES 4 +#define RX_PADDING1_BYTES 16 +struct rx_pkt_tlvs { + struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ + struct rx_attention_tlv attn_tlv; /* 16 bytes */ + struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ + uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ + struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ + struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ + uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ +#ifndef NO_RX_PKT_HDR_TLV + struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ +#endif +}; +#else /* RXDMA_OPTIMIZATION */ +struct rx_pkt_tlvs { + struct rx_attention_tlv attn_tlv; + struct rx_mpdu_start_tlv mpdu_start_tlv; + struct rx_msdu_start_tlv msdu_start_tlv; + struct rx_msdu_end_tlv msdu_end_tlv; + struct rx_mpdu_end_tlv mpdu_end_tlv; + struct rx_pkt_hdr_tlv pkt_hdr_tlv; +}; +#endif /* RXDMA_OPTIMIZATION */ + +/* rx_mon_pkt_tlvs structure should be used to process monitor data buffers */ +#ifdef RXDMA_OPTIMIZATION +struct rx_mon_pkt_tlvs { + struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */ + struct rx_attention_tlv attn_tlv; /* 16 bytes */ + struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */ + uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */ + struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */ + struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */ + uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */ + struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */ +}; +#else /* RXDMA_OPTIMIZATION */ +struct rx_mon_pkt_tlvs { + struct rx_attention_tlv attn_tlv; + struct rx_mpdu_start_tlv mpdu_start_tlv; + struct rx_msdu_start_tlv msdu_start_tlv; + struct rx_msdu_end_tlv msdu_end_tlv; + struct rx_mpdu_end_tlv mpdu_end_tlv; + struct rx_pkt_hdr_tlv pkt_hdr_tlv; +}; +#endif + +#define SIZE_OF_MONITOR_TLV sizeof(struct rx_mon_pkt_tlvs) +#define SIZE_OF_DATA_RX_TLV sizeof(struct rx_pkt_tlvs) + +#define RX_PKT_TLVS_LEN SIZE_OF_DATA_RX_TLV + +#define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field) + +#define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \ + RX_PKT_TLV_OFFSET(mpdu_start_tlv) +#define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv) +#define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \ + RX_PKT_TLV_OFFSET(msdu_start_tlv) +#define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv) +#define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv) +#define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv) + +/** + * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf + * + * @rx_buf_start: Pointer to data buffer field + * + * Returns: pointer to rx_pkt_tlvs + */ +static inline +struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start) +{ + return (struct rx_pkt_tlvs *)rx_buf_start; +} + +/** + * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs + * + * @pkt_tlvs: Pointer to pkt_tlvs + * Returns: pointer to rx_mpdu_info structure + */ +static inline +struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs) +{ + return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; +} + +/** + * hal_rx_mon_dest_get_buffer_info_from_tlv(): Retrieve mon dest frame info + * from the reserved bytes of rx_tlv_hdr. + * @buf: start of rx_tlv_hdr + * @buf_info: hal_rx_mon_dest_buf_info structure + * + * Return: void + */ +static inline void hal_rx_mon_dest_get_buffer_info_from_tlv( + uint8_t *buf, + struct hal_rx_mon_dest_buf_info *buf_info) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + + qdf_mem_copy(buf_info, pkt_tlvs->rx_padding0, + sizeof(struct hal_rx_mon_dest_buf_info)); +} + +/* + * Get msdu_done bit from the RX_ATTENTION TLV + */ +#define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_2_MSDU_DONE_OFFSET)), \ + RX_ATTENTION_2_MSDU_DONE_MASK, \ + RX_ATTENTION_2_MSDU_DONE_LSB)) + +#define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \ + RX_ATTENTION_1_FIRST_MPDU_MASK, \ + RX_ATTENTION_1_FIRST_MPDU_LSB)) + +#define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \ + RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \ + RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB)) + +/* + * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit + * from rx attention + * @buf: pointer to rx_pkt_tlvs + * + * Return: tcp_udp_cksum_fail + */ +static inline bool +hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint8_t tcp_udp_cksum_fail; + + tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn); + + return !!tcp_udp_cksum_fail; +} + +#define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \ + RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \ + RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB)) + +/* + * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit + * from rx attention + * @buf: pointer to rx_pkt_tlvs + * + * Return: ip_cksum_fail + */ +static inline bool +hal_rx_attn_ip_cksum_fail_get(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint8_t ip_cksum_fail; + + ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn); + + return !!ip_cksum_fail; +} + +#define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \ + RX_ATTENTION_0_PHY_PPDU_ID_MASK, \ + RX_ATTENTION_0_PHY_PPDU_ID_LSB)) + +#define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_1_CCE_MATCH_OFFSET)), \ + RX_ATTENTION_1_CCE_MATCH_MASK, \ + RX_ATTENTION_1_CCE_MATCH_LSB)) + +/* + * hal_rx_msdu_cce_match_get_rh(): get CCE match bit + * from rx attention + * @buf: pointer to rx_pkt_tlvs + * Return: CCE match value + */ +static inline bool +hal_rx_msdu_cce_match_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint8_t cce_match_val; + + cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn); + return !!cce_match_val; +} + +/* + * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START + */ +#define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \ + RX_MPDU_INFO_8_PEER_META_DATA_MASK, \ + RX_MPDU_INFO_8_PEER_META_DATA_LSB)) + +static inline uint32_t +hal_rx_mpdu_peer_meta_data_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + uint32_t peer_meta_data; + + peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info); + + return peer_meta_data; +} + +#define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \ + RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \ + RX_MPDU_INFO_12_AMPDU_FLAG_LSB)) + +/* + * LRO information needed from the TLVs + */ +#define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \ + RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \ + RX_MSDU_END_9_LRO_ELIGIBLE_LSB)) + +#define HAL_RX_TLV_GET_TCP_ACK(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \ + RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \ + RX_MSDU_END_8_TCP_ACK_NUMBER_LSB)) + +#define HAL_RX_TLV_GET_TCP_SEQ(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \ + RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \ + RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB)) + +#define HAL_RX_TLV_GET_TCP_WIN(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \ + RX_MSDU_END_9_WINDOW_SIZE_MASK, \ + RX_MSDU_END_9_WINDOW_SIZE_LSB)) + +#define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \ + RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \ + RX_MSDU_START_2_TCP_ONLY_ACK_LSB)) + +#define HAL_RX_TLV_GET_TCP_PROTO(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_2_TCP_PROTO_OFFSET)), \ + RX_MSDU_START_2_TCP_PROTO_MASK, \ + RX_MSDU_START_2_TCP_PROTO_LSB)) + +#define HAL_RX_TLV_GET_UDP_PROTO(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_2_UDP_PROTO_OFFSET)), \ + RX_MSDU_START_2_UDP_PROTO_MASK, \ + RX_MSDU_START_2_UDP_PROTO_LSB)) + +#define HAL_RX_TLV_GET_IPV6(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \ + RX_MSDU_START_2_IPV6_PROTO_MASK, \ + RX_MSDU_START_2_IPV6_PROTO_LSB)) + +#define HAL_RX_TLV_GET_IP_OFFSET(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_1_L3_OFFSET_OFFSET)), \ + RX_MSDU_START_1_L3_OFFSET_MASK, \ + RX_MSDU_START_1_L3_OFFSET_LSB)) + +#define HAL_RX_TLV_GET_TCP_OFFSET(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_1_L4_OFFSET_OFFSET)), \ + RX_MSDU_START_1_L4_OFFSET_MASK, \ + RX_MSDU_START_1_L4_OFFSET_LSB)) + +#define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_start_tlv.rx_msdu_start), \ + RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \ + RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \ + RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB)) + +#define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ + RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \ + RX_MSDU_START_1_MSDU_LENGTH_MASK, \ + RX_MSDU_START_1_MSDU_LENGTH_LSB)) + +#define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ + RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \ + RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \ + RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB)) + +#define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ + RX_MSDU_START_5_SGI_OFFSET)), \ + RX_MSDU_START_5_SGI_MASK, \ + RX_MSDU_START_5_SGI_LSB)) + +#define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ + RX_MSDU_START_5_RATE_MCS_OFFSET)), \ + RX_MSDU_START_5_RATE_MCS_MASK, \ + RX_MSDU_START_5_RATE_MCS_LSB)) + +#define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \ + RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \ + RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB)) + +/* + * Get key index from RX_MSDU_END + */ +#define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \ + RX_MSDU_END_2_KEY_ID_OCTET_MASK, \ + RX_MSDU_END_2_KEY_ID_OCTET_LSB)) + +#define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ + RX_MSDU_START_5_USER_RSSI_OFFSET)), \ + RX_MSDU_START_5_USER_RSSI_MASK, \ + RX_MSDU_START_5_USER_RSSI_LSB)) + +#define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ + RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \ + RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \ + RX_MSDU_START_7_SW_PHY_META_DATA_LSB)) + +#define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \ + RX_MSDU_START_5_PKT_TYPE_OFFSET)), \ + RX_MSDU_START_5_PKT_TYPE_MASK, \ + RX_MSDU_START_5_PKT_TYPE_LSB)) + +#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) + +#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) + +/******************************************************************************* + * RX ERROR APIS + ******************************************************************************/ + +#define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ + RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \ + RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \ + RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB)) + +#define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\ + RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \ + RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \ + RX_MPDU_END_1_TKIP_MIC_ERR_LSB)) + +/** + * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured + * humman readable format. + * @rx_attn: pointer the rx_attention TLV in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn, + uint8_t dbg_level) +{ + hal_verbose_debug("rx_attention tlv (1/2) - " + "rxpcu_mpdu_filter_in_category: %x " + "sw_frame_group_id: %x " + "reserved_0: %x " + "phy_ppdu_id: %x " + "first_mpdu : %x " + "reserved_1a: %x " + "mcast_bcast: %x " + "ast_index_not_found: %x " + "ast_index_timeout: %x " + "power_mgmt: %x " + "non_qos: %x " + "null_data: %x " + "mgmt_type: %x " + "ctrl_type: %x " + "more_data: %x " + "eosp: %x " + "a_msdu_error: %x " + "fragment_flag: %x " + "order: %x " + "cce_match: %x " + "overflow_err: %x " + "msdu_length_err: %x " + "tcp_udp_chksum_fail: %x " + "ip_chksum_fail: %x " + "sa_idx_invalid: %x " + "da_idx_invalid: %x " + "reserved_1b: %x " + "rx_in_tx_decrypt_byp: %x ", + rx_attn->rxpcu_mpdu_filter_in_category, + rx_attn->sw_frame_group_id, + rx_attn->reserved_0, + rx_attn->phy_ppdu_id, + rx_attn->first_mpdu, + rx_attn->reserved_1a, + rx_attn->mcast_bcast, + rx_attn->ast_index_not_found, + rx_attn->ast_index_timeout, + rx_attn->power_mgmt, + rx_attn->non_qos, + rx_attn->null_data, + rx_attn->mgmt_type, + rx_attn->ctrl_type, + rx_attn->more_data, + rx_attn->eosp, + rx_attn->a_msdu_error, + rx_attn->fragment_flag, + rx_attn->order, + rx_attn->cce_match, + rx_attn->overflow_err, + rx_attn->msdu_length_err, + rx_attn->tcp_udp_chksum_fail, + rx_attn->ip_chksum_fail, + rx_attn->sa_idx_invalid, + rx_attn->da_idx_invalid, + rx_attn->reserved_1b, + rx_attn->rx_in_tx_decrypt_byp); + + hal_verbose_debug("rx_attention tlv (2/2) - " + "encrypt_required: %x " + "directed: %x " + "buffer_fragment: %x " + "mpdu_length_err: %x " + "tkip_mic_err: %x " + "decrypt_err: %x " + "unencrypted_frame_err: %x " + "fcs_err: %x " + "flow_idx_timeout: %x " + "flow_idx_invalid: %x " + "wifi_parser_error: %x " + "amsdu_parser_error: %x " + "sa_idx_timeout: %x " + "da_idx_timeout: %x " + "msdu_limit_error: %x " + "da_is_valid: %x " + "da_is_mcbc: %x " + "sa_is_valid: %x " + "decrypt_status_code: %x " + "rx_bitmap_not_updated: %x " + "reserved_2: %x " + "msdu_done: %x ", + rx_attn->encrypt_required, + rx_attn->directed, + rx_attn->buffer_fragment, + rx_attn->mpdu_length_err, + rx_attn->tkip_mic_err, + rx_attn->decrypt_err, + rx_attn->unencrypted_frame_err, + rx_attn->fcs_err, + rx_attn->flow_idx_timeout, + rx_attn->flow_idx_invalid, + rx_attn->wifi_parser_error, + rx_attn->amsdu_parser_error, + rx_attn->sa_idx_timeout, + rx_attn->da_idx_timeout, + rx_attn->msdu_limit_error, + rx_attn->da_is_valid, + rx_attn->da_is_mcbc, + rx_attn->sa_is_valid, + rx_attn->decrypt_status_code, + rx_attn->rx_bitmap_not_updated, + rx_attn->reserved_2, + rx_attn->msdu_done); +} + +/** + * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured + * human readable format. + * @mpdu_end: pointer the mpdu_end TLV in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end, + uint8_t dbg_level) +{ + hal_verbose_debug("rx_mpdu_end tlv - " + "rxpcu_mpdu_filter_in_category: %x " + "sw_frame_group_id: %x " + "phy_ppdu_id: %x " + "unsup_ktype_short_frame: %x " + "rx_in_tx_decrypt_byp: %x " + "overflow_err: %x " + "mpdu_length_err: %x " + "tkip_mic_err: %x " + "decrypt_err: %x " + "unencrypted_frame_err: %x " + "pn_fields_contain_valid_info: %x " + "fcs_err: %x " + "msdu_length_err: %x " + "rxdma0_destination_ring: %x " + "rxdma1_destination_ring: %x " + "decrypt_status_code: %x " + "rx_bitmap_not_updated: %x ", + mpdu_end->rxpcu_mpdu_filter_in_category, + mpdu_end->sw_frame_group_id, + mpdu_end->phy_ppdu_id, + mpdu_end->unsup_ktype_short_frame, + mpdu_end->rx_in_tx_decrypt_byp, + mpdu_end->overflow_err, + mpdu_end->mpdu_length_err, + mpdu_end->tkip_mic_err, + mpdu_end->decrypt_err, + mpdu_end->unencrypted_frame_err, + mpdu_end->pn_fields_contain_valid_info, + mpdu_end->fcs_err, + mpdu_end->msdu_length_err, + mpdu_end->rxdma0_destination_ring, + mpdu_end->rxdma1_destination_ring, + mpdu_end->decrypt_status_code, + mpdu_end->rx_bitmap_not_updated); +} + +#ifdef NO_RX_PKT_HDR_TLV +static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, + uint8_t dbg_level) +{ +} +#else +/** + * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format + * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs, + uint8_t dbg_level) +{ + struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv; + + hal_verbose_debug("\n---------------\nrx_pkt_hdr_tlv" + "\n---------------\nphy_ppdu_id %d ", + pkt_hdr_tlv->phy_ppdu_id); + hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128); +} +#endif + +#define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \ + RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \ + RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB)) + +/** + * hal_rx_attn_msdu_done_get_rh() - Get msdi done flag from RX TLV + * @buf: RX tlv address + * + * Return: msdu done flag + */ +static inline uint32_t hal_rx_attn_msdu_done_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + uint32_t msdu_done; + + msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn); + + return msdu_done; +} + +#define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \ + (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \ + HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr)) + +/** + * hal_rx_msdu_flags_get_rh() - Get msdu flags from ring desc + * @msdu_desc_info_hdl: msdu desc info handle + * + * Return: msdu flags + */ + static inline +uint32_t hal_rx_msdu_flags_get_rh(rx_msdu_desc_info_t msdu_desc_info_hdl) +{ + struct rx_msdu_desc_info *msdu_desc_info = + (struct rx_msdu_desc_info *)msdu_desc_info_hdl; + + return HAL_RX_MSDU_FLAGS_GET(msdu_desc_info); +} + +#define HAL_RX_ATTN_MSDU_LEN_ERR_GET(_rx_attn) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \ + RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET)), \ + RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK, \ + RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB)) + +/** + * hal_rx_attn_msdu_len_err_get_rh(): Get msdu_len_err value from + * rx attention tlvs + * @buf: pointer to rx pkt tlvs hdr + * + * Return: msdu_len_err value + */ +static inline uint32_t +hal_rx_attn_msdu_len_err_get_rh(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; + + return HAL_RX_ATTN_MSDU_LEN_ERR_GET(rx_attn); +} +#endif /* _HAL_RH_RX_H_ */ diff --git a/hal/wifi3.0/rh/hal_rh_tx.h b/hal/wifi3.0/rh/hal_rh_tx.h new file mode 100644 index 0000000000..9eeef7e6dd --- /dev/null +++ b/hal/wifi3.0/rh/hal_rh_tx.h @@ -0,0 +1,335 @@ +/* + * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_RH_TX_H_ +#define _HAL_RH_TX_H_ + +/*--------------------------------------------------------------------------- + * Function declarations and documentation + * --------------------------------------------------------------------------- + */ + +/*--------------------------------------------------------------------------- + * TCL Descriptor accessor APIs + * --------------------------------------------------------------------------- + */ + +/** + * hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor + * @hal_soc_hdl: HAL SOC handle + * @desc: Handle to Tx Descriptor + * @paddr: Physical Address + * @pool_id: Return Buffer Manager ID + * @desc_id: Descriptor ID + * @type: 0 - Address points to a MSDU buffer + * 1 - Address points to MSDU extension descriptor + * + * Return: void + */ +static inline +void hal_tx_desc_set_buf_addr(hal_soc_handle_t hal_soc_hdl, void *desc, + dma_addr_t paddr, + uint8_t pool_id, uint32_t desc_id, + uint8_t type) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id, + desc_id, type); +} + +/** + * hal_tx_desc_set_lmac_id - Set the lmac_id value + * @hal_soc_hdl: HAL SOC handle + * @desc: Handle to Tx Descriptor + * @lmac_id: mac Id to ast matching + * b00 – mac 0 + * b01 – mac 1 + * b10 – mac 2 + * b11 – all macs (legacy HK way) + * + * Return: void + */ +static inline void hal_tx_desc_set_lmac_id(hal_soc_handle_t hal_soc_hdl, + void *desc, uint8_t lmac_id) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id); +} + +/** + * hal_tx_desc_set_search_type - Set the search type value + * @hal_soc_hdl: HAL SOC handle + * @desc: Handle to Tx Descriptor + * @search_type: search type + * 0 – Normal search + * 1 – Index based address search + * 2 – Index based flow search + * + * Return: void + */ +static inline void hal_tx_desc_set_search_type(hal_soc_handle_t hal_soc_hdl, + void *desc, + uint8_t search_type) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_search_type(desc, search_type); +} + +/** + * hal_tx_desc_set_search_index - Set the search index value + * @hal_soc_hdl: HAL SOC handle + * @desc: Handle to Tx Descriptor + * @search_index: The index that will be used for index based address or + * flow search. The field is valid when 'search_type' is + * 1 0r 2 + * + * Return: void + */ +static inline void hal_tx_desc_set_search_index(hal_soc_handle_t hal_soc_hdl, + void *desc, + uint32_t search_index) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_search_index(desc, search_index); +} + +/** + * hal_tx_desc_set_cache_set_num - Set the cache-set-num value + * @hal_soc_hdl: HAL SOC handle + * @desc: Handle to Tx Descriptor + * @cache_num: Cache set number that should be used to cache the index + * based search results, for address and flow search. + * This value should be equal to LSB four bits of the hash value + * of match data, in case of search index points to an entry + * which may be used in content based search also. The value can + * be anything when the entry pointed by search index will not be + * used for content based search. + * + * Return: void + */ +static inline void hal_tx_desc_set_cache_set_num(hal_soc_handle_t hal_soc_hdl, + void *desc, + uint8_t cache_num) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_cache_set_num(desc, cache_num); +} + +/** + * hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor + * @desc: Handle to Tx Descriptor + * @data_length: MSDU length in case of direct descriptor. + * Length of link extension descriptor in case of Link extension + * descriptor.Includes the length of Metadata + * Return: None + */ +static inline void hal_tx_desc_set_buf_length(void *desc, + uint16_t data_length) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_3, DATA_LENGTH) |= + HAL_TX_SM(TCL_DATA_CMD_3, DATA_LENGTH, data_length); +} + +/** + * hal_tx_desc_set_buf_offset - Sets Packet Offset field in Tx descriptor + * @desc: Handle to Tx Descriptor + * @offset: Packet offset from Metadata in case of direct buffer descriptor. + * + * Return: void + */ +static inline void hal_tx_desc_set_buf_offset(void *desc, + uint8_t offset) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_3, PACKET_OFFSET) |= + HAL_TX_SM(TCL_DATA_CMD_3, PACKET_OFFSET, offset); +} + +/** + * hal_tx_desc_set_encap_type - Set encapsulation type in Tx Descriptor + * @desc: Handle to Tx Descriptor + * @encap_type: Encapsulation that HW will perform + * + * Return: void + * + */ +static inline void hal_tx_desc_set_encap_type(void *desc, + enum hal_tx_encap_type encap_type) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCAP_TYPE) |= + HAL_TX_SM(TCL_DATA_CMD_2, ENCAP_TYPE, encap_type); +} + +/** + * hal_tx_desc_set_encrypt_type - Sets the Encrypt Type in Tx Descriptor + * @desc: Handle to Tx Descriptor + * @type: Encrypt Type + * + * Return: void + */ +static inline void hal_tx_desc_set_encrypt_type(void *desc, + enum hal_tx_encrypt_type type) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_2, ENCRYPT_TYPE) |= + HAL_TX_SM(TCL_DATA_CMD_2, ENCRYPT_TYPE, type); +} + +/** + * hal_tx_desc_set_addr_search_flags - Enable AddrX and AddrY search flags + * @desc: Handle to Tx Descriptor + * @flags: Bit 0 - AddrY search enable, Bit 1 - AddrX search enable + * + * Return: void + */ +static inline void hal_tx_desc_set_addr_search_flags(void *desc, + uint8_t flags) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRX_EN) |= + HAL_TX_SM(TCL_DATA_CMD_2, ADDRX_EN, (flags & 0x1)); + + HAL_SET_FLD(desc, TCL_DATA_CMD_2, ADDRY_EN) |= + HAL_TX_SM(TCL_DATA_CMD_2, ADDRY_EN, (flags >> 1)); +} + +/** + * hal_tx_desc_set_l4_checksum_en - Set TCP/IP checksum enable flags + * Tx Descriptor for MSDU_buffer type + * @desc: Handle to Tx Descriptor + * @en: UDP/TCP over ipv4/ipv6 checksum enable flags (5 bits) + * + * Return: void + */ +static inline void hal_tx_desc_set_l4_checksum_en(void *desc, + uint8_t en) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= + (HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV4_CHECKSUM_EN, en) | + HAL_TX_SM(TCL_DATA_CMD_3, UDP_OVER_IPV6_CHECKSUM_EN, en) | + HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV4_CHECKSUM_EN, en) | + HAL_TX_SM(TCL_DATA_CMD_3, TCP_OVER_IPV6_CHECKSUM_EN, en)); +} + +/** + * hal_tx_desc_set_l3_checksum_en - Set IPv4 checksum enable flag in + * Tx Descriptor for MSDU_buffer type + * @desc: Handle to Tx Descriptor + * @en: ipv4 checksum enable flags + * + * Return: void + */ +static inline void hal_tx_desc_set_l3_checksum_en(void *desc, + uint8_t en) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_3, IPV4_CHECKSUM_EN) |= + HAL_TX_SM(TCL_DATA_CMD_3, IPV4_CHECKSUM_EN, en); +} + +/** + * hal_tx_desc_set_fw_metadata- Sets the metadata that is part of TCL descriptor + * @desc:Handle to Tx Descriptor + * @metadata: Metadata to be sent to Firmware + * + * Return: void + */ +static inline void hal_tx_desc_set_fw_metadata(void *desc, + uint16_t metadata) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_2, TCL_CMD_NUMBER) |= + HAL_TX_SM(TCL_DATA_CMD_2, TCL_CMD_NUMBER, metadata); +} + +/** + * hal_tx_desc_set_to_fw - Set To_FW bit in Tx Descriptor. + * @desc:Handle to Tx Descriptor + * @to_fw: if set, Forward packet to FW along with classification result + * + * Return: void + */ +static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_3, TO_FW) |= + HAL_TX_SM(TCL_DATA_CMD_3, TO_FW, to_fw); +} + +/** + * hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor + * @hal_soc_hdl: hal soc handle + * @desc: Handle to Tx Descriptor + * @en: For raw WiFi frames, this indicates transmission to a mesh STA, + * enabling the interpretation of the 'Mesh Control Present' bit + * (bit 8) of QoS Control (otherwise this bit is ignored), + * For native WiFi frames, this indicates that a 'Mesh Control' field + * is present between the header and the LLC. + * + * Return: void + */ +static inline void hal_tx_desc_set_mesh_en(hal_soc_handle_t hal_soc_hdl, + void *desc, uint8_t en) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + + hal_soc->ops->hal_tx_desc_set_mesh_en(desc, en); +} + +/** + * hal_tx_desc_set_hlos_tid - Set the TID value (override DSCP/PCP fields in + * frame) to be used for Tx Frame + * @desc: Handle to Tx Descriptor + * @hlos_tid: HLOS TID + * + * Return: void + */ +static inline void hal_tx_desc_set_hlos_tid(void *desc, + uint8_t hlos_tid) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID) |= + HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID, hlos_tid); + + HAL_SET_FLD(desc, TCL_DATA_CMD_4, HLOS_TID_OVERWRITE) |= + HAL_TX_SM(TCL_DATA_CMD_4, HLOS_TID_OVERWRITE, 1); +} + +/** + * hal_tx_desc_clear - Clear the HW descriptor entry + * @hw_desc: Hardware descriptor to be cleared + * + * Return: void + */ +static inline void hal_tx_desc_clear(void *hw_desc) +{ + qdf_mem_set(hw_desc + sizeof(struct tlv_32_hdr), + HAL_TX_DESC_LEN_BYTES, 0); +} + +/** + * hal_tx_desc_sync - Commit the descriptor to Hardware + * @hal_tx_desc_cached: Cached descriptor that software maintains + * @hw_desc: Hardware descriptor to be updated + */ +static inline void hal_tx_desc_sync(void *hal_tx_desc_cached, + void *hw_desc) +{ + qdf_mem_copy((hw_desc + sizeof(struct tlv_32_hdr)), + hal_tx_desc_cached, HAL_TX_DESC_LEN_BYTES); +} +#endif /* _HAL_RH_TX_H_ */ diff --git a/hal/wifi3.0/wcn6450/hal_wcn6450.c b/hal/wifi3.0/wcn6450/hal_wcn6450.c index 280b541dc4..8c08cca675 100644 --- a/hal/wifi3.0/wcn6450/hal_wcn6450.c +++ b/hal/wifi3.0/wcn6450/hal_wcn6450.c @@ -1,4 +1,5 @@ /* + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for @@ -31,6 +32,87 @@ #include "rx_flow_search_entry.h" #include "hal_rx_flow_info.h" +#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ + RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET +#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ + RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK +#define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ + RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB +#define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ + PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET +#define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ + PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET +#define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ + PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET +#define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ + PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET +#define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ + PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET +#define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ + PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET +#define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ + PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET +#define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ + PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET +#define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ + PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET + +#define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ + PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET +#define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ + PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET +#define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ + RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET +#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ + RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET +#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ + RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET +#define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ + RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET +#define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ + REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET +#define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ + UNIFORM_REO_STATUS_HEADER_STATUS_HEADER +#define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ + RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET +#define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ + RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET + +#define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ + TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET +#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ + BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB +#define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ + BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK +#define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ + TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET +#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ + BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB +#define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ + BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK +#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ + BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB +#define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ + BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK +#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ + BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB +#define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ + BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK +#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ + TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET +#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ + TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB +#define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ + TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK + +#include "hal_wcn6450_tx.h" +#include "hal_wcn6450_rx.h" +#include +#include "hal_rh_rx.h" +#include "hal_rh_api.h" +#include "hal_api_mon.h" +#include "hal_rh_generic_api.h" + struct hal_hw_srng_config hw_srng_table_wcn6450[] = { /* TODO: max_rings can populated by querying HW capabilities */ {/* REO_DST */ 0}, @@ -105,6 +187,1757 @@ struct hal_hw_srng_config hw_srng_table_wcn6450[] = { { /* SW2RXDMA_NEW */ 0}, }; +static void hal_get_hw_hptp_6450(struct hal_soc *hal_soc, + hal_ring_handle_t hal_ring_hdl, + uint32_t *headp, uint32_t *tailp, + uint8_t ring) +{ +} + +static void hal_reo_setup_6450(struct hal_soc *soc, void *reoparams, + int qref_reset) +{ +} + +static void hal_reo_set_err_dst_remap_6450(void *hal_soc) +{ +} + +static void hal_tx_desc_set_dscp_tid_table_id_6450(void *desc, uint8_t id) +{ +} + +static void hal_tx_set_dscp_tid_map_6450(struct hal_soc *hal_soc, + uint8_t *map, uint8_t id) +{ +} + +static void hal_tx_update_dscp_tid_6450(struct hal_soc *hal_soc, uint8_t tid, + uint8_t id, uint8_t dscp) +{ +} + +static void hal_tx_comp_get_status_6450(void *desc, void *ts1, + struct hal_soc *hal) +{ +} + +static uint8_t hal_tx_comp_get_release_reason_6450(void *hal_desc) +{ + return 0; +} + +static uint8_t hal_get_wbm_internal_error_6450(void *hal_desc) +{ + return 0; +} + +static void hal_tx_init_cmd_credit_ring_6450(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl) +{ +} + +static uint32_t hal_get_link_desc_size_6450(void) +{ + return 0; +} + +static void hal_reo_status_get_header_6450(hal_ring_desc_t ring_desc, + int b, void *h1) +{ +} + +static void hal_rx_wbm_err_info_get_6450(void *wbm_desc, + void *wbm_er_info1) +{ +} + +static bool hal_rx_is_unicast_6450(uint8_t *buf) +{ + return true; +} + +static uint32_t hal_rx_tid_get_6450(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) +{ + return 0; +} + +static void *hal_rx_msdu0_buffer_addr_lsb_6450(void *link_desc_va) +{ + return NULL; +} + +static void *hal_rx_msdu_desc_info_ptr_get_6450(void *msdu0) +{ + return NULL; +} + +static void *hal_ent_mpdu_desc_info_6450(void *ent_ring_desc) +{ + return NULL; +} + +static void *hal_dst_mpdu_desc_info_6450(void *dst_ring_desc) +{ + return NULL; +} + +static uint8_t hal_rx_get_fc_valid_6450(uint8_t *buf) +{ + return HAL_RX_GET_FC_VALID(buf); +} + +static uint8_t hal_rx_get_to_ds_flag_6450(uint8_t *buf) +{ + return HAL_RX_GET_TO_DS_FLAG(buf); +} + +static uint8_t hal_rx_get_mac_addr2_valid_6450(uint8_t *buf) +{ + return HAL_RX_GET_MAC_ADDR2_VALID(buf); +} + +static uint8_t hal_rx_get_filter_category_6450(uint8_t *buf) +{ + return HAL_RX_GET_FILTER_CATEGORY(buf); +} + +static void hal_reo_config_6450(struct hal_soc *soc, + uint32_t reg_val, + struct hal_reo_params *reo_params) +{ +} + +/** + * hal_rx_msdu_flow_idx_get_6450: API to get flow index + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: flow index value from MSDU END TLV + */ +static inline uint32_t hal_rx_msdu_flow_idx_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); +} + +static void hal_compute_reo_remap_ix2_ix3_6450(uint32_t *ring, + uint32_t num_rings, + uint32_t *remap1, + uint32_t *remap2) +{ +} + +static void +hal_setup_link_idle_list_6450(struct hal_soc *soc, + qdf_dma_addr_t scatter_bufs_base_paddr[], + void *scatter_bufs_base_vaddr[], + uint32_t num_scatter_bufs, + uint32_t scatter_buf_size, + uint32_t last_buf_end_offset, + uint32_t num_entries) +{ +} + +static void hal_compute_reo_remap_ix0_6450(uint32_t *remap0) +{ +} + +/*TODO: update proper values */ +#define CE_WINDOW_REMAP_RANGE 0X37 +#define CMEM_WINDOW_REMAP_RANGE 0x2 + +/** + * hal_get_window_address_6450(): Function to get the ioremap address + * @hal_soc: Pointer to hal_soc + * @addr: address offset of register + * + * Return: modified address offset of register + */ +static inline qdf_iomem_t hal_get_window_address_6450(struct hal_soc *hal_soc, + qdf_iomem_t addr) +{ + uint32_t offset; + uint32_t window; + uint8_t scale; + + offset = addr - hal_soc->dev_base_addr; + window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK; + + /* CE: 2nd window, CMEM: 3rd window, unused: 4th window */ + switch (window) { + case CE_WINDOW_REMAP_RANGE: + scale = 1; + break; + case CMEM_WINDOW_REMAP_RANGE: + scale = 2; + break; + default: + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, + "%s: ERROR: Accessing Wrong register\n", __func__); + qdf_assert_always(0); + return 0; + } + + return hal_soc->dev_base_addr + (scale * WINDOW_START) + + (offset & WINDOW_RANGE_MASK); +} + +/* + * hal_rx_msdu_start_nss_get_6450(): API to get the NSS + * Interval from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(nss) + */ +static uint32_t hal_rx_msdu_start_nss_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint8_t mimo_ss_bitmap; + + mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); + + return qdf_get_hweight8(mimo_ss_bitmap); +} + +/** + * hal_rx_mon_hw_desc_get_mpdu_status_6450(): Retrieve MPDU status + * + * @hw_desc_addr: Start address of Rx HW TLVs + * @rs: Status for monitor mode + * + * Return: void + */ +static void hal_rx_mon_hw_desc_get_mpdu_status_6450(void *hw_desc_addr, + struct mon_rx_status *rs) +{ + struct rx_msdu_start *rx_msdu_start; + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; + uint32_t reg_value; + const uint32_t sgi_hw_to_cdp[] = { + CDP_SGI_0_8_US, + CDP_SGI_0_4_US, + CDP_SGI_1_6_US, + CDP_SGI_3_2_US, + }; + + rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; + + HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); + + rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, + RX_MSDU_START_5, USER_RSSI); + rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); + + reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); + rs->sgi = sgi_hw_to_cdp[reg_value]; + + reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); + rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; + /* TODO: rs->beamformed should be set for SU beamforming also */ +} + +/* + * hal_rx_get_tlv_6450(): API to get the tlv + * + * @rx_tlv: TLV data extracted from the rx packet + * Return: uint8_t + */ +static uint8_t hal_rx_get_tlv_6450(void *rx_tlv) +{ + return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); +} + +/** + * hal_rx_proc_phyrx_other_receive_info_tlv_6450() + * - process other receive info TLV + * @rx_tlv_hdr: pointer to TLV header + * @ppdu_info_handle: pointer to ppdu_info + * + * Return: None + */ +static +void hal_rx_proc_phyrx_other_receive_info_tlv_6450(void *rx_tlv_hdr, + void *ppdu_info_handle) +{ + uint32_t tlv_tag, tlv_len; + uint32_t temp_len, other_tlv_len, other_tlv_tag; + void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; + void *other_tlv_hdr = NULL; + void *other_tlv = NULL; + + tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); + tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); + temp_len = 0; + + other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE; + + other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr); + other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr); + temp_len += other_tlv_len; + other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE; + + switch (other_tlv_tag) { + default: + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, + "%s unhandled TLV type: %d, TLV len:%d", + __func__, other_tlv_tag, other_tlv_len); + break; + } +} + +/** + * hal_rx_dump_msdu_start_tlv_6450() : dump RX msdu_start TLV in structured + * human readable format. + * @msdustart: pointer the msdu_start TLV in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static void hal_rx_dump_msdu_start_tlv_6450(void *msdustart, uint8_t dbg_level) +{ + struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart; + + hal_verbose_debug( + "rx_msdu_start tlv (1/2) - " + "rxpcu_mpdu_filter_in_category: %x " + "sw_frame_group_id: %x " + "phy_ppdu_id: %x " + "msdu_length: %x " + "ipsec_esp: %x " + "l3_offset: %x " + "ipsec_ah: %x " + "l4_offset: %x " + "msdu_number: %x " + "decap_format: %x " + "ipv4_proto: %x " + "ipv6_proto: %x " + "tcp_proto: %x " + "udp_proto: %x " + "ip_frag: %x " + "tcp_only_ack: %x " + "da_is_bcast_mcast: %x " + "ip4_protocol_ip6_next_header: %x " + "toeplitz_hash_2_or_4: %x " + "flow_id_toeplitz: %x " + "user_rssi: %x " + "pkt_type: %x " + "stbc: %x " + "sgi: %x " + "rate_mcs: %x " + "receive_bandwidth: %x " + "reception_type: %x " + "ppdu_start_timestamp: %u ", + msdu_start->rxpcu_mpdu_filter_in_category, + msdu_start->sw_frame_group_id, + msdu_start->phy_ppdu_id, + msdu_start->msdu_length, + msdu_start->ipsec_esp, + msdu_start->l3_offset, + msdu_start->ipsec_ah, + msdu_start->l4_offset, + msdu_start->msdu_number, + msdu_start->decap_format, + msdu_start->ipv4_proto, + msdu_start->ipv6_proto, + msdu_start->tcp_proto, + msdu_start->udp_proto, + msdu_start->ip_frag, + msdu_start->tcp_only_ack, + msdu_start->da_is_bcast_mcast, + msdu_start->ip4_protocol_ip6_next_header, + msdu_start->toeplitz_hash_2_or_4, + msdu_start->flow_id_toeplitz, + msdu_start->user_rssi, + msdu_start->pkt_type, + msdu_start->stbc, + msdu_start->sgi, + msdu_start->rate_mcs, + msdu_start->receive_bandwidth, + msdu_start->reception_type, + msdu_start->ppdu_start_timestamp); + + hal_verbose_debug( + "rx_msdu_start tlv (2/2) - " + "sw_phy_meta_data: %x ", + msdu_start->sw_phy_meta_data); +} + +/** + * hal_rx_dump_msdu_end_tlv_6450: dump RX msdu_end TLV in structured + * human readable format. + * @msduend: pointer the msdu_end TLV in pkt. + * @dbg_level: log level. + * + * Return: void + */ +static void hal_rx_dump_msdu_end_tlv_6450(void *msduend, + uint8_t dbg_level) +{ + struct rx_msdu_end *msdu_end = (struct rx_msdu_end *)msduend; + + __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, + "rx_msdu_end tlv (1/3) - " + "rxpcu_mpdu_filter_in_category: %x " + "sw_frame_group_id: %x " + "phy_ppdu_id: %x " + "ip_hdr_chksum: %x " + "tcp_udp_chksum: %x " + "key_id_octet: %x " + "cce_super_rule: %x " + "cce_classify_not_done_truncat: %x " + "cce_classify_not_done_cce_dis: %x " + "reported_mpdu_length: %x " + "first_msdu: %x " + "last_msdu: %x " + "sa_idx_timeout: %x " + "da_idx_timeout: %x " + "msdu_limit_error: %x " + "flow_idx_timeout: %x " + "flow_idx_invalid: %x " + "wifi_parser_error: %x " + "amsdu_parser_error: %x", + msdu_end->rxpcu_mpdu_filter_in_category, + msdu_end->sw_frame_group_id, + msdu_end->phy_ppdu_id, + msdu_end->ip_hdr_chksum, + msdu_end->tcp_udp_chksum, + msdu_end->key_id_octet, + msdu_end->cce_super_rule, + msdu_end->cce_classify_not_done_truncate, + msdu_end->cce_classify_not_done_cce_dis, + msdu_end->reported_mpdu_length, + msdu_end->first_msdu, + msdu_end->last_msdu, + msdu_end->sa_idx_timeout, + msdu_end->da_idx_timeout, + msdu_end->msdu_limit_error, + msdu_end->flow_idx_timeout, + msdu_end->flow_idx_invalid, + msdu_end->wifi_parser_error, + msdu_end->amsdu_parser_error); + + __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, + "rx_msdu_end tlv (2/3)- " + "sa_is_valid: %x " + "da_is_valid: %x " + "da_is_mcbc: %x " + "l3_header_padding: %x " + "ipv6_options_crc: %x " + "tcp_seq_number: %x " + "tcp_ack_number: %x " + "tcp_flag: %x " + "lro_eligible: %x " + "window_size: %x " + "da_offset: %x " + "sa_offset: %x " + "da_offset_valid: %x " + "sa_offset_valid: %x " + "rule_indication_31_0: %x " + "rule_indication_63_32: %x " + "sa_idx: %x " + "da_idx: %x " + "msdu_drop: %x " + "reo_destination_indication: %x " + "flow_idx: %x " + "fse_metadata: %x " + "cce_metadata: %x " + "sa_sw_peer_id: %x ", + msdu_end->sa_is_valid, + msdu_end->da_is_valid, + msdu_end->da_is_mcbc, + msdu_end->l3_header_padding, + msdu_end->ipv6_options_crc, + msdu_end->tcp_seq_number, + msdu_end->tcp_ack_number, + msdu_end->tcp_flag, + msdu_end->lro_eligible, + msdu_end->window_size, + msdu_end->da_offset, + msdu_end->sa_offset, + msdu_end->da_offset_valid, + msdu_end->sa_offset_valid, + msdu_end->rule_indication_31_0, + msdu_end->rule_indication_63_32, + msdu_end->sa_idx, + msdu_end->da_idx_or_sw_peer_id, + msdu_end->msdu_drop, + msdu_end->reo_destination_indication, + msdu_end->flow_idx, + msdu_end->fse_metadata, + msdu_end->cce_metadata, + msdu_end->sa_sw_peer_id); + __QDF_TRACE_RL(dbg_level, QDF_MODULE_ID_DP, + "rx_msdu_end tlv (3/3)" + "aggregation_count %x " + "flow_aggregation_continuation %x " + "fisa_timeout %x " + "cumulative_l4_checksum %x " + "cumulative_ip_length %x", + msdu_end->aggregation_count, + msdu_end->flow_aggregation_continuation, + msdu_end->fisa_timeout, + msdu_end->cumulative_l4_checksum, + msdu_end->cumulative_ip_length); +} + +/* + * Get tid from RX_MPDU_START + */ +#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_7_TID_OFFSET)), \ + RX_MPDU_INFO_7_TID_MASK, \ + RX_MPDU_INFO_7_TID_LSB)) + +static uint32_t hal_rx_mpdu_start_tid_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + uint32_t tid; + + tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); + + return tid; +} + +#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \ + RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \ + RX_MSDU_START_5_RECEPTION_TYPE_MASK, \ + RX_MSDU_START_5_RECEPTION_TYPE_LSB)) + +/* + * hal_rx_msdu_start_reception_type_get(): API to get the reception type + * Interval from rx_msdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(reception_type) + */ +static +uint32_t hal_rx_msdu_start_reception_type_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t reception_type; + + reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); + + return reception_type; +} + +/** + * hal_rx_msdu_end_da_idx_get_6450: API to get da_idx + * from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: da index + */ +static uint16_t hal_rx_msdu_end_da_idx_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint16_t da_idx; + + da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); + + return da_idx; +} + +/** + * hal_rx_msdu_desc_info_get_ptr_6450() - Get msdu desc info ptr + * @msdu_details_ptr: Pointer to msdu_details_ptr + * + * Return - Pointer to rx_msdu_desc_info structure. + * + */ +static void *hal_rx_msdu_desc_info_get_ptr_6450(void *msdu_details_ptr) +{ + return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); +} + +/** + * hal_rx_link_desc_msdu0_ptr_6450 - Get pointer to rx_msdu details + * @link_desc: Pointer to link desc + * + * Return - Pointer to rx_msdu_details structure + * + */ +static void *hal_rx_link_desc_msdu0_ptr_6450(void *link_desc) +{ + return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); +} + +/** + * hal_rx_get_rx_fragment_number_6450(): Function to retrieve rx fragment number + * + * @buf: Network buffer + * Returns: rx fragment number + */ +static +uint8_t hal_rx_get_rx_fragment_number_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + + /* Return first 4 bits as fragment number */ + return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & + DOT11_SEQ_FRAG_MASK); +} + +/** + * hal_rx_msdu_end_da_is_mcbc_get_6450(): API to check if pkt is MCBC + * from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: da_is_mcbc + */ +static uint8_t +hal_rx_msdu_end_da_is_mcbc_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); +} + +/** + * hal_rx_msdu_end_sa_is_valid_get_6450(): API to get_6450 the + * sa_is_valid bit from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: sa_is_valid bit + */ +static uint8_t +hal_rx_msdu_end_sa_is_valid_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint8_t sa_is_valid; + + sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); + + return sa_is_valid; +} + +/** + * hal_rx_msdu_end_sa_idx_get_6450(): API to get_6450 the + * sa_idx from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: sa_idx (SA AST index) + */ +static +uint16_t hal_rx_msdu_end_sa_idx_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint16_t sa_idx; + + sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); + + return sa_idx; +} + +/** + * hal_rx_desc_is_first_msdu_6450() - Check if first msdu + * + * @hw_desc_addr: hardware descriptor address + * + * Return: 0 - success/ non-zero failure + */ +static uint32_t hal_rx_desc_is_first_msdu_6450(void *hw_desc_addr) +{ + struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; + struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); +} + +/** + * hal_rx_msdu_end_l3_hdr_padding_get_6450(): API to get_6450 the + * l3_header padding from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: number of l3 header padding bytes + */ +static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint32_t l3_header_padding; + + l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); + + return l3_header_padding; +} + +/* + * @ hal_rx_encryption_info_valid_6450: Returns encryption type. + * + * @ buf: rx_tlv_hdr of the received packet + * @ Return: encryption type + */ +static uint32_t hal_rx_encryption_info_valid_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); + + return encryption_info; +} + +/* + * @ hal_rx_print_pn_6450: Prints the PN of rx packet. + * + * @ buf: rx_tlv_hdr of the received packet + * @ Return: void + */ +static void hal_rx_print_pn_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + + uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); + uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); + uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); + uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); + + hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x ", + pn_127_96, pn_95_64, pn_63_32, pn_31_0); +} + +/** + * hal_rx_msdu_end_first_msdu_get_6450: API to get first msdu status + * from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: first_msdu + */ +static uint8_t hal_rx_msdu_end_first_msdu_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint8_t first_msdu; + + first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); + + return first_msdu; +} + +/** + * hal_rx_msdu_end_da_is_valid_get_6450: API to check if da is valid + * from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: da_is_valid + */ +static uint8_t hal_rx_msdu_end_da_is_valid_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint8_t da_is_valid; + + da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); + + return da_is_valid; +} + +/** + * hal_rx_msdu_end_last_msdu_get_6450: API to get last msdu status + * from rx_msdu_end TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: last_msdu + */ +static uint8_t hal_rx_msdu_end_last_msdu_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + uint8_t last_msdu; + + last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); + + return last_msdu; +} + +/* + * hal_rx_get_mpdu_mac_ad4_valid_6450(): Retrieves if mpdu 4th addr is valid + * + * @nbuf: Network buffer + * Returns: value of mpdu 4th address valid field + */ +static bool hal_rx_get_mpdu_mac_ad4_valid_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + bool ad4_valid = 0; + + ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); + + return ad4_valid; +} + +/** + * hal_rx_mpdu_start_sw_peer_id_get_6450: Retrieve sw peer_id + * @buf: network buffer + * + * Return: sw peer_id + */ +static uint32_t hal_rx_mpdu_start_sw_peer_id_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( + &mpdu_start->rx_mpdu_info_details); +} + +/** + * hal_rx_mpdu_get_to_ds_6450(): API to get the tods info + * from rx_mpdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(to_ds) + */ +static uint32_t hal_rx_mpdu_get_to_ds_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + + return HAL_RX_MPDU_GET_TODS(mpdu_info); +} + +/* + * hal_rx_mpdu_get_fr_ds_6450(): API to get the from ds info + * from rx_mpdu_start + * + * @buf: pointer to the start of RX PKT TLV header + * Return: uint32_t(fr_ds) + */ +static uint32_t hal_rx_mpdu_get_fr_ds_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + + return HAL_RX_MPDU_GET_FROMDS(mpdu_info); +} + +/* + * hal_rx_get_mpdu_frame_control_valid_6450(): Retrieves mpdu + * frame control valid + * + * @nbuf: Network buffer + * Returns: value of frame control valid field + */ +static uint8_t hal_rx_get_mpdu_frame_control_valid_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + + return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); +} + +/* + * hal_rx_mpdu_get_addr1_6450(): API to check get address1 of the mpdu + * + * @buf: pointer to the start of RX PKT TLV headera + * @mac_addr: pointer to mac address + * Return: success/failure + */ +static QDF_STATUS hal_rx_mpdu_get_addr1_6450(uint8_t *buf, uint8_t *mac_addr) +{ + struct __attribute__((__packed__)) hal_addr1 { + uint32_t ad1_31_0; + uint16_t ad1_47_32; + }; + + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; + uint32_t mac_addr_ad1_valid; + + mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); + + if (mac_addr_ad1_valid) { + addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); + addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); + return QDF_STATUS_SUCCESS; + } + + return QDF_STATUS_E_FAILURE; +} + +/* + * hal_rx_mpdu_get_addr2_6450(): API to check get address2 of the mpdu + * in the packet + * + * @buf: pointer to the start of RX PKT TLV header + * @mac_addr: pointer to mac address + * Return: success/failure + */ +static QDF_STATUS hal_rx_mpdu_get_addr2_6450(uint8_t *buf, + uint8_t *mac_addr) +{ + struct __attribute__((__packed__)) hal_addr2 { + uint16_t ad2_15_0; + uint32_t ad2_47_16; + }; + + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; + uint32_t mac_addr_ad2_valid; + + mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); + + if (mac_addr_ad2_valid) { + addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); + addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); + return QDF_STATUS_SUCCESS; + } + + return QDF_STATUS_E_FAILURE; +} + +/* + * hal_rx_mpdu_get_addr3_6450(): API to get address3 of the mpdu + * in the packet + * + * @buf: pointer to the start of RX PKT TLV header + * @mac_addr: pointer to mac address + * Return: success/failure + */ +static QDF_STATUS hal_rx_mpdu_get_addr3_6450(uint8_t *buf, uint8_t *mac_addr) +{ + struct __attribute__((__packed__)) hal_addr3 { + uint32_t ad3_31_0; + uint16_t ad3_47_32; + }; + + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; + uint32_t mac_addr_ad3_valid; + + mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); + + if (mac_addr_ad3_valid) { + addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); + addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); + return QDF_STATUS_SUCCESS; + } + + return QDF_STATUS_E_FAILURE; +} + +/* + * hal_rx_mpdu_get_addr4_6450(): API to get address4 of the mpdu + * in the packet + * + * @buf: pointer to the start of RX PKT TLV header + * @mac_addr: pointer to mac address + * Return: success/failure + */ +static QDF_STATUS hal_rx_mpdu_get_addr4_6450(uint8_t *buf, uint8_t *mac_addr) +{ + struct __attribute__((__packed__)) hal_addr4 { + uint32_t ad4_31_0; + uint16_t ad4_47_32; + }; + + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_mpdu_start *mpdu_start = + &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; + + struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; + struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; + uint32_t mac_addr_ad4_valid; + + mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); + + if (mac_addr_ad4_valid) { + addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); + addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); + return QDF_STATUS_SUCCESS; + } + + return QDF_STATUS_E_FAILURE; +} + +/* + * hal_rx_get_mpdu_sequence_control_valid_6450(): Get mpdu + * sequence control valid + * + * @nbuf: Network buffer + * Returns: value of sequence control valid field + */ +static uint8_t hal_rx_get_mpdu_sequence_control_valid_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + + return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); +} + +/** + * hal_rx_hw_desc_get_ppduid_get_6450(): retrieve ppdu id + * @rx_tlv_hdr: rx tlv header + * @rxdma_dst_ring_desc: rxdma HW descriptor + * + * Return: ppdu id + */ +static uint32_t hal_rx_hw_desc_get_ppduid_get_6450(void *rx_tlv_hdr, + void *rxdma_dst_ring_desc) +{ + struct rx_mpdu_info *rx_mpdu_info; + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; + + rx_mpdu_info = + &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; + + return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_9, PHY_PPDU_ID); +} + +static uint32_t +hal_rx_get_ppdu_id_6450(uint8_t *buf) +{ + return HAL_RX_GET_PPDU_ID(buf); +} + +/** + * hal_rx_msdu_flow_idx_invalid_6450: API to get flow index invalid + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: flow index invalid value from MSDU END TLV + */ +static bool hal_rx_msdu_flow_idx_invalid_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); +} + +/** + * hal_rx_msdu_flow_idx_timeout_6450: API to get flow index timeout + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: flow index timeout value from MSDU END TLV + */ +static bool hal_rx_msdu_flow_idx_timeout_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); +} + +/** + * hal_rx_msdu_fse_metadata_get_6450: API to get FSE metadata + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: fse metadata value from MSDU END TLV + */ +static uint32_t hal_rx_msdu_fse_metadata_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); +} + +/** + * hal_rx_msdu_cce_metadata_get_6450: API to get CCE metadata + * from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * + * Return: cce_metadata + */ +static uint16_t +hal_rx_msdu_cce_metadata_get_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); +} + +/** + * hal_rx_msdu_get_flow_params_6450: API to get flow index, flow index invalid + * and flow index timeout from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * @flow_invalid: pointer to return value of flow_idx_valid + * @flow_timeout: pointer to return value of flow_idx_timeout + * @flow_index: pointer to return value of flow_idx + * + * Return: none + */ +static inline void +hal_rx_msdu_get_flow_params_6450(uint8_t *buf, + bool *flow_invalid, + bool *flow_timeout, + uint32_t *flow_index) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); + *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); + *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); +} + +/** + * hal_rx_tlv_get_tcp_chksum_6450() - API to get tcp checksum + * @buf: rx_tlv_hdr + * + * Return: tcp checksum + */ +static uint16_t +hal_rx_tlv_get_tcp_chksum_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_TCP_CHKSUM(buf); +} + +/** + * hal_rx_get_rx_sequence_6450(): Function to retrieve rx sequence number + * + * @buf: Network buffer + * Returns: rx sequence number + */ +static +uint16_t hal_rx_get_rx_sequence_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); + struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); + + return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); +} + +/** + * hal_rx_get_fisa_cumulative_l4_checksum_6450() - Retrieve cumulative + * checksum + * @buf: buffer pointer + * + * Return: cumulative checksum + */ +static inline +uint16_t hal_rx_get_fisa_cumulative_l4_checksum_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf); +} + +/** + * hal_rx_get_fisa_cumulative_ip_length_6450() - Retrieve cumulative + * ip length + * @buf: buffer pointer + * + * Return: cumulative length + */ +static inline +uint16_t hal_rx_get_fisa_cumulative_ip_length_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf); +} + +/** + * hal_rx_get_udp_proto_6450() - Retrieve udp proto value + * @buf: buffer + * + * Return: udp proto bit + */ +static inline +bool hal_rx_get_udp_proto_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_UDP_PROTO(buf); +} + +/** + * hal_rx_get_flow_agg_continuation_6450() - retrieve flow agg + * continuation + * @buf: buffer + * + * Return: flow agg + */ +static inline +bool hal_rx_get_flow_agg_continuation_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf); +} + +/** + * hal_rx_get_flow_agg_count_6450()- Retrieve flow agg count + * @buf: buffer + * + * Return: flow agg count + */ +static inline +uint8_t hal_rx_get_flow_agg_count_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf); +} + +/** + * hal_rx_get_fisa_timeout_6450() - Retrieve fisa timeout + * @buf: buffer + * + * Return: fisa timeout + */ +static inline +bool hal_rx_get_fisa_timeout_6450(uint8_t *buf) +{ + return HAL_RX_TLV_GET_FISA_TIMEOUT(buf); +} + +/** + * hal_rx_mpdu_start_tlv_tag_valid_6450 () - API to check if RX_MPDU_START + * tlv tag is valid + * + *@rx_tlv_hdr: start address of rx_pkt_tlvs + * + * Return: true if RX_MPDU_START is valid, else false. + */ +static uint8_t hal_rx_mpdu_start_tlv_tag_valid_6450(void *rx_tlv_hdr) +{ + struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; + uint32_t tlv_tag; + + tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); + + return tlv_tag == WIFIRX_MPDU_START_E ? true : false; +} + +/* + * hal_rx_flow_setup_fse_6450() - Setup a flow search entry in HW FST + * @fst: Pointer to the Rx Flow Search Table + * @table_offset: offset into the table where the flow is to be setup + * @flow: Flow Parameters + * + * Flow table entry fields are updated in host byte order, little endian order. + * + * Return: Success/Failure + */ +static void * +hal_rx_flow_setup_fse_6450(uint8_t *rx_fst, uint32_t table_offset, + uint8_t *rx_flow) +{ + struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; + struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; + uint8_t *fse; + bool fse_valid; + + if (table_offset >= fst->max_entries) { + QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, + "HAL FSE table offset %u exceeds max entries %u", + table_offset, fst->max_entries); + return NULL; + } + + fse = (uint8_t *)fst->base_vaddr + + (table_offset * HAL_RX_FST_ENTRY_SIZE); + + fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); + + if (fse_valid) { + QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, + "HAL FSE %pK already valid", fse); + return NULL; + } + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, + (flow->tuple_info.src_ip_127_96)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, + (flow->tuple_info.src_ip_95_64)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, + (flow->tuple_info.src_ip_63_32)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, + (flow->tuple_info.src_ip_31_0)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, + (flow->tuple_info.dest_ip_127_96)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, + (flow->tuple_info.dest_ip_95_64)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, + (flow->tuple_info.dest_ip_63_32)); + + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, + (flow->tuple_info.dest_ip_31_0)); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, + (flow->tuple_info.dest_port)); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, + (flow->tuple_info.src_port)); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, + flow->tuple_info.l4_protocol); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, + flow->reo_destination_handler); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, + (flow->fse_metadata)); + + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); + HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= + HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, + REO_DESTINATION_INDICATION, + flow->reo_destination_indication); + + /* Reset all the other fields in FSE */ + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); + HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); + + return fse; +} + +/* + * hal_rx_flow_setup_cmem_fse_6450() - Setup a flow search entry in HW CMEM FST + * @hal_soc: hal_soc reference + * @cmem_ba: CMEM base address + * @table_offset: offset into the table where the flow is to be setup + * @flow: Flow Parameters + * + * Return: Success/Failure + */ +static uint32_t +hal_rx_flow_setup_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t cmem_ba, + uint32_t table_offset, uint8_t *rx_flow) +{ + struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; + uint32_t fse_offset; + uint32_t value; + + fse_offset = cmem_ba + (table_offset * HAL_RX_FST_ENTRY_SIZE); + + /* Reset the Valid bit */ + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, + VALID), 0); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, + (flow->tuple_info.src_ip_127_96)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_0, + SRC_IP_127_96), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, + (flow->tuple_info.src_ip_95_64)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_1, + SRC_IP_95_64), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, + (flow->tuple_info.src_ip_63_32)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_2, + SRC_IP_63_32), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, + (flow->tuple_info.src_ip_31_0)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_3, + SRC_IP_31_0), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, + (flow->tuple_info.dest_ip_127_96)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_4, + DEST_IP_127_96), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, + (flow->tuple_info.dest_ip_95_64)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_5, + DEST_IP_95_64), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, + (flow->tuple_info.dest_ip_63_32)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_6, + DEST_IP_63_32), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, + (flow->tuple_info.dest_ip_31_0)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_7, + DEST_IP_31_0), value); + + value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, + (flow->tuple_info.dest_port)); + value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, + (flow->tuple_info.src_port)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_8, + SRC_PORT), value); + + value = HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, + (flow->fse_metadata)); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_10, + METADATA), value); + + /* Reset all the other fields in FSE */ + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_11, + MSDU_COUNT), 0); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_12, + MSDU_BYTE_COUNT), 0); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, + TIMESTAMP), 0); + + value = 0 | HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, + flow->tuple_info.l4_protocol); + value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, + flow->reo_destination_handler); + value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, + REO_DESTINATION_INDICATION, + flow->reo_destination_indication); + value |= HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); + HAL_CMEM_WRITE(hal_soc, fse_offset + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_9, + L4_PROTOCOL), value); + + return fse_offset; +} + +/** + * hal_rx_flow_get_cmem_fse_ts_6450() - Get timestamp field from CMEM FSE + * @hal_soc: hal_soc reference + * @fse_offset: CMEM FSE offset + * + * Return: Timestamp + */ +static uint32_t hal_rx_flow_get_cmem_fse_ts_6450(struct hal_soc *hal_soc, + uint32_t fse_offset) +{ + return HAL_CMEM_READ(hal_soc, fse_offset + + HAL_OFFSET(RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP)); +} + +/** + * hal_rx_flow_get_cmem_fse_6450() - Get FSE from CMEM + * @hal_soc: hal_soc reference + * @fse_offset: CMEM FSE offset + * @fse: reference where FSE will be copied + * @len: length of FSE + * + * Return: If read is successful or not + */ +static void +hal_rx_flow_get_cmem_fse_6450(struct hal_soc *hal_soc, uint32_t fse_offset, + uint32_t *fse, qdf_size_t len) +{ + int i; + + if (len != HAL_RX_FST_ENTRY_SIZE) + return; + + for (i = 0; i < NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY; i++) + fse[i] = HAL_CMEM_READ(hal_soc, fse_offset + i * 4); +} + +/** + * hal_rx_msdu_get_reo_destination_indication_6450: API to get + * reo_destination_indication from rx_msdu_end TLV + * @buf: pointer to the start of RX PKT TLV headers + * @reo_destination_ind: pointer to return value + * of reo_destination_indication + * + * Return: none + */ +static void +hal_rx_msdu_get_reo_destination_indication_6450(uint8_t *buf, + uint32_t *reo_destination_ind) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; + + *reo_destination_ind = + HAL_RX_MSDU_END_REO_DEST_IND_GET(msdu_end); +} + +#ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET +static inline uint8_t hal_get_first_wow_wakeup_packet_6450(uint8_t *buf) +{ + return 0; +} +#endif + +/** + * hal_rx_msdu_start_get_len_6450(): API to get the MSDU length + * from rx_msdu_start TLV + * + * @buf: pointer to the start of RX PKT TLV headers + * Return: (uint32_t)msdu length + */ +static uint32_t hal_rx_msdu_start_get_len_6450(uint8_t *buf) +{ + struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; + struct rx_msdu_start *msdu_start = + &pkt_tlvs->msdu_start_tlv.rx_msdu_start; + uint32_t msdu_len; + + msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); + + return msdu_len; +} + +static void hal_hw_txrx_ops_attach_wcn6450(struct hal_soc *hal_soc) +{ + /* Initialize setup tx/rx ops here */ + hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; + hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; + hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_6450; + hal_soc->ops->hal_reo_setup = hal_reo_setup_6450; + hal_soc->ops->hal_get_window_address = hal_get_window_address_6450; + hal_soc->ops->hal_reo_set_err_dst_remap = + hal_reo_set_err_dst_remap_6450; + + /* tx */ + hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = + hal_tx_desc_set_dscp_tid_table_id_6450; + hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6450; + hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6450; + hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6450; + hal_soc->ops->hal_tx_desc_set_buf_addr = + hal_tx_desc_set_buf_addr_generic_rh; + hal_soc->ops->hal_tx_desc_set_search_type = + hal_tx_desc_set_search_type_generic_rh; + hal_soc->ops->hal_tx_desc_set_search_index = + hal_tx_desc_set_search_index_generic_rh; + hal_soc->ops->hal_tx_desc_set_cache_set_num = + hal_tx_desc_set_cache_set_num_generic_rh; + hal_soc->ops->hal_tx_comp_get_status = + hal_tx_comp_get_status_6450; + hal_soc->ops->hal_tx_comp_get_release_reason = + hal_tx_comp_get_release_reason_6450; + hal_soc->ops->hal_get_wbm_internal_error = + hal_get_wbm_internal_error_6450; + hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6450; + hal_soc->ops->hal_tx_init_cmd_credit_ring = + hal_tx_init_cmd_credit_ring_6450; + + /* rx */ + hal_soc->ops->hal_rx_msdu_start_nss_get = + hal_rx_msdu_start_nss_get_6450; + hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = + hal_rx_mon_hw_desc_get_mpdu_status_6450; + hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6450; + hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = + hal_rx_proc_phyrx_other_receive_info_tlv_6450; + hal_soc->ops->hal_rx_dump_msdu_start_tlv = + hal_rx_dump_msdu_start_tlv_6450; + hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6450; + hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6450; + hal_soc->ops->hal_rx_mpdu_start_tid_get = + hal_rx_mpdu_start_tid_get_6450; + hal_soc->ops->hal_rx_msdu_start_reception_type_get = + hal_rx_msdu_start_reception_type_get_6450; + hal_soc->ops->hal_rx_msdu_end_da_idx_get = + hal_rx_msdu_end_da_idx_get_6450; + hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = + hal_rx_msdu_desc_info_get_ptr_6450; + hal_soc->ops->hal_rx_link_desc_msdu0_ptr = + hal_rx_link_desc_msdu0_ptr_6450; + hal_soc->ops->hal_reo_status_get_header = + hal_reo_status_get_header_6450; + hal_soc->ops->hal_rx_status_get_tlv_info = + hal_rx_status_get_tlv_info_generic_rh; + hal_soc->ops->hal_rx_wbm_err_info_get = + hal_rx_wbm_err_info_get_6450; + hal_soc->ops->hal_rx_dump_mpdu_start_tlv = + hal_rx_dump_mpdu_start_tlv_generic_rh; + hal_soc->ops->hal_tx_set_pcp_tid_map = + hal_tx_set_pcp_tid_map_generic_rh; + hal_soc->ops->hal_tx_update_pcp_tid_map = + hal_tx_update_pcp_tid_generic_rh; + hal_soc->ops->hal_tx_set_tidmap_prty = + hal_tx_update_tidmap_prty_generic_rh; + hal_soc->ops->hal_rx_get_rx_fragment_number = + hal_rx_get_rx_fragment_number_6450; + hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = + hal_rx_msdu_end_da_is_mcbc_get_6450; + hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = + hal_rx_msdu_end_sa_is_valid_get_6450; + hal_soc->ops->hal_rx_msdu_end_sa_idx_get = + hal_rx_msdu_end_sa_idx_get_6450; + hal_soc->ops->hal_rx_desc_is_first_msdu = + hal_rx_desc_is_first_msdu_6450; + hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = + hal_rx_msdu_end_l3_hdr_padding_get_6450; + hal_soc->ops->hal_rx_encryption_info_valid = + hal_rx_encryption_info_valid_6450; + hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6450; + hal_soc->ops->hal_rx_msdu_end_first_msdu_get = + hal_rx_msdu_end_first_msdu_get_6450; + hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = + hal_rx_msdu_end_da_is_valid_get_6450; + hal_soc->ops->hal_rx_msdu_end_last_msdu_get = + hal_rx_msdu_end_last_msdu_get_6450; + hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = + hal_rx_get_mpdu_mac_ad4_valid_6450; + hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = + hal_rx_mpdu_start_sw_peer_id_get_6450; + hal_soc->ops->hal_rx_tlv_peer_meta_data_get = + hal_rx_mpdu_peer_meta_data_get_rh; + hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6450; + hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6450; + hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = + hal_rx_get_mpdu_frame_control_valid_6450; + hal_soc->ops->hal_rx_get_frame_ctrl_field = + hal_rx_get_frame_ctrl_field_rh; + hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6450; + hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6450; + hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6450; + hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6450; + hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = + hal_rx_get_mpdu_sequence_control_valid_6450; + hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6450; + hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6450; + hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = + hal_rx_hw_desc_get_ppduid_get_6450; + hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = + hal_rx_msdu0_buffer_addr_lsb_6450; + hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = + hal_rx_msdu_desc_info_ptr_get_6450; + hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6450; + hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6450; + hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6450; + hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6450; + hal_soc->ops->hal_rx_get_mac_addr2_valid = + hal_rx_get_mac_addr2_valid_6450; + hal_soc->ops->hal_rx_get_filter_category = + hal_rx_get_filter_category_6450; + hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6450; + hal_soc->ops->hal_reo_config = hal_reo_config_6450; + hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6450; + hal_soc->ops->hal_rx_msdu_flow_idx_invalid = + hal_rx_msdu_flow_idx_invalid_6450; + hal_soc->ops->hal_rx_msdu_flow_idx_timeout = + hal_rx_msdu_flow_idx_timeout_6450; + hal_soc->ops->hal_rx_msdu_fse_metadata_get = + hal_rx_msdu_fse_metadata_get_6450; + hal_soc->ops->hal_rx_msdu_cce_match_get = + hal_rx_msdu_cce_match_get_rh; + hal_soc->ops->hal_rx_msdu_cce_metadata_get = + hal_rx_msdu_cce_metadata_get_6450; + hal_soc->ops->hal_rx_msdu_get_flow_params = + hal_rx_msdu_get_flow_params_6450; + hal_soc->ops->hal_rx_tlv_get_tcp_chksum = + hal_rx_tlv_get_tcp_chksum_6450; + hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6450; +#if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \ + defined(WLAN_ENH_CFR_ENABLE) + hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6450; + hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6450; +#endif + + /* rx - msdu end fast path info fields */ + hal_soc->ops->hal_rx_msdu_packet_metadata_get = + hal_rx_msdu_packet_metadata_get_generic_rh; + hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum = + hal_rx_get_fisa_cumulative_l4_checksum_6450; + hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length = + hal_rx_get_fisa_cumulative_ip_length_6450; + hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6450; + hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation = + hal_rx_get_flow_agg_continuation_6450; + hal_soc->ops->hal_rx_get_fisa_flow_agg_count = + hal_rx_get_flow_agg_count_6450; + hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6450; + hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = + hal_rx_mpdu_start_tlv_tag_valid_6450; + + /* rx - TLV struct offsets */ + hal_soc->ops->hal_rx_msdu_end_offset_get = + hal_rx_msdu_end_offset_get_generic; + hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; + hal_soc->ops->hal_rx_msdu_start_offset_get = + hal_rx_msdu_start_offset_get_generic; + hal_soc->ops->hal_rx_mpdu_start_offset_get = + hal_rx_mpdu_start_offset_get_generic; + hal_soc->ops->hal_rx_mpdu_end_offset_get = + hal_rx_mpdu_end_offset_get_generic; +#ifndef NO_RX_PKT_HDR_TLV + hal_soc->ops->hal_rx_pkt_tlv_offset_get = + hal_rx_pkt_tlv_offset_get_generic; +#endif + hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6450; + hal_soc->ops->hal_rx_flow_get_tuple_info = + hal_rx_flow_get_tuple_info_rh; + hal_soc->ops->hal_rx_flow_delete_entry = + hal_rx_flow_delete_entry_rh; + hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_rh; + hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = + hal_compute_reo_remap_ix2_ix3_6450; + + /* CMEM FSE */ + hal_soc->ops->hal_rx_flow_setup_cmem_fse = + hal_rx_flow_setup_cmem_fse_6450; + hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = + hal_rx_flow_get_cmem_fse_ts_6450; + hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6450; + hal_soc->ops->hal_rx_msdu_get_reo_destination_indication = + hal_rx_msdu_get_reo_destination_indication_6450; + hal_soc->ops->hal_setup_link_idle_list = + hal_setup_link_idle_list_6450; +#ifdef WLAN_FEATURE_MARK_FIRST_WAKEUP_PACKET + hal_soc->ops->hal_get_first_wow_wakeup_packet = + hal_get_first_wow_wakeup_packet_6450; +#endif + hal_soc->ops->hal_compute_reo_remap_ix0 = + hal_compute_reo_remap_ix0_6450; + hal_soc->ops->hal_rx_tlv_msdu_len_get = + hal_rx_msdu_start_get_len_6450; +} + /** * hal_wcn6450_attach() - Attach 6450 target specific hal_soc ops, * offset and srng table @@ -115,4 +1948,6 @@ struct hal_hw_srng_config hw_srng_table_wcn6450[] = { void hal_wcn6450_attach(struct hal_soc *hal_soc) { hal_soc->hw_srng_table = hw_srng_table_wcn6450; + hal_hw_txrx_default_ops_attach_rh(hal_soc); + hal_hw_txrx_ops_attach_wcn6450(hal_soc); } diff --git a/hal/wifi3.0/wcn6450/hal_wcn6450_rx.h b/hal/wifi3.0/wcn6450/hal_wcn6450_rx.h new file mode 100644 index 0000000000..8048509541 --- /dev/null +++ b/hal/wifi3.0/wcn6450/hal_wcn6450_rx.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_6450_RX_H_ +#define _HAL_6450_RX_H_ +#include "qdf_util.h" +#include "qdf_types.h" +#include "qdf_lock.h" +#include "qdf_mem.h" +#include "qdf_nbuf.h" +#include "tcl_data_cmd.h" +#include "phyrx_rssi_legacy.h" +#include "rx_msdu_start.h" +#include "tlv_tag_def.h" +#include "hal_internal.h" +#include "cdp_txrx_mon_struct.h" +#include "qdf_trace.h" +#include "hal_rx.h" +#include "hal_tx.h" +#include "dp_types.h" +#include "hal_api_mon.h" +#include "phyrx_other_receive_info_ru_details.h" + +#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\ + RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \ + RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \ + RX_MSDU_START_5_MIMO_SS_BITMAP_LSB)) + +#define HAL_RX_MPDU_GET_SEQUENCE_NUMBER(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB)) + +#define HAL_RX_MSDU_END_DA_IS_MCBC_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_DA_IS_MCBC_OFFSET)), \ + RX_MSDU_END_10_DA_IS_MCBC_MASK, \ + RX_MSDU_END_10_DA_IS_MCBC_LSB)) + +#define HAL_RX_MSDU_END_SA_IS_VALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_SA_IS_VALID_OFFSET)), \ + RX_MSDU_END_10_SA_IS_VALID_MASK, \ + RX_MSDU_END_10_SA_IS_VALID_LSB)) + +#define HAL_RX_MSDU_END_SA_IDX_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_11_SA_IDX_OFFSET)), \ + RX_MSDU_END_11_SA_IDX_MASK, \ + RX_MSDU_END_11_SA_IDX_LSB)) + +#define HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET)), \ + RX_MSDU_END_10_L3_HEADER_PADDING_MASK, \ + RX_MSDU_END_10_L3_HEADER_PADDING_LSB)) + +#define HAL_RX_MPDU_ENCRYPTION_INFO_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET)), \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK, \ + RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB)) + +#define HAL_RX_MPDU_PN_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_3_PN_31_0_OFFSET)), \ + RX_MPDU_INFO_3_PN_31_0_MASK, \ + RX_MPDU_INFO_3_PN_31_0_LSB)) + +#define HAL_RX_MPDU_PN_63_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_4_PN_63_32_OFFSET)), \ + RX_MPDU_INFO_4_PN_63_32_MASK, \ + RX_MPDU_INFO_4_PN_63_32_LSB)) + +#define HAL_RX_MPDU_PN_95_64_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_5_PN_95_64_OFFSET)), \ + RX_MPDU_INFO_5_PN_95_64_MASK, \ + RX_MPDU_INFO_5_PN_95_64_LSB)) + +#define HAL_RX_MPDU_PN_127_96_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_6_PN_127_96_OFFSET)), \ + RX_MPDU_INFO_6_PN_127_96_MASK, \ + RX_MPDU_INFO_6_PN_127_96_LSB)) + +#define HAL_RX_MSDU_END_FIRST_MSDU_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FIRST_MSDU_OFFSET)), \ + RX_MSDU_END_10_FIRST_MSDU_MASK, \ + RX_MSDU_END_10_FIRST_MSDU_LSB)) + +#define HAL_RX_MSDU_END_DA_IS_VALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_DA_IS_VALID_OFFSET)), \ + RX_MSDU_END_10_DA_IS_VALID_MASK, \ + RX_MSDU_END_10_DA_IS_VALID_LSB)) + +#define HAL_RX_MSDU_END_LAST_MSDU_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_LAST_MSDU_OFFSET)), \ + RX_MSDU_END_10_LAST_MSDU_MASK, \ + RX_MSDU_END_10_LAST_MSDU_LSB)) + +#define HAL_RX_MPDU_GET_MAC_AD4_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) + +#define HAL_RX_MPDU_INFO_SW_PEER_ID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \ + RX_MPDU_INFO_10_SW_PEER_ID_OFFSET)), \ + RX_MPDU_INFO_10_SW_PEER_ID_MASK, \ + RX_MPDU_INFO_10_SW_PEER_ID_LSB)) + +#define HAL_RX_MPDU_GET_TODS(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_TO_DS_OFFSET)), \ + RX_MPDU_INFO_11_TO_DS_MASK, \ + RX_MPDU_INFO_11_TO_DS_LSB)) + +#define HAL_RX_MPDU_GET_FROMDS(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_FR_DS_OFFSET)), \ + RX_MPDU_INFO_11_FR_DS_MASK, \ + RX_MPDU_INFO_11_FR_DS_LSB)) + +#define HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK, \ + RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB)) + +#define HAL_RX_MPDU_AD1_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET)), \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK, \ + RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB)) + +#define HAL_RX_MPDU_AD1_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET)), \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK, \ + RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB)) + +#define HAL_RX_MPDU_AD2_15_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET)), \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK, \ + RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB)) + +#define HAL_RX_MPDU_AD2_47_16_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET)), \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK, \ + RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB)) + +#define HAL_RX_MPDU_AD3_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET)), \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK, \ + RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB)) + +#define HAL_RX_MPDU_AD3_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET)), \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK, \ + RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB)) + +#define HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK, \ + RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB)) + +#define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \ + RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB)) + +#define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \ + RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB)) + +#define HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(_rx_mpdu_info) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET)), \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK, \ + RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB)) + +#define HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET)), \ + RX_MSDU_END_14_SA_SW_PEER_ID_MASK, \ + RX_MSDU_END_14_SA_SW_PEER_ID_LSB)) + +#define HAL_RX_GET_FC_VALID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MPDU_FRAME_CONTROL_VALID) + +#define HAL_RX_GET_TO_DS_FLAG(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, TO_DS) + +#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD1_VALID) + +#define HAL_RX_GET_MAC_ADDR2_VALID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_11, MAC_ADDR_AD2_VALID) + +#define HAL_RX_GET_FILTER_CATEGORY(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, RXPCU_MPDU_FILTER_IN_CATEGORY) + +#define HAL_RX_GET_PPDU_ID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, PHY_PPDU_ID) + +#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_9, SW_FRAME_GROUP_ID) + +#define HAL_RX_GET_SW_PEER_ID(rx_mpdu_start) \ + HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO_10, SW_PEER_ID) + +#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ + ((struct rx_msdu_desc_info *) \ + _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ + RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) + +#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \ + ((struct rx_msdu_details *) \ + _OFFSET_TO_BYTE_PTR((link_desc),\ + RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET)) + +#define HAL_RX_MSDU_END_REO_DEST_IND_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET)), \ + RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK, \ + RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_12_FLOW_IDX_OFFSET)), \ + RX_MSDU_END_12_FLOW_IDX_MASK, \ + RX_MSDU_END_12_FLOW_IDX_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET)), \ + RX_MSDU_END_10_FLOW_IDX_INVALID_MASK, \ + RX_MSDU_END_10_FLOW_IDX_INVALID_LSB)) + +#define HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET)), \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK, \ + RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB)) + +#define HAL_RX_MSDU_END_FSE_METADATA_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_13_FSE_METADATA_OFFSET)), \ + RX_MSDU_END_13_FSE_METADATA_MASK, \ + RX_MSDU_END_13_FSE_METADATA_LSB)) + +#define HAL_RX_MSDU_END_CCE_METADATA_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_14_CCE_METADATA_OFFSET)), \ + RX_MSDU_END_14_CCE_METADATA_MASK, \ + RX_MSDU_END_14_CCE_METADATA_LSB)) + +#define HAL_RX_TLV_GET_TCP_CHKSUM(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET)), \ + RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK, \ + RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB)) + +#define HAL_RX_MSDU_END_DA_IDX_GET(_rx_msdu_end) \ + (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \ + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET)), \ + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK, \ + RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB)) + +#define HAL_RX_TLV_GET_FLOW_AGGR_CONT(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET)), \ + RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK, \ + RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB)) + +#define HAL_RX_TLV_GET_FLOW_AGGR_COUNT(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET)), \ + RX_MSDU_END_15_AGGREGATION_COUNT_MASK, \ + RX_MSDU_END_15_AGGREGATION_COUNT_LSB)) + +#define HAL_RX_TLV_GET_FISA_TIMEOUT(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_15_FISA_TIMEOUT_OFFSET)), \ + RX_MSDU_END_15_FISA_TIMEOUT_MASK, \ + RX_MSDU_END_15_FISA_TIMEOUT_LSB)) + +#define HAL_RX_TLV_GET_FISA_CUMULATIVE_L4_CHECKSUM(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET)), \ + RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK, \ + RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB)) + +#define HAL_RX_TLV_GET_FISA_CUMULATIVE_IP_LENGTH(buf) \ + (_HAL_MS( \ + (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\ + msdu_end_tlv.rx_msdu_end), \ + RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET)), \ + RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK, \ + RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB)) + +#if defined(QCA_WIFI_WCN6450) && defined(WLAN_CFR_ENABLE) && \ + defined(WLAN_ENH_CFR_ENABLE) +static inline +void hal_rx_get_bb_info_6450(void *rx_tlv, + void *ppdu_info_hdl) +{ + struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; + + ppdu_info->cfr_info.bb_captured_channel = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); + + ppdu_info->cfr_info.bb_captured_timeout = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); + + ppdu_info->cfr_info.bb_captured_reason = + HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); +} + +static inline +void hal_rx_get_rtt_info_6450(void *rx_tlv, + void *ppdu_info_hdl) +{ + struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; + + ppdu_info->cfr_info.rx_location_info_valid = + HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, + RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); + + ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RTT_CHE_BUFFER_POINTER_LOW32); + + ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RTT_CHE_BUFFER_POINTER_HIGH8); + + ppdu_info->cfr_info.chan_capture_status = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RESERVED_8); + ppdu_info->cfr_info.rx_start_ts = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RX_START_TS); + + ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t) + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RTT_CFO_MEASUREMENT); + + ppdu_info->cfr_info.agc_gain_info0 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_1_RX_PKT_END_DETAILS, + PHY_TIMESTAMP_1_LOWER_32); + + ppdu_info->cfr_info.agc_gain_info1 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_2_RX_PKT_END_DETAILS, + PHY_TIMESTAMP_1_UPPER_32); + + ppdu_info->cfr_info.agc_gain_info2 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_3_RX_PKT_END_DETAILS, + PHY_TIMESTAMP_2_LOWER_32); + + ppdu_info->cfr_info.agc_gain_info3 = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_4_RX_PKT_END_DETAILS, + PHY_TIMESTAMP_2_UPPER_32); + + ppdu_info->cfr_info.mcs_rate = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RTT_MCS_RATE); + + ppdu_info->cfr_info.gi_type = + HAL_RX_GET(rx_tlv, + PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, + RTT_GI_TYPE); +} +#endif +#endif diff --git a/hal/wifi3.0/wcn6450/hal_wcn6450_tx.h b/hal/wifi3.0/wcn6450/hal_wcn6450_tx.h new file mode 100644 index 0000000000..3abc303d4c --- /dev/null +++ b/hal/wifi3.0/wcn6450/hal_wcn6450_tx.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _HAL_6450_TX_H_ +#define _HAL_6450_TX_H_ +#include "tcl_data_cmd.h" +#include "phyrx_rssi_legacy.h" +#include "hal_internal.h" +#include "cdp_txrx_mon_struct.h" +#include "qdf_trace.h" +#include "hal_rx.h" +#include "hal_tx.h" +#include "dp_types.h" +#include "hal_api_mon.h" + +/** + * hal_tx_desc_set_lmac_id_6450 - Set the lmac_id value + * @desc: Handle to Tx Descriptor + * @lmac_id: mac Id to ast matching + * b00 – mac 0 + * b01 – mac 1 + * b10 – mac 2 + * b11 – all macs (legacy HK way) + * + * Return: void + */ +static void hal_tx_desc_set_lmac_id_6450(void *desc, uint8_t lmac_id) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |= + HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id); +} + +/** + * hal_tx_desc_set_mesh_en_6450 - Set mesh_enable flag in Tx descriptor + * @desc: Handle to Tx Descriptor + * @en: For raw WiFi frames, this indicates transmission to a mesh STA, + * enabling the interpretation of the 'Mesh Control Present' bit + * (bit 8) of QoS Control (otherwise this bit is ignored), + * For native WiFi frames, this indicates that a 'Mesh Control' field + * is present between the header and the LLC. + * + * Return: void + */ +static inline +void hal_tx_desc_set_mesh_en_6450(void *desc, uint8_t en) +{ + HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= + HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); +} +#endif