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disp: msm: dsi: Fix incorrect DSI PHY timing of version 4

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For DSI PHY timing of version 4, adds the missing configuation
of phy_clk_params and updates some extra clock parameters.
The less precision during calculation is fixed, which is caused by
not exactly following PHY timing document.

Change-Id: Ibb75d4d3e5b4a5979ff4a85dba1accf3677a6584
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This commit is contained in:
Yujun Zhang
2019-05-09 23:22:43 +08:00
committed by Gerrit - the friendly Code Review server
parent ba12b2cd36
commit 86162602c5
2 changed files with 19 additions and 19 deletions
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11
msm/dsi/dsi_phy_timing_calc.c
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@@ -474,9 +474,8 @@ static int calc_clk_post(struct dsi_phy_hw *phy,
t->rec_max = 255;
/* register value */
rec_cal1 = (t->rec_max - t->rec_min);
rec_cal2 = clk_params->clk_post_buf/100;
t->rec = rec_cal1 * rec_cal2 + t->rec_min;
t->rec = DIV_ROUND_UP((((t->rec_max - t->rec_min) *
clk_params->clk_post_buf) + (t->rec_min * 100)), 100);
rc = dsi_phy_cmn_validate_and_set(t, "clk_post");
if (rc)
@@ -501,7 +500,6 @@ static int calc_clk_pre(struct dsi_phy_hw *phy,
s64 rec_temp1;
s64 clk_prepare, clk_zero, clk_16;
u32 input1;
s64 rec_cal1, rec_cal2;
/* mipi min */
t->mipi_min = cal_clk_pulse_time(8, 0, clk_params->bitclk_mbps);
@@ -526,9 +524,8 @@ static int calc_clk_pre(struct dsi_phy_hw *phy,
t->rec_max = 255;
/* register value */
rec_cal1 = (t->rec_max - t->rec_min);
rec_cal2 = clk_params->clk_pre_buf/100;
t->rec = rec_cal1 * rec_cal2 + t->rec_min;
t->rec =DIV_ROUND_UP((((t->rec_max - t->rec_min) *
125) + (t->rec_min * 100 * 100)), 100 * 100);
rc = dsi_phy_cmn_validate_and_set(t, "clk_pre");
if (rc)