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@@ -1,7 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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*/
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#ifndef _CAM_IFE_CSID_LITE_880_H_
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#ifndef _CAM_IFE_CSID_LITE_880_H_
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@@ -190,7 +190,7 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_880_path_irq_desc[]
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{
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{
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.bitmask = BIT(14),
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.bitmask = BIT(14),
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.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
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.err_type = CAM_ISP_HW_ERROR_CSID_FRAME_SIZE,
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- .desc = "ERROR_PIX_COUNT",
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+ .desc = "ERROR_LINE_COUNT",
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.err_handler = cam_ife_csid_ver2_print_format_measure_info,
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.err_handler = cam_ife_csid_ver2_print_format_measure_info,
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},
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},
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{
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{
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@@ -464,6 +464,10 @@ static struct cam_ife_csid_ver2_common_reg_info
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.global_reset = 1,
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.global_reset = 1,
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.rup_supported = 1,
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.rup_supported = 1,
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.only_master_rup = 1,
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.only_master_rup = 1,
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+ .format_measure_height_mask_val = 0xFFFF,
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+ .format_measure_height_shift_val = 0x10,
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+ .format_measure_width_mask_val = 0xFFFF,
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+ .format_measure_width_shift_val = 0x0,
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.top_reset_irq_mask = 0x1,
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.top_reset_irq_mask = 0x1,
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.top_buf_done_irq_mask = 0x2000,
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.top_buf_done_irq_mask = 0x2000,
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.decode_format_payload_only = 0xF,
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.decode_format_payload_only = 0xF,
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@@ -540,7 +544,7 @@ static struct cam_ife_csid_csi2_rx_reg_info
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.epd_mode_shift_en = 8,
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.epd_mode_shift_en = 8,
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.eotp_shift_en = 9,
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.eotp_shift_en = 9,
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.dyn_sensor_switch_shift_en = 10,
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.dyn_sensor_switch_shift_en = 10,
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- .rup_aup_latch_shift = 11,
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+ .rup_aup_latch_shift = 13,
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.rup_aup_latch_supported = true,
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.rup_aup_latch_supported = true,
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.long_pkt_strobe_rst_shift = 0,
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.long_pkt_strobe_rst_shift = 0,
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.short_pkt_strobe_rst_shift = 1,
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.short_pkt_strobe_rst_shift = 1,
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@@ -636,8 +640,8 @@ static struct cam_ife_csid_ver2_path_reg_info
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.overflow_ctrl_mode_val = 0x8,
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.overflow_ctrl_mode_val = 0x8,
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.min_hbi_shift_val = 4,
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.min_hbi_shift_val = 4,
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.start_master_sel_shift_val = 4,
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.start_master_sel_shift_val = 4,
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- .fatal_err_mask = 0x7,
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- .non_fatal_err_mask = 0x10080000,
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+ .fatal_err_mask = 0x20186001,
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+ .non_fatal_err_mask = 0x12000004,
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.sof_irq_mask = 0x10,
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.sof_irq_mask = 0x10,
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.rup_irq_mask = 0x800000,
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.rup_irq_mask = 0x800000,
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.epoch0_irq_mask = 0x200000,
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.epoch0_irq_mask = 0x200000,
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@@ -729,8 +733,8 @@ static struct cam_ife_csid_ver2_path_reg_info
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.timestamp_en_shift_val = 6,
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.timestamp_en_shift_val = 6,
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.debug_byte_cntr_rst_shift_val = 2,
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.debug_byte_cntr_rst_shift_val = 2,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x5,
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- .non_fatal_err_mask = 0x10080000,
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+ .fatal_err_mask = 0x20186001,
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+ .non_fatal_err_mask = 0x12000004,
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.sof_irq_mask = 0x10,
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.sof_irq_mask = 0x10,
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.rup_irq_mask = 0x800000,
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.rup_irq_mask = 0x800000,
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.epoch0_irq_mask = 0x200000,
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.epoch0_irq_mask = 0x200000,
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@@ -822,8 +826,8 @@ static struct cam_ife_csid_ver2_path_reg_info
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.timestamp_en_shift_val = 6,
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.timestamp_en_shift_val = 6,
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.debug_byte_cntr_rst_shift_val = 2,
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.debug_byte_cntr_rst_shift_val = 2,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x5,
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- .non_fatal_err_mask = 0x10080000,
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+ .fatal_err_mask = 0x20186001,
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+ .non_fatal_err_mask = 0x12000004,
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.sof_irq_mask = 0x10,
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.sof_irq_mask = 0x10,
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.rup_irq_mask = 0x800000,
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.rup_irq_mask = 0x800000,
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.epoch0_irq_mask = 0x200000,
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.epoch0_irq_mask = 0x200000,
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@@ -915,8 +919,8 @@ static struct cam_ife_csid_ver2_path_reg_info
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.timestamp_en_shift_val = 6,
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.timestamp_en_shift_val = 6,
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.debug_byte_cntr_rst_shift_val = 2,
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.debug_byte_cntr_rst_shift_val = 2,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x5,
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- .non_fatal_err_mask = 0x10080000,
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+ .fatal_err_mask = 0x20186001,
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+ .non_fatal_err_mask = 0x12000004,
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.sof_irq_mask = 0x10,
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.sof_irq_mask = 0x10,
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.rup_irq_mask = 0x800000,
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.rup_irq_mask = 0x800000,
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.epoch0_irq_mask = 0x200000,
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.epoch0_irq_mask = 0x200000,
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@@ -1008,8 +1012,8 @@ static struct cam_ife_csid_ver2_path_reg_info
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.timestamp_en_shift_val = 6,
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.timestamp_en_shift_val = 6,
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.debug_byte_cntr_rst_shift_val = 2,
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.debug_byte_cntr_rst_shift_val = 2,
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.ccif_violation_en = 1,
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.ccif_violation_en = 1,
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- .fatal_err_mask = 0x5,
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- .non_fatal_err_mask = 0x10080000,
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+ .fatal_err_mask = 0x20186001,
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+ .non_fatal_err_mask = 0x12000004,
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.sof_irq_mask = 0x10,
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.sof_irq_mask = 0x10,
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.rup_irq_mask = 0x800000,
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.rup_irq_mask = 0x800000,
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.epoch0_irq_mask = 0x200000,
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.epoch0_irq_mask = 0x200000,
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