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disp: msm: dsi: Correct minimum bit clk calculation for cphy cmd mode

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For calculating bit rate in cphy, we multiply bit rate by a factor of
7/16 where 7 is the number of symbols and 16 is the bits per symbol.
But we are currently not considering the 7/16 factor while calculating
minimum bit clk value for command mode which is resulting in a smaller
bit rate value than the minimum bit clk.

Bit rate should always be greater than the minimum bit clk which otherwise
can lead to discrepancies. Correct minimum bit clk calculation for command
mode, by multiplying a factor of 7/16 if cphy.

Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This commit is contained in:
Srihitha Tangudu
2022-02-17 16:27:26 +05:30
committed by Gerrit - the friendly Code Review server
parent b3b8331cdb
commit 6fb25a2f3d
2 changed files with 10 additions and 0 deletions
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6
msm/dsi/dsi_panel.c
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@@ -4020,6 +4020,7 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
u32 jitter_numer, jitter_denom, prefill_lines;
u32 default_prefill_lines, actual_prefill_lines, vtotal;
u32 min_threshold_us, prefill_time_us, max_transfer_us, packet_overhead;
u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
u16 bpp;
/* Packet overhead in bits,
@@ -4065,6 +4066,11 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
timing->min_dsi_clk_hz = min_bitclk_hz;
if (config->phy_type == DSI_PHY_TYPE_CPHY) {
do_div(timing->min_dsi_clk_hz, bits_per_symbol);
timing->min_dsi_clk_hz *= num_of_symbols;
}
/*
* Apart from prefill line time, we need to take into account RSCC mode threshold time. In
* cases where RSC is disabled, as jitter is no longer considered we need to make sure we