From 6fb25a2f3d6fda2eba4e1fae506e18a7d3ffc13d Mon Sep 17 00:00:00 2001 From: Srihitha Tangudu Date: Thu, 17 Feb 2022 16:27:26 +0530 Subject: [PATCH] disp: msm: dsi: Correct minimum bit clk calculation for cphy cmd mode For calculating bit rate in cphy, we multiply bit rate by a factor of 7/16 where 7 is the number of symbols and 16 is the bits per symbol. But we are currently not considering the 7/16 factor while calculating minimum bit clk value for command mode which is resulting in a smaller bit rate value than the minimum bit clk. Bit rate should always be greater than the minimum bit clk which otherwise can lead to discrepancies. Correct minimum bit clk calculation for command mode, by multiplying a factor of 7/16 if cphy. Change-Id: I39b202dcafe60e2047549f84ff9388b46ae490a5 Signed-off-by: Srihitha Tangudu --- msm/dsi/dsi_ctrl.c | 4 ++++ msm/dsi/dsi_panel.c | 6 ++++++ 2 files changed, 10 insertions(+) diff --git a/msm/dsi/dsi_ctrl.c b/msm/dsi/dsi_ctrl.c index a33deda21e..707a9ca2fe 100644 --- a/msm/dsi/dsi_ctrl.c +++ b/msm/dsi/dsi_ctrl.c @@ -1076,6 +1076,10 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, } } else if (config->panel_mode == DSI_OP_CMD_MODE) { /* Calculate the bit rate needed to match dsi transfer time */ + if (host_cfg->phy_type == DSI_PHY_TYPE_CPHY) { + min_dsi_clk_hz *= bits_per_symbol; + do_div(min_dsi_clk_hz, num_of_symbols); + } bit_rate = min_dsi_clk_hz * frame_time_us; do_div(bit_rate, dsi_transfer_time_us); bit_rate = bit_rate * num_of_lanes; diff --git a/msm/dsi/dsi_panel.c b/msm/dsi/dsi_panel.c index 94ef74a5f1..a6a76fa523 100644 --- a/msm/dsi/dsi_panel.c +++ b/msm/dsi/dsi_panel.c @@ -4020,6 +4020,7 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, u32 jitter_numer, jitter_denom, prefill_lines; u32 default_prefill_lines, actual_prefill_lines, vtotal; u32 min_threshold_us, prefill_time_us, max_transfer_us, packet_overhead; + u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */ u16 bpp; /* Packet overhead in bits, @@ -4065,6 +4066,11 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config, timing->min_dsi_clk_hz = min_bitclk_hz; + if (config->phy_type == DSI_PHY_TYPE_CPHY) { + do_div(timing->min_dsi_clk_hz, bits_per_symbol); + timing->min_dsi_clk_hz *= num_of_symbols; + } + /* * Apart from prefill line time, we need to take into account RSCC mode threshold time. In * cases where RSC is disabled, as jitter is no longer considered we need to make sure we