qcacmn: add HAL support for qca6390
hal_hw_srng table and register offsets array, some target specific functions are defined separately for each new target. define the same for qca6290. Change-Id: I08c1243bc50460fac776e28186acfa192fb1ff66
This commit is contained in:
Balamurugan Mahalingam
committed by
nshrivas
nshrivas
parent
f72cb1f1ff
commit
6cf4c27417
@@ -37,6 +37,9 @@ void hal_qca6290_attach(struct hal_soc *hal);
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#ifdef QCA_WIFI_QCA8074
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#ifdef QCA_WIFI_QCA8074
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void hal_qca8074_attach(struct hal_soc *hal);
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void hal_qca8074_attach(struct hal_soc *hal);
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#endif
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#endif
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#ifdef QCA_WIFI_QCA6390
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void hal_qca6390_attach(struct hal_soc *hal);
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#endif
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/**
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/**
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* hal_get_srng_ring_id() - get the ring id of a descriped ring
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* hal_get_srng_ring_id() - get the ring id of a descriped ring
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@@ -221,6 +224,12 @@ static void hal_target_based_configure(struct hal_soc *hal)
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hal_qca6290_attach(hal);
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hal_qca6290_attach(hal);
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break;
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break;
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#endif
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#endif
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#ifdef QCA_WIFI_QCA6390
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case TARGET_TYPE_QCA6390:
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hal->use_register_windowing = true;
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hal_qca6390_attach(hal);
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break;
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#endif
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#ifdef QCA_WIFI_QCA8074
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#ifdef QCA_WIFI_QCA8074
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case TARGET_TYPE_QCA8074:
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case TARGET_TYPE_QCA8074:
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hal_qca8074_attach(hal);
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hal_qca8074_attach(hal);
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347
hal/wifi3.0/qca6390/hal_6390_rx.h
Normal file
347
hal/wifi3.0/qca6390/hal_6390_rx.h
Normal file
@@ -0,0 +1,347 @@
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/*
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* Copyright (c) 2018 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qdf_util.h"
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#include "qdf_types.h"
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#include "qdf_lock.h"
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#include "qdf_mem.h"
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#include "qdf_nbuf.h"
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#include "tcl_data_cmd.h"
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#include "mac_tcl_reg_seq_hwioreg.h"
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#include "phyrx_rssi_legacy.h"
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#include "rx_msdu_start.h"
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#include "tlv_tag_def.h"
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#include "hal_hw_headers.h"
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#include "hal_internal.h"
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#include "cdp_txrx_mon_struct.h"
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#include "qdf_trace.h"
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#include "hal_rx.h"
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#include "hal_tx.h"
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#include "dp_types.h"
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#include "hal_api_mon.h"
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#include "phyrx_other_receive_info_ru_details.h"
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#define HAL_RX_MSDU_START_MIMO_SS_BITMAP(_rx_msdu_start)\
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(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
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RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET)), \
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RX_MSDU_START_5_MIMO_SS_BITMAP_MASK, \
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RX_MSDU_START_5_MIMO_SS_BITMAP_LSB))
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/*
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* hal_rx_msdu_start_nss_get_6390(): API to get the NSS
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* Interval from rx_msdu_start
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*
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* @buf: pointer to the start of RX PKT TLV header
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* Return: uint32_t(nss)
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*/
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uint32_t
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hal_rx_msdu_start_nss_get_6390(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_msdu_start *msdu_start =
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&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
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uint8_t mimo_ss_bitmap;
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mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start);
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return qdf_get_hweight8(mimo_ss_bitmap);
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}
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qdf_export_symbol(hal_rx_msdu_start_nss_get_6390);
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/**
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* hal_rx_mon_hw_desc_get_mpdu_status_6390(): Retrieve MPDU status
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*
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* @ hw_desc_addr: Start address of Rx HW TLVs
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* @ rs: Status for monitor mode
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*
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* Return: void
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*/
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void hal_rx_mon_hw_desc_get_mpdu_status_6390(void *hw_desc_addr,
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struct mon_rx_status *rs)
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{
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struct rx_msdu_start *rx_msdu_start;
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struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
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uint32_t reg_value;
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const uint32_t sgi_hw_to_cdp[] = {
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CDP_SGI_0_8_US,
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CDP_SGI_0_4_US,
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CDP_SGI_1_6_US,
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CDP_SGI_3_2_US,
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};
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rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
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HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs);
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rs->ant_signal_db = HAL_RX_GET(rx_msdu_start,
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RX_MSDU_START_5, USER_RSSI);
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rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC);
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reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI);
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rs->sgi = sgi_hw_to_cdp[reg_value];
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reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, PKT_TYPE);
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switch (reg_value) {
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case HAL_RX_PKT_TYPE_11N:
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rs->ht_flags = 1;
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break;
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case HAL_RX_PKT_TYPE_11AC:
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rs->vht_flags = 1;
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reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5,
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RECEIVE_BANDWIDTH);
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rs->vht_flag_values2 = reg_value;
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break;
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case HAL_RX_PKT_TYPE_11AX:
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rs->he_flags = 1;
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break;
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default:
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break;
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}
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reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE);
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rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0;
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/* TODO: rs->beamformed should be set for SU beamforming also */
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}
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qdf_export_symbol(hal_rx_mon_hw_desc_get_mpdu_status_6390);
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#define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
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uint32_t hal_get_link_desc_size_6390(void)
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{
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return LINK_DESC_SIZE;
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}
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qdf_export_symbol(hal_get_link_desc_size_6390);
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/*
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* hal_rx_get_tlv_6390(): API to get the tlv
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*
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* @rx_tlv: TLV data extracted from the rx packet
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* Return: uint8_t
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*/
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uint8_t hal_rx_get_tlv_6390(void *rx_tlv)
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{
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return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH);
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}
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qdf_export_symbol(hal_rx_get_tlv_6390);
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/**
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* hal_rx_proc_phyrx_other_receive_info_tlv_6390()
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* - process other receive info TLV
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* @rx_tlv_hdr: pointer to TLV header
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* @ppdu_info: pointer to ppdu_info
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*
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* Return: None
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*/
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void hal_rx_proc_phyrx_other_receive_info_tlv_6390(void *rx_tlv_hdr,
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void *ppdu_info_handle)
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{
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uint32_t tlv_tag, tlv_len;
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uint32_t temp_len, other_tlv_len, other_tlv_tag;
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void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
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void *other_tlv_hdr = NULL;
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void *other_tlv = NULL;
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uint32_t ru_details_channel_0;
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struct hal_rx_ppdu_info *ppdu_info =
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(struct hal_rx_ppdu_info *)ppdu_info_handle;
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tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
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tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
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temp_len = 0;
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other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
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other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
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other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
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temp_len += other_tlv_len;
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other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
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switch (other_tlv_tag) {
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case WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E:
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ru_details_channel_0 =
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HAL_RX_GET(other_tlv,
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PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0,
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RU_DETAILS_CHANNEL_0);
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qdf_mem_copy(ppdu_info->rx_status.he_RU,
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&ru_details_channel_0,
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sizeof(ppdu_info->rx_status.he_RU));
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if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_20)
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ppdu_info->rx_status.he_sig_b_common_known |=
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QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0;
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if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_40)
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ppdu_info->rx_status.he_sig_b_common_known |=
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QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU1;
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if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_80)
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ppdu_info->rx_status.he_sig_b_common_known |=
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QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU2;
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if (ppdu_info->rx_status.bw >= HAL_FULL_RX_BW_160)
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ppdu_info->rx_status.he_sig_b_common_known |=
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QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU3;
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break;
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default:
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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"%s unhandled TLV type: %d, TLV len:%d",
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__func__, other_tlv_tag, other_tlv_len);
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break;
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}
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}
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qdf_export_symbol(hal_rx_proc_phyrx_other_receive_info_tlv_6390);
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/**
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* hal_rx_dump_msdu_start_tlv_6390() : dump RX msdu_start TLV in structured
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* human readable format.
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* @ msdu_start: pointer the msdu_start TLV in pkt.
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* @ dbg_level: log level.
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*
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* Return: void
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*/
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void hal_rx_dump_msdu_start_tlv_6390(void *msdustart, uint8_t dbg_level)
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{
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struct rx_msdu_start *msdu_start = (struct rx_msdu_start *)msdustart;
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QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
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"rx_msdu_start tlv - "
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"rxpcu_mpdu_filter_in_category: %d "
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"sw_frame_group_id: %d "
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"phy_ppdu_id: %d "
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"msdu_length: %d "
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"ipsec_esp: %d "
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"l3_offset: %d "
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"ipsec_ah: %d "
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"l4_offset: %d "
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"msdu_number: %d "
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"decap_format: %d "
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"ipv4_proto: %d "
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"ipv6_proto: %d "
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"tcp_proto: %d "
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"udp_proto: %d "
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"ip_frag: %d "
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"tcp_only_ack: %d "
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"da_is_bcast_mcast: %d "
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"ip4_protocol_ip6_next_header: %d "
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"toeplitz_hash_2_or_4: %d "
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"flow_id_toeplitz: %d "
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"user_rssi: %d "
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"pkt_type: %d "
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"stbc: %d "
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"sgi: %d "
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"rate_mcs: %d "
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"receive_bandwidth: %d "
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"reception_type: %d "
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"ppdu_start_timestamp: %d "
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"sw_phy_meta_data: %d ",
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msdu_start->rxpcu_mpdu_filter_in_category,
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msdu_start->sw_frame_group_id,
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msdu_start->phy_ppdu_id,
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msdu_start->msdu_length,
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msdu_start->ipsec_esp,
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msdu_start->l3_offset,
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msdu_start->ipsec_ah,
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msdu_start->l4_offset,
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msdu_start->msdu_number,
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msdu_start->decap_format,
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msdu_start->ipv4_proto,
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msdu_start->ipv6_proto,
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msdu_start->tcp_proto,
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msdu_start->udp_proto,
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msdu_start->ip_frag,
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msdu_start->tcp_only_ack,
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msdu_start->da_is_bcast_mcast,
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msdu_start->ip4_protocol_ip6_next_header,
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msdu_start->toeplitz_hash_2_or_4,
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msdu_start->flow_id_toeplitz,
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msdu_start->user_rssi,
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msdu_start->pkt_type,
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msdu_start->stbc,
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msdu_start->sgi,
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msdu_start->rate_mcs,
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msdu_start->receive_bandwidth,
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msdu_start->reception_type,
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msdu_start->ppdu_start_timestamp,
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msdu_start->sw_phy_meta_data);
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}
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qdf_export_symbol(hal_rx_dump_msdu_start_tlv_6390);
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/*
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* Get tid from RX_MPDU_START
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*/
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||||||
|
#define HAL_RX_MPDU_INFO_TID_GET(_rx_mpdu_info) \
|
||||||
|
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_info), \
|
||||||
|
RX_MPDU_INFO_3_TID_OFFSET)), \
|
||||||
|
RX_MPDU_INFO_3_TID_MASK, \
|
||||||
|
RX_MPDU_INFO_3_TID_LSB))
|
||||||
|
|
||||||
|
uint32_t hal_rx_mpdu_start_tid_get_6390(uint8_t *buf)
|
||||||
|
{
|
||||||
|
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
|
||||||
|
struct rx_mpdu_start *mpdu_start =
|
||||||
|
&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
|
||||||
|
uint32_t tid;
|
||||||
|
|
||||||
|
tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details);
|
||||||
|
|
||||||
|
return tid;
|
||||||
|
}
|
||||||
|
|
||||||
|
qdf_export_symbol(hal_rx_mpdu_start_tid_get_6390);
|
||||||
|
|
||||||
|
#define HAL_RX_MSDU_START_RECEPTION_TYPE_GET(_rx_msdu_start) \
|
||||||
|
(_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
|
||||||
|
RX_MSDU_START_5_RECEPTION_TYPE_OFFSET)), \
|
||||||
|
RX_MSDU_START_5_RECEPTION_TYPE_MASK, \
|
||||||
|
RX_MSDU_START_5_RECEPTION_TYPE_LSB))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* hal_rx_msdu_start_reception_type_get(): API to get the reception type
|
||||||
|
* Interval from rx_msdu_start
|
||||||
|
*
|
||||||
|
* @buf: pointer to the start of RX PKT TLV header
|
||||||
|
* Return: uint32_t(reception_type)
|
||||||
|
*/
|
||||||
|
uint32_t hal_rx_msdu_start_reception_type_get_6390(uint8_t *buf)
|
||||||
|
{
|
||||||
|
struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
|
||||||
|
struct rx_msdu_start *msdu_start =
|
||||||
|
&pkt_tlvs->msdu_start_tlv.rx_msdu_start;
|
||||||
|
uint32_t reception_type;
|
||||||
|
|
||||||
|
reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start);
|
||||||
|
|
||||||
|
return reception_type;
|
||||||
|
}
|
||||||
|
|
||||||
|
qdf_export_symbol(hal_rx_msdu_start_reception_type_get_6390);
|
||||||
|
|
||||||
511
hal/wifi3.0/qca6390/hal_6390_srng.c
Normal file
511
hal/wifi3.0/qca6390/hal_6390_srng.c
Normal file
@@ -0,0 +1,511 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met:
|
||||||
|
* * Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* * Redistributions in binary form must reproduce the above
|
||||||
|
* copyright notice, this list of conditions and the following
|
||||||
|
* disclaimer in the documentation and/or other materials provided
|
||||||
|
* with the distribution.
|
||||||
|
* * Neither the name of The Linux Foundation nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived
|
||||||
|
* from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||||
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||||
|
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||||
|
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "qdf_types.h"
|
||||||
|
#include "qdf_util.h"
|
||||||
|
#include "qdf_types.h"
|
||||||
|
#include "qdf_lock.h"
|
||||||
|
#include "qdf_mem.h"
|
||||||
|
#include "qdf_nbuf.h"
|
||||||
|
#include "hal_hw_headers.h"
|
||||||
|
#include "hal_internal.h"
|
||||||
|
#include "hal_api.h"
|
||||||
|
#include "target_type.h"
|
||||||
|
#include "wcss_version.h"
|
||||||
|
#include "qdf_module.h"
|
||||||
|
#include "hal_6390_tx.h"
|
||||||
|
#include "hal_6390_rx.h"
|
||||||
|
|
||||||
|
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
|
||||||
|
/* tx */
|
||||||
|
hal_tx_desc_set_dscp_tid_table_id_6390,
|
||||||
|
hal_tx_set_dscp_tid_map_6390,
|
||||||
|
hal_tx_update_dscp_tid_6390,
|
||||||
|
hal_tx_desc_set_lmac_id_6390,
|
||||||
|
|
||||||
|
/* rx */
|
||||||
|
hal_rx_msdu_start_nss_get_6390,
|
||||||
|
hal_rx_mon_hw_desc_get_mpdu_status_6390,
|
||||||
|
hal_rx_get_tlv_6390,
|
||||||
|
hal_rx_proc_phyrx_other_receive_info_tlv_6390,
|
||||||
|
hal_rx_dump_msdu_start_tlv_6390,
|
||||||
|
hal_get_link_desc_size_6390,
|
||||||
|
hal_rx_mpdu_start_tid_get_6390,
|
||||||
|
hal_rx_msdu_start_reception_type_get_6390,
|
||||||
|
};
|
||||||
|
|
||||||
|
struct hal_hw_srng_config hw_srng_table_6390[] = {
|
||||||
|
/* TODO: max_rings can populated by querying HW capabilities */
|
||||||
|
{ /* REO_DST */
|
||||||
|
.start_ring_id = HAL_SRNG_REO2SW1,
|
||||||
|
.max_rings = 4,
|
||||||
|
.entry_size = sizeof(struct reo_destination_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET)
|
||||||
|
},
|
||||||
|
.reg_size = {
|
||||||
|
HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
|
||||||
|
HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
|
||||||
|
HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
|
||||||
|
HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* REO_EXCEPTION */
|
||||||
|
/* Designating REO2TCL ring as exception ring. This ring is
|
||||||
|
* similar to other REO2SW rings though it is named as REO2TCL.
|
||||||
|
* Any of theREO2SW rings can be used as exception ring.
|
||||||
|
*/
|
||||||
|
.start_ring_id = HAL_SRNG_REO2TCL,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct reo_destination_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET)
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* REO_REINJECT */
|
||||||
|
.start_ring_id = HAL_SRNG_SW2REO,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct reo_entrance_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
HWIO_REO_R2_SW2REO_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET)
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* REO_CMD */
|
||||||
|
.start_ring_id = HAL_SRNG_REO_CMD,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = (sizeof(struct tlv_32_hdr) +
|
||||||
|
sizeof(struct reo_get_queue_stats)) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* REO_STATUS */
|
||||||
|
.start_ring_id = HAL_SRNG_REO_STATUS,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = (sizeof(struct tlv_32_hdr) +
|
||||||
|
sizeof(struct reo_get_queue_stats_status)) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_REO_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* TCL_DATA */
|
||||||
|
.start_ring_id = HAL_SRNG_SW2TCL1,
|
||||||
|
.max_rings = 3,
|
||||||
|
.entry_size = (sizeof(struct tlv_32_hdr) +
|
||||||
|
sizeof(struct tcl_data_cmd)) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
},
|
||||||
|
.reg_size = {
|
||||||
|
HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
|
||||||
|
HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
|
||||||
|
HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
|
||||||
|
HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* TCL_CMD */
|
||||||
|
.start_ring_id = HAL_SRNG_SW2TCL_CMD,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = (sizeof(struct tlv_32_hdr) +
|
||||||
|
sizeof(struct tcl_gse_cmd)) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* TCL_STATUS */
|
||||||
|
.start_ring_id = HAL_SRNG_TCL_STATUS,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = (sizeof(struct tlv_32_hdr) +
|
||||||
|
sizeof(struct tcl_status_ring)) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* CE_SRC */
|
||||||
|
.start_ring_id = HAL_SRNG_CE_0_SRC,
|
||||||
|
.max_rings = 12,
|
||||||
|
.entry_size = sizeof(struct ce_src_desc) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
|
||||||
|
},
|
||||||
|
.reg_size = {
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* CE_DST */
|
||||||
|
.start_ring_id = HAL_SRNG_CE_0_DST,
|
||||||
|
.max_rings = 12,
|
||||||
|
.entry_size = 8 >> 2,
|
||||||
|
/*TODO: entry_size above should actually be
|
||||||
|
* sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
|
||||||
|
* of struct ce_dst_desc in HW header files
|
||||||
|
*/
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||||
|
},
|
||||||
|
.reg_size = {
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* CE_DST_STATUS */
|
||||||
|
.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
|
||||||
|
.max_rings = 12,
|
||||||
|
.entry_size = sizeof(struct ce_stat_desc) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* TODO: check destination status ring registers */
|
||||||
|
.reg_size = {
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
|
||||||
|
SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* WBM_IDLE_LINK */
|
||||||
|
.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* SW2WBM_RELEASE */
|
||||||
|
.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct wbm_release_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
},
|
||||||
|
/* Single ring - provide ring size if multiple rings of this
|
||||||
|
* type are supported
|
||||||
|
*/
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* WBM2SW_RELEASE */
|
||||||
|
.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
|
||||||
|
.max_rings = 4,
|
||||||
|
.entry_size = sizeof(struct wbm_release_ring) >> 2,
|
||||||
|
.lmac_ring = FALSE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
.reg_start = {
|
||||||
|
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
},
|
||||||
|
.reg_size = {
|
||||||
|
HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
|
||||||
|
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
|
||||||
|
HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
|
||||||
|
},
|
||||||
|
.max_size =
|
||||||
|
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
|
||||||
|
HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_BUF */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
|
||||||
|
#ifdef IPA_OFFLOAD
|
||||||
|
.max_rings = 3,
|
||||||
|
#else
|
||||||
|
.max_rings = 2,
|
||||||
|
#endif
|
||||||
|
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_DST */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct reo_entrance_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_MONITOR_BUF */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_MONITOR_STATUS */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_MONITOR_DST */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct reo_entrance_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_DST_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* RXDMA_MONITOR_DESC */
|
||||||
|
.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
{ /* DIR_BUF_RX_DMA_SRC */
|
||||||
|
.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
#ifdef WLAN_FEATURE_CIF_CFR
|
||||||
|
{ /* WIFI_POS_SRC */
|
||||||
|
.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
|
||||||
|
.max_rings = 1,
|
||||||
|
.entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
|
||||||
|
.lmac_ring = TRUE,
|
||||||
|
.ring_dir = HAL_SRNG_SRC_RING,
|
||||||
|
/* reg_start is not set because LMAC rings are not accessed
|
||||||
|
* from host
|
||||||
|
*/
|
||||||
|
.reg_start = {},
|
||||||
|
.reg_size = {},
|
||||||
|
.max_size = HAL_RXDMA_MAX_RING_SIZE,
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
int32_t hal_hw_reg_offset_qca6390[] = {
|
||||||
|
/* dst */
|
||||||
|
REG_OFFSET(DST, HP),
|
||||||
|
REG_OFFSET(DST, TP),
|
||||||
|
REG_OFFSET(DST, ID),
|
||||||
|
REG_OFFSET(DST, MISC),
|
||||||
|
REG_OFFSET(DST, HP_ADDR_LSB),
|
||||||
|
REG_OFFSET(DST, HP_ADDR_MSB),
|
||||||
|
REG_OFFSET(DST, MSI1_BASE_LSB),
|
||||||
|
REG_OFFSET(DST, MSI1_BASE_MSB),
|
||||||
|
REG_OFFSET(DST, MSI1_DATA),
|
||||||
|
REG_OFFSET(DST, BASE_LSB),
|
||||||
|
REG_OFFSET(DST, BASE_MSB),
|
||||||
|
REG_OFFSET(DST, PRODUCER_INT_SETUP),
|
||||||
|
/* src */
|
||||||
|
REG_OFFSET(SRC, HP),
|
||||||
|
REG_OFFSET(SRC, TP),
|
||||||
|
REG_OFFSET(SRC, ID),
|
||||||
|
REG_OFFSET(SRC, MISC),
|
||||||
|
REG_OFFSET(SRC, TP_ADDR_LSB),
|
||||||
|
REG_OFFSET(SRC, TP_ADDR_MSB),
|
||||||
|
REG_OFFSET(SRC, MSI1_BASE_LSB),
|
||||||
|
REG_OFFSET(SRC, MSI1_BASE_MSB),
|
||||||
|
REG_OFFSET(SRC, MSI1_DATA),
|
||||||
|
REG_OFFSET(SRC, BASE_LSB),
|
||||||
|
REG_OFFSET(SRC, BASE_MSB),
|
||||||
|
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX0),
|
||||||
|
REG_OFFSET(SRC, CONSUMER_INT_SETUP_IX1),
|
||||||
|
};
|
||||||
|
|
||||||
|
void hal_qca6390_attach(struct hal_soc *hal_soc)
|
||||||
|
{
|
||||||
|
hal_soc->hw_srng_table = hw_srng_table_6390;
|
||||||
|
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
|
||||||
|
hal_soc->ops = &qca6390_hal_hw_txrx_ops;
|
||||||
|
}
|
||||||
187
hal/wifi3.0/qca6390/hal_6390_tx.h
Normal file
187
hal/wifi3.0/qca6390/hal_6390_tx.h
Normal file
@@ -0,0 +1,187 @@
|
|||||||
|
/*
|
||||||
|
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met:
|
||||||
|
* * Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* * Redistributions in binary form must reproduce the above
|
||||||
|
* copyright notice, this list of conditions and the following
|
||||||
|
* disclaimer in the documentation and/or other materials provided
|
||||||
|
* with the distribution.
|
||||||
|
* * Neither the name of The Linux Foundation nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived
|
||||||
|
* from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
|
||||||
|
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||||
|
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
|
||||||
|
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||||
|
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||||
|
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||||
|
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||||
|
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
|
||||||
|
* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
|
||||||
|
* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "tcl_data_cmd.h"
|
||||||
|
#include "mac_tcl_reg_seq_hwioreg.h"
|
||||||
|
#include "phyrx_rssi_legacy.h"
|
||||||
|
#include "hal_hw_headers.h"
|
||||||
|
#include "hal_internal.h"
|
||||||
|
#include "cdp_txrx_mon_struct.h"
|
||||||
|
#include "qdf_trace.h"
|
||||||
|
#include "hal_rx.h"
|
||||||
|
#include "hal_tx.h"
|
||||||
|
#include "dp_types.h"
|
||||||
|
#include "hal_api_mon.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_tx_desc_set_dscp_tid_table_id_6390() - Sets DSCP to TID conversion
|
||||||
|
* table ID
|
||||||
|
* @desc: Handle to Tx Descriptor
|
||||||
|
* @id: DSCP to tid conversion table to be used for this frame
|
||||||
|
*
|
||||||
|
* Return: void
|
||||||
|
*/
|
||||||
|
void hal_tx_desc_set_dscp_tid_table_id_6390(void *desc,
|
||||||
|
uint8_t id)
|
||||||
|
{
|
||||||
|
HAL_SET_FLD(desc, TCL_DATA_CMD_5,
|
||||||
|
DSCP_TID_TABLE_NUM) |=
|
||||||
|
HAL_TX_SM(TCL_DATA_CMD_5,
|
||||||
|
DSCP_TID_TABLE_NUM, id);
|
||||||
|
}
|
||||||
|
|
||||||
|
qdf_export_symbol(hal_tx_desc_set_dscp_tid_table_id_6390);
|
||||||
|
|
||||||
|
#define DSCP_TID_TABLE_SIZE 24
|
||||||
|
#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_tx_set_dscp_tid_map_6390() - Configure default DSCP to TID map table
|
||||||
|
* @soc: HAL SoC context
|
||||||
|
* @map: DSCP-TID mapping table
|
||||||
|
* @id: mapping table ID - 0-31
|
||||||
|
*
|
||||||
|
* DSCP are mapped to 8 TID values using TID values programmed
|
||||||
|
* in any of the 32 DSCP_TID_MAPS (id = 0-31).
|
||||||
|
*
|
||||||
|
* Return: none
|
||||||
|
*/
|
||||||
|
void hal_tx_set_dscp_tid_map_6390(void *hal_soc, uint8_t *map,
|
||||||
|
uint8_t id)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
uint32_t addr, cmn_reg_addr;
|
||||||
|
uint32_t value = 0, regval;
|
||||||
|
uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
|
||||||
|
|
||||||
|
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||||
|
|
||||||
|
if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX)
|
||||||
|
return;
|
||||||
|
|
||||||
|
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET);
|
||||||
|
|
||||||
|
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET,
|
||||||
|
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||||
|
|
||||||
|
/* Enable read/write access */
|
||||||
|
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||||
|
regval |=
|
||||||
|
(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||||
|
|
||||||
|
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||||
|
|
||||||
|
/* Write 8 (24 bits) DSCP-TID mappings in each interation */
|
||||||
|
for (i = 0; i < 64; i += 8) {
|
||||||
|
value = (map[i] |
|
||||||
|
(map[i + 1] << 0x3) |
|
||||||
|
(map[i + 2] << 0x6) |
|
||||||
|
(map[i + 3] << 0x9) |
|
||||||
|
(map[i + 4] << 0xc) |
|
||||||
|
(map[i + 5] << 0xf) |
|
||||||
|
(map[i + 6] << 0x12) |
|
||||||
|
(map[i + 7] << 0x15));
|
||||||
|
|
||||||
|
qdf_mem_copy(&val[cnt], (void *)&value, 3);
|
||||||
|
cnt += 3;
|
||||||
|
}
|
||||||
|
|
||||||
|
for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
|
||||||
|
regval = *(uint32_t *)(val + i);
|
||||||
|
HAL_REG_WRITE(soc, addr,
|
||||||
|
(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||||
|
addr += 4;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Diasble read/write access */
|
||||||
|
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||||
|
regval &=
|
||||||
|
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||||
|
|
||||||
|
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||||
|
}
|
||||||
|
|
||||||
|
qdf_export_symbol(hal_tx_set_dscp_tid_map_6390);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_tx_update_dscp_tid_6390() - Update the dscp tid map table as updated
|
||||||
|
* by the user
|
||||||
|
* @soc: HAL SoC context
|
||||||
|
* @map: DSCP-TID mapping table
|
||||||
|
* @id : MAP ID
|
||||||
|
* @dscp: DSCP_TID map index
|
||||||
|
*
|
||||||
|
* Return: void
|
||||||
|
*/
|
||||||
|
void hal_tx_update_dscp_tid_6390(void *hal_soc, uint8_t tid,
|
||||||
|
uint8_t id, uint8_t dscp)
|
||||||
|
{
|
||||||
|
int index;
|
||||||
|
uint32_t addr;
|
||||||
|
uint32_t value;
|
||||||
|
uint32_t regval;
|
||||||
|
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||||
|
|
||||||
|
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||||
|
SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
|
||||||
|
|
||||||
|
index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
|
||||||
|
addr += 4 * (dscp / HAL_TX_NUM_DSCP_PER_REGISTER);
|
||||||
|
value = tid << (HAL_TX_BITS_PER_TID * index);
|
||||||
|
|
||||||
|
regval = HAL_REG_READ(soc, addr);
|
||||||
|
regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
|
||||||
|
regval |= value;
|
||||||
|
|
||||||
|
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||||
|
}
|
||||||
|
|
||||||
|
qdf_export_symbol(hal_tx_update_dscp_tid_6390);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* hal_tx_desc_set_lmac_id - Set the lmac_id value
|
||||||
|
* @desc: Handle to Tx Descriptor
|
||||||
|
* @lmac_id: mac Id to ast matching
|
||||||
|
* b00 – mac 0
|
||||||
|
* b01 – mac 1
|
||||||
|
* b10 – mac 2
|
||||||
|
* b11 – all macs (legacy HK way)
|
||||||
|
*
|
||||||
|
* Return: void
|
||||||
|
*/
|
||||||
|
void hal_tx_desc_set_lmac_id_6390(void *desc,
|
||||||
|
uint8_t lmac_id)
|
||||||
|
{
|
||||||
|
HAL_SET_FLD(desc, TCL_DATA_CMD_4, LMAC_ID) |=
|
||||||
|
HAL_TX_SM(TCL_DATA_CMD_4, LMAC_ID, lmac_id);
|
||||||
|
}
|
||||||
|
qdf_export_symbol(hal_tx_desc_set_lmac_id_6390);
|
||||||
|
|
||||||
Reference in New Issue
Block a user