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Revert "Revert "asoc: lpass-cdc: Do not update VA clk muxsel register""

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This reverts commit a108d5c2bb.

Change-Id: Ie7d2bc6b05c62dff251cd80b2a4e81670e43108d
Signed-off-by: Vidyakumar Athota <vathota@codeaurora.org>
This commit is contained in:
Vidyakumar Athota
2021-06-02 19:16:27 -07:00
parent a108d5c2bb
commit 6a50edfffc
1 changed files with 38 additions and 18 deletions
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22
asoc/codecs/lpass-cdc/lpass-cdc-clk-rsc.c
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@@ -232,11 +232,13 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
if (enable) { if (enable) {
if (priv->clk_cnt[clk_id] == 0) { if (priv->clk_cnt[clk_id] == 0) {
if (clk_id != VA_CORE_CLK) {
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv, ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, default_clk_id,
true); true);
if (ret < 0) if (ret < 0)
goto done; goto done;
}
ret = clk_prepare_enable(priv->clk[clk_id]); ret = clk_prepare_enable(priv->clk[clk_id]);
if (ret < 0) { if (ret < 0) {
@@ -244,6 +246,13 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
__func__, clk_id); __func__, clk_id);
goto err_clk; goto err_clk;
} }
/*
* Temp SW workaround to address a glitch issue of
* VA GFMux instance responsible for switching from
* TX MCLK to VA MCLK. This configuration would be taken
* care in DSP itself
*/
if (clk_id != VA_CORE_CLK) {
if (priv->dev_up_gfmux) { if (priv->dev_up_gfmux) {
iowrite32(0x1, clk_muxsel); iowrite32(0x1, clk_muxsel);
muxsel = ioread32(clk_muxsel); muxsel = ioread32(clk_muxsel);
@@ -253,6 +262,7 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id,
false); false);
} }
}
priv->clk_cnt[clk_id]++; priv->clk_cnt[clk_id]++;
} else { } else {
if (priv->clk_cnt[clk_id] <= 0) { if (priv->clk_cnt[clk_id] <= 0) {
@@ -263,6 +273,14 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
} }
priv->clk_cnt[clk_id]--; priv->clk_cnt[clk_id]--;
if (priv->clk_cnt[clk_id] == 0) { if (priv->clk_cnt[clk_id] == 0) {
/*
* Temp SW workaround to address a glitch issue
* of VA GFMux instance responsible for
* switching from TX MCLK to VA MCLK.
* This configuration would be taken
* care in DSP itself.
*/
if (clk_id != VA_CORE_CLK) {
ret = lpass_cdc_clk_rsc_mux0_clk_request(priv, ret = lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, true); default_clk_id, true);
if (!ret && priv->dev_up_gfmux) { if (!ret && priv->dev_up_gfmux) {
@@ -271,8 +289,9 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
trace_printk("%s: muxsel value after disable: %d\n", trace_printk("%s: muxsel value after disable: %d\n",
__func__, muxsel); __func__, muxsel);
} }
}
clk_disable_unprepare(priv->clk[clk_id]); clk_disable_unprepare(priv->clk[clk_id]);
if (!ret) if (clk_id != VA_CORE_CLK && !ret)
lpass_cdc_clk_rsc_mux0_clk_request(priv, lpass_cdc_clk_rsc_mux0_clk_request(priv,
default_clk_id, false); default_clk_id, false);
} }
@@ -280,6 +299,7 @@ static int lpass_cdc_clk_rsc_mux1_clk_request(struct lpass_cdc_clk_rsc *priv,
return ret; return ret;
err_clk: err_clk:
if (clk_id != VA_CORE_CLK)
lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false); lpass_cdc_clk_rsc_mux0_clk_request(priv, default_clk_id, false);
done: done:
return ret; return ret;