video: driver: split control code

Split control code into msm_vidc_control.c and
msm_vidc_control_ext.c files.

Change-Id: I95f13d66f33fb75da4ebaa08e24bf31fe5de55b4
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>

Kbuild

@@ -62,6 +62,7 @@ msm_video-objs += driver/vidc/src/msm_vidc_v4l2.o \
                   driver/vidc/src/msm_venc.o \
                   driver/vidc/src/msm_vidc_driver.o \
                   driver/vidc/src/msm_vidc_control.o \
+                  driver/vidc/src/msm_vidc_control_ext.o \
                   driver/vidc/src/msm_vidc_buffer.o \
                   driver/vidc/src/msm_vidc_power.o \
                   driver/vidc/src/msm_vidc_probe.o \

driver/platform/anorak/src/msm_vidc_anorak.c

@@ -10,7 +10,7 @@
 #include "msm_vidc_platform.h"
 #include "msm_vidc_debug.h"
 #include "msm_vidc_internal.h"
-#include "msm_vidc_control.h"
+#include "msm_vidc_control_ext.h"
 #include "hfi_property.h"
 #include "msm_vidc_iris3.h"
 #include "hfi_command.h"

driver/platform/kalama/src/msm_vidc_kalama.c

@@ -10,7 +10,7 @@
 #include "msm_vidc_platform.h"
 #include "msm_vidc_debug.h"
 #include "msm_vidc_internal.h"
-#include "msm_vidc_control.h"
+#include "msm_vidc_control_ext.h"
 #include "hfi_property.h"
 #include "msm_vidc_iris3.h"
 #include "hfi_command.h"

driver/platform/waipio/src/msm_vidc_waipio.c

@@ -10,7 +10,7 @@
 #include "msm_vidc_platform.h"
 #include "msm_vidc_debug.h"
 #include "msm_vidc_internal.h"
-#include "msm_vidc_control.h"
+#include "msm_vidc_control_ext.h"
 #include "hfi_property.h"
 #include "hfi_command.h"
 

driver/vidc/inc/msm_vidc_control.h

@@ -23,7 +23,6 @@ int msm_vidc_adjust_profile(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_ltr_count(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_use_ltr(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_mark_ltr(void *instance, struct v4l2_ctrl *ctrl);
-int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_delta_based_rc(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_output_order(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_input_buf_host_max_count(void *instance, struct v4l2_ctrl *ctrl);
@@ -53,11 +52,8 @@ int msm_vidc_prepare_dependency_list(struct msm_vidc_inst *inst);
 int msm_vidc_adjust_session_priority(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_roi_info(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_all_intra(void *instance, struct v4l2_ctrl *ctrl);
-int msm_vidc_adjust_dec_frame_rate(void *instance, struct v4l2_ctrl *ctrl);
-int msm_vidc_adjust_dec_operating_rate(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_dec_outbuf_fence(void *instance, struct v4l2_ctrl *ctrl);
 int msm_vidc_adjust_preprocess(void *instance, struct v4l2_ctrl *ctrl);
-int msm_vidc_adjust_delivery_mode(void *instance, struct v4l2_ctrl *ctrl);
 
 int msm_vidc_set_header_mode(void *instance,
 	enum msm_vidc_inst_capability_type cap_id);
@@ -113,8 +109,6 @@ int msm_vidc_set_pipe(void *instance,
 	enum msm_vidc_inst_capability_type cap_id);
 int msm_vidc_set_csc_custom_matrix(void *instance,
 	enum msm_vidc_inst_capability_type cap_id);
-int msm_vidc_set_ir_period(void *instance,
-	enum msm_vidc_inst_capability_type cap_id);
 int msm_vidc_set_level(void *instance,
 	enum msm_vidc_inst_capability_type cap_id);
 int msm_vidc_set_preprocess(void *instance,
@@ -127,6 +121,14 @@ int msm_vidc_set_q16(void *instance,
 	enum msm_vidc_inst_capability_type cap_id);
 int msm_vidc_v4l2_menu_to_hfi(struct msm_vidc_inst *inst,
 	enum msm_vidc_inst_capability_type cap_id, u32 *value);
+int msm_vidc_packetize_control(struct msm_vidc_inst *inst,
+	enum msm_vidc_inst_capability_type cap_id, u32 payload_type,
+	void *hfi_val, u32 payload_size, const char *func);
+bool is_parent_available(struct msm_vidc_inst *inst,
+	u32 cap_id, u32 check_parent, const char *func);
+bool is_valid_cap_id(enum msm_vidc_inst_capability_type cap_id);
+enum msm_vidc_inst_capability_type msm_vidc_get_cap_id(
+	struct msm_vidc_inst *inst, u32 id);
 int msm_vidc_v4l2_to_hfi_enum(struct msm_vidc_inst *inst,
 	enum msm_vidc_inst_capability_type cap_id, u32 *value);
 int msm_vidc_update_cap_value(struct msm_vidc_inst *inst, u32 cap,

driver/vidc/inc/msm_vidc_control_ext.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _MSM_VIDC_CONTROL_EXT_H_
+#define _MSM_VIDC_CONTROL_EXT_H_
+
+#include "msm_vidc_control.h"
+
+int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl);
+int msm_vidc_adjust_dec_frame_rate(void *instance, struct v4l2_ctrl *ctrl);
+int msm_vidc_adjust_dec_operating_rate(void *instance, struct v4l2_ctrl *ctrl);
+int msm_vidc_adjust_delivery_mode(void *instance, struct v4l2_ctrl *ctrl);
+
+int msm_vidc_set_ir_period(void *instance,
+	enum msm_vidc_inst_capability_type cap_id);
+
+#endif

driver/vidc/src/msm_vidc_control.c

@@ -227,7 +227,7 @@ static inline bool is_root(struct msm_vidc_inst_cap *cap)
 	return !has_parents(cap);
 }
 
-static inline bool is_valid_cap_id(enum msm_vidc_inst_capability_type cap_id)
+bool is_valid_cap_id(enum msm_vidc_inst_capability_type cap_id)
 {
 	return cap_id > INST_CAP_NONE && cap_id < INST_CAP_MAX;
 }
@@ -326,7 +326,7 @@ static int swap_node(struct msm_vidc_inst_cap *rcap,
 	return 0;
 }
 
-static int msm_vidc_packetize_control(struct msm_vidc_inst *inst,
+int msm_vidc_packetize_control(struct msm_vidc_inst *inst,
 	enum msm_vidc_inst_capability_type cap_id, u32 payload_type,
 	void *hfi_val, u32 payload_size, const char *func)
 {
@@ -365,7 +365,7 @@ static int msm_vidc_packetize_control(struct msm_vidc_inst *inst,
 	return 0;
 }
 
-static enum msm_vidc_inst_capability_type msm_vidc_get_cap_id(
+enum msm_vidc_inst_capability_type msm_vidc_get_cap_id(
 	struct msm_vidc_inst *inst, u32 id)
 {
 	enum msm_vidc_inst_capability_type i = INST_CAP_NONE + 1;
@@ -430,7 +430,7 @@ static int msm_vidc_add_children(struct msm_vidc_inst *inst,
 	return rc;
 }
 
-static bool is_parent_available(struct msm_vidc_inst *inst,
+bool is_parent_available(struct msm_vidc_inst *inst,
 	u32 cap_id, u32 check_parent, const char *func)
 {
 	int i = 0;
@@ -1483,72 +1483,6 @@ int msm_vidc_adjust_mark_ltr(void *instance, struct v4l2_ctrl *ctrl)
 	return 0;
 }
 
-int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl)
-{
-	struct msm_vidc_inst_capability *capability;
-	s32 adjusted_value, all_intra = 0, roi_enable = 0,
-		pix_fmts = MSM_VIDC_FMT_NONE;
-	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
-
-	if (!inst || !inst->capabilities) {
-		d_vpr_e("%s: invalid params\n", __func__);
-		return -EINVAL;
-	}
-	capability = inst->capabilities;
-
-	adjusted_value = ctrl ? ctrl->val : capability->cap[IR_PERIOD].value;
-
-	if (msm_vidc_get_parent_value(inst, IR_PERIOD, ALL_INTRA,
-		&all_intra, __func__) ||
-		msm_vidc_get_parent_value(inst, IR_PERIOD, META_ROI_INFO,
-		&roi_enable, __func__))
-		return -EINVAL;
-
-	if (all_intra) {
-		adjusted_value = 0;
-		i_vpr_h(inst, "%s: intra refresh unsupported, all intra: %d\n",
-			__func__, all_intra);
-		goto exit;
-	}
-
-	if (roi_enable) {
-		i_vpr_h(inst,
-			"%s: intra refresh unsupported with roi metadata\n",
-			__func__);
-		adjusted_value = 0;
-		goto exit;
-	}
-
-	if (inst->codec == MSM_VIDC_HEVC) {
-		if (msm_vidc_get_parent_value(inst, IR_PERIOD,
-			PIX_FMTS, &pix_fmts, __func__))
-			return -EINVAL;
-
-		if (is_10bit_colorformat(pix_fmts)) {
-			i_vpr_h(inst,
-				"%s: intra refresh is supported only for 8 bit\n",
-				__func__);
-			adjusted_value = 0;
-			goto exit;
-		}
-	}
-
-	/*
-	 * BITRATE_MODE dependency is NOT common across all chipsets.
-	 * Hence, do not return error if not specified as one of the parent.
-	 */
-	if (is_parent_available(inst, IR_PERIOD, BITRATE_MODE, __func__) &&
-		inst->hfi_rc_type != HFI_RC_CBR_CFR &&
-		inst->hfi_rc_type != HFI_RC_CBR_VFR)
-		adjusted_value = 0;
-
-exit:
-	msm_vidc_update_cap_value(inst, IR_PERIOD,
-		adjusted_value, __func__);
-
-	return 0;
-}
-
 int msm_vidc_adjust_delta_based_rc(void *instance, struct v4l2_ctrl *ctrl)
 {
 	struct msm_vidc_inst_capability *capability;
@@ -2943,52 +2877,6 @@ int msm_vidc_adjust_roi_info(void *instance, struct v4l2_ctrl *ctrl)
 	return 0;
 }
 
-int msm_vidc_adjust_dec_frame_rate(void *instance, struct v4l2_ctrl *ctrl)
-{
-	struct msm_vidc_inst_capability *capability;
-	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
-	u32 adjusted_value = 0;
-
-	if (!inst || !inst->capabilities) {
-		d_vpr_e("%s: invalid params\n", __func__);
-		return -EINVAL;
-	}
-
-	if (is_encode_session(inst)) {
-		d_vpr_e("%s: adjust framerate invalid for enc\n", __func__);
-		return -EINVAL;
-	}
-
-	capability = inst->capabilities;
-	adjusted_value = ctrl ? ctrl->val : capability->cap[FRAME_RATE].value;
-	msm_vidc_update_cap_value(inst, FRAME_RATE, adjusted_value, __func__);
-
-	return 0;
-}
-
-int msm_vidc_adjust_dec_operating_rate(void *instance, struct v4l2_ctrl *ctrl)
-{
-	struct msm_vidc_inst_capability *capability;
-	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
-	u32 adjusted_value = 0;
-
-	if (!inst || !inst->capabilities) {
-		d_vpr_e("%s: invalid params\n", __func__);
-		return -EINVAL;
-	}
-
-	if (is_encode_session(inst)) {
-		d_vpr_e("%s: adjust operating rate invalid for enc\n", __func__);
-		return -EINVAL;
-	}
-
-	capability = inst->capabilities;
-	adjusted_value = ctrl ? ctrl->val : capability->cap[OPERATING_RATE].value;
-	msm_vidc_update_cap_value(inst, OPERATING_RATE, adjusted_value, __func__);
-
-	return 0;
-}
-
 int msm_vidc_adjust_dec_outbuf_fence(void *instance, struct v4l2_ctrl *ctrl)
 {
 	struct msm_vidc_inst_capability *capability;
@@ -3020,43 +2908,6 @@ int msm_vidc_adjust_dec_outbuf_fence(void *instance, struct v4l2_ctrl *ctrl)
 	return 0;
 }
 
-int msm_vidc_adjust_delivery_mode(void *instance, struct v4l2_ctrl *ctrl)
-{
-	struct msm_vidc_inst_capability *capability;
-	s32 adjusted_value;
-	s32 slice_mode = -1;
-	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
-
-	if (!inst || !inst->capabilities) {
-		d_vpr_e("%s: invalid params\n", __func__);
-		return -EINVAL;
-	}
-
-	if (is_decode_session(inst))
-		return 0;
-
-	capability = inst->capabilities;
-
-	adjusted_value = ctrl ? ctrl->val : capability->cap[DELIVERY_MODE].value;
-
-	if (msm_vidc_get_parent_value(inst, DELIVERY_MODE, SLICE_MODE,
-		&slice_mode, __func__))
-		return -EINVAL;
-
-	/* Slice encode delivery mode is only supported for Max MB slice mode */
-	if (slice_mode != V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
-		if (inst->codec == MSM_VIDC_HEVC)
-			adjusted_value = V4L2_MPEG_VIDC_HEVC_ENCODE_DELIVERY_MODE_FRAME_BASED;
-		else if (inst->codec == MSM_VIDC_H264)
-			adjusted_value = V4L2_MPEG_VIDC_H264_ENCODE_DELIVERY_MODE_FRAME_BASED;
-	}
-
-	msm_vidc_update_cap_value(inst, DELIVERY_MODE,
-		adjusted_value, __func__);
-
-	return 0;
-}
-
 int msm_vidc_prepare_dependency_list(struct msm_vidc_inst *inst)
 {
 	struct list_head root_list, opt_list;
@@ -4311,48 +4162,6 @@ int msm_vidc_set_level(void *instance,
 	return rc;
 }
 
-int msm_vidc_set_ir_period(void *instance,
-	enum msm_vidc_inst_capability_type cap_id)
-{
-	int rc = 0;
-	struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance;
-	u32 ir_type = 0;
-	struct msm_vidc_core *core;
-
-	if (!inst || !inst->capabilities) {
-		d_vpr_e("%s: invalid params\n", __func__);
-		return -EINVAL;
-	}
-
-	core = inst->core;
-
-	if (inst->capabilities->cap[IR_TYPE].value ==
-	    V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) {
-		if (inst->bufq[OUTPUT_PORT].vb2q->streaming) {
-			i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n",
-				__func__);
-			return 0;
-		}
-		ir_type = HFI_PROP_IR_RANDOM_PERIOD;
-	} else if (inst->capabilities->cap[IR_TYPE].value ==
-		   V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC) {
-		ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
-	} else {
-		i_vpr_e(inst, "%s: invalid ir_type %d\n",
-			__func__, inst->capabilities->cap[IR_TYPE]);
-		return -EINVAL;
-	}
-
-	rc = venus_hfi_set_ir_period(inst, ir_type, cap_id);
-	if (rc) {
-		i_vpr_e(inst, "%s: failed to set ir period %d\n",
-			__func__, inst->capabilities->cap[IR_PERIOD].value);
-		return rc;
-	}
-
-	return rc;
-}
-
 int msm_vidc_set_q16(void *instance,
 	enum msm_vidc_inst_capability_type cap_id)
 {

driver/vidc/src/msm_vidc_control_ext.c

@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "msm_vidc_control_ext.h"
+#include "msm_vidc_debug.h"
+#include "hfi_packet.h"
+#include "hfi_property.h"
+#include "venus_hfi.h"
+#include "msm_vidc_internal.h"
+#include "msm_vidc_driver.h"
+#include "msm_venc.h"
+#include "msm_vidc_platform.h"
+
+int msm_vidc_adjust_ir_period(void *instance, struct v4l2_ctrl *ctrl)
+{
+	struct msm_vidc_inst_capability *capability;
+	s32 adjusted_value, all_intra = 0, roi_enable = 0,
+		pix_fmts = MSM_VIDC_FMT_NONE;
+	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
+
+	if (!inst || !inst->capabilities) {
+		d_vpr_e("%s: invalid params\n", __func__);
+		return -EINVAL;
+	}
+	capability = inst->capabilities;
+
+	adjusted_value = ctrl ? ctrl->val : capability->cap[IR_PERIOD].value;
+
+	if (msm_vidc_get_parent_value(inst, IR_PERIOD, ALL_INTRA,
+		&all_intra, __func__) ||
+		msm_vidc_get_parent_value(inst, IR_PERIOD, META_ROI_INFO,
+		&roi_enable, __func__))
+		return -EINVAL;
+
+	if (all_intra) {
+		adjusted_value = 0;
+		i_vpr_h(inst, "%s: intra refresh unsupported, all intra: %d\n",
+			__func__, all_intra);
+		goto exit;
+	}
+
+	if (roi_enable) {
+		i_vpr_h(inst,
+			"%s: intra refresh unsupported with roi metadata\n",
+			__func__);
+		adjusted_value = 0;
+		goto exit;
+	}
+
+	if (inst->codec == MSM_VIDC_HEVC) {
+		if (msm_vidc_get_parent_value(inst, IR_PERIOD,
+			PIX_FMTS, &pix_fmts, __func__))
+			return -EINVAL;
+
+		if (is_10bit_colorformat(pix_fmts)) {
+			i_vpr_h(inst,
+				"%s: intra refresh is supported only for 8 bit\n",
+				__func__);
+			adjusted_value = 0;
+			goto exit;
+		}
+	}
+
+	/*
+	 * BITRATE_MODE dependency is NOT common across all chipsets.
+	 * Hence, do not return error if not specified as one of the parent.
+	 */
+	if (is_parent_available(inst, IR_PERIOD, BITRATE_MODE, __func__) &&
+		inst->hfi_rc_type != HFI_RC_CBR_CFR &&
+		inst->hfi_rc_type != HFI_RC_CBR_VFR)
+		adjusted_value = 0;
+
+exit:
+	msm_vidc_update_cap_value(inst, IR_PERIOD,
+		adjusted_value, __func__);
+
+	return 0;
+}
+
+int msm_vidc_adjust_dec_frame_rate(void *instance, struct v4l2_ctrl *ctrl)
+{
+	struct msm_vidc_inst_capability *capability;
+	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
+	u32 adjusted_value = 0;
+
+	if (!inst || !inst->capabilities) {
+		d_vpr_e("%s: invalid params\n", __func__);
+		return -EINVAL;
+	}
+
+	if (is_encode_session(inst)) {
+		d_vpr_e("%s: adjust framerate invalid for enc\n", __func__);
+		return -EINVAL;
+	}
+
+	capability = inst->capabilities;
+	adjusted_value = ctrl ? ctrl->val : capability->cap[FRAME_RATE].value;
+	msm_vidc_update_cap_value(inst, FRAME_RATE, adjusted_value, __func__);
+
+	return 0;
+}
+
+int msm_vidc_adjust_dec_operating_rate(void *instance, struct v4l2_ctrl *ctrl)
+{
+	struct msm_vidc_inst_capability *capability;
+	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
+	u32 adjusted_value = 0;
+
+	if (!inst || !inst->capabilities) {
+		d_vpr_e("%s: invalid params\n", __func__);
+		return -EINVAL;
+	}
+
+	if (is_encode_session(inst)) {
+		d_vpr_e("%s: adjust operating rate invalid for enc\n", __func__);
+		return -EINVAL;
+	}
+
+	capability = inst->capabilities;
+	adjusted_value = ctrl ? ctrl->val : capability->cap[OPERATING_RATE].value;
+	msm_vidc_update_cap_value(inst, OPERATING_RATE, adjusted_value, __func__);
+
+	return 0;
+}
+
+int msm_vidc_adjust_delivery_mode(void *instance, struct v4l2_ctrl *ctrl)
+{
+	struct msm_vidc_inst_capability *capability;
+	s32 adjusted_value;
+	s32 slice_mode = -1;
+	struct msm_vidc_inst *inst = (struct msm_vidc_inst *) instance;
+
+	if (!inst || !inst->capabilities) {
+		d_vpr_e("%s: invalid params\n", __func__);
+		return -EINVAL;
+	}
+
+	if (is_decode_session(inst))
+		return 0;
+
+	capability = inst->capabilities;
+
+	adjusted_value = ctrl ? ctrl->val : capability->cap[DELIVERY_MODE].value;
+
+	if (msm_vidc_get_parent_value(inst, DELIVERY_MODE, SLICE_MODE,
+		&slice_mode, __func__))
+		return -EINVAL;
+
+	/* Slice encode delivery mode is only supported for Max MB slice mode */
+	if (slice_mode != V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB) {
+		if (inst->codec == MSM_VIDC_HEVC)
+			adjusted_value = V4L2_MPEG_VIDC_HEVC_ENCODE_DELIVERY_MODE_FRAME_BASED;
+		else if (inst->codec == MSM_VIDC_H264)
+			adjusted_value = V4L2_MPEG_VIDC_H264_ENCODE_DELIVERY_MODE_FRAME_BASED;
+	}
+
+	msm_vidc_update_cap_value(inst, DELIVERY_MODE,
+		adjusted_value, __func__);
+
+	return 0;
+}
+
+int msm_vidc_set_ir_period(void *instance,
+	enum msm_vidc_inst_capability_type cap_id)
+{
+	int rc = 0;
+	struct msm_vidc_inst *inst = (struct msm_vidc_inst *)instance;
+	u32 ir_type = 0;
+	struct msm_vidc_core *core;
+
+	if (!inst || !inst->capabilities) {
+		d_vpr_e("%s: invalid params\n", __func__);
+		return -EINVAL;
+	}
+
+	core = inst->core;
+
+	if (inst->capabilities->cap[IR_TYPE].value ==
+	    V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) {
+		if (inst->bufq[OUTPUT_PORT].vb2q->streaming) {
+			i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n",
+				__func__);
+			return 0;
+		}
+		ir_type = HFI_PROP_IR_RANDOM_PERIOD;
+	} else if (inst->capabilities->cap[IR_TYPE].value ==
+		   V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC) {
+		ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
+	} else {
+		i_vpr_e(inst, "%s: invalid ir_type %d\n",
+			__func__, inst->capabilities->cap[IR_TYPE]);
+		return -EINVAL;
+	}
+
+	rc = venus_hfi_set_ir_period(inst, ir_type, cap_id);
+	if (rc) {
+		i_vpr_e(inst, "%s: failed to set ir period %d\n",
+			__func__, inst->capabilities->cap[IR_PERIOD].value);
+		return rc;
+	}
+
+	return rc;
+}
+