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cnss2: Dump PBL logging registers on RDDM timeout

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Dump PBL and SBL logging registers to debug RDDM failure.

Change-Id: I9225e95c529a928e6e6f9e4528dadbe7237440b3
This commit is contained in:
Naman Padhiar
2022-11-09 20:18:35 +05:30
committed by Madan Koyyalamudi
parent 8d75ecdd2d
commit 69cf56c2cf
1 changed files with 16 additions and 0 deletions
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16
cnss2/pci.c
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@@ -1710,6 +1710,9 @@ static int cnss_rddm_trigger_debug(struct cnss_pci_data *pci_priv)
if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID) if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID)
return -EOPNOTSUPP; return -EOPNOTSUPP;
if (cnss_pci_check_link_status(pci_priv))
return -EINVAL;
cnss_pr_err("Write GCC Spare with ACE55 Pattern"); cnss_pr_err("Write GCC Spare with ACE55 Pattern");
cnss_pci_reg_write(pci_priv, GCC_GCC_SPARE_REG_1, 0xACE55); cnss_pci_reg_write(pci_priv, GCC_GCC_SPARE_REG_1, 0xACE55);
ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val); ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val);
@@ -1723,13 +1726,26 @@ static int cnss_rddm_trigger_debug(struct cnss_pci_data *pci_priv)
static int cnss_rddm_trigger_check(struct cnss_pci_data *pci_priv) static int cnss_rddm_trigger_check(struct cnss_pci_data *pci_priv)
{ {
int read_val, ret; int read_val, ret;
u32 pbl_stage, sbl_log_start, sbl_log_size, pbl_wlan_boot_cfg;
if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID) if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID)
return -EOPNOTSUPP; return -EOPNOTSUPP;
if (cnss_pci_check_link_status(pci_priv))
return -EINVAL;
ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val); ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val);
cnss_pr_err("Read GCC spare to check reset status: 0x%x, ret: %d", cnss_pr_err("Read GCC spare to check reset status: 0x%x, ret: %d",
read_val, ret); read_val, ret);
cnss_pci_reg_read(pci_priv, TCSR_PBL_LOGGING_REG, &pbl_stage);
cnss_pci_reg_read(pci_priv, PCIE_BHI_ERRDBG2_REG, &sbl_log_start);
cnss_pci_reg_read(pci_priv, PCIE_BHI_ERRDBG3_REG, &sbl_log_size);
cnss_pci_reg_read(pci_priv, PBL_WLAN_BOOT_CFG, &pbl_wlan_boot_cfg);
cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: Start: 0x%08x Size:0x%08x \n",
pbl_stage, sbl_log_start, sbl_log_size);
cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x\n", pbl_wlan_boot_cfg);
return ret; return ret;
} }