From 69cf56c2cfe8f23c95319dd989084e25cdf80da5 Mon Sep 17 00:00:00 2001 From: Naman Padhiar Date: Wed, 9 Nov 2022 20:18:35 +0530 Subject: [PATCH] cnss2: Dump PBL logging registers on RDDM timeout Dump PBL and SBL logging registers to debug RDDM failure. Change-Id: I9225e95c529a928e6e6f9e4528dadbe7237440b3 --- cnss2/pci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/cnss2/pci.c b/cnss2/pci.c index ee8b3951d8..f5b7d4f851 100644 --- a/cnss2/pci.c +++ b/cnss2/pci.c @@ -1710,6 +1710,9 @@ static int cnss_rddm_trigger_debug(struct cnss_pci_data *pci_priv) if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID) return -EOPNOTSUPP; + if (cnss_pci_check_link_status(pci_priv)) + return -EINVAL; + cnss_pr_err("Write GCC Spare with ACE55 Pattern"); cnss_pci_reg_write(pci_priv, GCC_GCC_SPARE_REG_1, 0xACE55); ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val); @@ -1723,13 +1726,26 @@ static int cnss_rddm_trigger_debug(struct cnss_pci_data *pci_priv) static int cnss_rddm_trigger_check(struct cnss_pci_data *pci_priv) { int read_val, ret; + u32 pbl_stage, sbl_log_start, sbl_log_size, pbl_wlan_boot_cfg; if (!pci_priv || pci_priv->device_id != QCA6490_DEVICE_ID) return -EOPNOTSUPP; + if (cnss_pci_check_link_status(pci_priv)) + return -EINVAL; + ret = cnss_pci_reg_read(pci_priv, GCC_GCC_SPARE_REG_1, &read_val); cnss_pr_err("Read GCC spare to check reset status: 0x%x, ret: %d", read_val, ret); + + cnss_pci_reg_read(pci_priv, TCSR_PBL_LOGGING_REG, &pbl_stage); + cnss_pci_reg_read(pci_priv, PCIE_BHI_ERRDBG2_REG, &sbl_log_start); + cnss_pci_reg_read(pci_priv, PCIE_BHI_ERRDBG3_REG, &sbl_log_size); + cnss_pci_reg_read(pci_priv, PBL_WLAN_BOOT_CFG, &pbl_wlan_boot_cfg); + cnss_pr_dbg("TCSR_PBL_LOGGING: 0x%08x PCIE_BHI_ERRDBG: Start: 0x%08x Size:0x%08x \n", + pbl_stage, sbl_log_start, sbl_log_size); + cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x\n", pbl_wlan_boot_cfg); + return ret; }