[wifi 3.0] add firmware common files

add firmware common files into separated project.
Included firmware common htt and wmi.
Included hardware common header files for napier and hawkeye

Change-Id: I8724057eb9aa21f7614231d1943177e780ed16b1
CRs-fixed: 1074308

fw/a_osapi.h

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+/* ============================================================================== */
+/* This file contains the definitions of the basic atheros data types. */
+/* It is used to map the data types in atheros files to a platform specific */
+/* type. */
+/* */
+/* Author(s): ="Atheros" */
+/* ============================================================================== */
+#ifndef _A_OSAPI_H_
+#define _A_OSAPI_H_
+
+#if defined(__linux__) && !defined(LINUX_EMULATION)
+#include "osapi_linux.h"
+#endif
+
+/*=== the following primitives have the same definition for all platforms ===*/
+
+#define A_COMPILE_TIME_ASSERT(assertion_name, predicate) \
+	typedef char assertion_name[(predicate) ? 1 : -1]
+
+/*
+ * If N is a power of 2, then N and N-1 are orthogonal
+ * (N-1 has all the least-significant bits set which are zero in N)
+ * so  N ^ (N-1) = (N << 1) - 1
+ */
+#define A_COMPILE_TIME_ASSERT_IS_PWR2(assertion_name, value) \
+	A_COMPILE_TIME_ASSERT (assertion_name,			  \
+			       (((value) ^ ((value)-1)) == ((value) << 1) - 1))
+
+#ifndef __ubicom32__
+#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
+	os_malloc_CONSISTENT(osdev, size, pa, context, retry)
+#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
+	OS_FREE_CONSISTENT(osdev, size, vaddr, pa, context)
+#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context)
+#else
+#define HIF_MALLOC_DIAGMEM(osdev, size, pa, context, retry) \
+	os_malloc_NONCONSISTENT(osdev, size, pa, context, retry)
+#define HIF_FREE_DIAGMEM(osdev, size, vaddr, pa, context) \
+	OS_FREE_NONCONSISTENT(osdev, size, vaddr, pa, context)
+#define HIF_DIAGMEM_SYNC(osdev, pa, size, dir, context)	\
+	OS_SYNC_SINGLE(osdev, pa, size, dir, context)
+#endif /* ubicom32 */
+
+#endif /* _OSAPI_H_ */

fw/a_usb_defs.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+/*
+ *  Shared USB definitions
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __A_USB_DEFS_H__
+#define __A_USB_DEFS_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* USB endpoint definitions */
+
+#define USB_EP_ADDR_APP_CTRL_IN          0x81
+#define USB_EP_ADDR_APP_DATA_IN          0x82
+#define USB_EP_ADDR_APP_DATA2_IN         0x83
+#define USB_EP_ADDR_APP_INT_IN           0x84
+
+#define USB_EP_ADDR_APP_CTRL_OUT         0x01
+#define USB_EP_ADDR_APP_DATA_LP_OUT      0x02
+#define USB_EP_ADDR_APP_DATA_MP_OUT      0x03
+#define USB_EP_ADDR_APP_DATA_HP_OUT      0x04
+
+#define USB_CONTROL_REQ_SEND_BMI_CMD        1
+#define USB_CONTROL_REQ_RECV_BMI_RESP       2
+#define USB_CONTROL_REQ_DIAG_CMD            3
+#define USB_CONTROL_REQ_DIAG_RESP           4
+
+/* #define USB_CONTROL_MAX_BMI_TRANSFER_SIZE   64 */
+#define USB_CONTROL_MAX_BMI_TRANSFER_SIZE   252
+
+#define HIF_BMI_MAX_TRANSFER_SIZE           USB_CONTROL_MAX_BMI_TRANSFER_SIZE
+
+/* 512 Bytes Maxp for High Speed for BULK EP */
+#define USB_HS_BULK_MAXP_SIZE   0x200
+/* 64 Bytes Maxp for Full Speed for BULK EP */
+#define USB_FS_BULK_MAXP_SIZE   0x40
+
+/* diagnostic command defnitions */
+#define USB_CTRL_DIAG_CC_READ       0
+#define USB_CTRL_DIAG_CC_WRITE      1
+#define USB_CTRL_DIAG_CC_WARM_RESET 2
+
+typedef PREPACK struct {
+	A_UINT32 Cmd;
+	A_UINT32 Address;
+	A_UINT32 Value;
+	A_UINT32 _pad[1];
+} POSTPACK USB_CTRL_DIAG_CMD_WRITE;
+
+typedef PREPACK struct {
+	A_UINT32 Cmd;
+	A_UINT32 Address;
+} POSTPACK USB_CTRL_DIAG_CMD_READ;
+
+typedef PREPACK struct {
+	A_UINT32 ReadValue;
+} POSTPACK USB_CTRL_DIAG_RESP_READ;
+
+#define USB_CTRL_MAX_DIAG_CMD_SIZE  (sizeof(USB_CTRL_DIAG_CMD_WRITE))
+#define USB_CTRL_MAX_DIAG_RESP_SIZE (sizeof(USB_CTRL_DIAG_RESP_READ))
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif

fw/apb_athr_wlan_map.h

@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _APB_ATHR_WLAN_MAP_H_
+#define _APB_ATHR_WLAN_MAP_H_
+
+#define RTC_SOC_BASE_ADDRESS                     0x00004000
+#define RTC_WMAC_BASE_ADDRESS                    0x00005000
+#define MAC_COEX_BASE_ADDRESS                    0x00006000
+#define BT_COEX_BASE_ADDRESS                     0x00007000
+#define SOC_PCIE_BASE_ADDRESS                    0x00008000
+#define SOC_CORE_BASE_ADDRESS                    0x00009000
+#define WLAN_UART_BASE_ADDRESS                   0x0000c000
+#define WLAN_SI_BASE_ADDRESS                     0x00010000
+#define WLAN_GPIO_BASE_ADDRESS                   0x00014000
+#define WLAN_ANALOG_INTF_BASE_ADDRESS            0x0001c000
+#define WLAN_MAC_BASE_ADDRESS                    0x00020000
+#define EFUSE_BASE_ADDRESS                       0x00030000
+#define FPGA_REG_BASE_ADDRESS                    0x00039000
+#define WLAN_UART2_BASE_ADDRESS                  0x00054c00
+#define CE_WRAPPER_BASE_ADDRESS                  0x00057000
+#define CE0_BASE_ADDRESS                         0x00057400
+#define CE1_BASE_ADDRESS                         0x00057800
+#define CE2_BASE_ADDRESS                         0x00057c00
+#define CE3_BASE_ADDRESS                         0x00058000
+#define CE4_BASE_ADDRESS                         0x00058400
+#define CE5_BASE_ADDRESS                         0x00058800
+#define CE6_BASE_ADDRESS                         0x00058c00
+#define CE7_BASE_ADDRESS                         0x00059000
+#define DBI_BASE_ADDRESS                         0x00060000
+#define WLAN_MBOX_BASE_ADDRESS                   0x00068000
+#define WLAN_DBG_UART_BASE_ADDRESS               0x00069000
+#define USB_DMA_BASE_ADDRESS                     0x0006a000
+
+#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */

fw/athdefs.h

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef __ATHDEFS_H__
+#define __ATHDEFS_H__
+
+/*
+ * This file contains definitions that may be used across both
+ * Host and Target software.  Nothing here is module-dependent
+ * or platform-dependent.
+ */
+
+/*
+ * Generic error codes that can be used by hw, sta, ap, sim, dk
+ * and any other environments. Since these are enums, feel free to
+ * add any more codes that you need.
+ */
+
+typedef enum {
+	A_ERROR = -1,           /* Generic error return */
+	A_OK = 0,               /* success */
+	/* Following values start at 1 */
+	A_DEVICE_NOT_FOUND,     /* not able to find PCI device */
+	A_NO_MEMORY,            /* not able to allocate memory, not available */
+	A_MEMORY_NOT_AVAIL,     /* memory region is not free for mapping */
+	A_NO_FREE_DESC,         /* no free descriptors available */
+	A_BAD_ADDRESS,          /* address does not match descriptor */
+	A_WIN_DRIVER_ERROR,     /* used in NT_HW version, if problem at init */
+	A_REGS_NOT_MAPPED,      /* registers not correctly mapped */
+	A_EPERM,                /* Not superuser */
+	A_EACCES,               /* Access denied */
+	A_ENOENT,               /* No such entry, search failed, etc. */
+	A_EEXIST,               /* The object already exists (can't create) */
+	A_EFAULT,               /* Bad address fault */
+	A_EBUSY,                /* Object is busy */
+	A_EINVAL,               /* Invalid parameter */
+	A_EMSGSIZE,             /* Inappropriate message buffer length */
+	A_ECANCELED,            /* Operation canceled */
+	A_ENOTSUP,              /* Operation not supported */
+	A_ECOMM,                /* Communication error on send */
+	A_EPROTO,               /* Protocol error */
+	A_ENODEV,               /* No such device */
+	A_EDEVNOTUP,            /* device is not UP */
+	A_NO_RESOURCE,          /* No resources for requested operation */
+	A_HARDWARE,             /* Hardware failure */
+	A_PENDING,              /* Asynchronous routine; will send up results la
+	                           ter (typically in callback) */
+	A_EBADCHANNEL,          /* The channel cannot be used */
+	A_DECRYPT_ERROR,        /* Decryption error */
+	A_PHY_ERROR,            /* RX PHY error */
+	A_CONSUMED,             /* Object was consumed */
+	A_CLONE,                /* The buffer is cloned */
+	A_USB_ERROR,            /* Rome USB Target error */
+} A_STATUS;
+
+#define A_SUCCESS(x)        (x == A_OK)
+#define A_FAILED(x)         (!A_SUCCESS(x))
+
+#endif /* __ATHDEFS_H__ */

fw/athendpack.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifdef VXWORKS
+#endif /* VXWORKS */
+
+#if defined(LINUX) || defined(__linux__)
+#endif /* LINUX */
+
+#ifdef QNX
+#endif /* QNX */

fw/bin_sig.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2012,2014, 2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef BIN_SIGN_H_
+#define BIN_SIGN_H_
+
+
+/* Signed binary MetaData */
+typedef struct {
+	unsigned int magic_num;
+	unsigned int total_len;
+	unsigned int rampatch_len;
+	unsigned int product_id;
+	unsigned int patch_ver;
+	unsigned short sign_format_ver;
+	unsigned short sign_algorithm;
+	unsigned char reserved[8];
+} SIGN_HEADER_T;
+
+#endif /*  BIN_SIGN_H_ */

fw/bmi_msg.h

@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef __BMI_MSG_H__
+#define __BMI_MSG_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/*
+ * Bootloader Messaging Interface (BMI)
+ *
+ * BMI is a very simple messaging interface used during initialization
+ * to read memory, write memory, execute code, and to define an
+ * application entry PC.
+ *
+ * It is used to download an application to AR6K, to provide
+ * patches to code that is already resident on AR6K, and generally
+ * to examine and modify state.  The Host has an opportunity to use
+ * BMI only once during bootup.  Once the Host issues a BMI_DONE
+ * command, this opportunity ends.
+ *
+ * The Host writes BMI requests to mailbox0, and reads BMI responses
+ * from mailbox0.   BMI requests all begin with a command
+ * (see below for specific commands), and are followed by
+ * command-specific data.
+ *
+ * Flow control:
+ * The Host can only issue a command once the Target gives it a
+ * "BMI Command Credit", using AR6K Counter #4.  As soon as the
+ * Target has completed a command, it issues another BMI Command
+ * Credit (so the Host can issue the next command).
+ *
+ * BMI handles all required Target-side cache flushing.
+ */
+
+/* Maximum data size used for BMI transfers */
+#define BMI_DATASZ_MAX                      256
+
+/* BMI Commands */
+
+#define BMI_NO_COMMAND                      0
+
+#define BMI_DONE                            1
+/*
+ * Semantics: Host is done using BMI
+ * Request format:
+ *    A_UINT32      command (BMI_DONE)
+ * Response format: none
+ */
+
+#define BMI_READ_MEMORY                     2
+/*
+ * Semantics: Host reads AR6K memory
+ * Request format:
+ *    A_UINT32      command (BMI_READ_MEMORY)
+ *    A_UINT32      address
+ *    A_UINT32      length, at most BMI_DATASZ_MAX
+ * Response format:
+ *    A_UINT8       data[length]
+ */
+
+#define BMI_WRITE_MEMORY                    3
+/*
+ * Semantics: Host writes AR6K memory
+ * Request format:
+ *    A_UINT32      command (BMI_WRITE_MEMORY)
+ *    A_UINT32      address
+ *    A_UINT32      length, at most BMI_DATASZ_MAX
+ *    A_UINT8       data[length]
+ * Response format: none
+ */
+/*
+ * Capbility to write "segmented files" is provided for two reasons
+ * 1) backwards compatibility for certain situations where Hosts
+ *    have limited flexibility
+ * 2) because it's darn convenient.
+ *
+ * A segmented file consists of a file header followed by an arbitrary number
+ * of segments.  Each segment contains segment metadata -- a Target address and
+ * a length -- followed by "length" bytes of data. A segmented file ends with
+ * a segment that specifies length=BMI_SGMTFILE_DONE. When a segmented file
+ * is sent to the Target, firmware writes each segment to the specified address.
+ *
+ * Special cases:
+ * 1) If a segment's metadata indicates length=BMI_SGMTFILE_EXEC, then the
+ * specified address is used as a function entry point for a brief function
+ * with prototype "(void *)(void)". That function is called immediately.
+ * After execution of the function completes, firmware continues with the
+ * next segment. No data is expected when length=BMI_SGMTFILE_EXEC.
+ *
+ * 2) If a segment's metadata indicates length=BMI_SGMTFILE_BEGINADDR, then
+ * the specified address is established as the application start address
+ * so that a subsequent BMI_DONE jumps there.
+ *
+ * 3) If a segment's metadata indicates length=BMI_SGMTFILE_BDDATA, then
+ * the specified address is used as the (possibly compressed) length of board
+ * data, which is loaded into the proper Target address as specified by
+ * hi_board_data. In addition, the hi_board_data_initialized flag is set.
+ *
+ * A segmented file is sent to the Target using a sequence of 1 or more
+ * BMI_WRITE_MEMORY commands.  The first such command must have
+ * address=BMI_SEGMENTED_WRITE_ADDR.  Subsequent BMI_WRITE_MEMORY commands
+ * can use an arbitrary address.  In each BMI_WRITE_MEMORY command, the
+ * length specifies the number of data bytes transmitted (except for the
+ * special cases listed above).
+ *
+ * Alternatively, a segmented file may be sent to the Target using a
+ * BMI_LZ_STREAM_START command with address=BMI_SEGMENTED_WRITE_ADDR
+ * followed by a series of BMI_LZ_DATA commands that each send the next portion
+ * of the segmented file.
+ *
+ * The data segments may be lz77 compressed.  In this case, the segmented file
+ * header flag, BMI_SGMTFILE_FLAG_COMPRESS, must be set.  Note that segmented
+ * file METAdata is never compressed; only the data segments themselves are
+ * compressed. There is no way to mix compressed and uncompressed data segments
+ * in a single segmented file. Compressed (or uncompressed) segments are handled
+ * by both BMI_WRITE_MEMORY and by BMI_LZ_DATA commands.  (Compression is an
+ * attribute of the segmented file rather than of the command used to transmit
+ * it.)
+ */
+#define BMI_SEGMENTED_WRITE_ADDR 0x1234
+
+/* File header for a segmented file */
+struct bmi_segmented_file_header {
+	A_UINT32 magic_num;
+	A_UINT32 file_flags;
+};
+#define BMI_SGMTFILE_MAGIC_NUM          0x544d4753      /* "SGMT" */
+#define BMI_SGMTFILE_FLAG_COMPRESS      1
+
+/* Metadata for a segmented file segment */
+struct bmi_segmented_metadata {
+	A_UINT32 addr;
+	A_UINT32 length;
+};
+/* Special values for bmi_segmented_metadata.length (all have high bit set) */
+#define BMI_SGMTFILE_DONE               0xffffffff      /* end of segmented data */
+#define BMI_SGMTFILE_BDDATA             0xfffffffe      /* Board Data segment */
+#define BMI_SGMTFILE_BEGINADDR          0xfffffffd      /* set beginning address */
+#define BMI_SGMTFILE_EXEC               0xfffffffc      /* immediate function execution */
+
+#define BMI_EXECUTE                         4
+/*
+ * Semantics: Causes AR6K to execute code
+ * Request format:
+ *    A_UINT32      command (BMI_EXECUTE)
+ *    A_UINT32      address
+ *    A_UINT32      parameter
+ * Response format:
+ *    A_UINT32      return value
+ */
+/*
+ * Note: In order to support the segmented file feature
+ * (see BMI_WRITE_MEMORY), when the address specified in a
+ * BMI_EXECUTE command matches (same physical address)
+ * BMI_SEGMENTED_WRITE_ADDR, it is ignored. Instead, execution
+ * begins at the address specified by hi_app_start.
+ */
+
+#define BMI_SET_APP_START                   5
+/*
+ * Semantics: Set Target application starting address
+ * Request format:
+ *    A_UINT32      command (BMI_SET_APP_START)
+ *    A_UINT32      address
+ * Response format: none
+ */
+
+#define BMI_READ_SOC_REGISTER               6
+#define BMI_READ_SOC_WORD                   6
+/*
+ * Semantics: Read a 32-bit Target SOC word.
+ * Request format:
+ *    A_UINT32      command (BMI_READ_REGISTER)
+ *    A_UINT32      address
+ * Response format:
+ *    A_UINT32      value
+ */
+
+#define BMI_WRITE_SOC_REGISTER              7
+#define BMI_WRITE_SOC_WORD                  7
+/*
+ * Semantics: Write a 32-bit Target SOC word.
+ * Request format:
+ *    A_UINT32      command (BMI_WRITE_REGISTER)
+ *    A_UINT32      address
+ *    A_UINT32      value
+ *
+ * Response format: none
+ */
+
+#define BMI_GET_TARGET_ID                  8
+#define BMI_GET_TARGET_INFO                8
+/*
+ * Semantics: Fetch the 4-byte Target information
+ * Request format:
+ *    A_UINT32      command (BMI_GET_TARGET_ID/INFO)
+ *
+ * Response format1 (old firmware):
+ *    A_UINT32      TargetVersionID
+ *
+ * Response format2 (intermediate firmware, during transition):
+ *    A_UINT32      TARGET_VERSION_SENTINAL
+ *    struct bmi_target_info;
+ *
+ * Response format3 (newest firmware)
+ *    struct bmi_target_info;
+ */
+PREPACK struct bmi_target_info {
+	/* size of this structure */
+	A_UINT32 target_info_byte_count;
+	A_UINT32 target_ver;
+	A_UINT32 target_type;
+} POSTPACK;
+
+#define TARGET_VERSION_SENTINAL 0xffffffff
+#define TARGET_TYPE_UNKNOWN   0
+#define TARGET_TYPE_AR6001    1
+#define TARGET_TYPE_AR6002    2
+#define TARGET_TYPE_AR6003    3
+#define TARGET_TYPE_AR6004    5
+#define TARGET_TYPE_AR6006    6
+#define TARGET_TYPE_AR9888    7
+#define TARGET_TYPE_AR6320    8
+#define TARGET_TYPE_AR900B    9
+/* For attach Peregrine 2.0 board target_reg_tbl only */
+#define TARGET_TYPE_AR9888V2  10
+/* For attach Rome1.0 target_reg_tbl only*/
+#define TARGET_TYPE_AR6320V1  11
+/* For Rome2.0/2.1 target_reg_tbl ID*/
+#define TARGET_TYPE_AR6320V2  12
+/* For Rome3.0 target_reg_tbl ID*/
+#define TARGET_TYPE_AR6320V3  13
+/* For Tufello1.0 target_reg_tbl ID*/
+#define TARGET_TYPE_QCA9377V1 14
+/* cascade */
+#define TARGET_TYPE_QCA9984   15
+/* dakota */
+#define TARGET_TYPE_IPQ4019   16
+/* besra */
+#define TARGET_TYPE_QCA9888   17
+/* For Adrastea target */
+#define TARGET_TYPE_ADRASTEA  19
+
+extern void target_register_tbl_attach(A_UINT32 target_type);
+
+#define BMI_ROMPATCH_INSTALL               9
+/*
+ * Semantics: Install a ROM Patch.
+ * Request format:
+ *    A_UINT32      command (BMI_ROMPATCH_INSTALL)
+ *    A_UINT32      Target ROM Address
+ *    A_UINT32      Target RAM Address or Value (depending on Target Type)
+ *    A_UINT32      Size, in bytes
+ *    A_UINT32      Activate? 1-->activate;
+ *                            0-->install but do not activate
+ * Response format:
+ *    A_UINT32      PatchID
+ */
+
+#define BMI_ROMPATCH_UNINSTALL             10
+/*
+ * Semantics: Uninstall a previously-installed ROM Patch,
+ * automatically deactivating, if necessary.
+ * Request format:
+ *    A_UINT32      command (BMI_ROMPATCH_UNINSTALL)
+ *    A_UINT32      PatchID
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_ACTIVATE              11
+/*
+ * Semantics: Activate a list of previously-installed ROM Patches.
+ * Request format:
+ *    A_UINT32      command (BMI_ROMPATCH_ACTIVATE)
+ *    A_UINT32      rompatch_count
+ *    A_UINT32      PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+#define BMI_ROMPATCH_DEACTIVATE            12
+/*
+ * Semantics: Deactivate a list of active ROM Patches.
+ * Request format:
+ *    A_UINT32      command (BMI_ROMPATCH_DEACTIVATE)
+ *    A_UINT32      rompatch_count
+ *    A_UINT32      PatchID[rompatch_count]
+ *
+ * Response format: none
+ */
+
+#define BMI_LZ_STREAM_START                13
+/*
+ * Semantics: Begin an LZ-compressed stream of input
+ * which is to be uncompressed by the Target to an
+ * output buffer at address.  The output buffer must
+ * be sufficiently large to hold the uncompressed
+ * output from the compressed input stream.  This BMI
+ * command should be followed by a series of 1 or more
+ * BMI_LZ_DATA commands.
+ *    A_UINT32      command (BMI_LZ_STREAM_START)
+ *    A_UINT32      address
+ * Note: Not supported on all versions of ROM firmware.
+ */
+
+#define BMI_LZ_DATA                        14
+/*
+ * Semantics: Host writes AR6K memory with LZ-compressed
+ * data which is uncompressed by the Target.  This command
+ * must be preceded by a BMI_LZ_STREAM_START command. A series
+ * of BMI_LZ_DATA commands are considered part of a single
+ * input stream until another BMI_LZ_STREAM_START is issued.
+ * Request format:
+ *    A_UINT32      command (BMI_LZ_DATA)
+ *    A_UINT32      length (of compressed data),
+ *                  at most BMI_DATASZ_MAX
+ *    A_UINT8       CompressedData[length]
+ * Response format: none
+ * Note: Not supported on all versions of ROM firmware.
+ */
+
+#define BMI_NVRAM_PROCESS                  15
+#define BMI_NVRAM_SEG_NAME_SZ 16
+/*
+ * Semantics: Cause Target to search NVRAM (if any) for a
+ * segment with the specified name and process it according
+ * to NVRAM metadata.
+ * Request format:
+ *    A_UINT32      command (BMI_NVRAM_PROCESS)
+ *    A_UCHAR       name[BMI_NVRAM_SEG_NAME_SZ] name (LE format)
+ * Response format:
+ *    A_UINT32      0, if nothing was executed;
+ *                  otherwise the value returned from the
+ *                  last NVRAM segment that was executed
+ */
+
+#define BMI_SIGN_STREAM_START               17
+/*
+ * Semantics: Trigger target start/end binary signature verification
+ * flow.
+ * Request format:
+ *    A_UINT32      command (BMI_SIGN_STREAM_START)
+ *    A_UINT32      address
+ *    A_UINT32      length, at most BMI_DATASZ_MAX
+ *    A_UINT8       data[length]
+ * Response format: none
+ */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+/* TBDXXX: Need a better place for these */
+#define BMI_CE_NUM_TO_TARG 0
+#define BMI_CE_NUM_TO_HOST 1
+
+#endif /* __BMI_MSG_H__ */

fw/cepci.h

@@ -33,7 +33,6 @@
  * Structures shared between Host software and Target firmware.
  */
 
-
 /*
  * Total number of PCIe MSI interrupts requested for all interrupt sources.
  * PCIe standard forces this to be a power of 2.
@@ -55,9 +54,6 @@
 #define MSI_ASSIGN_CE_INITIAL 1 /* 7 MSIs for Copy Engines */
 #define MSI_ASSIGN_CE_MAX     7
 
-
-
-
 /*
  * PCI-specific Target state.  Much of this may be of interest
  * to the Host so HOST_INTEREST->hi_interconnect_state points
@@ -66,49 +62,50 @@
  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
  */
 struct pcie_state_s {
-    A_UINT32 pipe_cfg_addr;      /* Pipe configuration Target address */
-                                 /* NB: CE_pipe_config[CE_COUNT] */
-
-    A_UINT32 svc_to_pipe_map;    /* Service to pipe map Target address */
-                                 /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
-
-    A_UINT32 MSI_requested;      /* number of MSI interrupts requested */
-    A_UINT32 MSI_granted;        /* number of MSI interrupts granted */
-    A_UINT32 MSI_addr;           /* Message Signalled Interrupt address */
-    A_UINT32 MSI_data;           /* Base data */
-    A_UINT32 MSI_fw_intr_data;   /* Data for firmware interrupt;
-                                    MSI data for other interrupts are
-                                    in various SoC registers */
-
-    A_UINT32 power_mgmt_method;  /* PCIE_PWR_METHOD_* */
-    A_UINT32 config_flags;       /* PCIE_CONFIG_FLAG_* */
+	uint32_t pipe_cfg_addr; /* Pipe configuration Target address */
+	/* NB: CE_pipe_config[CE_COUNT] */
+
+	uint32_t svc_to_pipe_map;       /* Service to pipe map Target address */
+	/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
+
+	uint32_t MSI_requested; /* number of MSI interrupts requested */
+	uint32_t MSI_granted;   /* number of MSI interrupts granted */
+	uint32_t MSI_addr;      /* Message Signalled Interrupt address */
+	uint32_t MSI_data;      /* Base data */
+	uint32_t MSI_fw_intr_data;      /* Data for firmware interrupt;
+	                                   MSI data for other interrupts are
+	                                   in various SoC registers */
+
+	uint32_t power_mgmt_method;     /* PCIE_PWR_METHOD_* */
+	uint32_t config_flags;  /* PCIE_CONFIG_FLAG_* */
 };
 
 /*
  * PCIE_CONFIG_FLAG definitions
  */
-
-#define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
+#if defined(AR900B)
 #define CE_PKTLOG_PIPE   8      /* used by both host and target side */
+#endif
 
+#define PCIE_CONFIG_FLAG_ENABLE_L1          0x0000001
 #define PCIE_CONFIG_FLAG_CLK_GATING_L1      0x0000001
 #define PCIE_CONFIG_FLAG_CLK_SWITCH_WAIT    0x0000002
 #define PCIE_CONFIG_FLAG_AXI_CLK_GATE       0x0000004
 #define PCIE_CONFIG_FLAG_CLK_REQ_L1         0x0000008
 
-#define PIPE_TO_CE_MAP_CNT 32 /* simple implementation constant */
+#define PIPE_TO_CE_MAP_CNT 32   /* simple implementation constant */
 
 /*
  * Configuration information for a Copy Engine pipe.
  * Passed from Host to Target during startup (one per CE).
  */
 struct CE_pipe_config {
-    A_UINT32 pipenum;
-    A_UINT32 pipedir;
-    A_UINT32 nentries;
-    A_UINT32 nbytes_max;
-    A_UINT32 flags;
-    A_UINT32 reserved;
+	uint32_t pipenum;
+	uint32_t pipedir;
+	uint32_t nentries;
+	uint32_t nbytes_max;
+	uint32_t flags;
+	uint32_t reserved;
 };
 
 #endif /* __CEPCI_H__ */

fw/dbglog.h

@@ -32,83 +32,87 @@
 #include "athstartpack.h"
 #endif
 
-#include <wlan_module_ids.h>
+#include "wlan_module_ids.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 #define DBGLOG_TIMESTAMP_OFFSET          0
-#define DBGLOG_TIMESTAMP_MASK            0xFFFFFFFF /* Bit 0-15. Contains bit
-                                                       8-23 of the LF0 timer */
+
+/* Bit 0-15. Contains bit 8-23 of the LF0 timer */
+#define DBGLOG_TIMESTAMP_MASK            0xFFFFFFFF
 #define DBGLOG_DBGID_OFFSET              0
-#define DBGLOG_DBGID_MASK                0x000003FF /* Bit 0-9 */
-#define DBGLOG_DBGID_NUM_MAX             256 /* Upper limit is width of mask */
+
+#define DBGLOG_DBGID_MASK                0x000003FF     /* Bit 0-9 */
+/* Upper limit is width of mask */
+#define DBGLOG_DBGID_NUM_MAX             256
 
 #define DBGLOG_MODULEID_OFFSET           10
-#define DBGLOG_MODULEID_MASK             0x0003FC00 /* Bit 10-17 */
-#define DBGLOG_MODULEID_NUM_MAX          32 /* Upper limit is width of mask */
+#define DBGLOG_MODULEID_MASK             0x0003FC00     /* Bit 10-17 */
+/* Upper limit is width of mask */
+#define DBGLOG_MODULEID_NUM_MAX          32
+
+#define DBGLOG_VDEVID_OFFSET             18
+#define DBGLOG_VDEVID_MASK               0x03FC0000    /* Bit 20-25 */
+#define DBGLOG_VDEVID_NUM_MAX            16
 
-#define DBGLOG_VDEVID_OFFSET              18
-#define DBGLOG_VDEVID_MASK                0x03FC0000 /* Bit 20-25*/
-#define DBGLOG_VDEVID_NUM_MAX             16
+#define DBGLOG_NUM_ARGS_OFFSET           26
+#define DBGLOG_NUM_ARGS_MASK             0xFC000000    /* Bit 26-31 */
 
-#define DBGLOG_NUM_ARGS_OFFSET             26
-#define DBGLOG_NUM_ARGS_MASK               0xFC000000 /* Bit 26-31 */
-#define DBGLOG_NUM_ARGS_MAX                9 /* it is bcoz of limitation
-                                             of corebsp MSG*() to accept max 9 arg  */
+/* it is limited bcoz of limitations of corebsp MSG*() to accept max 9 arg */
+#define DBGLOG_NUM_ARGS_MAX               9
 
-#define DBGLOG_LOG_BUFFER_SIZE             1500
-#define DBGLOG_DBGID_DEFINITION_LEN_MAX    90
+#define DBGLOG_LOG_BUFFER_SIZE            1500
+#define DBGLOG_DBGID_DEFINITION_LEN_MAX   90
 
 #define DBGLOG_HOST_LOG_BUFFER_SIZE            DBGLOG_LOG_BUFFER_SIZE
 
 #define DBGLOG_GET_DBGID(arg) \
-    ((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
+	((arg & DBGLOG_DBGID_MASK) >> DBGLOG_DBGID_OFFSET)
 
 #define DBGLOG_GET_MODULEID(arg) \
-    ((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
+	((arg & DBGLOG_MODULEID_MASK) >> DBGLOG_MODULEID_OFFSET)
 
 #define DBGLOG_GET_VDEVID(arg) \
-    ((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
+	((arg & DBGLOG_VDEVID_MASK) >> DBGLOG_VDEVID_OFFSET)
 
-#define DBGLOG_GET_NUMARGS(arg) \
-    ((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
+#define DBGLOG_GET_NUMARGS(arg)	\
+	((arg & DBGLOG_NUM_ARGS_MASK) >> DBGLOG_NUM_ARGS_OFFSET)
 
 #define DBGLOG_GET_TIME_STAMP(arg) \
-    ((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
+	((arg & DBGLOG_TIMESTAMP_MASK) >> DBGLOG_TIMESTAMP_OFFSET)
 
 
 /* Debug Log levels*/
 
-typedef enum {
-    DBGLOG_VERBOSE = 0,
-    DBGLOG_INFO,
-    DBGLOG_INFO_LVL_1,
-    DBGLOG_INFO_LVL_2,
-    DBGLOG_WARN,
-    DBGLOG_ERR,
-    DBGLOG_LVL_MAX
-}DBGLOG_LOG_LVL;
+enum DBGLOG_LOG_LVL {
+	DBGLOG_VERBOSE = 0,
+	DBGLOG_INFO,
+	DBGLOG_INFO_LVL_1,
+	DBGLOG_INFO_LVL_2,
+	DBGLOG_WARN,
+	DBGLOG_ERR,
+	DBGLOG_LVL_MAX
+};
 
 PREPACK struct dbglog_buf_s {
-    struct dbglog_buf_s *next;
-    A_UINT8             *buffer;
-    A_UINT32             bufsize;
-    A_UINT32             length;
-    A_UINT32             count;
-    A_UINT32             free;
+	struct dbglog_buf_s *next;
+	A_UINT8 *buffer;
+	A_UINT32 bufsize;
+	A_UINT32 length;
+	A_UINT32 count;
+	A_UINT32 free;
 } POSTPACK;
 
 PREPACK struct dbglog_hdr_s {
-    struct dbglog_buf_s *dbuf;
-    A_UINT32             dropped;
+	struct dbglog_buf_s *dbuf;
+	A_UINT32 dropped;
 } POSTPACK;
 
-#define DBGLOG_MAX_VDEVID 15 /* 0-15 */
+
+#define DBGLOG_MAX_VDEVID 15    /* 0-15 */
 
 #ifdef __cplusplus
 }
 #endif
-
-
 #endif /* _DBGLOG_H_ */

fw/dbglog_id.h

@@ -41,21 +41,20 @@ extern "C" {
  */
 
 /*
-* The target state machine framework will send dbglog messages on behalf on
-* other modules. We do this do avoid each module adding identical dbglog code
-* for state transitions and event processing. We also don't want to force each
-* module to define the the same XXX_DBGID_SM_MSG with the same value below.
-* Instead we use a special ID that the host dbglog code recognizes as a
-* message sent by the SM on behalf on another module.
-*/
+ * The target state machine framework will send dbglog messages on behalf on
+ * other modules. We do this do avoid each module adding identical dbglog code
+ * for state transitions and event processing. We also don't want to force each
+ * module to define the the same XXX_DBGID_SM_MSG with the same value below.
+ * Instead we use a special ID that the host dbglog code recognizes as a
+ * message sent by the SM on behalf on another module.
+ */
 #define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000
 
-
 /* INF debug identifier definitions */
 #define INF_DBGID_DEFINITION_START                    0
 #define INF_ASSERTION_FAILED                          1
 #define INF_TARGET_ID                                 2
-#define INF_TARGET_MEM_REMAING                3
+#define INF_TARGET_MEM_REMAING                                3
 #define INF_TARGET_MEM_EXT_REMAING                    4
 #define INF_TARGET_MEM_ALLOC_TRACK                    5
 #define INF_TARGET_MEM_ALLOC_RAM                      6
@@ -298,7 +297,7 @@ extern "C" {
 #define WHAL_ERROR_XTAL_SET                        49
 #define WHAL_DBGID_DEFINITION_END                  50
 
-#define COEX_DEBUGID_START                          0
+#define COEX_DEBUGID_START              0
 #define BTCOEX_DBG_MCI_1                            1
 #define BTCOEX_DBG_MCI_2                            2
 #define BTCOEX_DBG_MCI_3                            3
@@ -688,6 +687,7 @@ extern "C" {
 #define WAL_DBGID_TX_SCH_REGISTER_TIDQ              12
 #define WAL_DBGID_TX_SCH_UNREGISTER_TIDQ            13
 #define WAL_DBGID_TX_SCH_TICKLE_TIDQ                14
+
 #define WAL_DBGID_XCESS_FAILURES                    15
 #define WAL_DBGID_AST_ADD_WDS_ENTRY                 16
 #define WAL_DBGID_AST_DEL_WDS_ENTRY                 17
@@ -780,6 +780,7 @@ extern "C" {
 #define ANI_DBGID_MRC_CCK                           10
 #define ANI_DBGID_SELF_CORR_LOW                     11
 #define ANI_DBGID_ENABLE                            12
+
 #define ANI_DBGID_CURRENT_LEVEL                     13
 #define ANI_DBGID_POLL_PERIOD                       14
 #define ANI_DBGID_LISTEN_PERIOD                     15
@@ -864,8 +865,7 @@ extern "C" {
 #define P2P_GO_BCN_TX_COMP                                  38
 #define P2P_DBGID_DEFINITION_END                            39
 
-
-//CSA modules DBGIDs
+/* CSA modules DBGIDs */
 #define CSA_DBGID_DEFINITION_START 0
 #define CSA_OFFLOAD_POOL_INIT 1
 #define CSA_OFFLOAD_REGISTER_VDEV 2
@@ -925,7 +925,6 @@ extern "C" {
 #define WOW_IBSS_VDEV_ALLOW      23
 #define WOW_DBGID_DEFINITION_END 24
 
-
 /* SWBMISS module DBGIDs */
 #define SWBMISS_DBGID_DEFINITION_START  0
 #define SWBMISS_ENABLED                 1
@@ -1145,6 +1144,7 @@ extern "C" {
 #define RTT_CHANNEL_SWITCH_PREEMPT    18
 #define RTT_CHANNEL_SWITCH_STOP       19
 #define RTT_TIMER_START               20
+
 #define RTT_FTM_PARAM_INFO            21
 #define RTT_RX_TM_FRAME               22
 #define RTT_INITR_TSTAMP              23
@@ -1186,7 +1186,7 @@ extern "C" {
 #define WLAN_PHTERR_DFS_DBDID_FILTER_STATUS       5
 #define WLAN_PHYERR_DFS_DBGID_DEFINITION_END      6
 
-/* RMC DBGIDs*/
+/* RMC DBGIDs */
 #define RMC_DBGID_DEFINITION_START             0
 #define RMC_CREATE_INSTANCE                    1
 #define RMC_DELETE_INSTANCE                    2
@@ -1246,7 +1246,6 @@ extern "C" {
 #define WLAN_STATS_DBGID_RSSI                            6
 #define WLAN_STATS_DBGID_CNE_RSSI                        7
 #define WLAN_STATS_DBGID_DEFINITION_END                  8
-
 /* NAN DBGIDs */
 #define NAN_DBGID_START                             0
 
@@ -1491,46 +1490,51 @@ extern "C" {
 #define NAN_DBGID_BEACON_RX_LAST                (NAN_DBGID_OTA_PKT_LAST + 20)
 
 /* NaN Datapath Timekeeper debug IDs */
-#define NAN_DBGID_TMKR_BASE                        NAN_DBGID_BEACON_RX_LAST   /* 116 + 20 = 136 */
-#define NAN_DBGID_TMKR_INIT                        (NAN_DBGID_TMKR_BASE + 0)  /* 136 */
-#define NAN_DBGID_TMKR_OPEN                        (NAN_DBGID_TMKR_BASE + 1)  /* 137 */
-#define NAN_DBGID_TMKR_CLOSE                       (NAN_DBGID_TMKR_BASE + 2)  /* 138 */
-#define NAN_DBGID_TMKR_NEGOTIATE                   (NAN_DBGID_TMKR_BASE + 3)  /* 139 */
-#define NAN_DBGID_TMKR_TMR_HNDLR                   (NAN_DBGID_TMKR_BASE + 4)  /* 140 */
-#define NAN_DBGID_TMKR_UNITTEST                    (NAN_DBGID_TMKR_BASE + 5)  /* 141 */
-#define NAN_DBGID_TMKR_LF_TMR_HNDLR                (NAN_DBGID_TMKR_BASE + 6)  /* 142 */
-#define NAN_DBGID_TMKR_DEINIT                      (NAN_DBGID_TMKR_BASE + 7)  /* 143 */
-#define NAN_DBGID_TMKR_SLOTBITMAP                  (NAN_DBGID_TMKR_BASE + 8)  /* 144 */
-#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP           (NAN_DBGID_TMKR_BASE + 9)  /* 145 */
-#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP          (NAN_DBGID_TMKR_BASE + 10) /* 146 */
-#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP          (NAN_DBGID_TMKR_BASE + 11) /* 147 */
-#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT            (NAN_DBGID_TMKR_BASE + 12) /* 148 */
-#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT         (NAN_DBGID_TMKR_BASE + 13) /* 149 */
-#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT           (NAN_DBGID_TMKR_BASE + 14) /* 150 */
-#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP  (NAN_DBGID_TMKR_BASE + 15) /* 151 */
-#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP           (NAN_DBGID_TMKR_BASE + 16) /* 152 */
-#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG              (NAN_DBGID_TMKR_BASE + 17) /* 153 */
-#define NAN_DBGID_TMKR_POPULATE_MASTER             (NAN_DBGID_TMKR_BASE + 18) /* 154 */
-#define NAN_DBGID_TMKR_ALLOCATE_SLOTS              (NAN_DBGID_TMKR_BASE + 19) /* 155 */
-#define NAN_DBGID_TMKR_RELEASE_SLOTS               (NAN_DBGID_TMKR_BASE + 20) /* 156 */
-#define NAN_DBGID_TMKR_ENABLE                      (NAN_DBGID_TMKR_BASE + 21) /* 157 */
-#define NAN_DBGID_TMKR_DISABLE                     (NAN_DBGID_TMKR_BASE + 22) /* 158 */
-#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW         (NAN_DBGID_TMKR_BASE + 23) /* 159 */
-#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING          (NAN_DBGID_TMKR_BASE + 24) /* 160 */
-#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW  (NAN_DBGID_TMKR_BASE + 25) /* 161 */
-#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING         (NAN_DBGID_TMKR_BASE + 26) /* 162 */
-#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW    (NAN_DBGID_TMKR_BASE + 27) /* 163 */
-#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME            (NAN_DBGID_TMKR_BASE + 28) /* 164 */
-#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL         (NAN_DBGID_TMKR_BASE + 29) /* 165 */
-#define NAN_DBGID_TMKR_SCHEDULE_EVENT              (NAN_DBGID_TMKR_BASE + 30) /* 166 */
-#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT    (NAN_DBGID_TMKR_BASE + 31) /* 167 */
-#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT   (NAN_DBGID_TMKR_BASE + 32) /* 168 */
-#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT          (NAN_DBGID_TMKR_BASE + 33) /* 169 */
-#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT      (NAN_DBGID_TMKR_BASE + 34) /* 170 */
-#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT     (NAN_DBGID_TMKR_BASE + 35) /* 171 */
-#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT    (NAN_DBGID_TMKR_BASE + 36) /* 172 */
-#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT          (NAN_DBGID_TMKR_BASE + 37) /* 173 */
-#define NAN_DBGID_TMKR_LAST                        (NAN_DBGID_TMKR_BASE + 38) /* 174 */
+/* 116 + 20 = 136 */
+#define NAN_DBGID_TMKR_BASE                        NAN_DBGID_BEACON_RX_LAST
+/* 136 */
+#define NAN_DBGID_TMKR_INIT                        (NAN_DBGID_TMKR_BASE + 0)
+#define NAN_DBGID_TMKR_OPEN                        (NAN_DBGID_TMKR_BASE + 1)
+#define NAN_DBGID_TMKR_CLOSE                       (NAN_DBGID_TMKR_BASE + 2)
+#define NAN_DBGID_TMKR_NEGOTIATE                   (NAN_DBGID_TMKR_BASE + 3)
+#define NAN_DBGID_TMKR_TMR_HNDLR                   (NAN_DBGID_TMKR_BASE + 4)
+#define NAN_DBGID_TMKR_UNITTEST                    (NAN_DBGID_TMKR_BASE + 5)
+#define NAN_DBGID_TMKR_LF_TMR_HNDLR                (NAN_DBGID_TMKR_BASE + 6)
+#define NAN_DBGID_TMKR_DEINIT                      (NAN_DBGID_TMKR_BASE + 7)
+#define NAN_DBGID_TMKR_SLOTBITMAP                  (NAN_DBGID_TMKR_BASE + 8)
+#define NAN_DBGID_TMKR_CANCEL_SLOTBITMAP           (NAN_DBGID_TMKR_BASE + 9)
+#define NAN_DBGID_TMKR_CONFIRM_SLOTBITMAP          (NAN_DBGID_TMKR_BASE + 10)
+#define NAN_DBGID_TMKR_RESOLVE_SLOTBITMAP          (NAN_DBGID_TMKR_BASE + 11)
+#define NAN_DBGID_TMKR_ADD_CHAN_ELEMENT            (NAN_DBGID_TMKR_BASE + 12)
+#define NAN_DBGID_TMKR_REMOVE_CHAN_ELEMENT         (NAN_DBGID_TMKR_BASE + 13)
+/* 150 */
+#define NAN_DBGID_TMKR_FIND_CHAN_ELEMENT           (NAN_DBGID_TMKR_BASE + 14)
+#define NAN_DBGID_TMKR_QUERY_COMMITTED_SLOTBITMAP  (NAN_DBGID_TMKR_BASE + 15)
+#define NAN_DBGID_TMKR_ENCODE_SLOTBITMAP           (NAN_DBGID_TMKR_BASE + 16)
+#define NAN_DBGID_TMKR_SLOT_ARRAY_DBG              (NAN_DBGID_TMKR_BASE + 17)
+#define NAN_DBGID_TMKR_POPULATE_MASTER             (NAN_DBGID_TMKR_BASE + 18)
+#define NAN_DBGID_TMKR_ALLOCATE_SLOTS              (NAN_DBGID_TMKR_BASE + 19)
+#define NAN_DBGID_TMKR_RELEASE_SLOTS               (NAN_DBGID_TMKR_BASE + 20)
+#define NAN_DBGID_TMKR_ENABLE                      (NAN_DBGID_TMKR_BASE + 21)
+#define NAN_DBGID_TMKR_DISABLE                     (NAN_DBGID_TMKR_BASE + 22)
+#define NAN_DBGID_TMKR_GET_NEXT_SLOTWINDOW         (NAN_DBGID_TMKR_BASE + 23)
+#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING          (NAN_DBGID_TMKR_BASE + 24)
+#define NAN_DBGID_TMKR_RESYNC_TO_DISCOVERY_WINDOW  (NAN_DBGID_TMKR_BASE + 25)
+/* 162 */
+#define NAN_DBGID_TMKR_SUSPEND_TIMEKEEPING         (NAN_DBGID_TMKR_BASE + 26)
+#define NAN_DBGID_TMKR_SYNC_TO_DISCOVERY_WINDOW    (NAN_DBGID_TMKR_BASE + 27)
+#define NAN_DBGID_TMKR_GET_NEXT_TSFTIME            (NAN_DBGID_TMKR_BASE + 28)
+#define NAN_DBGID_TMKR_SETUP_NEXT_INTERVAL         (NAN_DBGID_TMKR_BASE + 29)
+#define NAN_DBGID_TMKR_SCHEDULE_EVENT              (NAN_DBGID_TMKR_BASE + 30)
+#define NAN_DBGID_TMKR_ENABLE_TIMEKEEPING_EVENT    (NAN_DBGID_TMKR_BASE + 31)
+#define NAN_DBGID_TMKR_DISABLE_TIMEKEEPING_EVENT   (NAN_DBGID_TMKR_BASE + 32)
+#define NAN_DBGID_TMKR_SYNC_WITH_DW_EVENT          (NAN_DBGID_TMKR_BASE + 33)
+#define NAN_DBGID_TMKR_INTERVAL_EXPIRED_EVENT      (NAN_DBGID_TMKR_BASE + 34)
+#define NAN_DBGID_TMKR_PAUSE_TIMEKEEPING_EVENT     (NAN_DBGID_TMKR_BASE + 35)
+/* 172 */
+#define NAN_DBGID_TMKR_RESUME_TIMEKEEPING_EVENT    (NAN_DBGID_TMKR_BASE + 36)
+#define NAN_DBGID_TMKR_RESYNC_TO_DW_EVENT          (NAN_DBGID_TMKR_BASE + 37)
+#define NAN_DBGID_TMKR_LAST                        (NAN_DBGID_TMKR_BASE + 38)
 
 #define NAN_DBGID_END                              (NAN_DBGID_TMKR_LAST)
 
@@ -1631,6 +1635,7 @@ extern "C" {
 #define ERE_DBGID_STATS_RX                              12
 #define ERE_DBGID_DEFINITION_END                        13
 /* IDs 14 - 251 reserved for ERE */
+
 /* Timekeeper debug IDs */
 #define TIMEKEEPER_INIT                                 252
 #define TIMEKEEPER_OPEN                                 253
@@ -1736,9 +1741,8 @@ extern "C" {
 #define WLAN_MODULE_QBOOST_DBGID_WLAN_PEER_NOT_FOUND      1
 #define WLAN_MODULE_QBOOST_DEFINITION_END                 2
 
+
 #ifdef __cplusplus
 }
 #endif
-
 #endif /* _DBGLOG_ID_H_ */
-

fw/efuse_reg.h

@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _EFUSE_REG_REG_H_
+#define _EFUSE_REG_REG_H_
+
+#define EFUSE_WR_ENABLE_REG_ADDRESS              0x00000000
+#define EFUSE_WR_ENABLE_REG_OFFSET               0x00000000
+#define EFUSE_WR_ENABLE_REG_V_MSB                0
+#define EFUSE_WR_ENABLE_REG_V_LSB                0
+#define EFUSE_WR_ENABLE_REG_V_MASK               0x00000001
+#define EFUSE_WR_ENABLE_REG_V_GET(x)             (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
+#define EFUSE_WR_ENABLE_REG_V_SET(x)             (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_ENABLE_REG_ADDRESS             0x00000004
+#define EFUSE_INT_ENABLE_REG_OFFSET              0x00000004
+#define EFUSE_INT_ENABLE_REG_V_MSB               0
+#define EFUSE_INT_ENABLE_REG_V_LSB               0
+#define EFUSE_INT_ENABLE_REG_V_MASK              0x00000001
+#define EFUSE_INT_ENABLE_REG_V_GET(x)            (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
+#define EFUSE_INT_ENABLE_REG_V_SET(x)            (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
+
+#define EFUSE_INT_STATUS_REG_ADDRESS             0x00000008
+#define EFUSE_INT_STATUS_REG_OFFSET              0x00000008
+#define EFUSE_INT_STATUS_REG_V_MSB               0
+#define EFUSE_INT_STATUS_REG_V_LSB               0
+#define EFUSE_INT_STATUS_REG_V_MASK              0x00000001
+#define EFUSE_INT_STATUS_REG_V_GET(x)            (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
+#define EFUSE_INT_STATUS_REG_V_SET(x)            (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
+
+#define BITMASK_WR_REG_ADDRESS                   0x0000000c
+#define BITMASK_WR_REG_OFFSET                    0x0000000c
+#define BITMASK_WR_REG_V_MSB                     31
+#define BITMASK_WR_REG_V_LSB                     0
+#define BITMASK_WR_REG_V_MASK                    0xffffffff
+#define BITMASK_WR_REG_V_GET(x)                  (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
+#define BITMASK_WR_REG_V_SET(x)                  (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
+
+#define VDDQ_SETTLE_TIME_REG_ADDRESS             0x00000010
+#define VDDQ_SETTLE_TIME_REG_OFFSET              0x00000010
+#define VDDQ_SETTLE_TIME_REG_V_MSB               31
+#define VDDQ_SETTLE_TIME_REG_V_LSB               0
+#define VDDQ_SETTLE_TIME_REG_V_MASK              0xffffffff
+#define VDDQ_SETTLE_TIME_REG_V_GET(x)            (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
+#define VDDQ_SETTLE_TIME_REG_V_SET(x)            (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
+
+#define VDDQ_HOLD_TIME_REG_ADDRESS               0x00000014
+#define VDDQ_HOLD_TIME_REG_OFFSET                0x00000014
+#define VDDQ_HOLD_TIME_REG_V_MSB                 31
+#define VDDQ_HOLD_TIME_REG_V_LSB                 0
+#define VDDQ_HOLD_TIME_REG_V_MASK                0xffffffff
+#define VDDQ_HOLD_TIME_REG_V_GET(x)              (((x) & VDDQ_HOLD_TIME_REG_V_MASK) >> VDDQ_HOLD_TIME_REG_V_LSB)
+#define VDDQ_HOLD_TIME_REG_V_SET(x)              (((x) << VDDQ_HOLD_TIME_REG_V_LSB) & VDDQ_HOLD_TIME_REG_V_MASK)
+
+#define RD_STROBE_PW_REG_ADDRESS                 0x00000018
+#define RD_STROBE_PW_REG_OFFSET                  0x00000018
+#define RD_STROBE_PW_REG_V_MSB                   31
+#define RD_STROBE_PW_REG_V_LSB                   0
+#define RD_STROBE_PW_REG_V_MASK                  0xffffffff
+#define RD_STROBE_PW_REG_V_GET(x)                (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
+#define RD_STROBE_PW_REG_V_SET(x)                (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
+
+#define PG_STROBE_PW_REG_ADDRESS                 0x0000001c
+#define PG_STROBE_PW_REG_OFFSET                  0x0000001c
+#define PG_STROBE_PW_REG_V_MSB                   31
+#define PG_STROBE_PW_REG_V_LSB                   0
+#define PG_STROBE_PW_REG_V_MASK                  0xffffffff
+#define PG_STROBE_PW_REG_V_GET(x)                (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
+#define PG_STROBE_PW_REG_V_SET(x)                (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
+
+#define PGENB_SETUP_HOLD_TIME_REG_ADDRESS        0x00000020
+#define PGENB_SETUP_HOLD_TIME_REG_OFFSET         0x00000020
+#define PGENB_SETUP_HOLD_TIME_REG_V_MSB          31
+#define PGENB_SETUP_HOLD_TIME_REG_V_LSB          0
+#define PGENB_SETUP_HOLD_TIME_REG_V_MASK         0xffffffff
+#define PGENB_SETUP_HOLD_TIME_REG_V_GET(x)       (((x) & PGENB_SETUP_HOLD_TIME_REG_V_MASK) >> PGENB_SETUP_HOLD_TIME_REG_V_LSB)
+#define PGENB_SETUP_HOLD_TIME_REG_V_SET(x)       (((x) << PGENB_SETUP_HOLD_TIME_REG_V_LSB) & PGENB_SETUP_HOLD_TIME_REG_V_MASK)
+
+#define STROBE_PULSE_INTERVAL_REG_ADDRESS        0x00000024
+#define STROBE_PULSE_INTERVAL_REG_OFFSET         0x00000024
+#define STROBE_PULSE_INTERVAL_REG_V_MSB          31
+#define STROBE_PULSE_INTERVAL_REG_V_LSB          0
+#define STROBE_PULSE_INTERVAL_REG_V_MASK         0xffffffff
+#define STROBE_PULSE_INTERVAL_REG_V_GET(x)       (((x) & STROBE_PULSE_INTERVAL_REG_V_MASK) >> STROBE_PULSE_INTERVAL_REG_V_LSB)
+#define STROBE_PULSE_INTERVAL_REG_V_SET(x)       (((x) << STROBE_PULSE_INTERVAL_REG_V_LSB) & STROBE_PULSE_INTERVAL_REG_V_MASK)
+
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_ADDRESS     0x00000028
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_OFFSET      0x00000028
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MSB       31
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB       0
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK      0xffffffff
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_GET(x)    (((x) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK) >> CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB)
+#define CSB_ADDR_LOAD_SETUP_HOLD_REG_V_SET(x)    (((x) << CSB_ADDR_LOAD_SETUP_HOLD_REG_V_LSB) & CSB_ADDR_LOAD_SETUP_HOLD_REG_V_MASK)
+
+#define EFUSE_INTF0_ADDRESS                      0x00000800
+#define EFUSE_INTF0_OFFSET                       0x00000800
+#define EFUSE_INTF0_R_MSB                        31
+#define EFUSE_INTF0_R_LSB                        0
+#define EFUSE_INTF0_R_MASK                       0xffffffff
+#define EFUSE_INTF0_R_GET(x)                     (((x) & EFUSE_INTF0_R_MASK) >> EFUSE_INTF0_R_LSB)
+#define EFUSE_INTF0_R_SET(x)                     (((x) << EFUSE_INTF0_R_LSB) & EFUSE_INTF0_R_MASK)
+
+#define EFUSE_INTF1_ADDRESS                      0x00001000
+#define EFUSE_INTF1_OFFSET                       0x00001000
+#define EFUSE_INTF1_R_MSB                        31
+#define EFUSE_INTF1_R_LSB                        0
+#define EFUSE_INTF1_R_MASK                       0xffffffff
+#define EFUSE_INTF1_R_GET(x)                     (((x) & EFUSE_INTF1_R_MASK) >> EFUSE_INTF1_R_LSB)
+#define EFUSE_INTF1_R_SET(x)                     (((x) << EFUSE_INTF1_R_LSB) & EFUSE_INTF1_R_MASK)
+
+#ifndef __ASSEMBLER__
+typedef struct efuse_reg_reg_s {
+	volatile unsigned int efuse_wr_enable_reg;
+	volatile unsigned int efuse_int_enable_reg;
+	volatile unsigned int efuse_int_status_reg;
+	volatile unsigned int bitmask_wr_reg;
+	volatile unsigned int vddq_settle_time_reg;
+	volatile unsigned int vddq_hold_time_reg;
+	volatile unsigned int rd_strobe_pw_reg;
+	volatile unsigned int pg_strobe_pw_reg;
+	volatile unsigned int pgenb_setup_hold_time_reg;
+	volatile unsigned int strobe_pulse_interval_reg;
+	volatile unsigned int csb_addr_load_setup_hold_reg;
+	unsigned char pad0[2004];       /* pad to 0x800 */
+	volatile unsigned int efuse_intf0[512];
+	volatile unsigned int efuse_intf1[512];
+} efuse_reg_reg_t;
+#endif /* __ASSEMBLER__ */
+
+#endif /* _EFUSE_REG_H_ */

fw/enet.h

@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _ENET__H_
+#define _ENET__H_
+
+#if defined(ATH_TARGET)
+#include <osapi.h>              /* A_UINT8 */
+#else
+#include <a_types.h>            /* A_UINT8 */
+#endif
+
+#define ETHERNET_ADDR_LEN 6     /* bytes */
+#define ETHERNET_TYPE_LEN 2     /* bytes - length of the Ethernet type field */
+
+struct ethernet_hdr_t {
+	A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
+	A_UINT8 src_addr[ETHERNET_ADDR_LEN];
+	A_UINT8 ethertype[ETHERNET_TYPE_LEN];
+};
+
+#define ETHERNET_HDR_LEN (sizeof(struct ethernet_hdr_t))
+
+#define ETHERNET_CRC_LEN  4     /* bytes - length of the Ethernet CRC */
+#define ETHERNET_MAX_LEN  1518  /* bytes */
+
+#define ETHERNET_MTU (ETHERNET_MAX_LEN - (ETHERNET_HDR_LEN + ETHERNET_CRC_LEN))
+
+
+struct llc_snap_hdr_t {
+	A_UINT8 dsap;
+	A_UINT8 ssap;
+	A_UINT8 cntl;
+	A_UINT8 org_code[3];
+	A_UINT8 ethertype[2];
+};
+
+#define LLC_SNAP_HDR_LEN (sizeof(struct llc_snap_hdr_t))
+#define LLC_SNAP_HDR_OFFSET_ETHERTYPE \
+	(offsetof(struct llc_snap_hdr_t, ethertype[0]))
+
+#define ETHERTYPE_VLAN_LEN  4
+
+struct ethernet_vlan_hdr_t {
+	A_UINT8 dest_addr[ETHERNET_ADDR_LEN];
+	A_UINT8 src_addr[ETHERNET_ADDR_LEN];
+	A_UINT8 vlan_tpid[2];
+	A_UINT8 vlan_tci[2];
+	A_UINT8 ethertype[2];
+};
+
+#define ETHERTYPE_IS_EAPOL_WAPI(typeorlen)	     \
+	((typeorlen) == ETHERTYPE_PAE ||  \
+	 (typeorlen) == ETHERTYPE_WAI)
+
+#define IS_ETHERTYPE(_typeOrLen) ((_typeOrLen) >= 0x0600)
+
+#ifndef ETHERTYPE_IPV4
+#define ETHERTYPE_IPV4  0x0800  /* Internet Protocol, Version 4 (IPv4) */
+#endif
+
+#ifndef ETHERTYPE_AARP
+#define ETHERTYPE_AARP  0x80f3  /* Internal QCA AARP protocol */
+#endif
+
+#ifndef ETHERTYPE_IPX
+#define ETHERTYPE_IPX    0x8137 /* IPX over DIX protocol */
+#endif
+
+#ifndef ETHERTYPE_ARP
+#define ETHERTYPE_ARP   0x0806  /* Address Resolution Protocol (ARP) */
+#endif
+
+#ifndef ETHERTYPE_RARP
+#define ETHERTYPE_RARP  0x8035  /* Reverse Address Resolution Protocol (RARP) */
+#endif
+
+#ifndef ETHERTYPE_VLAN
+#define ETHERTYPE_VLAN  0x8100  /* VLAN TAG protocol */
+#endif
+
+#ifndef ETHERTYPE_SNMP
+#define ETHERTYPE_SNMP  0x814C  /* Simple Network Management Protocol (SNMP) */
+#endif
+
+#ifndef ETHERTYPE_IPV6
+#define ETHERTYPE_IPV6  0x86DD  /* Internet Protocol, Version 6 (IPv6) */
+#endif
+
+#ifndef ETHERTYPE_PAE
+#define ETHERTYPE_PAE   0x888E  /* EAP over LAN (EAPOL) */
+#endif
+
+#ifndef ETHERTYPE_WAI
+#define ETHERTYPE_WAI   0x88B4  /* WAPI */
+#endif
+
+#ifndef ETHERTYPE_TDLS
+#define ETHERTYPE_TDLS  0x890D  /* TDLS */
+#endif
+
+#define LLC_SNAP_LSAP 0xaa
+#define LLC_UI 0x3
+
+#define RFC1042_SNAP_ORGCODE_0 0x00
+#define RFC1042_SNAP_ORGCODE_1 0x00
+#define RFC1042_SNAP_ORGCODE_2 0x00
+
+#define BTEP_SNAP_ORGCODE_0 0x00
+#define BTEP_SNAP_ORGCODE_1 0x00
+#define BTEP_SNAP_ORGCODE_2 0xf8
+
+#define IS_SNAP(_llc) ((_llc)->dsap == LLC_SNAP_LSAP &&	\
+		       (_llc)->ssap == LLC_SNAP_LSAP &&	\
+		       (_llc)->cntl == LLC_UI)
+
+#define IS_RFC1042(_llc) ((_llc)->org_code[0] == RFC1042_SNAP_ORGCODE_0 && \
+			  (_llc)->org_code[1] == RFC1042_SNAP_ORGCODE_1 && \
+			  (_llc)->org_code[2] == RFC1042_SNAP_ORGCODE_2)
+
+#define IS_BTEP(_llc) ((_llc)->org_code[0] == BTEP_SNAP_ORGCODE_0 && \
+		       (_llc)->org_code[1] == BTEP_SNAP_ORGCODE_1 && \
+		       (_llc)->org_code[2] == BTEP_SNAP_ORGCODE_2)
+
+#endif /* _ENET__H_ */

fw/epping_test.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+/* This file contains shared definitions for the host/target endpoint ping test */
+
+#ifndef EPPING_TEST_H
+#define EPPING_TEST_H
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+
+/* alignment to 4-bytes */
+#define EPPING_ALIGNMENT_PAD  (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
+
+#ifndef A_OFFSETOF
+#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
+#endif
+
+#define EPPING_RSVD_FILL                  0xCC
+
+#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET  7
+
+typedef PREPACK struct {
+	A_UINT8 _HCIRsvd[8];    /* reserved for HCI packet header (GMBOX) testing */
+	A_UINT8 StreamEcho_h;   /* stream no. to echo this packet on (filled by host) */
+	A_UINT8 StreamEchoSent_t;       /* stream no. packet was echoed to (filled by target)
+	                                   When echoed: StreamEchoSent_t == StreamEcho_h */
+	A_UINT8 StreamRecv_t;   /* stream no. that target received this packet on (filled by target) */
+	A_UINT8 StreamNo_h;     /* stream number to send on (filled by host) */
+	A_UINT8 Magic_h[4];     /* magic number to filter for this packet on the host */
+	A_UINT8 _rsvd[6];       /* reserved fields that must be set to a "reserved" value
+	                           since this packet maps to a 14-byte ethernet frame we want
+	                           to make sure ethertype field is set to something unknown */
+
+	A_UINT8 _pad[2];        /* padding for alignment */
+	A_UINT8 TimeStamp[8];   /* timestamp of packet (host or target) */
+	A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
+	A_UINT32 SeqNo;         /* sequence number (set by host or target) */
+	A_UINT16 Cmd_h;         /* ping command (filled by host) */
+	A_UINT16 CmdFlags_h;    /* optional flags */
+	A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
+	A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
+	A_UINT16 DataLength;    /* length of data */
+	A_UINT16 DataCRC;       /* 16 bit CRC of data */
+	A_UINT16 HeaderCRC;     /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
+} POSTPACK EPPING_HEADER;
+
+#define EPPING_PING_MAGIC_0           0xAA
+#define EPPING_PING_MAGIC_1           0x55
+#define EPPING_PING_MAGIC_2           0xCE
+#define EPPING_PING_MAGIC_3           0xEC
+
+#define IS_EPPING_PACKET(pPkt)   (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
+				  ((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
+				  ((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
+				  ((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
+
+#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
+					(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
+					(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
+					(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3; }
+
+#define CMD_FLAGS_DATA_CRC            (1 << 0)  /* DataCRC field is valid */
+#define CMD_FLAGS_DELAY_ECHO          (1 << 1)  /* delay the echo of the packet */
+#define CMD_FLAGS_NO_DROP             (1 << 2)  /* do not drop at HTC layer no matter what the stream is */
+
+#define IS_EPING_PACKET_NO_DROP(pPkt)  ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
+
+#define EPPING_CMD_ECHO_PACKET          1       /* echo packet test */
+#define EPPING_CMD_RESET_RECV_CNT       2       /* reset recv count */
+#define EPPING_CMD_CAPTURE_RECV_CNT     3       /* fetch recv count, 4-byte count returned in CmdBuffer_t */
+#define EPPING_CMD_NO_ECHO              4       /* non-echo packet test (tx-only) */
+#define EPPING_CMD_CONT_RX_START        5       /* continous RX packets, parameters are in CmdBuffer_h */
+#define EPPING_CMD_CONT_RX_STOP         6       /* stop continuous RX packet transmission */
+
+/* test command parameters may be no more than 8 bytes */
+typedef PREPACK struct {
+	A_UINT16 BurstCnt;      /* number of packets to burst together (for HTC 2.1 testing) */
+	A_UINT16 PacketLength;  /* length of packet to generate including header */
+	A_UINT16 Flags;         /* flags */
+
+#define EPPING_CONT_RX_DATA_CRC     (1 << 0)    /* Add CRC to all data */
+#define EPPING_CONT_RX_RANDOM_DATA  (1 << 1)    /* randomize the data pattern */
+#define EPPING_CONT_RX_RANDOM_LEN   (1 << 2)    /* randomize the packet lengths */
+#define EPPING_CONT_RX_NO_DATA_FILL (1 << 3)    /* target will not fill buffers */
+	A_UINT16 Context;       /* flags */
+
+} POSTPACK EPPING_CONT_RX_PARAMS;
+
+#define EPPING_HDR_CRC_OFFSET    A_OFFSETOF(EPPING_HEADER,StreamNo_h)
+#define EPPING_HDR_BYTES_CRC     (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
+
+#define HCI_TRANSPORT_STREAM_NUM  16    /* this number is higher than the define WMM AC classes so we
+	                                   can use this to distinguish packets */
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* EPPING_TEST_H */

fw/htc.h

@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2012-2014, 2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef __HTC_H__
+#define __HTC_H__
+
+#ifndef ATH_TARGET
+#include "athstartpack.h"
+#endif
+#ifdef ATHR_WIN_NWF
+#pragma warning(disable:4214)
+#endif
+#undef MS
+#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
+#undef SM
+#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
+#undef WO
+#define WO(_f)      ((_f ## _OFFSET) >> 2)
+
+#undef GET_FIELD
+#define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
+#undef SET_FIELD
+#define SET_FIELD(_addr, _f, _val)  \
+	(*((A_UINT32 *)(_addr) + WO(_f)) = \
+		 (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
+
+#define HTC_GET_FIELD(_msg_buf, _msg_type, _f) \
+	GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
+
+#define HTC_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
+	SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
+
+#define HTC_WRITE32(_addr, _val) \
+	(*(A_UINT32 *)(_addr) = (_val))
+
+#ifndef A_OFFSETOF
+#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
+#endif
+
+#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
+	(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
+
+/****** DANGER DANGER ***************
+ *
+ *   The frame header length and message formats defined herein were
+ *   selected to accommodate optimal alignment for target processing.  This reduces code
+ *   size and improves performance.
+ *
+ *   Any changes to the header length may alter the alignment and cause exceptions
+ *   on the target. When adding to the message structures insure that fields are
+ *   properly aligned.
+ *
+ */
+
+/* HTC frame header */
+typedef PREPACK struct _HTC_FRAME_HDR {
+	/* do not remove or re-arrange these fields, these are minimally required
+	 * to take advantage of 4-byte lookaheads in some hardware implementations */
+	A_UINT32 EndpointID : 8, Flags : 8, PayloadLen : 16;  /* length of data (including trailer) that follows the header */
+
+	/***** end of 4-byte lookahead ****/
+
+	A_UINT32 ControlBytes0 : 8,/*used for CRC check if CRC_CHECK flag set*/
+		 ControlBytes1 : 8, /*used for seq check if SEQ_CHECK flag set*/
+		 reserved : 16; /*used by bundle processing in SDIO systems*/
+
+	/* message payload starts after the header */
+
+} POSTPACK HTC_FRAME_HDR;
+
+#define HTC_FRAME_HDR_ENDPOINTID_LSB                0
+#define HTC_FRAME_HDR_ENDPOINTID_MASK               0x000000ff
+#define HTC_FRAME_HDR_ENDPOINTID_OFFSET             0x00000000
+#define HTC_FRAME_HDR_FLAGS_LSB                     8
+#define HTC_FRAME_HDR_FLAGS_MASK                    0x0000ff00
+#define HTC_FRAME_HDR_FLAGS_OFFSET                  0x00000000
+#define HTC_FRAME_HDR_PAYLOADLEN_LSB                16
+#define HTC_FRAME_HDR_PAYLOADLEN_MASK               0xffff0000
+#define HTC_FRAME_HDR_PAYLOADLEN_OFFSET             0x00000000
+#define HTC_FRAME_HDR_CONTROLBYTES0_LSB             0
+#define HTC_FRAME_HDR_CONTROLBYTES0_MASK            0x000000ff
+#define HTC_FRAME_HDR_CONTROLBYTES0_OFFSET          0x00000004
+#define HTC_FRAME_HDR_CONTROLBYTES1_LSB             8
+#define HTC_FRAME_HDR_CONTROLBYTES1_MASK            0x0000ff00
+#define HTC_FRAME_HDR_CONTROLBYTES1_OFFSET          0x00000004
+#define HTC_FRAME_HDR_RESERVED_LSB                  16
+#define HTC_FRAME_HDR_RESERVED_MASK                 0xffff0000
+#define HTC_FRAME_HDR_RESERVED_OFFSET               0x00000004
+
+/* frame header flags */
+
+/* send direction */
+#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
+#define HTC_FLAGS_SEND_BUNDLE        (1 << 1)   /* start or part of bundle */
+#define HTC_FLAGS_SEQ_CHECK          (1 << 2) /* seq check on rx side */
+#define HTC_FLAGS_CRC_CHECK          (1 << 3) /* CRC check on rx side */
+/* receive direction */
+#define HTC_FLAGS_RECV_1MORE_BLOCK   (1 << 0) /* bit 0 bundle trailer present */
+#define HTC_FLAGS_RECV_TRAILER       (1 << 1) /* bit 1 trailer data present */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK   (0xFC)    /* bits 7..2  */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT  2
+/*
+ * To be compatible with an older definition of a smaller (4-bit)
+ * bundle count field, the bundle count is stored in a segmented
+ * format - the 4 LSbs of the bundle count value are stored in bits 5:2
+ * of the BUNDLE_CNT field, which is bits 7:4 of the HTC_FLAGS word;
+ * the next 2 bits of the bundle count value are stored in bits 1:0 of
+ * the BUNDLE_CNT field, which is bits 3:2 of the HTC_FLAGS word.
+ */
+#define HTC_FLAGS_RECV_BUNDLE_CNT_SET(x)  \
+	((((x) << 2) | ((x) >> 4)) << HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT)
+#define HTC_FLAGS_RECV_BUNDLE_CNT_GET(x)  \
+	((((x) & HTC_FLAGS_RECV_BUNDLE_CNT_MASK) >> \
+	(HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT + 2)) | \
+	((((x) >> HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT) & 0x3) << 4))
+
+#define HTC_HDR_LENGTH  (sizeof(HTC_FRAME_HDR))
+#define HTC_HDR_ALIGNMENT_PADDING	    \
+	(((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
+#define HTC_MAX_TRAILER_LENGTH   255
+#define HTC_MAX_PAYLOAD_LENGTH   (4096 - sizeof(HTC_FRAME_HDR))
+
+/* HTC control message IDs */
+
+#define HTC_MSG_READY_ID                    1
+#define HTC_MSG_CONNECT_SERVICE_ID          2
+#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
+#define HTC_MSG_SETUP_COMPLETE_ID           4
+#define HTC_MSG_SETUP_COMPLETE_EX_ID        5
+#define HTC_MSG_SEND_SUSPEND_COMPLETE       6
+#define HTC_MSG_NACK_SUSPEND                7
+#define HTC_MSG_WAKEUP_FROM_SUSPEND_ID      8
+
+#define HTC_MAX_CONTROL_MESSAGE_LENGTH  256
+
+/* base message ID header */
+typedef PREPACK struct {
+	A_UINT32 MessageID : 16, reserved : 16;
+} POSTPACK HTC_UNKNOWN_MSG;
+
+#define HTC_UNKNOWN_MSG_MESSAGEID_LSB                 0
+#define HTC_UNKNOWN_MSG_MESSAGEID_MASK                0x0000ffff
+#define HTC_UNKNOWN_MSG_MESSAGEID_OFFSET              0x00000000
+
+/* HTC ready message
+ * direction : target-to-host  */
+typedef PREPACK struct {
+	A_UINT32 MessageID : 16,  /* ID */
+		 CreditCount : 16; /* number of credits the target can offer */
+	A_UINT32 CreditSize : 16, /* size of each credit */
+		 MaxEndpoints : 8, /* maximum number of endpoints the target has resources for */
+		 _Pad1 : 8;
+} POSTPACK HTC_READY_MSG;
+
+#define HTC_READY_MSG_MESSAGEID_LSB                   0
+#define HTC_READY_MSG_MESSAGEID_MASK                  0x0000ffff
+#define HTC_READY_MSG_MESSAGEID_OFFSET                0x00000000
+#define HTC_READY_MSG_CREDITCOUNT_LSB                 16
+#define HTC_READY_MSG_CREDITCOUNT_MASK                0xffff0000
+#define HTC_READY_MSG_CREDITCOUNT_OFFSET              0x00000000
+#define HTC_READY_MSG_CREDITSIZE_LSB                  0
+#define HTC_READY_MSG_CREDITSIZE_MASK                 0x0000ffff
+#define HTC_READY_MSG_CREDITSIZE_OFFSET               0x00000004
+#define HTC_READY_MSG_MAXENDPOINTS_LSB                16
+#define HTC_READY_MSG_MAXENDPOINTS_MASK               0x00ff0000
+#define HTC_READY_MSG_MAXENDPOINTS_OFFSET             0x00000004
+
+/* extended HTC ready message */
+typedef PREPACK struct {
+	HTC_READY_MSG Version2_0_Info;  /* legacy version 2.0 information at the front... */
+	/* extended information */
+	A_UINT32 HTCVersion : 8, MaxMsgsPerHTCBundle : 8, reserved : 16;
+} POSTPACK HTC_READY_EX_MSG;
+
+#define HTC_READY_EX_MSG_HTCVERSION_LSB               0
+#define HTC_READY_EX_MSG_HTCVERSION_MASK              0x000000ff
+#define HTC_READY_EX_MSG_HTCVERSION_OFFSET            sizeof(HTC_READY_MSG)
+#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_LSB      8
+#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_MASK     0x0000ff00
+#define HTC_READY_EX_MSG_MAXMSGSPERHTCBUNDLE_OFFSET   sizeof(HTC_READY_MSG)
+
+#define HTC_VERSION_2P0  0x00
+#define HTC_VERSION_2P1  0x01   /* HTC 2.1 */
+
+#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
+
+/* connect service
+ * direction : host-to-target */
+typedef PREPACK struct {
+	/* service ID of the service to connect to */
+	A_UINT32 MessageID:16, service_id:16;
+	A_UINT32 ConnectionFlags : 16,    /* connection flags */
+#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2)
+	/* reduce credit dribbling when
+	   the host needs credits */
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK             (0x3)
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH        0x0
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF          0x1
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS     0x2
+#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY             0x3
+	/* disable credit flow control on a specific service */
+#define HTC_CONNECT_FLAGS_DISABLE_CREDIT_FLOW_CTRL          (1 << 3)
+	/* enable htc schedule on a specific service */
+#define HTC_CONNECT_FLAGS_ENABLE_HTC_SCHEDULE               (1 << 4)
+	ServiceMetaLength : 8,  /* length of meta data that follows */
+	_Pad1 : 8;
+
+	/* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_MSG;
+
+#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_LSB             0
+#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_MASK            0x0000ffff
+#define HTC_CONNECT_SERVICE_MSG_MESSAGEID_OFFSET          0x00000000
+#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_LSB            16
+#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_MASK           0xffff0000
+#define HTC_CONNECT_SERVICE_MSG_SERVICE_ID_OFFSET         0x00000000
+#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_LSB       0
+#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_MASK      0x0000ffff
+#define HTC_CONNECT_SERVICE_MSG_CONNECTIONFLAGS_OFFSET    0x00000004
+#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_LSB     16
+#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_MASK    0x00ff0000
+#define HTC_CONNECT_SERVICE_MSG_SERVICEMETALENGTH_OFFSET  0x00000004
+
+#define HTC_SET_RECV_ALLOC_SHIFT    8
+#define HTC_SET_RECV_ALLOC_MASK     0xFF00
+#define HTC_CONNECT_FLAGS_SET_RECV_ALLOCATION(value) (((A_UINT8)value) << HTC_SET_RECV_ALLOC_SHIFT)
+#define HTC_CONNECT_FLAGS_GET_RECV_ALLOCATION(value) (A_UINT8)(((value) & HTC_SET_RECV_ALLOC_MASK) >> HTC_SET_RECV_ALLOC_SHIFT)
+
+/* connect response
+ * direction : target-to-host */
+typedef PREPACK struct {
+	/* service ID that the connection request was made */
+	A_UINT32 MessageID:16, service_id:16;
+	A_UINT32 Status : 8,      /* service connection status */
+		 EndpointID : 8, /* assigned endpoint ID */
+		 MaxMsgSize : 16; /* maximum expected message size on this endpoint */
+	A_UINT32 ServiceMetaLength : 8,   /* length of meta data that follows */
+		 _Pad1 : 8, reserved : 16;
+
+	/* service-specific meta data starts after the header */
+
+} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
+
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_LSB            0
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_MASK           0x0000ffff
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MESSAGEID_OFFSET         0x00000000
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_LSB            16
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_MASK           0xffff0000
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEID_OFFSET         0x00000000
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_LSB               0
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_MASK              0x000000ff
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_STATUS_OFFSET            0x00000004
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_LSB           8
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_MASK          0x0000ff00
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_ENDPOINTID_OFFSET        0x00000004
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_LSB           16
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_MASK          0xffff0000
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_MAXMSGSIZE_OFFSET        0x00000004
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_LSB    0
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_MASK   0x000000ff
+#define HTC_CONNECT_SERVICE_RESPONSE_MSG_SERVICEMETALENGTH_OFFSET 0x00000008
+
+typedef PREPACK struct {
+	A_UINT32 MessageID : 16, reserved : 16;
+	/* currently, no other fields */
+} POSTPACK HTC_SETUP_COMPLETE_MSG;
+
+#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_LSB          0
+#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_MASK         0x0000ffff
+#define HTC_SETUP_COMPLETE_MSG_MESSAGEID_OFFSET       0x00000000
+
+/* extended setup completion message */
+typedef PREPACK struct {
+	A_UINT32 MessageID : 16, reserved : 16;
+	A_UINT32 SetupFlags : 32;
+	A_UINT32 MaxMsgsPerBundledRecv : 8, Rsvd0 : 8, Rsvd1 : 8, Rsvd2 : 8;
+} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
+
+#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_LSB               0
+#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_MASK              0x0000ffff
+#define HTC_SETUP_COMPLETE_EX_MSG_MESSAGEID_OFFSET            0x00000000
+#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_LSB              0
+#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_MASK             0xffffffff
+#define HTC_SETUP_COMPLETE_EX_MSG_SETUPFLAGS_OFFSET           0x00000004
+#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_LSB       0
+#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_MASK      0x000000ff
+#define HTC_SETUP_COMPLETE_EX_MSG_MAXMSGSPERBUNDLEDRECV_OFFSET    0x00000008
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_LSB                   8
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_MASK                  0x0000ff00
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD0_OFFSET                0x00000008
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_LSB                   16
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_MASK                  0x00ff0000
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD1_OFFSET                0x00000008
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_LSB                   24
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_MASK                  0xff000000
+#define HTC_SETUP_COMPLETE_EX_MSG_RSVD2_OFFSET                0x00000008
+
+#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV     (1 << 0)        /* enable recv bundling from target */
+#define HTC_SETUP_COMPLETE_FLAGS_DISABLE_TX_CREDIT_FLOW (1 << 1)        /* disable credit based flow control,
+	                                                                   only supported on some interconnects */
+
+/* connect response status codes */
+#define HTC_SERVICE_SUCCESS      0      /* success */
+#define HTC_SERVICE_NOT_FOUND    1      /* service could not be found */
+#define HTC_SERVICE_FAILED       2      /* specific service failed the connect */
+#define HTC_SERVICE_NO_RESOURCES 3      /* no resources (i.e. no more endpoints) */
+#define HTC_SERVICE_NO_MORE_EP   4      /* specific service is not allowing any more
+	                                   endpoints */
+
+/* report record IDs */
+
+#define HTC_RECORD_NULL             0
+#define HTC_RECORD_CREDITS          1
+#define HTC_RECORD_LOOKAHEAD        2
+#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
+
+typedef PREPACK struct {
+	A_UINT32 RecordID : 8,    /* Record ID */
+		 Length : 8,    /* Length of record */
+		 reserved : 16;
+} POSTPACK HTC_RECORD_HDR;
+
+#define HTC_RECORD_HDR_RECORDID_LSB           0
+#define HTC_RECORD_HDR_RECORDID_MASK          0x000000ff
+#define HTC_RECORD_HDR_RECORDID_OFFSET        0x00000000
+#define HTC_RECORD_HDR_LENGTH_LSB             8
+#define HTC_RECORD_HDR_LENGTH_MASK            0x0000ff00
+#define HTC_RECORD_HDR_LENGTH_OFFSET          0x00000000
+
+typedef PREPACK struct {
+	A_UINT32 EndpointID : 8,  /* Endpoint that owns these credits */
+		 Credits : 8,   /* credits to report since last report */
+		 reserved : 16;
+} POSTPACK HTC_CREDIT_REPORT;
+
+#define HTC_CREDIT_REPORT_ENDPOINTID_LSB      0
+#define HTC_CREDIT_REPORT_ENDPOINTID_MASK     0x000000ff
+#define HTC_CREDIT_REPORT_ENDPOINTID_OFFSET   0x00000000
+#define HTC_CREDIT_REPORT_CREDITS_LSB         8
+#define HTC_CREDIT_REPORT_CREDITS_MASK        0x0000ff00
+#define HTC_CREDIT_REPORT_CREDITS_OFFSET      0x00000000
+
+typedef PREPACK struct {
+	A_UINT32 PreValid : 8,    /* pre valid guard */
+		 reserved0 : 24;
+	A_UINT32 LookAhead0 : 8,  /* 4 byte lookahead */
+		 LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
+	A_UINT32 PostValid : 8,   /* post valid guard */
+		 reserved1 : 24;
+
+	/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
+	 * The PreValid bytes must equal the inverse of the PostValid byte */
+
+} POSTPACK HTC_LOOKAHEAD_REPORT;
+
+#define HTC_LOOKAHEAD_REPORT_PREVALID_LSB         0
+#define HTC_LOOKAHEAD_REPORT_PREVALID_MASK        0x000000ff
+#define HTC_LOOKAHEAD_REPORT_PREVALID_OFFSET      0x00000000
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB       0
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK      0x000000ff
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET    0x00000004
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB       8
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK      0x0000ff00
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET    0x00000004
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB       16
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK      0x00ff0000
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET    0x00000004
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB       24
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK      0xff000000
+#define HTC_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET    0x00000004
+#define HTC_LOOKAHEAD_REPORT_POSTVALID_LSB        0
+#define HTC_LOOKAHEAD_REPORT_POSTVALID_MASK       0x000000ff
+#define HTC_LOOKAHEAD_REPORT_POSTVALID_OFFSET     0x00000008
+
+typedef PREPACK struct {
+	A_UINT32 LookAhead0 : 8,  /* 4 byte lookahead */
+		 LookAhead1 : 8, LookAhead2 : 8, LookAhead3 : 8;
+} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
+
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_LSB           0
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_MASK          0x000000ff
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD0_OFFSET        0x00000000
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_LSB           8
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_MASK          0x0000ff00
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD1_OFFSET        0x00000000
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_LSB           16
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_MASK          0x00ff0000
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD2_OFFSET        0x00000000
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_LSB           24
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_MASK          0xff000000
+#define HTC_BUNDLED_LOOKAHEAD_REPORT_LOOKAHEAD3_OFFSET        0x00000000
+
+#ifndef ATH_TARGET
+#include "athendpack.h"
+#endif
+
+#endif /* __HTC_H__ */

fw/htc_services.h

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2012, 2014, 2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef __HTC_SERVICES_H__
+#define __HTC_SERVICES_H__
+
+/* Current service IDs */
+
+typedef enum {
+	RSVD_SERVICE_GROUP = 0,
+	WMI_SERVICE_GROUP = 1,
+	NMI_SERVICE_GROUP = 2,
+	HTT_SERVICE_GROUP = 3,
+	CFG_NV_SERVICE_GROUP = 4,
+	WDI_IPA_SERVICE_GROUP = 5,
+	PACKET_LOG_SERVICE_GROUP = 6,
+	HTC_TEST_GROUP = 254,
+	HTC_SERVICE_GROUP_LAST = 255
+} HTC_SERVICE_GROUP_IDS;
+
+#define MAKE_SERVICE_ID(group,index) \
+	(int)(((int)group << 8) | (int)(index))
+
+/* NOTE: service ID of 0x0000 is reserved and should never be used */
+#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
+#define WMI_CONTROL_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
+#define WMI_DATA_BE_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
+#define WMI_DATA_BK_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
+#define WMI_DATA_VI_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
+#define WMI_DATA_VO_SVC   MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
+#define WMI_MAX_SERVICES  5
+
+#define NMI_CONTROL_SVC   MAKE_SERVICE_ID(NMI_SERVICE_GROUP,0)
+#define NMI_DATA_SVC      MAKE_SERVICE_ID(NMI_SERVICE_GROUP,1)
+
+#define HTT_DATA_MSG_SVC  MAKE_SERVICE_ID(HTT_SERVICE_GROUP,0)
+#define HTT_DATA2_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP,1)
+#define HTT_DATA3_MSG_SVC MAKE_SERVICE_ID(HTT_SERVICE_GROUP, 2)
+
+/* raw stream service (i.e. flash, tcmd, calibration apps) */
+#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
+
+#define CFG_NV_SVC  MAKE_SERVICE_ID(CFG_NV_SERVICE_GROUP,0)
+#define WDI_IPA_TX_SVC MAKE_SERVICE_ID(WDI_IPA_SERVICE_GROUP,0)
+
+#define PACKET_LOG_SVC MAKE_SERVICE_ID(PACKET_LOG_SERVICE_GROUP, 0)
+
+/*
+ * Directions for interconnect pipe configuration.
+ * These definitions may be used during configuration and are shared
+ * between Host and Target.
+ *
+ * Pipe Directions are relative to the Host, so PIPEDIR_IN means
+ * "coming IN over air through Target to Host" as with a WiFi Rx operation.
+ * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
+ * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
+ * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
+ * over the interconnect.
+ */
+typedef A_UINT32 PIPEDIR;
+#define PIPEDIR_NONE      0
+#define PIPEDIR_IN        1  /* Target-->Host, WiFi Rx direction */
+#define PIPEDIR_OUT       2  /* Host->Target, WiFi Tx direction */
+#define PIPEDIR_INOUT     3  /* bidirectional, target to target */
+#define PIPEDIR_INOUT_T2T PIPEDIR_INOUT
+#define PIPEDIR_INOUT_H2H 4  /* bidirectional, host to host */
+#define PIPEDIR_MATCH(d1, d2) (((PIPEDIR)(d1) & (PIPEDIR)(d2)) != 0)
+
+/* Establish a mapping between a service/direction and a pipe. */
+struct service_to_pipe {
+	A_UINT32 service_id;
+	A_UINT32 pipedir;
+	A_UINT32 pipenum;
+};
+
+#endif /*HTC_SERVICES_H_ */

fw/htt_common.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
  *
  * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
  *
@@ -35,43 +35,43 @@
 #define _HTT_COMMON_H_
 
 enum htt_sec_type {
-    htt_sec_type_none,
-    htt_sec_type_wep128,
-    htt_sec_type_wep104,
-    htt_sec_type_wep40,
-    htt_sec_type_tkip,
-    htt_sec_type_tkip_nomic,
-    htt_sec_type_aes_ccmp,
-    htt_sec_type_wapi,
-    htt_sec_type_aes_ccmp_256,
-    htt_sec_type_aes_gcmp,
-    htt_sec_type_aes_gcmp_256,
-
-    /* keep this last! */
-    htt_num_sec_types
+	htt_sec_type_none,
+	htt_sec_type_wep128,
+	htt_sec_type_wep104,
+	htt_sec_type_wep40,
+	htt_sec_type_tkip,
+	htt_sec_type_tkip_nomic,
+	htt_sec_type_aes_ccmp,
+	htt_sec_type_wapi,
+	htt_sec_type_aes_ccmp_256,
+	htt_sec_type_aes_gcmp,
+	htt_sec_type_aes_gcmp_256,
+
+	/* keep this last! */
+	htt_num_sec_types
 };
 
 enum htt_rx_ind_mpdu_status {
-    HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
-    HTT_RX_IND_MPDU_STATUS_OK,
-    HTT_RX_IND_MPDU_STATUS_ERR_FCS,
-    HTT_RX_IND_MPDU_STATUS_ERR_DUP,
-    HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
-    HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
-    HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER, /* only accept EAPOL frames */
-    HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
-    HTT_RX_IND_MPDU_STATUS_MGMT_CTRL, /* Non-data in promiscous mode */
-    HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
-    HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
-    HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
-    HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
-    HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
-
-    /*
-     * MISC: discard for unspecified reasons.
-     * Leave this enum value last.
-     */
-    HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
+	HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
+	HTT_RX_IND_MPDU_STATUS_OK,
+	HTT_RX_IND_MPDU_STATUS_ERR_FCS,
+	HTT_RX_IND_MPDU_STATUS_ERR_DUP,
+	HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
+	HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
+	HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,  /* only accept EAPOL frames */
+	HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
+	HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,    /* Non-data in promiscous mode */
+	HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
+	HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
+	HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
+	HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
+	HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
+
+	/*
+	 * MISC: discard for unspecified reasons.
+	 * Leave this enum value last.
+	 */
+	HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
 };
 
 #define HTT_INVALID_PEER    0xffff
@@ -103,18 +103,31 @@ enum htt_rx_ind_mpdu_status {
  * type rather than L2 header type.
  */
 enum htt_pkt_type {
-    htt_pkt_type_raw = 0,
-    htt_pkt_type_native_wifi = 1,
-    htt_pkt_type_ethernet = 2,
-    htt_pkt_type_mgmt = 3,
-    htt_pkt_type_eth2 = 4,
-
-    /* keep this last */
-    htt_pkt_num_types
+	htt_pkt_type_raw = 0,
+	htt_pkt_type_native_wifi = 1,
+	htt_pkt_type_ethernet = 2,
+	htt_pkt_type_mgmt = 3,
+	htt_pkt_type_eth2 = 4,
+
+	/* keep this last */
+	htt_pkt_num_types
 };
 
+/*
+ * TX MSDU ID partition -
+ * FW supports bigger MSDU ID partition which is defined as
+ * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
+ * When both host and FW support new partition, FW uses
+ * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN
+ * If host doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
+ * Handshaking is done through WMI_READY and WMI_INIT
+ */
 #define HTT_TX_HOST_MSDU_ID_SPACE_BEGIN 0
 #define HTT_TX_IPA_MSDU_ID_SPACE_BEGIN  3000
 #define TGT_RX2TX_MSDU_ID_SPACE_BEGIN 6000
+/* 8192 = 0xr2000 */
+#define HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN 8192
+/* 12288 = 0x3000 */
+#define TGT_RX2TX_NEW_MSDU_ID_SPACE_BEGIN  12288
 
 #endif /* _HTT_COMMON_H_ */

fw/htt_isoc.h

@@ -0,0 +1,1244 @@
+/*
+ * Copyright (c) 2012-2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+/**
+ * @file htt_isoc.h
+ *
+ * @details
+ *  This file defines the target --> host messages that configure the
+ *  host data-path SW with the information required for data transfers
+ *  to and from the target.
+ */
+
+#ifndef _HTT_ISOC_H_
+#define _HTT_ISOC_H_
+
+#include <a_types.h>    /* A_UINT32, A_UINT8 */
+#include <a_osapi.h>          /* A_COMPILE_TIME_ASSERT */
+
+#ifdef ATHR_WIN_NWF
+#pragma warning(disable:4214) /* bit field types other than int */
+#endif
+
+#include "htt_common.h"
+
+/*=== definitions that apply to all messages ================================*/
+
+typedef enum htt_isoc_t2h_msg_type {
+	/* 0x0 reserved for VERSION message (probably not needed) */
+
+	/* PEER_INFO - specify ID and parameters of a new peer */
+	HTT_ISOC_T2H_MSG_TYPE_PEER_INFO = 0x1,
+
+	/* PEER_UNMAP - deallocate the ID that refers to a peer */
+	HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP = 0x2,
+
+	/* ADDBA - start rx aggregation for the specified peer-TID */
+	HTT_ISOC_T2H_MSG_TYPE_RX_ADDBA = 0x3,
+
+	/* DELBA - stop rx aggregation for the specified peer-TID */
+	HTT_ISOC_T2H_MSG_TYPE_RX_DELBA = 0x4,
+
+	/* TX_COMPL_IND - over-the-air tx completion notification for a tx frame */
+	HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND = 0x5,
+
+	/* SEC_IND - notification of the type of security used for a new peer */
+	HTT_ISOC_T2H_MSG_TYPE_SEC_IND = 0x6,
+
+	/* PEER_TX_READY - the target is ready to transmit to a new peer */
+	HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY = 0x7,
+
+	/* RX_ERR - notification that an rx frame was discarded due to errors */
+	HTT_ISOC_T2H_MSG_TYPE_RX_ERR = 0x8,
+
+	/* NLO_MATCH - notification that target found NLO match */
+	HTT_ISOC_T2H_MSG_TYPE_NLO_MATCH     = 0x9,
+
+	/* NLO_SCAN_END - notification that target NLO SCAN END 1:1 map with  NLO_MATCH */
+	HTT_ISOC_T2H_MSG_TYPE_NLO_SCAN_END  = 0xA,
+	/* keep this last */
+	HTT_ISOC_T2H_NUM_MSGS
+} htt_isoc_t2h_msg_type;
+
+/*
+ * HTT ISOC target to host message type -
+ * stored in bits 7:0 of the first word of the message
+ */
+#define HTT_ISOC_T2H_MSG_TYPE_M      0xff
+#define HTT_ISOC_T2H_MSG_TYPE_S      0
+
+#define HTT_ISOC_T2H_MSG_TYPE_SET(msg_addr, msg_type) \
+	(*((A_UINT8 *) msg_addr) = (msg_type))
+#define HTT_ISOC_T2H_MSG_TYPE_GET(msg_addr) \
+	(*((A_UINT8 *) msg_addr))
+
+#ifndef INLINE
+#ifdef QCA_SUPPORT_INTEGRATED_SOC
+/* host SW */
+#define INLINE inline
+#else
+/* target FW */
+#define INLINE __inline
+#endif
+#define HTT_ISOC_INLINE_DEF
+#endif /* INLINE */
+
+static INLINE void
+htt_isoc_t2h_field_set(
+	A_UINT32 *msg_addr32,
+	unsigned offset32,
+	unsigned mask,
+	unsigned shift,
+	unsigned value)
+{
+	/* sanity check: make sure the value fits within the field */
+	/* qdf_assert(value << shift == (value << shift) | mask); */
+
+	msg_addr32 += offset32;
+	/* clear the field */
+	*msg_addr32 &= ~mask;
+	/* write the new value */
+	*msg_addr32 |= (value << shift);
+}
+
+#ifdef HTT_ISOC_INLINE_DEF
+#undef HTT_ISOC_INLINE_DEF
+#undef INLINE
+#endif
+
+#define HTT_ISOC_T2H_FIELD_GET(msg_addr32, offset32, mask, shift) \
+	(((*(msg_addr32 + offset32)) & mask) >> shift)
+
+typedef enum {
+	/* ASSOC - "real" peer from STA-AP association */
+	HTT_ISOC_T2H_PEER_TYPE_ASSOC = 0x0,
+
+	/* SELF - self-peer for unicast tx to unassociated peer */
+	HTT_ISOC_T2H_PEER_TYPE_SELF = 0x1,
+
+	/* BSSID - reserved for FW use for BT-AMP+IBSS */
+	HTT_ISOC_T2H_PEER_TYPE_BSSID = 0x2,
+
+	/* BCAST - self-peer for multicast / broadcast tx */
+	HTT_ISOC_T2H_PEER_TYPE_BCAST = 0x3
+} HTT_ISOC_T2H_PEER_TYPE_ENUM;
+
+enum {
+	HTT_ISOC_NON_QOS = 0,
+	HTT_ISOC_QOS = 1
+};
+
+enum {
+	HTT_ISOC_RMF_DISABLED = 0,
+	HTT_ISOC_RMF_ENABLED = 1
+};
+
+enum {
+	HTT_ISOC_TID_MGMT = 7
+};
+
+/*=== definitions for specific messages =====================================*/
+
+/*=== PEER_INFO message ===*/
+
+/**
+ * @brief target -> host peer info message definition
+ *
+ * @details
+ * The following diagram shows the format of the peer info message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31          25|24|23       18|17|16|15      11|10|9|8|7|6|            0|
+ * |-----------------------------------------------------------------------|
+ * |   mgmt DPU idx  |  bcast DPU idx  |     DPU idx     |     msg type    |
+ * |-----------------------------------------------------------------------|
+ * | mgmt DPU sig |bcast DPU sig |     DPU sig    |       peer ID          |
+ * |-----------------------------------------------------------------------|
+ * |    MAC addr 1   |    MAC addr 0   |     vdev ID     | |R|  peer type  |
+ * |-----------------------------------------------------------------------|
+ * |    MAC addr 5   |    MAC addr 4   |    MAC addr 3   |    MAC addr 2   |
+ * |-----------------------------------------------------------------------|
+ *
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as peer info message
+ *     Value: 0x1
+ *   - DPU_IDX
+ *     Bits 15:8
+ *     Purpose: specify the DPU index (a.k.a. security key ID) to use for
+ *         unicast data frames sent to this peer
+ *     Value: key ID
+ *   - BCAST_DPU_IDX
+ *     Bits 23:16
+ *     Purpose: specify the DPU index (a.k.a. security key ID) to use for
+ *         broadcast data frames sent by this (self) peer
+ *     Value: key ID
+ *   - MGMT_DPU_IDX
+ *     Bits 31:24
+ *     Purpose: specify the DPU index (a.k.a. security key ID) to use for
+ *         unicast management frames sent by this (self) peer
+ *     Value: key ID
+ * WORD 1:
+ *   - PEER_ID
+ *     Bits 10:0
+ *     Purpose: The ID that the target has allocated to refer to the peer
+ *   - DPU_SIG
+ *     Bits 17:11
+ *     Purpose: specify the DPU signature (a.k.a. security key validity
+ *         magic number) to specify for unicast data frames sent to this peer
+ *   - BCAST_DPU_SIG
+ *     Bits 24:18
+ *     Purpose: specify the DPU signature (a.k.a. security key validity
+ *         magic number) to specify for broadcast data frames sent by this
+ *         (self) peer
+ *   - MGMT_DPU_SIG
+ *     Bits 31:25
+ *     Purpose: specify the DPU signature (a.k.a. security key validity
+ *         magic number) to specify for unicast management frames sent by this
+ *         (self) peer
+ * WORD 2:
+ *   - PEER_TYPE
+ *     Bits 5:0
+ *     Purpose: specify whether the peer in question is a real peer or
+ *         one of the types of "self-peer" created for the vdev
+ *     Value: HTT_ISOC_T2H_PEER_TYPE enum
+ *   - RMF_ENABLED (R)
+ *     Bit 6
+ *     Purpose: specify whether the peer in question has enable robust
+ *         management frames, to encrypt certain managment frames
+ *     Value: HTT_ISOC_RMF enum
+ *     Value: HTT_ISOC_NON_QOS or HTT_ISOC_QOS
+ *   - VDEV_ID
+ *     Bits 15:8
+ *     Purpose: For a real peer, the vdev ID indicates which virtual device
+ *         the peer is associated with.  For a self-peer, the vdev ID shows
+ *         which virtual device the self-peer represents.
+ *   - MAC_ADDR_L16
+ *     Bits 31:16
+ *     Purpose: Identifies which peer the peer ID is for.
+ *     Value: lower 2 bytes of the peer's MAC address
+ *         For a self-peer, the peer's MAC address is the MAC address of the
+ *         vdev the self-peer represents.
+ * WORD 3:
+ *   - MAC_ADDR_U32
+ *     Bits 31:0
+ *     Purpose: Identifies which peer the peer ID is for.
+ *     Value: upper 4 bytes of the peer's MAC address
+ *         For a self-peer, the peer's MAC address is the MAC address of the
+ *         vdev the self-peer represents.
+ */
+typedef struct htt_isoc_t2h_peer_info_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_PEER_INFO */
+		 dpu_idx:8, bcast_dpu_idx:8, mgmt_dpu_idx:8;
+	/* word 1 */
+	A_UINT32 peer_id:11, dpu_sig:7, bcast_dpu_sig:7, mgmt_dpu_sig:7;
+	/* word 2 */
+	A_UINT32
+		peer_type:6, rmf_enabled:1, reserved0:1, vdev_id:8, mac_addr_l16:16;
+	/* word 3 */
+	A_UINT32 mac_addr_u32;
+} htt_isoc_t2h_peer_info_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_OFFSET32        0
+#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_M               0x0000ff00
+#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_S               8
+
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_OFFSET32  0
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M         0x00ff0000
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S         16
+
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_OFFSET32   0
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M          0xff000000
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_S          24
+
+/* word 1 */
+#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_OFFSET32        1
+#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_M               0x000007ff
+#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_S               0
+
+#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_OFFSET32        1
+#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M               0x0003f800
+#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_S               11
+
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_OFFSET32  1
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M         0x01fc0000
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_S         18
+
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_OFFSET32   1
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_M          0xfe000000
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_S          25
+
+/* word 2 */
+#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_OFFSET32      2
+#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_M             0x0000003f
+#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_S             0
+
+#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_OFFSET32    2
+#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_M           0x00000040
+#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_S           6
+
+#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_OFFSET32        2
+#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_M               0x0000ff00
+#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_S               8
+
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_OFFSET32   2
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_M          0xffff0000
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_S          16
+
+/* word 3 */
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_OFFSET32   3
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_M          0xffffffff
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_S          0
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_PEER_INFO_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					     \
+		((A_UINT32 *) msg_addr),				 \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _OFFSET32,		 \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _M,			 \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _S,			 \
+		value)
+
+#define HTT_ISOC_T2H_PEER_INFO_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				      \
+		((A_UINT32 *) msg_addr),			  \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _OFFSET32,	  \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _M,		  \
+		HTT_ISOC_T2H_PEER_INFO_ ## field ## _S)
+
+/* access macros for specific fields */
+
+#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(DPU_IDX, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_DPU_IDX_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_IDX, msg_addr)
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_S) \
+		<= ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(BCAST_DPU_IDX, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_IDX_GET(msg_addr) \
+	(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(BCAST_DPU_IDX, msg_addr))
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_M >> HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_S) \
+		<= ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MGMT_DPU_IDX, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_IDX_GET(msg_addr) \
+	(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MGMT_DPU_IDX, msg_addr))
+
+#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_PEER_ID_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(PEER_ID, msg_addr)
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_INFO_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_DPU_SIG_S)\
+		<= ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(DPU_SIG, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_DPU_SIG_GET(msg_addr) \
+	(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(DPU_SIG, msg_addr))
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_M >> HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_S)\
+		<= ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(BCAST_DPU_SIG, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_BCAST_DPU_SIG_GET(msg_addr) \
+	(A_UINT8)(HTT_ISOC_T2H_PEER_INFO_FIELD_GET(BCAST_DPU_SIG, msg_addr))
+
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MGMT_DPU_SIG, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_MGMT_DPU_SIG_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MGMT_DPU_SIG, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(PEER_TYPE, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_PEER_TYPE_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(PEER_TYPE, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_QOS_CAPABLE_SET(msg_addr, value)	\
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(QOS_CAPABLE, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_QOS_CAPABLE_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(QOS_CAPABLE, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_SET(msg_addr, value)	\
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(RMF_ENABLED, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_RMF_ENABLED_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(RMF_ENABLED, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(VDEV_ID, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_VDEV_ID_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(VDEV_ID, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MAC_ADDR_L16, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_L16_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MAC_ADDR_L16, msg_addr)
+
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_SET(MAC_ADDR_U32, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_INFO_MAC_ADDR_U32_GET(msg_addr) \
+	HTT_ISOC_T2H_PEER_INFO_FIELD_GET(MAC_ADDR_U32, msg_addr)
+
+/*=== PEER_UNMAP message ===*/
+
+/**
+ * @brief target -> host peer unmap message definition
+ *
+ * @details
+ * The following diagram shows the format of the peer unmap message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31                      19|18                       8|7               0|
+ * |-----------------------------------------------------------------------|
+ * |         reserved         |          peer ID         |     msg type    |
+ * |-----------------------------------------------------------------------|
+ *
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as peer unmap message
+ *     Value: 0x2
+ *   - PEER_ID
+ *     Bits 18:8
+ *     Purpose: The ID that the target has allocated to refer to the peer
+ */
+typedef struct htt_isoc_t2h_peer_unmap_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_PEER_UNMAP */
+		 peer_id:11, reserved0:13;
+} htt_isoc_t2h_peer_unmap_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_OFFSET32        0
+#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M               0x0007ff00
+#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S               8
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					      \
+		((A_UINT32 *) msg_addr),				  \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _OFFSET32,		  \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _M,		  \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _S,		  \
+		value)
+
+#define HTT_ISOC_T2H_PEER_UNMAP_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				       \
+		((A_UINT32 *) msg_addr),			   \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _OFFSET32,	   \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _M,	   \
+		HTT_ISOC_T2H_PEER_UNMAP_ ## field ## _S)
+
+/* access macros for specific fields */
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_M >> HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_S) \
+		< ((A_UINT16)~((A_UINT16)0)));
+#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_UNMAP_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_UNMAP_PEER_ID_GET(msg_addr) \
+	(A_UINT16)(HTT_ISOC_T2H_PEER_UNMAP_FIELD_GET(PEER_ID, msg_addr))
+
+/*=== ADDBA message ===*/
+enum {
+	htt_isoc_addba_success = 0,
+	/* TBD: use different failure values to specify failure causes? */
+	htt_isoc_addba_fail = 1,
+};
+
+/**
+ * @brief target -> host ADDBA message definition
+ *
+ * @details
+ * The following diagram shows the format of the rx ADDBA message sent
+ * from the target to the host:
+ *
+ * |31                      20|19  16|15     12|11    8|7               0|
+ * |---------------------------------------------------------------------|
+ * |          peer ID         |  TID |   window size   |     msg type    |
+ * |---------------------------------------------------------------------|
+ * |                  reserved                |S|      start seq num     |
+ * |---------------------------------------------------------------------|
+ *
+ * The following field definitions describe the format of the ADDBA
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as an ADDBA message
+ *     Value: 0x3
+ *   - WIN_SIZE
+ *     Bits 15:8
+ *     Purpose: Specifies the length of the block ack window (max = 64).
+ *     Value:
+ *         block ack window length specified by the received ADDBA
+ *         management message.
+ *   - TID
+ *     Bits 19:16
+ *     Purpose: Specifies which traffic identifier the ADDBA is for.
+ *     Value:
+ *         TID specified by the received ADDBA management message.
+ *   - PEER_ID
+ *     Bits 31:20
+ *     Purpose: Identifies which peer sent the ADDBA.
+ *     Value:
+ *         ID (hash value) used by the host for fast, direct lookup of
+ *         host SW peer info, including rx reorder states.
+ *   - START_SEQ_NUM
+ *     Bits 11:0
+ *     Purpose: Specifies the initial location of the block ack window
+ *     Value: start sequence value specified by the ADDBA-request message
+ *   - STATUS
+ *     Bit 12
+ *     Purpose: status of the WMI ADDBA request
+ *     Value: 0 - SUCCESS, 1 - FAILURE
+ */
+typedef struct htt_isoc_t2h_addba_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_ADDBA */
+		 win_size:8, tid:4, peer_id:12;
+	/* word 1 */
+	A_UINT32 start_seq_num:12, status:1, reserved0:19;
+} htt_isoc_t2h_addba_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_OFFSET32       0
+#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_M              0x0000ff00
+#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_S              8
+
+#define HTT_ISOC_T2H_ADDBA_TID_OFFSET32            0
+#define HTT_ISOC_T2H_ADDBA_TID_M                   0x000f0000
+#define HTT_ISOC_T2H_ADDBA_TID_S                   16
+
+#define HTT_ISOC_T2H_ADDBA_PEER_ID_OFFSET32        0
+#define HTT_ISOC_T2H_ADDBA_PEER_ID_M               0xfff00000
+#define HTT_ISOC_T2H_ADDBA_PEER_ID_S               20
+
+/* word 1 */
+#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_OFFSET32  1
+#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_M         0x00000fff
+#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_S         0
+
+#define HTT_ISOC_T2H_ADDBA_STATUS_OFFSET32         1
+#define HTT_ISOC_T2H_ADDBA_STATUS_M                0x00001000
+#define HTT_ISOC_T2H_ADDBA_STATUS_S                12
+
+/* general field access macros */
+#define HTT_ISOC_T2H_ADDBA_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					      \
+		((A_UINT32 *) msg_addr),				  \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _OFFSET32,	     \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _M,		     \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _S,		     \
+		value)
+
+#define HTT_ISOC_T2H_ADDBA_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				       \
+		((A_UINT32 *) msg_addr),			   \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _OFFSET32,    \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _M,	      \
+		HTT_ISOC_T2H_ADDBA_ ## field ## _S)
+
+/* access macros for specific fields */
+
+#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_SET(msg_addr, value) \
+	HTT_ISOC_T2H_ADDBA_FIELD_SET(WIN_SIZE, msg_addr, value)
+#define HTT_ISOC_T2H_ADDBA_WIN_SIZE_GET(msg_addr) \
+	HTT_ISOC_T2H_ADDBA_FIELD_GET(WIN_SIZE, msg_addr)
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_ADDBA_TID_M_Size_Check,
+	(HTT_ISOC_T2H_ADDBA_TID_M >> HTT_ISOC_T2H_ADDBA_TID_S) \
+		< ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_ADDBA_TID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_ADDBA_FIELD_SET(TID, msg_addr, value)
+#define HTT_ISOC_T2H_ADDBA_TID_GET(msg_addr) \
+	(A_UINT8)(HTT_ISOC_T2H_ADDBA_FIELD_GET(TID, msg_addr))
+
+#define HTT_ISOC_T2H_ADDBA_PEER_ID_SET(msg_addr, value)	\
+	HTT_ISOC_T2H_ADDBA_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_ADDBA_PEER_ID_GET(msg_addr) \
+	HTT_ISOC_T2H_ADDBA_FIELD_GET(PEER_ID, msg_addr)
+
+#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_SET(msg_addr, value) \
+	HTT_ISOC_T2H_ADDBA_FIELD_SET(START_SEQ_NUM, msg_addr, value)
+#define HTT_ISOC_T2H_ADDBA_START_SEQ_NUM_GET(msg_addr) \
+	HTT_ISOC_T2H_ADDBA_FIELD_GET(START_SEQ_NUM, msg_addr)
+
+#define HTT_ISOC_T2H_ADDBA_STATUS_SET(msg_addr, value) \
+	HTT_ISOC_T2H_ADDBA_FIELD_SET(STATUS, msg_addr, value)
+#define HTT_ISOC_T2H_ADDBA_STATUS_GET(msg_addr)	\
+	HTT_ISOC_T2H_ADDBA_FIELD_GET(STATUS, msg_addr)
+
+/*=== DELBA message ===*/
+
+/**
+ * @brief target -> host DELBA message definition
+ *
+ * @details
+ * The following diagram shows the format of the rx DELBA message sent
+ * from the target to the host:
+ *
+ * |31                      20|19  16|15     12|11    8|7               0|
+ * |---------------------------------------------------------------------|
+ * |          peer ID         |  TID |    reserved   |S|     msg type    |
+ * |---------------------------------------------------------------------|
+ *
+ * The following field definitions describe the format of the ADDBA
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as an DELBA message
+ *     Value: 0x4
+ *   - TID
+ *     Bits 19:16
+ *     Purpose: Specifies which traffic identifier the DELBA is for.
+ *     Value:
+ *         TID specified by the received DELBA management message.
+ *   - PEER_ID
+ *     Bits 31:20
+ *     Purpose: Identifies which peer sent the DELBA.
+ *     Value:
+ *         ID (hash value) used by the host for fast, direct lookup of
+ *         host SW peer info, including rx reorder states.
+ *   - STATUS
+ *     Bit 8
+ *     Purpose: status of the WMI DELBA request
+ *     Value: 0 - SUCCESS, 1 - FAILURE
+ */
+typedef struct htt_isoc_t2h_delba_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_DELBA */
+		 status:1, reserved0:7, tid:4, peer_id:12;
+} htt_isoc_t2h_delba_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_DELBA_TID_OFFSET32            0
+#define HTT_ISOC_T2H_DELBA_TID_M                   0x000f0000
+#define HTT_ISOC_T2H_DELBA_TID_S                   16
+
+#define HTT_ISOC_T2H_DELBA_PEER_ID_OFFSET32        0
+#define HTT_ISOC_T2H_DELBA_PEER_ID_M               0xfff00000
+#define HTT_ISOC_T2H_DELBA_PEER_ID_S               20
+
+#define HTT_ISOC_T2H_DELBA_STATUS_OFFSET32         0
+#define HTT_ISOC_T2H_DELBA_STATUS_M                0x00000100
+#define HTT_ISOC_T2H_DELBA_STATUS_S                8
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_DELBA_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					      \
+		((A_UINT32 *) msg_addr),				  \
+		HTT_ISOC_T2H_DELBA_ ## field ## _OFFSET32,	     \
+		HTT_ISOC_T2H_DELBA_ ## field ## _M,		     \
+		HTT_ISOC_T2H_DELBA_ ## field ## _S,		     \
+		value)
+
+#define HTT_ISOC_T2H_DELBA_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				       \
+		((A_UINT32 *) msg_addr),			   \
+		HTT_ISOC_T2H_DELBA_ ## field ## _OFFSET32,    \
+		HTT_ISOC_T2H_DELBA_ ## field ## _M,	      \
+		HTT_ISOC_T2H_DELBA_ ## field ## _S)
+
+/* access macros for specific fields */
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_DELBA_TID_M_Size_Check,
+	(HTT_ISOC_T2H_DELBA_TID_M >> HTT_ISOC_T2H_DELBA_TID_S) \
+		< ((A_UINT8)~((A_UINT8)0)));
+#define HTT_ISOC_T2H_DELBA_TID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_DELBA_FIELD_SET(TID, msg_addr, value)
+#define HTT_ISOC_T2H_DELBA_TID_GET(msg_addr) \
+	(A_UINT8)HTT_ISOC_T2H_DELBA_FIELD_GET(TID, msg_addr)
+
+#define HTT_ISOC_T2H_DELBA_PEER_ID_SET(msg_addr, value)	\
+	HTT_ISOC_T2H_DELBA_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_DELBA_PEER_ID_GET(msg_addr) \
+	HTT_ISOC_T2H_DELBA_FIELD_GET(PEER_ID, msg_addr)
+
+#define HTT_ISOC_T2H_DELBA_STATUS_SET(msg_addr, value) \
+	HTT_ISOC_T2H_DELBA_FIELD_SET(STATUS, msg_addr, value)
+#define HTT_ISOC_T2H_DELBA_STATUS_GET(msg_addr)	\
+	HTT_ISOC_T2H_DELBA_FIELD_GET(STATUS, msg_addr)
+
+/*=== SEC_IND message ===*/
+
+/**
+ * @brief target -> host Security indication message definition
+ *
+ * @details
+ * The following diagram shows the format of the SEC_IND message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31          25|24|23       18|17|16|15      11|10|9|8|7|6|            0|
+ * |-----------------------------------------------------------------------|
+ * |   is unicast    |  sec type       |     Peer id     |     msg type    |
+ * |-----------------------------------------------------------------------|
+ * |                    mic key1                                           |
+ * |-----------------------------------------------------------------------|
+ * |                    mic key2                                           |
+ * |-----------------------------------------------------------------------|
+ *
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as SEC_IND message
+ *     Value: 0x6
+ *   - PEER_ID
+ *     Bits 15:8
+ *     Purpose: The ID that the target has allocated to refer to the peer
+ *     Value: Peer ID
+ *   - SEC_TYPE
+ *     Bits 23:16
+ *     Purpose: specify the security encryption type
+ *     Value: htt_sec_type
+ *   - is unicast
+ *     Bits 31:24
+ *     Purpose: specify unicast/bcast
+ *     Value: 1-unicast/0-bcast
+ * WORD 1:
+ *   - MIC1
+ *     Bits 31:0
+ *     Purpose: Mickey1
+ * WORD 2:
+ *   - MIC2
+ *     Bits 31:0
+ *     Purpose: Mickey2
+ */
+typedef struct htt_isoc_t2h_sec_ind_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_SEC_IND */
+		 peer_id:8, sec_type:8, is_unicast:8;
+	/* word 1 */
+	A_UINT32 mic_key1;
+	/* word 2 */
+	A_UINT32 mic_key2;
+	/* word 3 */
+	A_UINT32 status;
+} htt_isoc_t2h_sec_ind_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_SEC_IND_PEER_ID_OFFSET32        0
+#define HTT_ISOC_T2H_SEC_IND_PEER_ID_M               0x0000ff00
+#define HTT_ISOC_T2H_SEC_IND_PEER_ID_S               8
+
+#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_OFFSET32       0
+#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_M              0x00ff0000
+#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_S              16
+
+#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_OFFSET32     0
+#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_M            0xff000000
+#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_S            24
+
+/* word 1 */
+#define HTT_ISOC_T2H_SEC_IND_MIC1_OFFSET32           1
+#define HTT_ISOC_T2H_SEC_IND_MIC1_M                  0xffffffff
+#define HTT_ISOC_T2H_SEC_IND_MIC1_S                  0
+
+/* word 2 */
+#define HTT_ISOC_T2H_SEC_IND_MIC2_OFFSET32           2
+#define HTT_ISOC_T2H_SEC_IND_MIC2_M                  0xffffffff
+#define HTT_ISOC_T2H_SEC_IND_MIC2_S                  0
+
+/* general field access macros */
+#define HTT_ISOC_T2H_SEC_IND_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					     \
+		((A_UINT32 *) msg_addr),				 \
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _OFFSET32,	       \
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _M,		       \
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _S,		       \
+		value)
+
+#define HTT_ISOC_T2H_SEC_IND_FIELD_GET(field, msg_addr)	\
+	HTT_ISOC_T2H_FIELD_GET(				      \
+		((A_UINT32 *) msg_addr),			  \
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _OFFSET32,	\
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _M,		\
+		HTT_ISOC_T2H_SEC_IND_ ## field ## _S)
+
+/* access macros for specific fields */
+#define HTT_ISOC_T2H_SEC_IND_PEER_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_SEC_IND_PEER_ID_GET(msg_addr) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_GET(PEER_ID, msg_addr)
+
+#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_SET(msg_addr, value) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_SET(SEC_TYPE, msg_addr, value)
+#define HTT_ISOC_T2H_SEC_IND_SEC_TYPE_GET(msg_addr) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_GET(SEC_TYPE, msg_addr)
+
+#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_SET(msg_addr, value) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_SET(IS_UNICAST, msg_addr, value)
+#define HTT_ISOC_T2H_SEC_IND_IS_UNICAST_GET(msg_addr) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_GET(IS_UNICAST, msg_addr)
+
+#define HTT_ISOC_T2H_SEC_IND_MIC1_SET(msg_addr, value) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_SET(MIC1, msg_addr, value)
+#define HTT_ISOC_T2H_SEC_IND_MIC1_GET(msg_addr)	\
+	HTT_ISOC_T2H_SEC_IND_FIELD_GET(MIC1, msg_addr)
+
+#define HTT_ISOC_T2H_SEC_IND_MIC2_SET(msg_addr, value) \
+	HTT_ISOC_T2H_SEC_IND_FIELD_SET(MIC2, msg_addr, value)
+#define HTT_ISOC_T2H_SEC_IND_MIC2_GET(msg_addr)	\
+	HTT_ISOC_T2H_SEC_IND_FIELD_GET(MIC2, msg_addr)
+
+/*=== PEER_TX_READY message ===*/
+
+/**
+ * @brief target -> host peer tx ready message definition
+ *
+ * @details
+ * The following diagram shows the format of the peer tx ready message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31                      19|18                       8|7               0|
+ * |-----------------------------------------------------------------------|
+ * |         reserved         |          peer ID         |     msg type    |
+ * |-----------------------------------------------------------------------|
+ *
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as peer tx ready message
+ *     Value: 0x7
+ *   - PEER_ID
+ *     Bits 18:8
+ *     Purpose: The ID assigned to the peer by the PEER_INFO message
+ */
+typedef struct htt_isoc_t2h_peer_tx_ready_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_PEER_TX_READY */
+		 peer_id:11, reserved0:13;
+} htt_isoc_t2h_peer_tx_ready_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_OFFSET32        0
+#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M               0x0007ff00
+#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S               8
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					      \
+		((A_UINT32 *) msg_addr),				  \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _OFFSET32,	     \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _M,		     \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _S,		     \
+		value)
+
+#define HTT_ISOC_T2H_PEER_TX_READY_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				       \
+		((A_UINT32 *) msg_addr),			   \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _OFFSET32,    \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _M,	      \
+		HTT_ISOC_T2H_PEER_TX_READY_ ## field ## _S)
+
+/* access macros for specific fields */
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M_Size_Check,
+	(HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_M >> \
+	HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_S) < ((A_UINT16)~((A_UINT16)0)));
+
+#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_PEER_TX_READY_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_PEER_TX_READY_PEER_ID_GET(msg_addr) \
+	((A_UINT16)(HTT_ISOC_T2H_PEER_TX_READY_FIELD_GET(PEER_ID, msg_addr)))
+
+
+/*=== RX_ERR message ===*/
+
+/**
+ * @brief target -> host rx error notification message definition
+ *
+ * @details
+ * The following diagram shows the format of the rx err message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31                               16|15              8|7|6|5|4       0|
+ * |---------------------------------------------------------------------|
+ * |               peer ID             |   rx err type   |    msg type   |
+ * |---------------------------------------------------------------------|
+ * |               reserved            |   rx err count  |M| r | ext TID |
+ * |---------------------------------------------------------------------|
+ * M = multicast
+ * r = reserved
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as an rx err message
+ *     Value: 0x8
+ *   - RX_ERR_TYPE
+ *     Bits 15:8
+ *     Purpose: specifies which type of rx error is being reported
+ *     Value: htt_rx_ind_mpdu_status enum
+ *   - PEER_ID
+ *     Bits 31:16
+ *     Purpose: specify which peer sent the frame that resulted in an error
+ * WORD 1:
+ *   - EXT_TID
+ *     Bits 4:0
+ *     Purpose: specifies which traffic type had the rx error
+ *     Value: 0-15 for a real TID value, 16 for non-QoS data, 31 for unknown
+ *   - MCAST
+ *     Bit 6
+ *     Purpose: specify whether the rx error frame was unicast or multicast
+ *     Value: 0 -> unicast, 1 -> multicast
+ *   - L2_HDR_IS_80211
+ *     Bit 7
+ *     Purpose: specifies whether the included L2 header (if present) is in
+ *         802.3 or 802.11 format
+ *     Value: 0 -> 802.3, 1 -> 802.11
+ *   - L2_HDR_BYTES
+ *     Bits 15:8
+ *     Purpose: Specify the size of the L2 header in this rx error report.
+ *     Value:
+ *         If no L2 header is included, this field shall be 0.
+ *         If a 802.3 + LLC/SNAP header is included, this field shall be
+ *         14 (ethernet header) + 8 (LLC/SNAP).
+ *         If a 802.11 header is included, this field shall be 24 bytes for
+ *         a basic header, or 26 bytes if a QoS control field is included,
+ *         or 30 bytes if a 4th address is included, or 32 bytes if a 4th
+ *         address and a QoS control field are included, etc.
+ *         Though the L2 header included in the message needs to include
+ *         padding up to a 4-byte boundary, this L2 header size field need
+ *         not account for the padding following the L2 header.
+ *   - SEC_HDR_BYTES
+ *     Bits 23:16
+ *     Purpose: Specify the size of the security encapsulation header in
+ *         this rx error report.
+ *     Value:
+ *         If no security header is included, this field shall be 0.
+ *         If a security header is included, this field depends on the
+ *         security type, which can be inferred from the rx error type.
+ *         For TKIP MIC errors, the security header could be any of:
+ *             8  - if IV / KeyID and Extended IV are included
+ *             16 - if MIC is also included
+ *             20 - if ICV is also included
+ *   - RX_ERR_CNT
+ *     Bits 31:24
+ *     Purpose: specifies how many rx errors are reported in this message
+ *     Value:
+ *         Rx error reports that include a L2 header and/or security header
+ *         will set this field to 1, to indicate that the error notification
+ *         is for a single frame.
+ *         Rx error reports that don't include a L2 header or security header
+ *         can use this field to send a single message to report multiple
+ *         erroneous rx frames.
+ */
+typedef struct htt_isoc_t2h_rx_err_s {
+	/* word 0 */
+	A_UINT32 msg_type:8,    /* HTT_ISOC_T2H_MSG_TYPE_RX_ERR */
+		 rx_err_type:8, peer_id:16;
+	/* word 1 */
+	A_UINT32
+		ext_tid:5,
+		reserved1:1,
+		mcast:1,
+		l2_hdr_is_80211:1, l2_hdr_bytes:8, sec_hdr_bytes:8, rx_err_cnt:8;
+	/* words 2 - M-1: L2 header */
+	/* words M - N: security header */
+} htt_isoc_t2h_rx_err_t;
+
+/* This needs to be exact bytes for structure htt_isoc_t2h_rx_err_t
+ *  * Since it is shared between host and FW, sizeof may not be used.
+ *  * */
+#define HTT_ISOC_T2H_RX_ERR_BASE_BYTES                20
+
+/* word 0 */
+#define HTT_ISOC_T2H_RX_ERR_TYPE_OFFSET32             0
+#define HTT_ISOC_T2H_RX_ERR_TYPE_M                    0x0000ff00
+#define HTT_ISOC_T2H_RX_ERR_TYPE_ID_S                 8
+
+#define HTT_ISOC_T2H_RX_ERR_PEER_ID_OFFSET32          0
+#define HTT_ISOC_T2H_RX_ERR_PEER_ID_M                 0xffff0000
+#define HTT_ISOC_T2H_RX_ERR_PEER_ID_S                 16
+
+/* word 1 */
+#define HTT_ISOC_T2H_RX_ERR_EXT_TID_OFFSET32          1
+#define HTT_ISOC_T2H_RX_ERR_EXT_TID_M                 0x0000001f
+#define HTT_ISOC_T2H_RX_ERR_EXT_TID_S                 0
+
+#define HTT_ISOC_T2H_RX_ERR_MCAST_OFFSET32            1
+#define HTT_ISOC_T2H_RX_ERR_MCAST_M                   0x00000040
+#define HTT_ISOC_T2H_RX_ERR_MCAST_S                   6
+
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_OFFSET32  1
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_M         0x00000080
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_S         7
+
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_OFFSET32     1
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_M            0x0000ff00
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_S            8
+
+#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_OFFSET32    1
+#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_M           0x00ff0000
+#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_S           16
+
+#define HTT_ISOC_T2H_RX_ERR_CNT_OFFSET32              1
+#define HTT_ISOC_T2H_RX_ERR_CNT_M                     0xff000000
+#define HTT_ISOC_T2H_RX_ERR_CNT_S                     24
+
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_RX_ERR_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(					      \
+		((A_UINT32 *) msg_addr),				  \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _OFFSET32,	      \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _M,		      \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _S,		      \
+		value)
+
+#define HTT_ISOC_T2H_RX_ERR_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(				       \
+		((A_UINT32 *) msg_addr),			   \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _OFFSET32,    \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _M,	       \
+		HTT_ISOC_T2H_RX_ERR_ ## field ## _S)
+
+/* access macros for specific fields */
+
+#define HTT_ISOC_T2H_RX_ERR_TYPE_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(TYPE, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_TYPE_GET(msg_addr) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(TYPE, msg_addr)
+
+A_COMPILE_TIME_ASSERT(HTT_ISOC_T2H_RX_ERR_PEER_ID_M_Size_Check,
+	(HTT_ISOC_T2H_RX_ERR_PEER_ID_M >> HTT_ISOC_T2H_RX_ERR_PEER_ID_S) \
+		<= ((A_UINT16)~((A_UINT16)0)));
+#define HTT_ISOC_T2H_RX_ERR_PEER_ID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(PEER_ID, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_PEER_ID_GET(msg_addr) \
+	((A_UINT16)HTT_ISOC_T2H_RX_ERR_FIELD_GET(PEER_ID, msg_addr))
+
+#define HTT_ISOC_T2H_RX_ERR_EXT_TID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(EXT_TID, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_EXT_TID_GET(msg_addr) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(EXT_TID, msg_addr)
+
+#define HTT_ISOC_T2H_RX_ERR_MCAST_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(MCAST, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_MCAST_GET(msg_addr)	\
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(MCAST, msg_addr)
+
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(L2_HDR_IS_80211, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_IS_80211_GET(msg_addr) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(L2_HDR_IS_80211, msg_addr)
+
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(L2_HDR_BYTES, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_L2_HDR_BYTES_GET(msg_addr) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(L2_HDR_BYTES, msg_addr)
+
+#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(SEC_HDR_BYTES, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_SEC_HDR_BYTES_GET(msg_addr)	\
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(SEC_HDR_BYTES, msg_addr)
+
+#define HTT_ISOC_T2H_RX_ERR_CNT_SET(msg_addr, value) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_SET(CNT, msg_addr, value)
+#define HTT_ISOC_T2H_RX_ERR_CNT_GET(msg_addr) \
+	HTT_ISOC_T2H_RX_ERR_FIELD_GET(CNT, msg_addr)
+
+/*=== TX OTA complete indication message ===*/
+
+/**
+ * @brief target -> tx complete indicate message
+ *
+ * @details
+ * The following diagram shows the format of the tx complete indication message sent
+ * from the target to the host.  This layout assumes the target operates
+ * as little-endian.
+ *
+ * |31                      19|18                       8|7               0|
+ * |-----------------------------------------------------------------------|
+ * |         reserved         |          status          |     msg type    |
+ * |-----------------------------------------------------------------------|
+ *
+ *
+ * The following field definitions describe the format of the peer info
+ * message sent from the target to the host.
+ *
+ * WORD 0:
+ *   - MSG_TYPE
+ *     Bits 7:0
+ *     Purpose: identifies this as tx complete indication message
+ *     Value: 0x7
+ *   - status
+ *     Bits 18:8
+ *     Purpose: TX completion status
+ */
+typedef struct htt_isoc_t2h_tx_compl_s {
+	/* word 0 */
+	A_UINT32
+	/* HTT_ISOC_T2H_MSG_TYPE_TX_COMPL_IND */
+	qmsg_type:8,
+	status:11,
+	reserved0:13;
+} htt_isoc_t2h_tx_compl_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_OFFSET32        0
+#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_M               0x0007ff00
+#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_S               8
+
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_TX_COMPL_IND_FIELD_SET(field, msg_addr, value) \
+	htt_isoc_t2h_field_set(                                       \
+	((A_UINT32 *) msg_addr),                                  \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _OFFSET32,           \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _M,                  \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _S,                  \
+	value)
+
+#define HTT_ISOC_T2H_TX_COMPL_IND_FIELD_GET(field, msg_addr) \
+	HTT_ISOC_T2H_FIELD_GET(                                \
+	((A_UINT32 *) msg_addr),                           \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _OFFSET32,    \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _M,           \
+	HTT_ISOC_T2H_TX_COMPL_IND_ ## field ## _S)
+
+/* access macros for specific fields */
+
+#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_SET(msg_addr, value) \
+	HTT_ISOC_T2H_TX_COMPL_IND_FIELD_SET(STATUS, msg_addr, value)
+#define HTT_ISOC_T2H_TX_COMPL_IND_STATUS_GET(msg_addr) \
+	HTT_ISOC_T2H_TX_COMPL_IND_FIELD_GET(STATUS, msg_addr)
+
+#define HTT_TX_COMPL_IND_STAT_OK          0
+#define HTT_TX_COMPL_IND_STAT_DISCARD     1
+#define HTT_TX_COMPL_IND_STAT_NO_ACK      2
+#define HTT_TX_COMPL_IND_STAT_POSTPONE    3
+
+/*=== NLO indication message ===*/
+
+/**
+* @brief target -> NLO indicate message
+*
+* @details
+* The following diagram shows the format of the NLO indication message sent
+* from the target to the host.  This layout assumes the target operates
+* as little-endian.
+*
+* |31                                                  8|7               0|
+* |-----------------------------------------------------------------------|
+* |                      reserved                       |     msg type    |
+* |-----------------------------------------------------------------------|
+*
+*
+* The following field definitions describe the format of NLO MATCH indication
+* message sent from the target to the host.
+*
+* WORD 0:
+*   - MSG_TYPE
+*     Bits 7:0
+*     Purpose: identifies this as NLO indication message
+*     Value: 0x9 - HTT_ISOC_T2H_MSG_TYPE_NLO_MATCH
+*     Value: 0xA - HTT_ISOC_T2H_MSG_TYPE_NLO_SCAN_END
+*/
+typedef struct htt_isoc_t2h_nlo_ind_s {
+	/* word 0 */
+	A_UINT32
+	msg_type:8,
+	vdev_id:8,
+	reserved0:16;
+} htt_isoc_t2h_nlo_ind_t;
+
+/* word 0 */
+#define HTT_ISOC_T2H_NLO_IND_VDEVID_OFFSET32            0
+#define HTT_ISOC_T2H_NLO_IND_VDEVID_M                   0x0000ff00
+#define HTT_ISOC_T2H_NLO_IND_VDEVID_S                   8
+
+
+/* general field access macros */
+
+#define HTT_ISOC_T2H_NLO_IND_FIELD_SET(field, msg_addr, value)  \
+	htt_isoc_t2h_field_set(                                     \
+	((A_UINT32 *) msg_addr),                                \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _OFFSET32,            \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _M,                   \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _S,                   \
+	value)
+
+#define HTT_ISOC_T2H_NLO_IND_FIELD_GET(field, msg_addr)     \
+	HTT_ISOC_T2H_FIELD_GET(                                 \
+	((A_UINT32 *) msg_addr),                            \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _OFFSET32,        \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _M,               \
+	HTT_ISOC_T2H_NLO_IND_ ## field ## _S)
+
+/* access macros for specific fields */
+
+#define HTT_ISOC_T2H_NLO_IND_VDEVID_SET(msg_addr, value) \
+	HTT_ISOC_T2H_NLO_IND_FIELD_SET(VDEVID, msg_addr, value)
+#define HTT_ISOC_T2H_NLO_IND_VDEVID_GET(msg_addr) \
+	HTT_ISOC_T2H_NLO_IND_FIELD_GET(VDEVID, msg_addr)
+
+
+#endif /* _HTT_ISOC_H_ */

fw/ip_prot.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _IP_PROT__H_
+#define _IP_PROT__H_
+
+#define IP_PROTOCOL_ICMP        0x01    /* Internet Control Message Protocol */
+#define IP_PROTOCOL_IGMP        0x02    /* Internet Group Management Protocol */
+#define IP_PROTOCOL_IPV4        0x04    /* IPv4 (encapsulation) */
+#define IP_PROTOCOL_TCP         0x06    /* Transmission Control Protocol */
+#define IP_PROTOCOL_UDP         0x11    /* User Datagram Protocol */
+#define IP_PROTOCOL_RDP         0x1B    /* Reliable Datagram Protocol */
+#define IP_PROTOCOL_IPV6        0x29    /* IPv6 (encapsulation) */
+#define IP_PROTOCOL_IPV6_ROUTE  0x2B    /* Routing Header for IPv6 */
+#define IP_PROTOCOL_IPV6_FRAG   0x2C    /* Fragment Header for IPv6 */
+#define IP_PROTOCOL_RSVP        0x2E    /* Resource Reservation Protocol */
+#define IP_PROTOCOL_GRE         0x2F    /* Generic Routing Encapsulation */
+#define IP_PROTOCOL_MHRP        0x30    /* Mobile Host Routing Protocol */
+#define IP_PROTOCOL_BNA         0x31    /* BNA */
+#define IP_PROTOCOL_ESP         0x32    /* Encapsulating Security Payload */
+#define IP_PROTOCOL_MOBILE      0x37    /* IP Mobility (Min Encap) */
+#define IP_PROTOCOL_IPV6_ICMP   0x3A    /* ICMP for IPv6 */
+#define IP_PROTOCOL_IPV6_NONXT  0x3B    /* No Next Header for IPv6 */
+#define IP_PROTOCOL_IPV6_OPTS   0x3C    /* Destination Options for IPv6 */
+#define IP_PROTOCOL_IPCOMP      0x6C    /* IP Payload Compression Protocol */
+#define IP_PROTOCOL_L2TP        0x73    /* Layer Two Tunneling Protocol Version 3 */
+#define IP_PROTOCOL_SMP         0x79    /* Simple Message Protocol */
+#define IP_PROTOCOL_SCTP        0x84    /* Stream Control Transmission Protocol */
+#define IP_PROTOCOL_SHIM6       0x8C    /* Site Multihoming by IPv6 Intermediation */
+
+/* IPv6 ICMP types */
+#define IPV6_ICMP_TYPE_MLD 0x8F
+
+#endif /* _IP_PROT__H_ */

fw/ipv4.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2012, 2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _IPV4__H_
+#define _IPV4__H_
+
+#if defined(ATH_TARGET)
+#include <osapi.h>              /* A_UINT8 */
+#else
+#include <a_types.h>            /* A_UINT8 */
+#endif
+
+#define IPV4_ADDR_LEN 4         /* bytes */
+struct ipv4_hdr_t {
+	A_UINT8 ver_hdrlen;     /* version and hdr length */
+	A_UINT8 tos;            /* type of service */
+	A_UINT8 len[2];         /* total length */
+	A_UINT8 id[2];
+	A_UINT8 flags_fragoff[2];       /* flags and fragment offset field */
+	A_UINT8 ttl;            /* time to live */
+	A_UINT8 protocol;
+	A_UINT8 hdr_checksum[2];
+	A_UINT8 src_addr[IPV4_ADDR_LEN];
+	A_UINT8 dst_addr[IPV4_ADDR_LEN];
+};
+
+#define IPV4_HDR_LEN (sizeof(struct ipv4_hdr_t))
+#define IPV4_HDR_OFFSET_PROTOCOL (offsetof(struct ipv4_hdr_t, protocol))
+#define IPV4_HDR_OFFSET_DST_ADDR (offsetof(struct ipv4_hdr_t, dst_addr[0]))
+
+#endif /* _IPV4__H_ */

fw/ol_fw_tx_dbg.h

@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2012, 2014-2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+/**
+ * @file ol_fw_tx_dbg.h
+ *
+ * @details data structs used for uploading summary info about the FW's tx
+ */
+
+#ifndef _OL_FW_TX_DBG__H_
+#define _OL_FW_TX_DBG__H_
+
+/*
+ * Undef ATH_SUPPORT_FW_TX_DBG to remove the FW tx debug feature.
+ * Removing the FW tx debug feature saves a modest amount of program memory.
+ * The data memory allocation for the FW tx debug feature is controlled
+ * by the host --> target resource configuration parameters; even if
+ * ATH_SUPPORT_FW_TX_DBG is defined, no data memory will be allocated for
+ * the FW tx debug log unless the host --> target resource configuration
+ * specifies it.
+ */
+#define ATH_SUPPORT_FW_TX_DBG 1 /* enabled */
+/* #undef ATH_SUPPORT_FW_TX_DBG / * disabled * / */
+
+#if defined(ATH_TARGET)
+#include <osapi.h>              /* A_UINT32 */
+#else
+#include <a_types.h>    /* A_UINT32 */
+#include <a_osapi.h>    /* PREPACK, POSTPACK */
+#endif
+
+enum ol_fw_tx_dbg_log_mode {
+	ol_fw_tx_dbg_log_mode_wraparound,       /* overwrite old data with new */
+	ol_fw_tx_dbg_log_mode_single,   /* fill log once, then stop */
+};
+
+/*
+ * tx PPDU stats upload message header
+ */
+struct ol_fw_tx_dbg_ppdu_msg_hdr {
+	/* word 0 */
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_WORD  0
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_S     0
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_BYTES_M     0x000000ff
+	A_UINT8 mpdu_bytes_array_len;   /* length of array of per-MPDU byte counts */
+
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_WORD  0
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_S     8
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MSDU_BYTES_M     0x0000ff00
+	A_UINT8 msdu_bytes_array_len;   /* length of array of per-MSDU byte counts */
+
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_WORD  0
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_S     16
+#define OL_FW_TX_DBG_PPDU_HDR_NUM_MPDU_MSDUS_M     0x00ff0000
+	A_UINT8 mpdu_msdus_array_len;   /* length of array of per-MPDU MSDU counts */
+
+	A_UINT8 reserved;
+
+	/* word 1 */
+#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_WORD  1
+#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_S     0
+#define OL_FW_TX_DBG_PPDU_HDR_MICROSEC_PER_TICK_M     0xffffffff
+	A_UINT32 microsec_per_tick;     /* conversion for timestamp entries */
+};
+
+/*
+ * tx PPDU log element / stats upload message element
+ */
+struct ol_fw_tx_dbg_ppdu_base {
+	/* word 0 - filled in during tx enqueue */
+#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_WORD    0
+#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_S     0
+#define OL_FW_TX_DBG_PPDU_START_SEQ_NUM_M     0x0000ffff
+	A_UINT16 start_seq_num;
+#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_WORD    0
+#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_S     16
+#define OL_FW_TX_DBG_PPDU_START_PN_LSBS_M     0xffff0000
+	A_UINT16 start_pn_lsbs;
+
+	/* word 1 - filled in during tx enqueue */
+#define OL_FW_TX_DBG_PPDU_NUM_BYTES_WORD        1
+#define OL_FW_TX_DBG_PPDU_NUM_BYTES_S         0
+#define OL_FW_TX_DBG_PPDU_NUM_BYTES_M         0xffffffff
+	A_UINT32 num_bytes;
+
+	/* word 2 - filled in during tx enqueue */
+#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_WORD        2
+#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_S         0
+#define OL_FW_TX_DBG_PPDU_NUM_MSDUS_M         0x000000ff
+	A_UINT8 num_msdus;
+#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_WORD        2
+#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_S         8
+#define OL_FW_TX_DBG_PPDU_NUM_MPDUS_M         0x0000ff00
+	A_UINT8 num_mpdus;
+	A_UINT16
+#define OL_FW_TX_DBG_PPDU_EXT_TID_WORD          2
+#define OL_FW_TX_DBG_PPDU_EXT_TID_S           16
+#define OL_FW_TX_DBG_PPDU_EXT_TID_M           0x001f0000
+	ext_tid : 5,
+#define OL_FW_TX_DBG_PPDU_PEER_ID_WORD          2
+#define OL_FW_TX_DBG_PPDU_PEER_ID_S           21
+#define OL_FW_TX_DBG_PPDU_PEER_ID_M           0xffe00000
+	peer_id : 11;
+
+	/* word 3 - filled in during tx enqueue */
+#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_WORD     3
+#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_S      0
+#define OL_FW_TX_DBG_PPDU_TIME_ENQUEUE_M      0xffffffff
+	A_UINT32 timestamp_enqueue;
+
+	/* word 4 - filled in during tx completion */
+#define OL_FW_TX_DBG_PPDU_TIME_COMPL_WORD       4
+#define OL_FW_TX_DBG_PPDU_TIME_COMPL_S        0
+#define OL_FW_TX_DBG_PPDU_TIME_COMPL_M        0xffffffff
+	A_UINT32 timestamp_completion;
+
+	/* word 5 - filled in during tx completion */
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_WORD   5
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_S    0
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_LSBS_M    0xffffffff
+	A_UINT32 block_ack_bitmap_lsbs;
+
+	/* word 6 - filled in during tx completion */
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_WORD   6
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_S    0
+#define OL_FW_TX_DBG_PPDU_BLOCK_ACK_MSBS_M    0xffffffff
+	A_UINT32 block_ack_bitmap_msbs;
+
+	/* word 7 - filled in during tx completion (enqueue would work too) */
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_WORD    7
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_S     0
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_LSBS_M     0xffffffff
+	A_UINT32 enqueued_bitmap_lsbs;
+
+	/* word 8 - filled in during tx completion (enqueue would work too) */
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_WORD    8
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_S     0
+#define OL_FW_TX_DBG_PPDU_ENQUEUED_MSBS_M     0xffffffff
+	A_UINT32 enqueued_bitmap_msbs;
+
+	/* word 9 - filled in during tx completion */
+#define OL_FW_TX_DBG_PPDU_RATE_CODE_WORD        9
+#define OL_FW_TX_DBG_PPDU_RATE_CODE_S         0
+#define OL_FW_TX_DBG_PPDU_RATE_CODE_M         0x000000ff
+	A_UINT8 rate_code;
+#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_WORD        9
+#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_S        8
+#define OL_FW_TX_DBG_PPDU_RATE_FLAGS_M        0x0000ff00
+	A_UINT8 rate_flags;     /* includes dynamic bandwidth info */
+#define OL_FW_TX_DBG_PPDU_TRIES_WORD            9
+#define OL_FW_TX_DBG_PPDU_TRIES_S             16
+#define OL_FW_TX_DBG_PPDU_TRIES_M             0x00ff0000
+	A_UINT8 tries;
+#define OL_FW_TX_DBG_PPDU_COMPLETE_WORD         9
+#define OL_FW_TX_DBG_PPDU_COMPLETE_S          24
+#define OL_FW_TX_DBG_PPDU_COMPLETE_M          0xff000000
+	A_UINT8 complete;
+};
+
+#endif /* _OL_FW_TX_DBG__H_ */

fw/rtc_soc_reg.h

@@ -0,0 +1,1966 @@
+/*
+ * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef _RTC_SOC_REG_REG_H_
+#define _RTC_SOC_REG_REG_H_
+
+#define SOC_RESET_CONTROL_ADDRESS                0x00000000
+#define SOC_RESET_CONTROL_OFFSET                 0x00000000
+#define SOC_RESET_CONTROL_SPI2_RST_MSB           30
+#define SOC_RESET_CONTROL_SPI2_RST_LSB           30
+#define SOC_RESET_CONTROL_SPI2_RST_MASK          0x40000000
+#define SOC_RESET_CONTROL_SPI2_RST_GET(x)        (((x) & SOC_RESET_CONTROL_SPI2_RST_MASK) >> SOC_RESET_CONTROL_SPI2_RST_LSB)
+#define SOC_RESET_CONTROL_SPI2_RST_SET(x)        (((x) << SOC_RESET_CONTROL_SPI2_RST_LSB) & SOC_RESET_CONTROL_SPI2_RST_MASK)
+#define SOC_RESET_CONTROL_I2S_1_RST_MSB          29
+#define SOC_RESET_CONTROL_I2S_1_RST_LSB          29
+#define SOC_RESET_CONTROL_I2S_1_RST_MASK         0x20000000
+#define SOC_RESET_CONTROL_I2S_1_RST_GET(x)       (((x) & SOC_RESET_CONTROL_I2S_1_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_RST_LSB)
+#define SOC_RESET_CONTROL_I2S_1_RST_SET(x)       (((x) << SOC_RESET_CONTROL_I2S_1_RST_LSB) & SOC_RESET_CONTROL_I2S_1_RST_MASK)
+#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MSB     28
+#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB     28
+#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK    0x10000000
+#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_GET(x)  (((x) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB)
+#define SOC_RESET_CONTROL_I2S_1_MBOX_RST_SET(x)  (((x) << SOC_RESET_CONTROL_I2S_1_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_1_MBOX_RST_MASK)
+#define SOC_RESET_CONTROL_I2C_SLAVE_RST_MSB      27
+#define SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB      27
+#define SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK     0x08000000
+#define SOC_RESET_CONTROL_I2C_SLAVE_RST_GET(x)   (((x) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK) >> SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB)
+#define SOC_RESET_CONTROL_I2C_SLAVE_RST_SET(x)   (((x) << SOC_RESET_CONTROL_I2C_SLAVE_RST_LSB) & SOC_RESET_CONTROL_I2C_SLAVE_RST_MASK)
+#define SOC_RESET_CONTROL_USB_PHY_ARST_MSB       26
+#define SOC_RESET_CONTROL_USB_PHY_ARST_LSB       26
+#define SOC_RESET_CONTROL_USB_PHY_ARST_MASK      0x04000000
+#define SOC_RESET_CONTROL_USB_PHY_ARST_GET(x)    (((x) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK) >> SOC_RESET_CONTROL_USB_PHY_ARST_LSB)
+#define SOC_RESET_CONTROL_USB_PHY_ARST_SET(x)    (((x) << SOC_RESET_CONTROL_USB_PHY_ARST_LSB) & SOC_RESET_CONTROL_USB_PHY_ARST_MASK)
+#define SOC_RESET_CONTROL_USB_PHY_RST_MSB        25
+#define SOC_RESET_CONTROL_USB_PHY_RST_LSB        25
+#define SOC_RESET_CONTROL_USB_PHY_RST_MASK       0x02000000
+#define SOC_RESET_CONTROL_USB_PHY_RST_GET(x)     (((x) & SOC_RESET_CONTROL_USB_PHY_RST_MASK) >> SOC_RESET_CONTROL_USB_PHY_RST_LSB)
+#define SOC_RESET_CONTROL_USB_PHY_RST_SET(x)     (((x) << SOC_RESET_CONTROL_USB_PHY_RST_LSB) & SOC_RESET_CONTROL_USB_PHY_RST_MASK)
+#define SOC_RESET_CONTROL_USB_RST_MSB            24
+#define SOC_RESET_CONTROL_USB_RST_LSB            24
+#define SOC_RESET_CONTROL_USB_RST_MASK           0x01000000
+#define SOC_RESET_CONTROL_USB_RST_GET(x)         (((x) & SOC_RESET_CONTROL_USB_RST_MASK) >> SOC_RESET_CONTROL_USB_RST_LSB)
+#define SOC_RESET_CONTROL_USB_RST_SET(x)         (((x) << SOC_RESET_CONTROL_USB_RST_LSB) & SOC_RESET_CONTROL_USB_RST_MASK)
+#define SOC_RESET_CONTROL_MMAC_RST_MSB           23
+#define SOC_RESET_CONTROL_MMAC_RST_LSB           23
+#define SOC_RESET_CONTROL_MMAC_RST_MASK          0x00800000
+#define SOC_RESET_CONTROL_MMAC_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MMAC_RST_MASK) >> SOC_RESET_CONTROL_MMAC_RST_LSB)
+#define SOC_RESET_CONTROL_MMAC_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MMAC_RST_LSB) & SOC_RESET_CONTROL_MMAC_RST_MASK)
+#define SOC_RESET_CONTROL_MDIO_RST_MSB           22
+#define SOC_RESET_CONTROL_MDIO_RST_LSB           22
+#define SOC_RESET_CONTROL_MDIO_RST_MASK          0x00400000
+#define SOC_RESET_CONTROL_MDIO_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MDIO_RST_MASK) >> SOC_RESET_CONTROL_MDIO_RST_LSB)
+#define SOC_RESET_CONTROL_MDIO_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MDIO_RST_LSB) & SOC_RESET_CONTROL_MDIO_RST_MASK)
+#define SOC_RESET_CONTROL_GE0_RST_MSB            21
+#define SOC_RESET_CONTROL_GE0_RST_LSB            21
+#define SOC_RESET_CONTROL_GE0_RST_MASK           0x00200000
+#define SOC_RESET_CONTROL_GE0_RST_GET(x)         (((x) & SOC_RESET_CONTROL_GE0_RST_MASK) >> SOC_RESET_CONTROL_GE0_RST_LSB)
+#define SOC_RESET_CONTROL_GE0_RST_SET(x)         (((x) << SOC_RESET_CONTROL_GE0_RST_LSB) & SOC_RESET_CONTROL_GE0_RST_MASK)
+#define SOC_RESET_CONTROL_I2S_RST_MSB            20
+#define SOC_RESET_CONTROL_I2S_RST_LSB            20
+#define SOC_RESET_CONTROL_I2S_RST_MASK           0x00100000
+#define SOC_RESET_CONTROL_I2S_RST_GET(x)         (((x) & SOC_RESET_CONTROL_I2S_RST_MASK) >> SOC_RESET_CONTROL_I2S_RST_LSB)
+#define SOC_RESET_CONTROL_I2S_RST_SET(x)         (((x) << SOC_RESET_CONTROL_I2S_RST_LSB) & SOC_RESET_CONTROL_I2S_RST_MASK)
+#define SOC_RESET_CONTROL_I2S_MBOX_RST_MSB       19
+#define SOC_RESET_CONTROL_I2S_MBOX_RST_LSB       19
+#define SOC_RESET_CONTROL_I2S_MBOX_RST_MASK      0x00080000
+#define SOC_RESET_CONTROL_I2S_MBOX_RST_GET(x)    (((x) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK) >> SOC_RESET_CONTROL_I2S_MBOX_RST_LSB)
+#define SOC_RESET_CONTROL_I2S_MBOX_RST_SET(x)    (((x) << SOC_RESET_CONTROL_I2S_MBOX_RST_LSB) & SOC_RESET_CONTROL_I2S_MBOX_RST_MASK)
+/* TODO: */
+#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MSB   18
+#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB   18
+#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK  0x00040000
+#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_GET(x) (((x) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK) >> SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB)
+#define SOC_RESET_CONTROL_CHECKSUM_ACC_RST_SET(x) (((x) << SOC_RESET_CONTROL_CHECKSUM_ACC_RST_LSB) & SOC_RESET_CONTROL_CHECKSUM_ACC_RST_MASK)
+#define SOC_RESET_CONTROL_CE_RST_MSB             18
+#define SOC_RESET_CONTROL_CE_RST_LSB             18
+#define SOC_RESET_CONTROL_CE_RST_MASK            0x00040000
+#define SOC_RESET_CONTROL_CE_RST_GET(x)          (((x) & SOC_RESET_CONTROL_CE_RST_MASK) >> SOC_RESET_CONTROL_CE_RST_LSB)
+#define SOC_RESET_CONTROL_CE_RST_SET(x)          (((x) << SOC_RESET_CONTROL_CE_RST_LSB) & SOC_RESET_CONTROL_CE_RST_MASK)
+#define SOC_RESET_CONTROL_UART2_RST_MSB          17
+#define SOC_RESET_CONTROL_UART2_RST_LSB          17
+#define SOC_RESET_CONTROL_UART2_RST_MASK         0x00020000
+#define SOC_RESET_CONTROL_UART2_RST_GET(x)       (((x) & SOC_RESET_CONTROL_UART2_RST_MASK) >> SOC_RESET_CONTROL_UART2_RST_LSB)
+#define SOC_RESET_CONTROL_UART2_RST_SET(x)       (((x) << SOC_RESET_CONTROL_UART2_RST_LSB) & SOC_RESET_CONTROL_UART2_RST_MASK)
+#define SOC_RESET_CONTROL_DEBUG_UART_RST_MSB     16
+#define SOC_RESET_CONTROL_DEBUG_UART_RST_LSB     16
+#define SOC_RESET_CONTROL_DEBUG_UART_RST_MASK    0x00010000
+#define SOC_RESET_CONTROL_DEBUG_UART_RST_GET(x)  (((x) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK) >> SOC_RESET_CONTROL_DEBUG_UART_RST_LSB)
+#define SOC_RESET_CONTROL_DEBUG_UART_RST_SET(x)  (((x) << SOC_RESET_CONTROL_DEBUG_UART_RST_LSB) & SOC_RESET_CONTROL_DEBUG_UART_RST_MASK)
+#define SOC_RESET_CONTROL_CPU_INIT_RESET_MSB     11
+#define SOC_RESET_CONTROL_CPU_INIT_RESET_LSB     11
+#define SOC_RESET_CONTROL_CPU_INIT_RESET_MASK    0x00000800
+#define SOC_RESET_CONTROL_CPU_INIT_RESET_GET(x)  (((x) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK) >> SOC_RESET_CONTROL_CPU_INIT_RESET_LSB)
+#define SOC_RESET_CONTROL_CPU_INIT_RESET_SET(x)  (((x) << SOC_RESET_CONTROL_CPU_INIT_RESET_LSB) & SOC_RESET_CONTROL_CPU_INIT_RESET_MASK)
+#define SOC_RESET_CONTROL_RST_OUT_MSB            9
+#define SOC_RESET_CONTROL_RST_OUT_LSB            9
+#define SOC_RESET_CONTROL_RST_OUT_MASK           0x00000200
+#define SOC_RESET_CONTROL_RST_OUT_GET(x)         (((x) & SOC_RESET_CONTROL_RST_OUT_MASK) >> SOC_RESET_CONTROL_RST_OUT_LSB)
+#define SOC_RESET_CONTROL_RST_OUT_SET(x)         (((x) << SOC_RESET_CONTROL_RST_OUT_LSB) & SOC_RESET_CONTROL_RST_OUT_MASK)
+#define SOC_RESET_CONTROL_COLD_RST_MSB           8
+#define SOC_RESET_CONTROL_COLD_RST_LSB           8
+#define SOC_RESET_CONTROL_COLD_RST_MASK          0x00000100
+#define SOC_RESET_CONTROL_COLD_RST_GET(x)        (((x) & SOC_RESET_CONTROL_COLD_RST_MASK) >> SOC_RESET_CONTROL_COLD_RST_LSB)
+#define SOC_RESET_CONTROL_COLD_RST_SET(x)        (((x) << SOC_RESET_CONTROL_COLD_RST_LSB) & SOC_RESET_CONTROL_COLD_RST_MASK)
+#define SOC_RESET_CONTROL_CPU_WARM_RST_MSB       6
+#define SOC_RESET_CONTROL_CPU_WARM_RST_LSB       6
+#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK      0x00000040
+#define SOC_RESET_CONTROL_CPU_WARM_RST_GET(x)    (((x) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK) >> SOC_RESET_CONTROL_CPU_WARM_RST_LSB)
+#define SOC_RESET_CONTROL_CPU_WARM_RST_SET(x)    (((x) << SOC_RESET_CONTROL_CPU_WARM_RST_LSB) & SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
+/* TODO: */
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MSB 2
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_GET(x) (((x) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK) >> SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB)
+#define SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_SET(x) (((x) << SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB) & SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK)
+#define SOC_RESET_CONTROL_MBOX_RST_MSB           2
+#define SOC_RESET_CONTROL_MBOX_RST_LSB           2
+#define SOC_RESET_CONTROL_MBOX_RST_MASK          0x00000004
+#define SOC_RESET_CONTROL_MBOX_RST_GET(x)        (((x) & SOC_RESET_CONTROL_MBOX_RST_MASK) >> SOC_RESET_CONTROL_MBOX_RST_LSB)
+#define SOC_RESET_CONTROL_MBOX_RST_SET(x)        (((x) << SOC_RESET_CONTROL_MBOX_RST_LSB) & SOC_RESET_CONTROL_MBOX_RST_MASK)
+#define SOC_RESET_CONTROL_UART_RST_MSB           1
+#define SOC_RESET_CONTROL_UART_RST_LSB           1
+#define SOC_RESET_CONTROL_UART_RST_MASK          0x00000002
+#define SOC_RESET_CONTROL_UART_RST_GET(x)        (((x) & SOC_RESET_CONTROL_UART_RST_MASK) >> SOC_RESET_CONTROL_UART_RST_LSB)
+#define SOC_RESET_CONTROL_UART_RST_SET(x)        (((x) << SOC_RESET_CONTROL_UART_RST_LSB) & SOC_RESET_CONTROL_UART_RST_MASK)
+#define SOC_RESET_CONTROL_SI0_RST_MSB            0
+#define SOC_RESET_CONTROL_SI0_RST_LSB            0
+#define SOC_RESET_CONTROL_SI0_RST_MASK           0x00000001
+#define SOC_RESET_CONTROL_SI0_RST_GET(x)         (((x) & SOC_RESET_CONTROL_SI0_RST_MASK) >> SOC_RESET_CONTROL_SI0_RST_LSB)
+#define SOC_RESET_CONTROL_SI0_RST_SET(x)         (((x) << SOC_RESET_CONTROL_SI0_RST_LSB) & SOC_RESET_CONTROL_SI0_RST_MASK)
+
+#define SOC_TCXO_DETECT_ADDRESS                  0x00000004
+#define SOC_TCXO_DETECT_OFFSET                   0x00000004
+#define SOC_TCXO_DETECT_PRESENT_MSB              0
+#define SOC_TCXO_DETECT_PRESENT_LSB              0
+#define SOC_TCXO_DETECT_PRESENT_MASK             0x00000001
+#define SOC_TCXO_DETECT_PRESENT_GET(x)           (((x) & SOC_TCXO_DETECT_PRESENT_MASK) >> SOC_TCXO_DETECT_PRESENT_LSB)
+#define SOC_TCXO_DETECT_PRESENT_SET(x)           (((x) << SOC_TCXO_DETECT_PRESENT_LSB) & SOC_TCXO_DETECT_PRESENT_MASK)
+
+#define SOC_XTAL_TEST_ADDRESS                    0x00000008
+#define SOC_XTAL_TEST_OFFSET                     0x00000008
+#define SOC_XTAL_TEST_NOTCXODET_MSB              0
+#define SOC_XTAL_TEST_NOTCXODET_LSB              0
+#define SOC_XTAL_TEST_NOTCXODET_MASK             0x00000001
+#define SOC_XTAL_TEST_NOTCXODET_GET(x)           (((x) & SOC_XTAL_TEST_NOTCXODET_MASK) >> SOC_XTAL_TEST_NOTCXODET_LSB)
+#define SOC_XTAL_TEST_NOTCXODET_SET(x)           (((x) << SOC_XTAL_TEST_NOTCXODET_LSB) & SOC_XTAL_TEST_NOTCXODET_MASK)
+
+#define SOC_CPU_CLOCK_ADDRESS                    0x00000020
+#define SOC_CPU_CLOCK_OFFSET                     0x00000020
+#define SOC_CPU_CLOCK_STANDARD_MSB               1
+#define SOC_CPU_CLOCK_STANDARD_LSB               0
+#define SOC_CPU_CLOCK_STANDARD_MASK              0x00000003
+#define SOC_CPU_CLOCK_STANDARD_GET(x)            (((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
+#define SOC_CPU_CLOCK_STANDARD_SET(x)            (((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
+
+#define SOC_CLOCK_CONTROL_ADDRESS                0x00000028
+#define SOC_CLOCK_CONTROL_OFFSET                 0x00000028
+#define SOC_CLOCK_CONTROL_USB_CLOCK_MSB          3
+#define SOC_CLOCK_CONTROL_USB_CLOCK_LSB          3
+#define SOC_CLOCK_CONTROL_USB_CLOCK_MASK         0x00000008
+#define SOC_CLOCK_CONTROL_USB_CLOCK_GET(x)       (((x) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK) >> SOC_CLOCK_CONTROL_USB_CLOCK_LSB)
+#define SOC_CLOCK_CONTROL_USB_CLOCK_SET(x)       (((x) << SOC_CLOCK_CONTROL_USB_CLOCK_LSB) & SOC_CLOCK_CONTROL_USB_CLOCK_MASK)
+#define SOC_CLOCK_CONTROL_LF_CLK32_MSB           2
+#define SOC_CLOCK_CONTROL_LF_CLK32_LSB           2
+#define SOC_CLOCK_CONTROL_LF_CLK32_MASK          0x00000004
+#define SOC_CLOCK_CONTROL_LF_CLK32_GET(x)        (((x) & SOC_CLOCK_CONTROL_LF_CLK32_MASK) >> SOC_CLOCK_CONTROL_LF_CLK32_LSB)
+#define SOC_CLOCK_CONTROL_LF_CLK32_SET(x)        (((x) << SOC_CLOCK_CONTROL_LF_CLK32_LSB) & SOC_CLOCK_CONTROL_LF_CLK32_MASK)
+#define SOC_CLOCK_CONTROL_SI0_CLK_MSB            0
+#define SOC_CLOCK_CONTROL_SI0_CLK_LSB            0
+#define SOC_CLOCK_CONTROL_SI0_CLK_MASK           0x00000001
+#define SOC_CLOCK_CONTROL_SI0_CLK_GET(x)         (((x) & SOC_CLOCK_CONTROL_SI0_CLK_MASK) >> SOC_CLOCK_CONTROL_SI0_CLK_LSB)
+#define SOC_CLOCK_CONTROL_SI0_CLK_SET(x)         (((x) << SOC_CLOCK_CONTROL_SI0_CLK_LSB) & SOC_CLOCK_CONTROL_SI0_CLK_MASK)
+
+#define SOC_WDT_CONTROL_ADDRESS                  0x00000030
+#define SOC_WDT_CONTROL_OFFSET                   0x00000030
+#define SOC_WDT_CONTROL_ACTION_MSB               2
+#define SOC_WDT_CONTROL_ACTION_LSB               0
+#define SOC_WDT_CONTROL_ACTION_MASK              0x00000007
+#define SOC_WDT_CONTROL_ACTION_GET(x)            (((x) & SOC_WDT_CONTROL_ACTION_MASK) >> SOC_WDT_CONTROL_ACTION_LSB)
+#define SOC_WDT_CONTROL_ACTION_SET(x)            (((x) << SOC_WDT_CONTROL_ACTION_LSB) & SOC_WDT_CONTROL_ACTION_MASK)
+
+#define SOC_WDT_STATUS_ADDRESS                   0x00000034
+#define SOC_WDT_STATUS_OFFSET                    0x00000034
+#define SOC_WDT_STATUS_INTERRUPT_MSB             0
+#define SOC_WDT_STATUS_INTERRUPT_LSB             0
+#define SOC_WDT_STATUS_INTERRUPT_MASK            0x00000001
+#define SOC_WDT_STATUS_INTERRUPT_GET(x)          (((x) & SOC_WDT_STATUS_INTERRUPT_MASK) >> SOC_WDT_STATUS_INTERRUPT_LSB)
+#define SOC_WDT_STATUS_INTERRUPT_SET(x)          (((x) << SOC_WDT_STATUS_INTERRUPT_LSB) & SOC_WDT_STATUS_INTERRUPT_MASK)
+
+#define SOC_WDT_ADDRESS                          0x00000038
+#define SOC_WDT_OFFSET                           0x00000038
+#define SOC_WDT_TARGET_MSB                       21
+#define SOC_WDT_TARGET_LSB                       0
+#define SOC_WDT_TARGET_MASK                      0x003fffff
+#define SOC_WDT_TARGET_GET(x)                    (((x) & SOC_WDT_TARGET_MASK) >> SOC_WDT_TARGET_LSB)
+#define SOC_WDT_TARGET_SET(x)                    (((x) << SOC_WDT_TARGET_LSB) & SOC_WDT_TARGET_MASK)
+
+#define SOC_WDT_COUNT_ADDRESS                    0x0000003c
+#define SOC_WDT_COUNT_OFFSET                     0x0000003c
+#define SOC_WDT_COUNT_VALUE_MSB                  21
+#define SOC_WDT_COUNT_VALUE_LSB                  0
+#define SOC_WDT_COUNT_VALUE_MASK                 0x003fffff
+#define SOC_WDT_COUNT_VALUE_GET(x)               (((x) & SOC_WDT_COUNT_VALUE_MASK) >> SOC_WDT_COUNT_VALUE_LSB)
+#define SOC_WDT_COUNT_VALUE_SET(x)               (((x) << SOC_WDT_COUNT_VALUE_LSB) & SOC_WDT_COUNT_VALUE_MASK)
+
+#define SOC_WDT_RESET_ADDRESS                    0x00000040
+#define SOC_WDT_RESET_OFFSET                     0x00000040
+#define SOC_WDT_RESET_VALUE_MSB                  0
+#define SOC_WDT_RESET_VALUE_LSB                  0
+#define SOC_WDT_RESET_VALUE_MASK                 0x00000001
+#define SOC_WDT_RESET_VALUE_GET(x)               (((x) & SOC_WDT_RESET_VALUE_MASK) >> SOC_WDT_RESET_VALUE_LSB)
+#define SOC_WDT_RESET_VALUE_SET(x)               (((x) << SOC_WDT_RESET_VALUE_LSB) & SOC_WDT_RESET_VALUE_MASK)
+
+#define SOC_INT_STATUS_ADDRESS                   0x00000044
+#define SOC_INT_STATUS_OFFSET                    0x00000044
+#define SOC_INT_STATUS_MAC_4_MSB                 23
+#define SOC_INT_STATUS_MAC_4_LSB                 23
+#define SOC_INT_STATUS_MAC_4_MASK                0x00800000
+#define SOC_INT_STATUS_MAC_4_GET(x)              (((x) & SOC_INT_STATUS_MAC_4_MASK) >> SOC_INT_STATUS_MAC_4_LSB)
+#define SOC_INT_STATUS_MAC_4_SET(x)              (((x) << SOC_INT_STATUS_MAC_4_LSB) & SOC_INT_STATUS_MAC_4_MASK)
+#define SOC_INT_STATUS_MAC_3_MSB                 22
+#define SOC_INT_STATUS_MAC_3_LSB                 22
+#define SOC_INT_STATUS_MAC_3_MASK                0x00400000
+#define SOC_INT_STATUS_MAC_3_GET(x)              (((x) & SOC_INT_STATUS_MAC_3_MASK) >> SOC_INT_STATUS_MAC_3_LSB)
+#define SOC_INT_STATUS_MAC_3_SET(x)              (((x) << SOC_INT_STATUS_MAC_3_LSB) & SOC_INT_STATUS_MAC_3_MASK)
+#define SOC_INT_STATUS_MAC_2_MSB                 21
+#define SOC_INT_STATUS_MAC_2_LSB                 21
+#define SOC_INT_STATUS_MAC_2_MASK                0x00200000
+#define SOC_INT_STATUS_MAC_2_GET(x)              (((x) & SOC_INT_STATUS_MAC_2_MASK) >> SOC_INT_STATUS_MAC_2_LSB)
+#define SOC_INT_STATUS_MAC_2_SET(x)              (((x) << SOC_INT_STATUS_MAC_2_LSB) & SOC_INT_STATUS_MAC_2_MASK)
+#define SOC_INT_STATUS_MAC_1_MSB                 20
+#define SOC_INT_STATUS_MAC_1_LSB                 20
+#define SOC_INT_STATUS_MAC_1_MASK                0x00100000
+#define SOC_INT_STATUS_MAC_1_GET(x)              (((x) & SOC_INT_STATUS_MAC_1_MASK) >> SOC_INT_STATUS_MAC_1_LSB)
+#define SOC_INT_STATUS_MAC_1_SET(x)              (((x) << SOC_INT_STATUS_MAC_1_LSB) & SOC_INT_STATUS_MAC_1_MASK)
+#define SOC_INT_STATUS_USBDMA_MSB                19
+#define SOC_INT_STATUS_USBDMA_LSB                19
+#define SOC_INT_STATUS_USBDMA_MASK               0x00080000
+#define SOC_INT_STATUS_USBDMA_GET(x)             (((x) & SOC_INT_STATUS_USBDMA_MASK) >> SOC_INT_STATUS_USBDMA_LSB)
+#define SOC_INT_STATUS_USBDMA_SET(x)             (((x) << SOC_INT_STATUS_USBDMA_LSB) & SOC_INT_STATUS_USBDMA_MASK)
+#define SOC_INT_STATUS_USBIP_MSB                 18
+#define SOC_INT_STATUS_USBIP_LSB                 18
+#define SOC_INT_STATUS_USBIP_MASK                0x00040000
+#define SOC_INT_STATUS_USBIP_GET(x)              (((x) & SOC_INT_STATUS_USBIP_MASK) >> SOC_INT_STATUS_USBIP_LSB)
+#define SOC_INT_STATUS_USBIP_SET(x)              (((x) << SOC_INT_STATUS_USBIP_LSB) & SOC_INT_STATUS_USBIP_MASK)
+#define SOC_INT_STATUS_THERM_MSB                 17
+#define SOC_INT_STATUS_THERM_LSB                 17
+#define SOC_INT_STATUS_THERM_MASK                0x00020000
+#define SOC_INT_STATUS_THERM_GET(x)              (((x) & SOC_INT_STATUS_THERM_MASK) >> SOC_INT_STATUS_THERM_LSB)
+#define SOC_INT_STATUS_THERM_SET(x)              (((x) << SOC_INT_STATUS_THERM_LSB) & SOC_INT_STATUS_THERM_MASK)
+#define SOC_INT_STATUS_EFUSE_OVERWRITE_MSB       16
+#define SOC_INT_STATUS_EFUSE_OVERWRITE_LSB       16
+#define SOC_INT_STATUS_EFUSE_OVERWRITE_MASK      0x00010000
+#define SOC_INT_STATUS_EFUSE_OVERWRITE_GET(x)    (((x) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK) >> SOC_INT_STATUS_EFUSE_OVERWRITE_LSB)
+#define SOC_INT_STATUS_EFUSE_OVERWRITE_SET(x)    (((x) << SOC_INT_STATUS_EFUSE_OVERWRITE_LSB) & SOC_INT_STATUS_EFUSE_OVERWRITE_MASK)
+#define SOC_INT_STATUS_RDMA_MSB                  15
+#define SOC_INT_STATUS_RDMA_LSB                  15
+#define SOC_INT_STATUS_RDMA_MASK                 0x00008000
+#define SOC_INT_STATUS_RDMA_GET(x)               (((x) & SOC_INT_STATUS_RDMA_MASK) >> SOC_INT_STATUS_RDMA_LSB)
+#define SOC_INT_STATUS_RDMA_SET(x)               (((x) << SOC_INT_STATUS_RDMA_LSB) & SOC_INT_STATUS_RDMA_MASK)
+#define SOC_INT_STATUS_BTCOEX_MSB                14
+#define SOC_INT_STATUS_BTCOEX_LSB                14
+#define SOC_INT_STATUS_BTCOEX_MASK               0x00004000
+#define SOC_INT_STATUS_BTCOEX_GET(x)             (((x) & SOC_INT_STATUS_BTCOEX_MASK) >> SOC_INT_STATUS_BTCOEX_LSB)
+#define SOC_INT_STATUS_BTCOEX_SET(x)             (((x) << SOC_INT_STATUS_BTCOEX_LSB) & SOC_INT_STATUS_BTCOEX_MASK)
+#define SOC_INT_STATUS_RTC_POWER_MSB             13
+#define SOC_INT_STATUS_RTC_POWER_LSB             13
+#define SOC_INT_STATUS_RTC_POWER_MASK            0x00002000
+#define SOC_INT_STATUS_RTC_POWER_GET(x)          (((x) & SOC_INT_STATUS_RTC_POWER_MASK) >> SOC_INT_STATUS_RTC_POWER_LSB)
+#define SOC_INT_STATUS_RTC_POWER_SET(x)          (((x) << SOC_INT_STATUS_RTC_POWER_LSB) & SOC_INT_STATUS_RTC_POWER_MASK)
+#define SOC_INT_STATUS_MAC_MSB                   12
+#define SOC_INT_STATUS_MAC_LSB                   12
+#define SOC_INT_STATUS_MAC_MASK                  0x00001000
+#define SOC_INT_STATUS_MAC_GET(x)                (((x) & SOC_INT_STATUS_MAC_MASK) >> SOC_INT_STATUS_MAC_LSB)
+#define SOC_INT_STATUS_MAC_SET(x)                (((x) << SOC_INT_STATUS_MAC_LSB) & SOC_INT_STATUS_MAC_MASK)
+#define SOC_INT_STATUS_MAILBOX_MSB               11
+#define SOC_INT_STATUS_MAILBOX_LSB               11
+#define SOC_INT_STATUS_MAILBOX_MASK              0x00000800
+#define SOC_INT_STATUS_MAILBOX_GET(x)            (((x) & SOC_INT_STATUS_MAILBOX_MASK) >> SOC_INT_STATUS_MAILBOX_LSB)
+#define SOC_INT_STATUS_MAILBOX_SET(x)            (((x) << SOC_INT_STATUS_MAILBOX_LSB) & SOC_INT_STATUS_MAILBOX_MASK)
+#define SOC_INT_STATUS_RTC_ALARM_MSB             10
+#define SOC_INT_STATUS_RTC_ALARM_LSB             10
+#define SOC_INT_STATUS_RTC_ALARM_MASK            0x00000400
+#define SOC_INT_STATUS_RTC_ALARM_GET(x)          (((x) & SOC_INT_STATUS_RTC_ALARM_MASK) >> SOC_INT_STATUS_RTC_ALARM_LSB)
+#define SOC_INT_STATUS_RTC_ALARM_SET(x)          (((x) << SOC_INT_STATUS_RTC_ALARM_LSB) & SOC_INT_STATUS_RTC_ALARM_MASK)
+#define SOC_INT_STATUS_HF_TIMER_MSB              9
+#define SOC_INT_STATUS_HF_TIMER_LSB              9
+#define SOC_INT_STATUS_HF_TIMER_MASK             0x00000200
+#define SOC_INT_STATUS_HF_TIMER_GET(x)           (((x) & SOC_INT_STATUS_HF_TIMER_MASK) >> SOC_INT_STATUS_HF_TIMER_LSB)
+#define SOC_INT_STATUS_HF_TIMER_SET(x)           (((x) << SOC_INT_STATUS_HF_TIMER_LSB) & SOC_INT_STATUS_HF_TIMER_MASK)
+#define SOC_INT_STATUS_LF_TIMER3_MSB             8
+#define SOC_INT_STATUS_LF_TIMER3_LSB             8
+#define SOC_INT_STATUS_LF_TIMER3_MASK            0x00000100
+#define SOC_INT_STATUS_LF_TIMER3_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER3_MASK) >> SOC_INT_STATUS_LF_TIMER3_LSB)
+#define SOC_INT_STATUS_LF_TIMER3_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER3_LSB) & SOC_INT_STATUS_LF_TIMER3_MASK)
+#define SOC_INT_STATUS_LF_TIMER2_MSB             7
+#define SOC_INT_STATUS_LF_TIMER2_LSB             7
+#define SOC_INT_STATUS_LF_TIMER2_MASK            0x00000080
+#define SOC_INT_STATUS_LF_TIMER2_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER2_MASK) >> SOC_INT_STATUS_LF_TIMER2_LSB)
+#define SOC_INT_STATUS_LF_TIMER2_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER2_LSB) & SOC_INT_STATUS_LF_TIMER2_MASK)
+#define SOC_INT_STATUS_LF_TIMER1_MSB             6
+#define SOC_INT_STATUS_LF_TIMER1_LSB             6
+#define SOC_INT_STATUS_LF_TIMER1_MASK            0x00000040
+#define SOC_INT_STATUS_LF_TIMER1_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER1_MASK) >> SOC_INT_STATUS_LF_TIMER1_LSB)
+#define SOC_INT_STATUS_LF_TIMER1_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER1_LSB) & SOC_INT_STATUS_LF_TIMER1_MASK)
+#define SOC_INT_STATUS_LF_TIMER0_MSB             5
+#define SOC_INT_STATUS_LF_TIMER0_LSB             5
+#define SOC_INT_STATUS_LF_TIMER0_MASK            0x00000020
+#define SOC_INT_STATUS_LF_TIMER0_GET(x)          (((x) & SOC_INT_STATUS_LF_TIMER0_MASK) >> SOC_INT_STATUS_LF_TIMER0_LSB)
+#define SOC_INT_STATUS_LF_TIMER0_SET(x)          (((x) << SOC_INT_STATUS_LF_TIMER0_LSB) & SOC_INT_STATUS_LF_TIMER0_MASK)
+#define SOC_INT_STATUS_SI_MSB                    4
+#define SOC_INT_STATUS_SI_LSB                    4
+#define SOC_INT_STATUS_SI_MASK                   0x00000010
+#define SOC_INT_STATUS_SI_GET(x)                 (((x) & SOC_INT_STATUS_SI_MASK) >> SOC_INT_STATUS_SI_LSB)
+#define SOC_INT_STATUS_SI_SET(x)                 (((x) << SOC_INT_STATUS_SI_LSB) & SOC_INT_STATUS_SI_MASK)
+#define SOC_INT_STATUS_GPIO_MSB                  3
+#define SOC_INT_STATUS_GPIO_LSB                  3
+#define SOC_INT_STATUS_GPIO_MASK                 0x00000008
+#define SOC_INT_STATUS_GPIO_GET(x)               (((x) & SOC_INT_STATUS_GPIO_MASK) >> SOC_INT_STATUS_GPIO_LSB)
+#define SOC_INT_STATUS_GPIO_SET(x)               (((x) << SOC_INT_STATUS_GPIO_LSB) & SOC_INT_STATUS_GPIO_MASK)
+#define SOC_INT_STATUS_DEBUG_UART_MSB            2
+#define SOC_INT_STATUS_DEBUG_UART_LSB            2
+#define SOC_INT_STATUS_DEBUG_UART_MASK           0x00000004
+#define SOC_INT_STATUS_DEBUG_UART_GET(x)         (((x) & SOC_INT_STATUS_DEBUG_UART_MASK) >> SOC_INT_STATUS_DEBUG_UART_LSB)
+#define SOC_INT_STATUS_DEBUG_UART_SET(x)         (((x) << SOC_INT_STATUS_DEBUG_UART_LSB) & SOC_INT_STATUS_DEBUG_UART_MASK)
+#define SOC_INT_STATUS_ERROR_MSB                 1
+#define SOC_INT_STATUS_ERROR_LSB                 1
+#define SOC_INT_STATUS_ERROR_MASK                0x00000002
+#define SOC_INT_STATUS_ERROR_GET(x)              (((x) & SOC_INT_STATUS_ERROR_MASK) >> SOC_INT_STATUS_ERROR_LSB)
+#define SOC_INT_STATUS_ERROR_SET(x)              (((x) << SOC_INT_STATUS_ERROR_LSB) & SOC_INT_STATUS_ERROR_MASK)
+#define SOC_INT_STATUS_WDT_INT_MSB               0
+#define SOC_INT_STATUS_WDT_INT_LSB               0
+#define SOC_INT_STATUS_WDT_INT_MASK              0x00000001
+#define SOC_INT_STATUS_WDT_INT_GET(x)            (((x) & SOC_INT_STATUS_WDT_INT_MASK) >> SOC_INT_STATUS_WDT_INT_LSB)
+#define SOC_INT_STATUS_WDT_INT_SET(x)            (((x) << SOC_INT_STATUS_WDT_INT_LSB) & SOC_INT_STATUS_WDT_INT_MASK)
+
+#define SOC_LF_TIMER0_ADDRESS                    0x00000048
+#define SOC_LF_TIMER0_OFFSET                     0x00000048
+#define SOC_LF_TIMER0_TARGET_MSB                 31
+#define SOC_LF_TIMER0_TARGET_LSB                 0
+#define SOC_LF_TIMER0_TARGET_MASK                0xffffffff
+#define SOC_LF_TIMER0_TARGET_GET(x)              (((x) & SOC_LF_TIMER0_TARGET_MASK) >> SOC_LF_TIMER0_TARGET_LSB)
+#define SOC_LF_TIMER0_TARGET_SET(x)              (((x) << SOC_LF_TIMER0_TARGET_LSB) & SOC_LF_TIMER0_TARGET_MASK)
+
+#define SOC_LF_TIMER_COUNT0_ADDRESS              0x0000004c
+#define SOC_LF_TIMER_COUNT0_OFFSET               0x0000004c
+#define SOC_LF_TIMER_COUNT0_VALUE_MSB            31
+#define SOC_LF_TIMER_COUNT0_VALUE_LSB            0
+#define SOC_LF_TIMER_COUNT0_VALUE_MASK           0xffffffff
+#define SOC_LF_TIMER_COUNT0_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT0_VALUE_MASK) >> SOC_LF_TIMER_COUNT0_VALUE_LSB)
+#define SOC_LF_TIMER_COUNT0_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT0_VALUE_LSB) & SOC_LF_TIMER_COUNT0_VALUE_MASK)
+
+#define SOC_LF_TIMER_CONTROL0_ADDRESS            0x00000050
+#define SOC_LF_TIMER_CONTROL0_OFFSET             0x00000050
+#define SOC_LF_TIMER_CONTROL0_ENABLE_MSB         2
+#define SOC_LF_TIMER_CONTROL0_ENABLE_LSB         2
+#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK        0x00000004
+#define SOC_LF_TIMER_CONTROL0_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL0_ENABLE_LSB)
+#define SOC_LF_TIMER_CONTROL0_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL0_ENABLE_LSB) & SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
+#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MSB   1
+#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB   1
+#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK  0x00000002
+#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
+#define SOC_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
+#define SOC_LF_TIMER_CONTROL0_RESET_MSB          0
+#define SOC_LF_TIMER_CONTROL0_RESET_LSB          0
+#define SOC_LF_TIMER_CONTROL0_RESET_MASK         0x00000001
+#define SOC_LF_TIMER_CONTROL0_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL0_RESET_MASK) >> SOC_LF_TIMER_CONTROL0_RESET_LSB)
+#define SOC_LF_TIMER_CONTROL0_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL0_RESET_LSB) & SOC_LF_TIMER_CONTROL0_RESET_MASK)
+
+#define SOC_LF_TIMER_STATUS0_ADDRESS             0x00000054
+#define SOC_LF_TIMER_STATUS0_OFFSET              0x00000054
+#define SOC_LF_TIMER_STATUS0_INTERRUPT_MSB       0
+#define SOC_LF_TIMER_STATUS0_INTERRUPT_LSB       0
+#define SOC_LF_TIMER_STATUS0_INTERRUPT_MASK      0x00000001
+#define SOC_LF_TIMER_STATUS0_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS0_INTERRUPT_LSB)
+#define SOC_LF_TIMER_STATUS0_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS0_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS0_INTERRUPT_MASK)
+
+#define SOC_LF_TIMER1_ADDRESS                    0x00000058
+#define SOC_LF_TIMER1_OFFSET                     0x00000058
+#define SOC_LF_TIMER1_TARGET_MSB                 31
+#define SOC_LF_TIMER1_TARGET_LSB                 0
+#define SOC_LF_TIMER1_TARGET_MASK                0xffffffff
+#define SOC_LF_TIMER1_TARGET_GET(x)              (((x) & SOC_LF_TIMER1_TARGET_MASK) >> SOC_LF_TIMER1_TARGET_LSB)
+#define SOC_LF_TIMER1_TARGET_SET(x)              (((x) << SOC_LF_TIMER1_TARGET_LSB) & SOC_LF_TIMER1_TARGET_MASK)
+
+#define SOC_LF_TIMER_COUNT1_ADDRESS              0x0000005c
+#define SOC_LF_TIMER_COUNT1_OFFSET               0x0000005c
+#define SOC_LF_TIMER_COUNT1_VALUE_MSB            31
+#define SOC_LF_TIMER_COUNT1_VALUE_LSB            0
+#define SOC_LF_TIMER_COUNT1_VALUE_MASK           0xffffffff
+#define SOC_LF_TIMER_COUNT1_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT1_VALUE_MASK) >> SOC_LF_TIMER_COUNT1_VALUE_LSB)
+#define SOC_LF_TIMER_COUNT1_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT1_VALUE_LSB) & SOC_LF_TIMER_COUNT1_VALUE_MASK)
+
+#define SOC_LF_TIMER_CONTROL1_ADDRESS            0x00000060
+#define SOC_LF_TIMER_CONTROL1_OFFSET             0x00000060
+#define SOC_LF_TIMER_CONTROL1_ENABLE_MSB         2
+#define SOC_LF_TIMER_CONTROL1_ENABLE_LSB         2
+#define SOC_LF_TIMER_CONTROL1_ENABLE_MASK        0x00000004
+#define SOC_LF_TIMER_CONTROL1_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL1_ENABLE_LSB)
+#define SOC_LF_TIMER_CONTROL1_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL1_ENABLE_LSB) & SOC_LF_TIMER_CONTROL1_ENABLE_MASK)
+#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MSB   1
+#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB   1
+#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK  0x00000002
+#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
+#define SOC_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
+#define SOC_LF_TIMER_CONTROL1_RESET_MSB          0
+#define SOC_LF_TIMER_CONTROL1_RESET_LSB          0
+#define SOC_LF_TIMER_CONTROL1_RESET_MASK         0x00000001
+#define SOC_LF_TIMER_CONTROL1_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL1_RESET_MASK) >> SOC_LF_TIMER_CONTROL1_RESET_LSB)
+#define SOC_LF_TIMER_CONTROL1_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL1_RESET_LSB) & SOC_LF_TIMER_CONTROL1_RESET_MASK)
+
+#define SOC_LF_TIMER_STATUS1_ADDRESS             0x00000064
+#define SOC_LF_TIMER_STATUS1_OFFSET              0x00000064
+#define SOC_LF_TIMER_STATUS1_INTERRUPT_MSB       0
+#define SOC_LF_TIMER_STATUS1_INTERRUPT_LSB       0
+#define SOC_LF_TIMER_STATUS1_INTERRUPT_MASK      0x00000001
+#define SOC_LF_TIMER_STATUS1_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS1_INTERRUPT_LSB)
+#define SOC_LF_TIMER_STATUS1_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS1_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS1_INTERRUPT_MASK)
+
+#define SOC_LF_TIMER2_ADDRESS                    0x00000068
+#define SOC_LF_TIMER2_OFFSET                     0x00000068
+#define SOC_LF_TIMER2_TARGET_MSB                 31
+#define SOC_LF_TIMER2_TARGET_LSB                 0
+#define SOC_LF_TIMER2_TARGET_MASK                0xffffffff
+#define SOC_LF_TIMER2_TARGET_GET(x)              (((x) & SOC_LF_TIMER2_TARGET_MASK) >> SOC_LF_TIMER2_TARGET_LSB)
+#define SOC_LF_TIMER2_TARGET_SET(x)              (((x) << SOC_LF_TIMER2_TARGET_LSB) & SOC_LF_TIMER2_TARGET_MASK)
+
+#define SOC_LF_TIMER_COUNT2_ADDRESS              0x0000006c
+#define SOC_LF_TIMER_COUNT2_OFFSET               0x0000006c
+#define SOC_LF_TIMER_COUNT2_VALUE_MSB            31
+#define SOC_LF_TIMER_COUNT2_VALUE_LSB            0
+#define SOC_LF_TIMER_COUNT2_VALUE_MASK           0xffffffff
+#define SOC_LF_TIMER_COUNT2_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT2_VALUE_MASK) >> SOC_LF_TIMER_COUNT2_VALUE_LSB)
+#define SOC_LF_TIMER_COUNT2_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT2_VALUE_LSB) & SOC_LF_TIMER_COUNT2_VALUE_MASK)
+
+#define SOC_LF_TIMER_CONTROL2_ADDRESS            0x00000070
+#define SOC_LF_TIMER_CONTROL2_OFFSET             0x00000070
+#define SOC_LF_TIMER_CONTROL2_ENABLE_MSB         2
+#define SOC_LF_TIMER_CONTROL2_ENABLE_LSB         2
+#define SOC_LF_TIMER_CONTROL2_ENABLE_MASK        0x00000004
+#define SOC_LF_TIMER_CONTROL2_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL2_ENABLE_LSB)
+#define SOC_LF_TIMER_CONTROL2_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL2_ENABLE_LSB) & SOC_LF_TIMER_CONTROL2_ENABLE_MASK)
+#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MSB   1
+#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB   1
+#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK  0x00000002
+#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
+#define SOC_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
+#define SOC_LF_TIMER_CONTROL2_RESET_MSB          0
+#define SOC_LF_TIMER_CONTROL2_RESET_LSB          0
+#define SOC_LF_TIMER_CONTROL2_RESET_MASK         0x00000001
+#define SOC_LF_TIMER_CONTROL2_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL2_RESET_MASK) >> SOC_LF_TIMER_CONTROL2_RESET_LSB)
+#define SOC_LF_TIMER_CONTROL2_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL2_RESET_LSB) & SOC_LF_TIMER_CONTROL2_RESET_MASK)
+
+#define SOC_LF_TIMER_STATUS2_ADDRESS             0x00000074
+#define SOC_LF_TIMER_STATUS2_OFFSET              0x00000074
+#define SOC_LF_TIMER_STATUS2_INTERRUPT_MSB       0
+#define SOC_LF_TIMER_STATUS2_INTERRUPT_LSB       0
+#define SOC_LF_TIMER_STATUS2_INTERRUPT_MASK      0x00000001
+#define SOC_LF_TIMER_STATUS2_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS2_INTERRUPT_LSB)
+#define SOC_LF_TIMER_STATUS2_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS2_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS2_INTERRUPT_MASK)
+
+#define SOC_LF_TIMER3_ADDRESS                    0x00000078
+#define SOC_LF_TIMER3_OFFSET                     0x00000078
+#define SOC_LF_TIMER3_TARGET_MSB                 31
+#define SOC_LF_TIMER3_TARGET_LSB                 0
+#define SOC_LF_TIMER3_TARGET_MASK                0xffffffff
+#define SOC_LF_TIMER3_TARGET_GET(x)              (((x) & SOC_LF_TIMER3_TARGET_MASK) >> SOC_LF_TIMER3_TARGET_LSB)
+#define SOC_LF_TIMER3_TARGET_SET(x)              (((x) << SOC_LF_TIMER3_TARGET_LSB) & SOC_LF_TIMER3_TARGET_MASK)
+
+#define SOC_LF_TIMER_COUNT3_ADDRESS              0x0000007c
+#define SOC_LF_TIMER_COUNT3_OFFSET               0x0000007c
+#define SOC_LF_TIMER_COUNT3_VALUE_MSB            31
+#define SOC_LF_TIMER_COUNT3_VALUE_LSB            0
+#define SOC_LF_TIMER_COUNT3_VALUE_MASK           0xffffffff
+#define SOC_LF_TIMER_COUNT3_VALUE_GET(x)         (((x) & SOC_LF_TIMER_COUNT3_VALUE_MASK) >> SOC_LF_TIMER_COUNT3_VALUE_LSB)
+#define SOC_LF_TIMER_COUNT3_VALUE_SET(x)         (((x) << SOC_LF_TIMER_COUNT3_VALUE_LSB) & SOC_LF_TIMER_COUNT3_VALUE_MASK)
+
+#define SOC_LF_TIMER_CONTROL3_ADDRESS            0x00000080
+#define SOC_LF_TIMER_CONTROL3_OFFSET             0x00000080
+#define SOC_LF_TIMER_CONTROL3_ENABLE_MSB         2
+#define SOC_LF_TIMER_CONTROL3_ENABLE_LSB         2
+#define SOC_LF_TIMER_CONTROL3_ENABLE_MASK        0x00000004
+#define SOC_LF_TIMER_CONTROL3_ENABLE_GET(x)      (((x) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK) >> SOC_LF_TIMER_CONTROL3_ENABLE_LSB)
+#define SOC_LF_TIMER_CONTROL3_ENABLE_SET(x)      (((x) << SOC_LF_TIMER_CONTROL3_ENABLE_LSB) & SOC_LF_TIMER_CONTROL3_ENABLE_MASK)
+#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MSB   1
+#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB   1
+#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK  0x00000002
+#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
+#define SOC_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << SOC_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & SOC_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
+#define SOC_LF_TIMER_CONTROL3_RESET_MSB          0
+#define SOC_LF_TIMER_CONTROL3_RESET_LSB          0
+#define SOC_LF_TIMER_CONTROL3_RESET_MASK         0x00000001
+#define SOC_LF_TIMER_CONTROL3_RESET_GET(x)       (((x) & SOC_LF_TIMER_CONTROL3_RESET_MASK) >> SOC_LF_TIMER_CONTROL3_RESET_LSB)
+#define SOC_LF_TIMER_CONTROL3_RESET_SET(x)       (((x) << SOC_LF_TIMER_CONTROL3_RESET_LSB) & SOC_LF_TIMER_CONTROL3_RESET_MASK)
+
+#define SOC_LF_TIMER_STATUS3_ADDRESS             0x00000084
+#define SOC_LF_TIMER_STATUS3_OFFSET              0x00000084
+#define SOC_LF_TIMER_STATUS3_INTERRUPT_MSB       0
+#define SOC_LF_TIMER_STATUS3_INTERRUPT_LSB       0
+#define SOC_LF_TIMER_STATUS3_INTERRUPT_MASK      0x00000001
+#define SOC_LF_TIMER_STATUS3_INTERRUPT_GET(x)    (((x) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK) >> SOC_LF_TIMER_STATUS3_INTERRUPT_LSB)
+#define SOC_LF_TIMER_STATUS3_INTERRUPT_SET(x)    (((x) << SOC_LF_TIMER_STATUS3_INTERRUPT_LSB) & SOC_LF_TIMER_STATUS3_INTERRUPT_MASK)
+
+#define SOC_HF_TIMER_ADDRESS                     0x00000088
+#define SOC_HF_TIMER_OFFSET                      0x00000088
+#define SOC_HF_TIMER_TARGET_MSB                  31
+#define SOC_HF_TIMER_TARGET_LSB                  12
+#define SOC_HF_TIMER_TARGET_MASK                 0xfffff000
+#define SOC_HF_TIMER_TARGET_GET(x)               (((x) & SOC_HF_TIMER_TARGET_MASK) >> SOC_HF_TIMER_TARGET_LSB)
+#define SOC_HF_TIMER_TARGET_SET(x)               (((x) << SOC_HF_TIMER_TARGET_LSB) & SOC_HF_TIMER_TARGET_MASK)
+
+#define SOC_HF_TIMER_COUNT_ADDRESS               0x0000008c
+#define SOC_HF_TIMER_COUNT_OFFSET                0x0000008c
+#define SOC_HF_TIMER_COUNT_VALUE_MSB             31
+#define SOC_HF_TIMER_COUNT_VALUE_LSB             12
+#define SOC_HF_TIMER_COUNT_VALUE_MASK            0xfffff000
+#define SOC_HF_TIMER_COUNT_VALUE_GET(x)          (((x) & SOC_HF_TIMER_COUNT_VALUE_MASK) >> SOC_HF_TIMER_COUNT_VALUE_LSB)
+#define SOC_HF_TIMER_COUNT_VALUE_SET(x)          (((x) << SOC_HF_TIMER_COUNT_VALUE_LSB) & SOC_HF_TIMER_COUNT_VALUE_MASK)
+
+#define SOC_HF_LF_COUNT_ADDRESS                  0x00000090
+#define SOC_HF_LF_COUNT_OFFSET                   0x00000090
+#define SOC_HF_LF_COUNT_VALUE_MSB                31
+#define SOC_HF_LF_COUNT_VALUE_LSB                0
+#define SOC_HF_LF_COUNT_VALUE_MASK               0xffffffff
+#define SOC_HF_LF_COUNT_VALUE_GET(x)             (((x) & SOC_HF_LF_COUNT_VALUE_MASK) >> SOC_HF_LF_COUNT_VALUE_LSB)
+#define SOC_HF_LF_COUNT_VALUE_SET(x)             (((x) << SOC_HF_LF_COUNT_VALUE_LSB) & SOC_HF_LF_COUNT_VALUE_MASK)
+
+#define SOC_HF_TIMER_CONTROL_ADDRESS             0x00000094
+#define SOC_HF_TIMER_CONTROL_OFFSET              0x00000094
+#define SOC_HF_TIMER_CONTROL_ENABLE_MSB          3
+#define SOC_HF_TIMER_CONTROL_ENABLE_LSB          3
+#define SOC_HF_TIMER_CONTROL_ENABLE_MASK         0x00000008
+#define SOC_HF_TIMER_CONTROL_ENABLE_GET(x)       (((x) & SOC_HF_TIMER_CONTROL_ENABLE_MASK) >> SOC_HF_TIMER_CONTROL_ENABLE_LSB)
+#define SOC_HF_TIMER_CONTROL_ENABLE_SET(x)       (((x) << SOC_HF_TIMER_CONTROL_ENABLE_LSB) & SOC_HF_TIMER_CONTROL_ENABLE_MASK)
+#define SOC_HF_TIMER_CONTROL_ON_MSB              2
+#define SOC_HF_TIMER_CONTROL_ON_LSB              2
+#define SOC_HF_TIMER_CONTROL_ON_MASK             0x00000004
+#define SOC_HF_TIMER_CONTROL_ON_GET(x)           (((x) & SOC_HF_TIMER_CONTROL_ON_MASK) >> SOC_HF_TIMER_CONTROL_ON_LSB)
+#define SOC_HF_TIMER_CONTROL_ON_SET(x)           (((x) << SOC_HF_TIMER_CONTROL_ON_LSB) & SOC_HF_TIMER_CONTROL_ON_MASK)
+#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MSB    1
+#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB    1
+#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK   0x00000002
+#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
+#define SOC_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << SOC_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & SOC_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
+#define SOC_HF_TIMER_CONTROL_RESET_MSB           0
+#define SOC_HF_TIMER_CONTROL_RESET_LSB           0
+#define SOC_HF_TIMER_CONTROL_RESET_MASK          0x00000001
+#define SOC_HF_TIMER_CONTROL_RESET_GET(x)        (((x) & SOC_HF_TIMER_CONTROL_RESET_MASK) >> SOC_HF_TIMER_CONTROL_RESET_LSB)
+#define SOC_HF_TIMER_CONTROL_RESET_SET(x)        (((x) << SOC_HF_TIMER_CONTROL_RESET_LSB) & SOC_HF_TIMER_CONTROL_RESET_MASK)
+
+#define SOC_HF_TIMER_STATUS_ADDRESS              0x00000098
+#define SOC_HF_TIMER_STATUS_OFFSET               0x00000098
+#define SOC_HF_TIMER_STATUS_INTERRUPT_MSB        0
+#define SOC_HF_TIMER_STATUS_INTERRUPT_LSB        0
+#define SOC_HF_TIMER_STATUS_INTERRUPT_MASK       0x00000001
+#define SOC_HF_TIMER_STATUS_INTERRUPT_GET(x)     (((x) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK) >> SOC_HF_TIMER_STATUS_INTERRUPT_LSB)
+#define SOC_HF_TIMER_STATUS_INTERRUPT_SET(x)     (((x) << SOC_HF_TIMER_STATUS_INTERRUPT_LSB) & SOC_HF_TIMER_STATUS_INTERRUPT_MASK)
+
+#define SOC_RTC_CONTROL_ADDRESS                  0x0000009c
+#define SOC_RTC_CONTROL_OFFSET                   0x0000009c
+#define SOC_RTC_CONTROL_ENABLE_MSB               2
+#define SOC_RTC_CONTROL_ENABLE_LSB               2
+#define SOC_RTC_CONTROL_ENABLE_MASK              0x00000004
+#define SOC_RTC_CONTROL_ENABLE_GET(x)            (((x) & SOC_RTC_CONTROL_ENABLE_MASK) >> SOC_RTC_CONTROL_ENABLE_LSB)
+#define SOC_RTC_CONTROL_ENABLE_SET(x)            (((x) << SOC_RTC_CONTROL_ENABLE_LSB) & SOC_RTC_CONTROL_ENABLE_MASK)
+#define SOC_RTC_CONTROL_LOAD_RTC_MSB             1
+#define SOC_RTC_CONTROL_LOAD_RTC_LSB             1
+#define SOC_RTC_CONTROL_LOAD_RTC_MASK            0x00000002
+#define SOC_RTC_CONTROL_LOAD_RTC_GET(x)          (((x) & SOC_RTC_CONTROL_LOAD_RTC_MASK) >> SOC_RTC_CONTROL_LOAD_RTC_LSB)
+#define SOC_RTC_CONTROL_LOAD_RTC_SET(x)          (((x) << SOC_RTC_CONTROL_LOAD_RTC_LSB) & SOC_RTC_CONTROL_LOAD_RTC_MASK)
+#define SOC_RTC_CONTROL_LOAD_ALARM_MSB           0
+#define SOC_RTC_CONTROL_LOAD_ALARM_LSB           0
+#define SOC_RTC_CONTROL_LOAD_ALARM_MASK          0x00000001
+#define SOC_RTC_CONTROL_LOAD_ALARM_GET(x)        (((x) & SOC_RTC_CONTROL_LOAD_ALARM_MASK) >> SOC_RTC_CONTROL_LOAD_ALARM_LSB)
+#define SOC_RTC_CONTROL_LOAD_ALARM_SET(x)        (((x) << SOC_RTC_CONTROL_LOAD_ALARM_LSB) & SOC_RTC_CONTROL_LOAD_ALARM_MASK)
+
+#define SOC_RTC_TIME_ADDRESS                     0x000000a0
+#define SOC_RTC_TIME_OFFSET                      0x000000a0
+#define SOC_RTC_TIME_WEEK_DAY_MSB                26
+#define SOC_RTC_TIME_WEEK_DAY_LSB                24
+#define SOC_RTC_TIME_WEEK_DAY_MASK               0x07000000
+#define SOC_RTC_TIME_WEEK_DAY_GET(x)             (((x) & SOC_RTC_TIME_WEEK_DAY_MASK) >> SOC_RTC_TIME_WEEK_DAY_LSB)
+#define SOC_RTC_TIME_WEEK_DAY_SET(x)             (((x) << SOC_RTC_TIME_WEEK_DAY_LSB) & SOC_RTC_TIME_WEEK_DAY_MASK)
+#define SOC_RTC_TIME_HOUR_MSB                    21
+#define SOC_RTC_TIME_HOUR_LSB                    16
+#define SOC_RTC_TIME_HOUR_MASK                   0x003f0000
+#define SOC_RTC_TIME_HOUR_GET(x)                 (((x) & SOC_RTC_TIME_HOUR_MASK) >> SOC_RTC_TIME_HOUR_LSB)
+#define SOC_RTC_TIME_HOUR_SET(x)                 (((x) << SOC_RTC_TIME_HOUR_LSB) & SOC_RTC_TIME_HOUR_MASK)
+#define SOC_RTC_TIME_MINUTE_MSB                  14
+#define SOC_RTC_TIME_MINUTE_LSB                  8
+#define SOC_RTC_TIME_MINUTE_MASK                 0x00007f00
+#define SOC_RTC_TIME_MINUTE_GET(x)               (((x) & SOC_RTC_TIME_MINUTE_MASK) >> SOC_RTC_TIME_MINUTE_LSB)
+#define SOC_RTC_TIME_MINUTE_SET(x)               (((x) << SOC_RTC_TIME_MINUTE_LSB) & SOC_RTC_TIME_MINUTE_MASK)
+#define SOC_RTC_TIME_SECOND_MSB                  6
+#define SOC_RTC_TIME_SECOND_LSB                  0
+#define SOC_RTC_TIME_SECOND_MASK                 0x0000007f
+#define SOC_RTC_TIME_SECOND_GET(x)               (((x) & SOC_RTC_TIME_SECOND_MASK) >> SOC_RTC_TIME_SECOND_LSB)
+#define SOC_RTC_TIME_SECOND_SET(x)               (((x) << SOC_RTC_TIME_SECOND_LSB) & SOC_RTC_TIME_SECOND_MASK)
+
+#define SOC_RTC_DATE_ADDRESS                     0x000000a4
+#define SOC_RTC_DATE_OFFSET                      0x000000a4
+#define SOC_RTC_DATE_YEAR_MSB                    23
+#define SOC_RTC_DATE_YEAR_LSB                    16
+#define SOC_RTC_DATE_YEAR_MASK                   0x00ff0000
+#define SOC_RTC_DATE_YEAR_GET(x)                 (((x) & SOC_RTC_DATE_YEAR_MASK) >> SOC_RTC_DATE_YEAR_LSB)
+#define SOC_RTC_DATE_YEAR_SET(x)                 (((x) << SOC_RTC_DATE_YEAR_LSB) & SOC_RTC_DATE_YEAR_MASK)
+#define SOC_RTC_DATE_MONTH_MSB                   12
+#define SOC_RTC_DATE_MONTH_LSB                   8
+#define SOC_RTC_DATE_MONTH_MASK                  0x00001f00
+#define SOC_RTC_DATE_MONTH_GET(x)                (((x) & SOC_RTC_DATE_MONTH_MASK) >> SOC_RTC_DATE_MONTH_LSB)
+#define SOC_RTC_DATE_MONTH_SET(x)                (((x) << SOC_RTC_DATE_MONTH_LSB) & SOC_RTC_DATE_MONTH_MASK)
+#define SOC_RTC_DATE_MONTH_DAY_MSB               5
+#define SOC_RTC_DATE_MONTH_DAY_LSB               0
+#define SOC_RTC_DATE_MONTH_DAY_MASK              0x0000003f
+#define SOC_RTC_DATE_MONTH_DAY_GET(x)            (((x) & SOC_RTC_DATE_MONTH_DAY_MASK) >> SOC_RTC_DATE_MONTH_DAY_LSB)
+#define SOC_RTC_DATE_MONTH_DAY_SET(x)            (((x) << SOC_RTC_DATE_MONTH_DAY_LSB) & SOC_RTC_DATE_MONTH_DAY_MASK)
+
+#define SOC_RTC_SET_TIME_ADDRESS                 0x000000a8
+#define SOC_RTC_SET_TIME_OFFSET                  0x000000a8
+#define SOC_RTC_SET_TIME_WEEK_DAY_MSB            26
+#define SOC_RTC_SET_TIME_WEEK_DAY_LSB            24
+#define SOC_RTC_SET_TIME_WEEK_DAY_MASK           0x07000000
+#define SOC_RTC_SET_TIME_WEEK_DAY_GET(x)         (((x) & SOC_RTC_SET_TIME_WEEK_DAY_MASK) >> SOC_RTC_SET_TIME_WEEK_DAY_LSB)
+#define SOC_RTC_SET_TIME_WEEK_DAY_SET(x)         (((x) << SOC_RTC_SET_TIME_WEEK_DAY_LSB) & SOC_RTC_SET_TIME_WEEK_DAY_MASK)
+#define SOC_RTC_SET_TIME_HOUR_MSB                21
+#define SOC_RTC_SET_TIME_HOUR_LSB                16
+#define SOC_RTC_SET_TIME_HOUR_MASK               0x003f0000
+#define SOC_RTC_SET_TIME_HOUR_GET(x)             (((x) & SOC_RTC_SET_TIME_HOUR_MASK) >> SOC_RTC_SET_TIME_HOUR_LSB)
+#define SOC_RTC_SET_TIME_HOUR_SET(x)             (((x) << SOC_RTC_SET_TIME_HOUR_LSB) & SOC_RTC_SET_TIME_HOUR_MASK)
+#define SOC_RTC_SET_TIME_MINUTE_MSB              14
+#define SOC_RTC_SET_TIME_MINUTE_LSB              8
+#define SOC_RTC_SET_TIME_MINUTE_MASK             0x00007f00
+#define SOC_RTC_SET_TIME_MINUTE_GET(x)           (((x) & SOC_RTC_SET_TIME_MINUTE_MASK) >> SOC_RTC_SET_TIME_MINUTE_LSB)
+#define SOC_RTC_SET_TIME_MINUTE_SET(x)           (((x) << SOC_RTC_SET_TIME_MINUTE_LSB) & SOC_RTC_SET_TIME_MINUTE_MASK)
+#define SOC_RTC_SET_TIME_SECOND_MSB              6
+#define SOC_RTC_SET_TIME_SECOND_LSB              0
+#define SOC_RTC_SET_TIME_SECOND_MASK             0x0000007f
+#define SOC_RTC_SET_TIME_SECOND_GET(x)           (((x) & SOC_RTC_SET_TIME_SECOND_MASK) >> SOC_RTC_SET_TIME_SECOND_LSB)
+#define SOC_RTC_SET_TIME_SECOND_SET(x)           (((x) << SOC_RTC_SET_TIME_SECOND_LSB) & SOC_RTC_SET_TIME_SECOND_MASK)
+
+#define SOC_RTC_SET_DATE_ADDRESS                 0x000000ac
+#define SOC_RTC_SET_DATE_OFFSET                  0x000000ac
+#define SOC_RTC_SET_DATE_YEAR_MSB                23
+#define SOC_RTC_SET_DATE_YEAR_LSB                16
+#define SOC_RTC_SET_DATE_YEAR_MASK               0x00ff0000
+#define SOC_RTC_SET_DATE_YEAR_GET(x)             (((x) & SOC_RTC_SET_DATE_YEAR_MASK) >> SOC_RTC_SET_DATE_YEAR_LSB)
+#define SOC_RTC_SET_DATE_YEAR_SET(x)             (((x) << SOC_RTC_SET_DATE_YEAR_LSB) & SOC_RTC_SET_DATE_YEAR_MASK)
+#define SOC_RTC_SET_DATE_MONTH_MSB               12
+#define SOC_RTC_SET_DATE_MONTH_LSB               8
+#define SOC_RTC_SET_DATE_MONTH_MASK              0x00001f00
+#define SOC_RTC_SET_DATE_MONTH_GET(x)            (((x) & SOC_RTC_SET_DATE_MONTH_MASK) >> SOC_RTC_SET_DATE_MONTH_LSB)
+#define SOC_RTC_SET_DATE_MONTH_SET(x)            (((x) << SOC_RTC_SET_DATE_MONTH_LSB) & SOC_RTC_SET_DATE_MONTH_MASK)
+#define SOC_RTC_SET_DATE_MONTH_DAY_MSB           5
+#define SOC_RTC_SET_DATE_MONTH_DAY_LSB           0
+#define SOC_RTC_SET_DATE_MONTH_DAY_MASK          0x0000003f
+#define SOC_RTC_SET_DATE_MONTH_DAY_GET(x)        (((x) & SOC_RTC_SET_DATE_MONTH_DAY_MASK) >> SOC_RTC_SET_DATE_MONTH_DAY_LSB)
+#define SOC_RTC_SET_DATE_MONTH_DAY_SET(x)        (((x) << SOC_RTC_SET_DATE_MONTH_DAY_LSB) & SOC_RTC_SET_DATE_MONTH_DAY_MASK)
+
+#define SOC_RTC_SET_ALARM_ADDRESS                0x000000b0
+#define SOC_RTC_SET_ALARM_OFFSET                 0x000000b0
+#define SOC_RTC_SET_ALARM_HOUR_MSB               21
+#define SOC_RTC_SET_ALARM_HOUR_LSB               16
+#define SOC_RTC_SET_ALARM_HOUR_MASK              0x003f0000
+#define SOC_RTC_SET_ALARM_HOUR_GET(x)            (((x) & SOC_RTC_SET_ALARM_HOUR_MASK) >> SOC_RTC_SET_ALARM_HOUR_LSB)
+#define SOC_RTC_SET_ALARM_HOUR_SET(x)            (((x) << SOC_RTC_SET_ALARM_HOUR_LSB) & SOC_RTC_SET_ALARM_HOUR_MASK)
+#define SOC_RTC_SET_ALARM_MINUTE_MSB             14
+#define SOC_RTC_SET_ALARM_MINUTE_LSB             8
+#define SOC_RTC_SET_ALARM_MINUTE_MASK            0x00007f00
+#define SOC_RTC_SET_ALARM_MINUTE_GET(x)          (((x) & SOC_RTC_SET_ALARM_MINUTE_MASK) >> SOC_RTC_SET_ALARM_MINUTE_LSB)
+#define SOC_RTC_SET_ALARM_MINUTE_SET(x)          (((x) << SOC_RTC_SET_ALARM_MINUTE_LSB) & SOC_RTC_SET_ALARM_MINUTE_MASK)
+#define SOC_RTC_SET_ALARM_SECOND_MSB             6
+#define SOC_RTC_SET_ALARM_SECOND_LSB             0
+#define SOC_RTC_SET_ALARM_SECOND_MASK            0x0000007f
+#define SOC_RTC_SET_ALARM_SECOND_GET(x)          (((x) & SOC_RTC_SET_ALARM_SECOND_MASK) >> SOC_RTC_SET_ALARM_SECOND_LSB)
+#define SOC_RTC_SET_ALARM_SECOND_SET(x)          (((x) << SOC_RTC_SET_ALARM_SECOND_LSB) & SOC_RTC_SET_ALARM_SECOND_MASK)
+
+#define SOC_RTC_CONFIG_ADDRESS                   0x000000b4
+#define SOC_RTC_CONFIG_OFFSET                    0x000000b4
+#define SOC_RTC_CONFIG_BCD_MSB                   2
+#define SOC_RTC_CONFIG_BCD_LSB                   2
+#define SOC_RTC_CONFIG_BCD_MASK                  0x00000004
+#define SOC_RTC_CONFIG_BCD_GET(x)                (((x) & SOC_RTC_CONFIG_BCD_MASK) >> SOC_RTC_CONFIG_BCD_LSB)
+#define SOC_RTC_CONFIG_BCD_SET(x)                (((x) << SOC_RTC_CONFIG_BCD_LSB) & SOC_RTC_CONFIG_BCD_MASK)
+#define SOC_RTC_CONFIG_TWELVE_HOUR_MSB           1
+#define SOC_RTC_CONFIG_TWELVE_HOUR_LSB           1
+#define SOC_RTC_CONFIG_TWELVE_HOUR_MASK          0x00000002
+#define SOC_RTC_CONFIG_TWELVE_HOUR_GET(x)        (((x) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK) >> SOC_RTC_CONFIG_TWELVE_HOUR_LSB)
+#define SOC_RTC_CONFIG_TWELVE_HOUR_SET(x)        (((x) << SOC_RTC_CONFIG_TWELVE_HOUR_LSB) & SOC_RTC_CONFIG_TWELVE_HOUR_MASK)
+#define SOC_RTC_CONFIG_DSE_MSB                   0
+#define SOC_RTC_CONFIG_DSE_LSB                   0
+#define SOC_RTC_CONFIG_DSE_MASK                  0x00000001
+#define SOC_RTC_CONFIG_DSE_GET(x)                (((x) & SOC_RTC_CONFIG_DSE_MASK) >> SOC_RTC_CONFIG_DSE_LSB)
+#define SOC_RTC_CONFIG_DSE_SET(x)                (((x) << SOC_RTC_CONFIG_DSE_LSB) & SOC_RTC_CONFIG_DSE_MASK)
+
+#define SOC_RTC_ALARM_STATUS_ADDRESS             0x000000b8
+#define SOC_RTC_ALARM_STATUS_OFFSET              0x000000b8
+#define SOC_RTC_ALARM_STATUS_ENABLE_MSB          1
+#define SOC_RTC_ALARM_STATUS_ENABLE_LSB          1
+#define SOC_RTC_ALARM_STATUS_ENABLE_MASK         0x00000002
+#define SOC_RTC_ALARM_STATUS_ENABLE_GET(x)       (((x) & SOC_RTC_ALARM_STATUS_ENABLE_MASK) >> SOC_RTC_ALARM_STATUS_ENABLE_LSB)
+#define SOC_RTC_ALARM_STATUS_ENABLE_SET(x)       (((x) << SOC_RTC_ALARM_STATUS_ENABLE_LSB) & SOC_RTC_ALARM_STATUS_ENABLE_MASK)
+#define SOC_RTC_ALARM_STATUS_INTERRUPT_MSB       0
+#define SOC_RTC_ALARM_STATUS_INTERRUPT_LSB       0
+#define SOC_RTC_ALARM_STATUS_INTERRUPT_MASK      0x00000001
+#define SOC_RTC_ALARM_STATUS_INTERRUPT_GET(x)    (((x) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK) >> SOC_RTC_ALARM_STATUS_INTERRUPT_LSB)
+#define SOC_RTC_ALARM_STATUS_INTERRUPT_SET(x)    (((x) << SOC_RTC_ALARM_STATUS_INTERRUPT_LSB) & SOC_RTC_ALARM_STATUS_INTERRUPT_MASK)
+
+#define SOC_UART_WAKEUP_ADDRESS                  0x000000bc
+#define SOC_UART_WAKEUP_OFFSET                   0x000000bc
+#define SOC_UART_WAKEUP_ENABLE_MSB               0
+#define SOC_UART_WAKEUP_ENABLE_LSB               0
+#define SOC_UART_WAKEUP_ENABLE_MASK              0x00000001
+#define SOC_UART_WAKEUP_ENABLE_GET(x)            (((x) & SOC_UART_WAKEUP_ENABLE_MASK) >> SOC_UART_WAKEUP_ENABLE_LSB)
+#define SOC_UART_WAKEUP_ENABLE_SET(x)            (((x) << SOC_UART_WAKEUP_ENABLE_LSB) & SOC_UART_WAKEUP_ENABLE_MASK)
+
+#define SOC_RESET_CAUSE_ADDRESS                  0x000000c0
+#define SOC_RESET_CAUSE_OFFSET                   0x000000c0
+#define SOC_RESET_CAUSE_LAST_MSB                 2
+#define SOC_RESET_CAUSE_LAST_LSB                 0
+#define SOC_RESET_CAUSE_LAST_MASK                0x00000007
+#define SOC_RESET_CAUSE_LAST_GET(x)              (((x) & SOC_RESET_CAUSE_LAST_MASK) >> SOC_RESET_CAUSE_LAST_LSB)
+#define SOC_RESET_CAUSE_LAST_SET(x)              (((x) << SOC_RESET_CAUSE_LAST_LSB) & SOC_RESET_CAUSE_LAST_MASK)
+
+#define SOC_SYSTEM_SLEEP_ADDRESS                 0x000000c4
+#define SOC_SYSTEM_SLEEP_OFFSET                  0x000000c4
+#define SOC_SYSTEM_SLEEP_MCI_MSB                 5
+#define SOC_SYSTEM_SLEEP_MCI_LSB                 5
+#define SOC_SYSTEM_SLEEP_MCI_MASK                0x00000020
+#define SOC_SYSTEM_SLEEP_MCI_GET(x)              (((x) & SOC_SYSTEM_SLEEP_MCI_MASK) >> SOC_SYSTEM_SLEEP_MCI_LSB)
+#define SOC_SYSTEM_SLEEP_MCI_SET(x)              (((x) << SOC_SYSTEM_SLEEP_MCI_LSB) & SOC_SYSTEM_SLEEP_MCI_MASK)
+#define SOC_SYSTEM_SLEEP_HOST_IF_MSB             4
+#define SOC_SYSTEM_SLEEP_HOST_IF_LSB             4
+#define SOC_SYSTEM_SLEEP_HOST_IF_MASK            0x00000010
+#define SOC_SYSTEM_SLEEP_HOST_IF_GET(x)          (((x) & SOC_SYSTEM_SLEEP_HOST_IF_MASK) >> SOC_SYSTEM_SLEEP_HOST_IF_LSB)
+#define SOC_SYSTEM_SLEEP_HOST_IF_SET(x)          (((x) << SOC_SYSTEM_SLEEP_HOST_IF_LSB) & SOC_SYSTEM_SLEEP_HOST_IF_MASK)
+#define SOC_SYSTEM_SLEEP_MBOX_MSB                3
+#define SOC_SYSTEM_SLEEP_MBOX_LSB                3
+#define SOC_SYSTEM_SLEEP_MBOX_MASK               0x00000008
+#define SOC_SYSTEM_SLEEP_MBOX_GET(x)             (((x) & SOC_SYSTEM_SLEEP_MBOX_MASK) >> SOC_SYSTEM_SLEEP_MBOX_LSB)
+#define SOC_SYSTEM_SLEEP_MBOX_SET(x)             (((x) << SOC_SYSTEM_SLEEP_MBOX_LSB) & SOC_SYSTEM_SLEEP_MBOX_MASK)
+#define SOC_SYSTEM_SLEEP_MAC_IF_MSB              2
+#define SOC_SYSTEM_SLEEP_MAC_IF_LSB              2
+#define SOC_SYSTEM_SLEEP_MAC_IF_MASK             0x00000004
+#define SOC_SYSTEM_SLEEP_MAC_IF_GET(x)           (((x) & SOC_SYSTEM_SLEEP_MAC_IF_MASK) >> SOC_SYSTEM_SLEEP_MAC_IF_LSB)
+#define SOC_SYSTEM_SLEEP_MAC_IF_SET(x)           (((x) << SOC_SYSTEM_SLEEP_MAC_IF_LSB) & SOC_SYSTEM_SLEEP_MAC_IF_MASK)
+#define SOC_SYSTEM_SLEEP_LIGHT_MSB               1
+#define SOC_SYSTEM_SLEEP_LIGHT_LSB               1
+#define SOC_SYSTEM_SLEEP_LIGHT_MASK              0x00000002
+#define SOC_SYSTEM_SLEEP_LIGHT_GET(x)            (((x) & SOC_SYSTEM_SLEEP_LIGHT_MASK) >> SOC_SYSTEM_SLEEP_LIGHT_LSB)
+#define SOC_SYSTEM_SLEEP_LIGHT_SET(x)            (((x) << SOC_SYSTEM_SLEEP_LIGHT_LSB) & SOC_SYSTEM_SLEEP_LIGHT_MASK)
+#define SOC_SYSTEM_SLEEP_DISABLE_MSB             0
+#define SOC_SYSTEM_SLEEP_DISABLE_LSB             0
+#define SOC_SYSTEM_SLEEP_DISABLE_MASK            0x00000001
+#define SOC_SYSTEM_SLEEP_DISABLE_GET(x)          (((x) & SOC_SYSTEM_SLEEP_DISABLE_MASK) >> SOC_SYSTEM_SLEEP_DISABLE_LSB)
+#define SOC_SYSTEM_SLEEP_DISABLE_SET(x)          (((x) << SOC_SYSTEM_SLEEP_DISABLE_LSB) & SOC_SYSTEM_SLEEP_DISABLE_MASK)
+
+#define SOC_SDIO_WRAPPER_ADDRESS                 0x000000c8
+#define SOC_SDIO_WRAPPER_OFFSET                  0x000000c8
+#define SOC_SDIO_WRAPPER_SLEEP_MSB               3
+#define SOC_SDIO_WRAPPER_SLEEP_LSB               3
+#define SOC_SDIO_WRAPPER_SLEEP_MASK              0x00000008
+#define SOC_SDIO_WRAPPER_SLEEP_GET(x)            (((x) & SOC_SDIO_WRAPPER_SLEEP_MASK) >> SOC_SDIO_WRAPPER_SLEEP_LSB)
+#define SOC_SDIO_WRAPPER_SLEEP_SET(x)            (((x) << SOC_SDIO_WRAPPER_SLEEP_LSB) & SOC_SDIO_WRAPPER_SLEEP_MASK)
+#define SOC_SDIO_WRAPPER_WAKEUP_MSB              2
+#define SOC_SDIO_WRAPPER_WAKEUP_LSB              2
+#define SOC_SDIO_WRAPPER_WAKEUP_MASK             0x00000004
+#define SOC_SDIO_WRAPPER_WAKEUP_GET(x)           (((x) & SOC_SDIO_WRAPPER_WAKEUP_MASK) >> SOC_SDIO_WRAPPER_WAKEUP_LSB)
+#define SOC_SDIO_WRAPPER_WAKEUP_SET(x)           (((x) << SOC_SDIO_WRAPPER_WAKEUP_LSB) & SOC_SDIO_WRAPPER_WAKEUP_MASK)
+#define SOC_SDIO_WRAPPER_SOC_ON_MSB              1
+#define SOC_SDIO_WRAPPER_SOC_ON_LSB              1
+#define SOC_SDIO_WRAPPER_SOC_ON_MASK             0x00000002
+#define SOC_SDIO_WRAPPER_SOC_ON_GET(x)           (((x) & SOC_SDIO_WRAPPER_SOC_ON_MASK) >> SOC_SDIO_WRAPPER_SOC_ON_LSB)
+#define SOC_SDIO_WRAPPER_SOC_ON_SET(x)           (((x) << SOC_SDIO_WRAPPER_SOC_ON_LSB) & SOC_SDIO_WRAPPER_SOC_ON_MASK)
+#define SOC_SDIO_WRAPPER_ON_MSB                  0
+#define SOC_SDIO_WRAPPER_ON_LSB                  0
+#define SOC_SDIO_WRAPPER_ON_MASK                 0x00000001
+#define SOC_SDIO_WRAPPER_ON_GET(x)               (((x) & SOC_SDIO_WRAPPER_ON_MASK) >> SOC_SDIO_WRAPPER_ON_LSB)
+#define SOC_SDIO_WRAPPER_ON_SET(x)               (((x) << SOC_SDIO_WRAPPER_ON_LSB) & SOC_SDIO_WRAPPER_ON_MASK)
+
+#define SOC_INT_SLEEP_MASK_ADDRESS               0x000000cc
+#define SOC_INT_SLEEP_MASK_OFFSET                0x000000cc
+#define SOC_INT_SLEEP_MASK_BITMAP_MSB            31
+#define SOC_INT_SLEEP_MASK_BITMAP_LSB            0
+#define SOC_INT_SLEEP_MASK_BITMAP_MASK           0xffffffff
+#define SOC_INT_SLEEP_MASK_BITMAP_GET(x)         (((x) & SOC_INT_SLEEP_MASK_BITMAP_MASK) >> SOC_INT_SLEEP_MASK_BITMAP_LSB)
+#define SOC_INT_SLEEP_MASK_BITMAP_SET(x)         (((x) << SOC_INT_SLEEP_MASK_BITMAP_LSB) & SOC_INT_SLEEP_MASK_BITMAP_MASK)
+
+#define SOC_LPO_CAL_TIME_ADDRESS                 0x000000d4
+#define SOC_LPO_CAL_TIME_OFFSET                  0x000000d4
+#define SOC_LPO_CAL_TIME_LENGTH_MSB              13
+#define SOC_LPO_CAL_TIME_LENGTH_LSB              0
+#define SOC_LPO_CAL_TIME_LENGTH_MASK             0x00003fff
+#define SOC_LPO_CAL_TIME_LENGTH_GET(x)           (((x) & SOC_LPO_CAL_TIME_LENGTH_MASK) >> SOC_LPO_CAL_TIME_LENGTH_LSB)
+#define SOC_LPO_CAL_TIME_LENGTH_SET(x)           (((x) << SOC_LPO_CAL_TIME_LENGTH_LSB) & SOC_LPO_CAL_TIME_LENGTH_MASK)
+
+#define SOC_LPO_INIT_DIVIDEND_INT_ADDRESS        0x000000d8
+#define SOC_LPO_INIT_DIVIDEND_INT_OFFSET         0x000000d8
+#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MSB      23
+#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB      0
+#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK     0x00ffffff
+#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)   (((x) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
+#define SOC_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)   (((x) << SOC_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
+
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_ADDRESS   0x000000dc
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_OFFSET    0x000000dc
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
+#define SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & SOC_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
+
+#define SOC_LPO_CAL_ADDRESS                      0x000000e0
+#define SOC_LPO_CAL_OFFSET                       0x000000e0
+#define SOC_LPO_CAL_ENABLE_MSB                   20
+#define SOC_LPO_CAL_ENABLE_LSB                   20
+#define SOC_LPO_CAL_ENABLE_MASK                  0x00100000
+#define SOC_LPO_CAL_ENABLE_GET(x)                (((x) & SOC_LPO_CAL_ENABLE_MASK) >> SOC_LPO_CAL_ENABLE_LSB)
+#define SOC_LPO_CAL_ENABLE_SET(x)                (((x) << SOC_LPO_CAL_ENABLE_LSB) & SOC_LPO_CAL_ENABLE_MASK)
+#define SOC_LPO_CAL_COUNT_MSB                    19
+#define SOC_LPO_CAL_COUNT_LSB                    0
+#define SOC_LPO_CAL_COUNT_MASK                   0x000fffff
+#define SOC_LPO_CAL_COUNT_GET(x)                 (((x) & SOC_LPO_CAL_COUNT_MASK) >> SOC_LPO_CAL_COUNT_LSB)
+#define SOC_LPO_CAL_COUNT_SET(x)                 (((x) << SOC_LPO_CAL_COUNT_LSB) & SOC_LPO_CAL_COUNT_MASK)
+
+#define SOC_LPO_CAL_TEST_CONTROL_ADDRESS         0x000000e4
+#define SOC_LPO_CAL_TEST_CONTROL_OFFSET          0x000000e4
+#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MSB      16
+#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB      16
+#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK     0x00010000
+#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)   (((x) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
+#define SOC_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)   (((x) << SOC_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & SOC_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
+#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB  15
+#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB  0
+#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000ffff
+#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
+#define SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & SOC_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
+
+#define SOC_LPO_CAL_TEST_STATUS_ADDRESS          0x000000e8
+#define SOC_LPO_CAL_TEST_STATUS_OFFSET           0x000000e8
+#define SOC_LPO_CAL_TEST_STATUS_READY_MSB        16
+#define SOC_LPO_CAL_TEST_STATUS_READY_LSB        16
+#define SOC_LPO_CAL_TEST_STATUS_READY_MASK       0x00010000
+#define SOC_LPO_CAL_TEST_STATUS_READY_GET(x)     (((x) & SOC_LPO_CAL_TEST_STATUS_READY_MASK) >> SOC_LPO_CAL_TEST_STATUS_READY_LSB)
+#define SOC_LPO_CAL_TEST_STATUS_READY_SET(x)     (((x) << SOC_LPO_CAL_TEST_STATUS_READY_LSB) & SOC_LPO_CAL_TEST_STATUS_READY_MASK)
+#define SOC_LPO_CAL_TEST_STATUS_COUNT_MSB        15
+#define SOC_LPO_CAL_TEST_STATUS_COUNT_LSB        0
+#define SOC_LPO_CAL_TEST_STATUS_COUNT_MASK       0x0000ffff
+#define SOC_LPO_CAL_TEST_STATUS_COUNT_GET(x)     (((x) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK) >> SOC_LPO_CAL_TEST_STATUS_COUNT_LSB)
+#define SOC_LPO_CAL_TEST_STATUS_COUNT_SET(x)     (((x) << SOC_LPO_CAL_TEST_STATUS_COUNT_LSB) & SOC_LPO_CAL_TEST_STATUS_COUNT_MASK)
+
+#define LEGACY_SOC_CHIP_ID_ADDRESS               0x000000ec
+#define LEGACY_SOC_CHIP_ID_OFFSET                0x000000ec
+#define LEGACY_SOC_CHIP_ID_DEVICE_ID_MSB         31
+#define LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB         16
+#define LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK        0xffff0000
+#define LEGACY_SOC_CHIP_ID_DEVICE_ID_GET(x)      (((x) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK) >> LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB)
+#define LEGACY_SOC_CHIP_ID_DEVICE_ID_SET(x)      (((x) << LEGACY_SOC_CHIP_ID_DEVICE_ID_LSB) & LEGACY_SOC_CHIP_ID_DEVICE_ID_MASK)
+#define LEGACY_SOC_CHIP_ID_CONFIG_ID_MSB         15
+#define LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB         4
+#define LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK        0x0000fff0
+#define LEGACY_SOC_CHIP_ID_CONFIG_ID_GET(x)      (((x) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK) >> LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB)
+#define LEGACY_SOC_CHIP_ID_CONFIG_ID_SET(x)      (((x) << LEGACY_SOC_CHIP_ID_CONFIG_ID_LSB) & LEGACY_SOC_CHIP_ID_CONFIG_ID_MASK)
+#define LEGACY_SOC_CHIP_ID_VERSION_ID_MSB        3
+#define LEGACY_SOC_CHIP_ID_VERSION_ID_LSB        0
+#define LEGACY_SOC_CHIP_ID_VERSION_ID_MASK       0x0000000f
+#define LEGACY_SOC_CHIP_ID_VERSION_ID_GET(x)     (((x) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK) >> LEGACY_SOC_CHIP_ID_VERSION_ID_LSB)
+#define LEGACY_SOC_CHIP_ID_VERSION_ID_SET(x)     (((x) << LEGACY_SOC_CHIP_ID_VERSION_ID_LSB) & LEGACY_SOC_CHIP_ID_VERSION_ID_MASK)
+
+#define SOC_CHIP_ID_ADDRESS                      0x000000f0
+#define SOC_CHIP_ID_OFFSET                       0x000000f0
+#define SOC_CHIP_ID_DEVICE_ID_MSB                31
+#define SOC_CHIP_ID_DEVICE_ID_LSB                16
+#define SOC_CHIP_ID_DEVICE_ID_MASK               0xffff0000
+#define SOC_CHIP_ID_DEVICE_ID_GET(x)             (((x) & SOC_CHIP_ID_DEVICE_ID_MASK) >> SOC_CHIP_ID_DEVICE_ID_LSB)
+#define SOC_CHIP_ID_DEVICE_ID_SET(x)             (((x) << SOC_CHIP_ID_DEVICE_ID_LSB) & SOC_CHIP_ID_DEVICE_ID_MASK)
+#define SOC_CHIP_ID_CONFIG_ID_MSB                15
+#define SOC_CHIP_ID_CONFIG_ID_LSB                4
+#define SOC_CHIP_ID_CONFIG_ID_MASK               0x0000fff0
+#define SOC_CHIP_ID_CONFIG_ID_GET(x)             (((x) & SOC_CHIP_ID_CONFIG_ID_MASK) >> SOC_CHIP_ID_CONFIG_ID_LSB)
+#define SOC_CHIP_ID_CONFIG_ID_SET(x)             (((x) << SOC_CHIP_ID_CONFIG_ID_LSB) & SOC_CHIP_ID_CONFIG_ID_MASK)
+#define SOC_CHIP_ID_VERSION_ID_MSB               3
+#define SOC_CHIP_ID_VERSION_ID_LSB               0
+#define SOC_CHIP_ID_VERSION_ID_MASK              0x0000000f
+#define SOC_CHIP_ID_VERSION_ID_GET(x)            (((x) & SOC_CHIP_ID_VERSION_ID_MASK) >> SOC_CHIP_ID_VERSION_ID_LSB)
+#define SOC_CHIP_ID_VERSION_ID_SET(x)            (((x) << SOC_CHIP_ID_VERSION_ID_LSB) & SOC_CHIP_ID_VERSION_ID_MASK)
+
+#define SOC_POWER_REG_ADDRESS                    0x0000010c
+#define SOC_POWER_REG_OFFSET                     0x0000010c
+#define SOC_POWER_REG_DISCON_MODE_EN_MSB         16
+#define SOC_POWER_REG_DISCON_MODE_EN_LSB         16
+#define SOC_POWER_REG_DISCON_MODE_EN_MASK        0x00010000
+#define SOC_POWER_REG_DISCON_MODE_EN_GET(x)      (((x) & SOC_POWER_REG_DISCON_MODE_EN_MASK) >> SOC_POWER_REG_DISCON_MODE_EN_LSB)
+#define SOC_POWER_REG_DISCON_MODE_EN_SET(x)      (((x) << SOC_POWER_REG_DISCON_MODE_EN_LSB) & SOC_POWER_REG_DISCON_MODE_EN_MASK)
+#define SOC_POWER_REG_DEEP_SLEEP_EN_MSB          15
+#define SOC_POWER_REG_DEEP_SLEEP_EN_LSB          15
+#define SOC_POWER_REG_DEEP_SLEEP_EN_MASK         0x00008000
+#define SOC_POWER_REG_DEEP_SLEEP_EN_GET(x)       (((x) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK) >> SOC_POWER_REG_DEEP_SLEEP_EN_LSB)
+#define SOC_POWER_REG_DEEP_SLEEP_EN_SET(x)       (((x) << SOC_POWER_REG_DEEP_SLEEP_EN_LSB) & SOC_POWER_REG_DEEP_SLEEP_EN_MASK)
+#define SOC_POWER_REG_DEBUG_EN_MSB               14
+#define SOC_POWER_REG_DEBUG_EN_LSB               14
+#define SOC_POWER_REG_DEBUG_EN_MASK              0x00004000
+#define SOC_POWER_REG_DEBUG_EN_GET(x)            (((x) & SOC_POWER_REG_DEBUG_EN_MASK) >> SOC_POWER_REG_DEBUG_EN_LSB)
+#define SOC_POWER_REG_DEBUG_EN_SET(x)            (((x) << SOC_POWER_REG_DEBUG_EN_LSB) & SOC_POWER_REG_DEBUG_EN_MASK)
+#define SOC_POWER_REG_WLAN_BB_PWD_EN_MSB         13
+#define SOC_POWER_REG_WLAN_BB_PWD_EN_LSB         13
+#define SOC_POWER_REG_WLAN_BB_PWD_EN_MASK        0x00002000
+#define SOC_POWER_REG_WLAN_BB_PWD_EN_GET(x)      (((x) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_BB_PWD_EN_LSB)
+#define SOC_POWER_REG_WLAN_BB_PWD_EN_SET(x)      (((x) << SOC_POWER_REG_WLAN_BB_PWD_EN_LSB) & SOC_POWER_REG_WLAN_BB_PWD_EN_MASK)
+#define SOC_POWER_REG_WLAN_MAC_PWD_EN_MSB        12
+#define SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB        12
+#define SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK       0x00001000
+#define SOC_POWER_REG_WLAN_MAC_PWD_EN_GET(x)     (((x) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB)
+#define SOC_POWER_REG_WLAN_MAC_PWD_EN_SET(x)     (((x) << SOC_POWER_REG_WLAN_MAC_PWD_EN_LSB) & SOC_POWER_REG_WLAN_MAC_PWD_EN_MASK)
+#define SOC_POWER_REG_CPU_INT_ENABLE_MSB         7
+#define SOC_POWER_REG_CPU_INT_ENABLE_LSB         7
+#define SOC_POWER_REG_CPU_INT_ENABLE_MASK        0x00000080
+#define SOC_POWER_REG_CPU_INT_ENABLE_GET(x)      (((x) & SOC_POWER_REG_CPU_INT_ENABLE_MASK) >> SOC_POWER_REG_CPU_INT_ENABLE_LSB)
+#define SOC_POWER_REG_CPU_INT_ENABLE_SET(x)      (((x) << SOC_POWER_REG_CPU_INT_ENABLE_LSB) & SOC_POWER_REG_CPU_INT_ENABLE_MASK)
+#define SOC_POWER_REG_WLAN_ISO_DIS_MSB           6
+#define SOC_POWER_REG_WLAN_ISO_DIS_LSB           6
+#define SOC_POWER_REG_WLAN_ISO_DIS_MASK          0x00000040
+#define SOC_POWER_REG_WLAN_ISO_DIS_GET(x)        (((x) & SOC_POWER_REG_WLAN_ISO_DIS_MASK) >> SOC_POWER_REG_WLAN_ISO_DIS_LSB)
+#define SOC_POWER_REG_WLAN_ISO_DIS_SET(x)        (((x) << SOC_POWER_REG_WLAN_ISO_DIS_LSB) & SOC_POWER_REG_WLAN_ISO_DIS_MASK)
+#define SOC_POWER_REG_WLAN_ISO_CNTL_MSB          5
+#define SOC_POWER_REG_WLAN_ISO_CNTL_LSB          5
+#define SOC_POWER_REG_WLAN_ISO_CNTL_MASK         0x00000020
+#define SOC_POWER_REG_WLAN_ISO_CNTL_GET(x)       (((x) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK) >> SOC_POWER_REG_WLAN_ISO_CNTL_LSB)
+#define SOC_POWER_REG_WLAN_ISO_CNTL_SET(x)       (((x) << SOC_POWER_REG_WLAN_ISO_CNTL_LSB) & SOC_POWER_REG_WLAN_ISO_CNTL_MASK)
+#define SOC_POWER_REG_RADIO_PWD_EN_MSB           4
+#define SOC_POWER_REG_RADIO_PWD_EN_LSB           4
+#define SOC_POWER_REG_RADIO_PWD_EN_MASK          0x00000010
+#define SOC_POWER_REG_RADIO_PWD_EN_GET(x)        (((x) & SOC_POWER_REG_RADIO_PWD_EN_MASK) >> SOC_POWER_REG_RADIO_PWD_EN_LSB)
+#define SOC_POWER_REG_RADIO_PWD_EN_SET(x)        (((x) << SOC_POWER_REG_RADIO_PWD_EN_LSB) & SOC_POWER_REG_RADIO_PWD_EN_MASK)
+#define SOC_POWER_REG_SOC_ISO_EN_MSB             3
+#define SOC_POWER_REG_SOC_ISO_EN_LSB             3
+#define SOC_POWER_REG_SOC_ISO_EN_MASK            0x00000008
+#define SOC_POWER_REG_SOC_ISO_EN_GET(x)          (((x) & SOC_POWER_REG_SOC_ISO_EN_MASK) >> SOC_POWER_REG_SOC_ISO_EN_LSB)
+#define SOC_POWER_REG_SOC_ISO_EN_SET(x)          (((x) << SOC_POWER_REG_SOC_ISO_EN_LSB) & SOC_POWER_REG_SOC_ISO_EN_MASK)
+#define SOC_POWER_REG_WLAN_ISO_EN_MSB            2
+#define SOC_POWER_REG_WLAN_ISO_EN_LSB            2
+#define SOC_POWER_REG_WLAN_ISO_EN_MASK           0x00000004
+#define SOC_POWER_REG_WLAN_ISO_EN_GET(x)         (((x) & SOC_POWER_REG_WLAN_ISO_EN_MASK) >> SOC_POWER_REG_WLAN_ISO_EN_LSB)
+#define SOC_POWER_REG_WLAN_ISO_EN_SET(x)         (((x) << SOC_POWER_REG_WLAN_ISO_EN_LSB) & SOC_POWER_REG_WLAN_ISO_EN_MASK)
+#define SOC_POWER_REG_WLAN_PWD_EN_MSB            1
+#define SOC_POWER_REG_WLAN_PWD_EN_LSB            1
+#define SOC_POWER_REG_WLAN_PWD_EN_MASK           0x00000002
+#define SOC_POWER_REG_WLAN_PWD_EN_GET(x)         (((x) & SOC_POWER_REG_WLAN_PWD_EN_MASK) >> SOC_POWER_REG_WLAN_PWD_EN_LSB)
+#define SOC_POWER_REG_WLAN_PWD_EN_SET(x)         (((x) << SOC_POWER_REG_WLAN_PWD_EN_LSB) & SOC_POWER_REG_WLAN_PWD_EN_MASK)
+#define SOC_POWER_REG_POWER_EN_MSB               0
+#define SOC_POWER_REG_POWER_EN_LSB               0
+#define SOC_POWER_REG_POWER_EN_MASK              0x00000001
+#define SOC_POWER_REG_POWER_EN_GET(x)            (((x) & SOC_POWER_REG_POWER_EN_MASK) >> SOC_POWER_REG_POWER_EN_LSB)
+#define SOC_POWER_REG_POWER_EN_SET(x)            (((x) << SOC_POWER_REG_POWER_EN_LSB) & SOC_POWER_REG_POWER_EN_MASK)
+
+#define SOC_CORE_CLK_CTRL_ADDRESS                0x00000110
+#define SOC_CORE_CLK_CTRL_OFFSET                 0x00000110
+#define SOC_CORE_CLK_CTRL_DIV_MSB                2
+#define SOC_CORE_CLK_CTRL_DIV_LSB                0
+#define SOC_CORE_CLK_CTRL_DIV_MASK               0x00000007
+#define SOC_CORE_CLK_CTRL_DIV_GET(x)             (((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
+#define SOC_CORE_CLK_CTRL_DIV_SET(x)             (((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
+
+#define SOC_GPIO_WAKEUP_CONTROL_ADDRESS          0x00000114
+#define SOC_GPIO_WAKEUP_CONTROL_OFFSET           0x00000114
+#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MSB       0
+#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB       0
+#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK      0x00000001
+#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)    (((x) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
+#define SOC_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)    (((x) << SOC_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & SOC_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
+
+#define SLEEP_RETENTION_ADDRESS                  0x00000214
+#define SLEEP_RETENTION_OFFSET                   0x00000214
+#define SLEEP_RETENTION_GREEN_SAVE_MSB           10
+#define SLEEP_RETENTION_GREEN_SAVE_LSB           10
+#define SLEEP_RETENTION_GREEN_SAVE_MASK          0x00000400
+#define SLEEP_RETENTION_GREEN_SAVE_GET(x)        (((x) & SLEEP_RETENTION_GREEN_SAVE_MASK) >> SLEEP_RETENTION_GREEN_SAVE_LSB)
+#define SLEEP_RETENTION_GREEN_SAVE_SET(x)        (((x) << SLEEP_RETENTION_GREEN_SAVE_LSB) & SLEEP_RETENTION_GREEN_SAVE_MASK)
+#define SLEEP_RETENTION_TIME_MSB                 9
+#define SLEEP_RETENTION_TIME_LSB                 2
+#define SLEEP_RETENTION_TIME_MASK                0x000003fc
+#define SLEEP_RETENTION_TIME_GET(x)              (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
+#define SLEEP_RETENTION_TIME_SET(x)              (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
+#define SLEEP_RETENTION_MODE_MSB                 1
+#define SLEEP_RETENTION_MODE_LSB                 1
+#define SLEEP_RETENTION_MODE_MASK                0x00000002
+#define SLEEP_RETENTION_MODE_GET(x)              (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
+#define SLEEP_RETENTION_MODE_SET(x)              (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
+#define SLEEP_RETENTION_ENABLE_MSB               0
+#define SLEEP_RETENTION_ENABLE_LSB               0
+#define SLEEP_RETENTION_ENABLE_MASK              0x00000001
+#define SLEEP_RETENTION_ENABLE_GET(x)            (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
+#define SLEEP_RETENTION_ENABLE_SET(x)            (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
+
+#define LP_PERF_COUNTER_ADDRESS                  0x00000284
+#define LP_PERF_COUNTER_OFFSET                   0x00000284
+#define LP_PERF_COUNTER_EN_MSB                   0
+#define LP_PERF_COUNTER_EN_LSB                   0
+#define LP_PERF_COUNTER_EN_MASK                  0x00000001
+#define LP_PERF_COUNTER_EN_GET(x)                (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
+#define LP_PERF_COUNTER_EN_SET(x)                (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
+
+#define LP_PERF_LIGHT_SLEEP_ADDRESS              0x00000288
+#define LP_PERF_LIGHT_SLEEP_OFFSET               0x00000288
+#define LP_PERF_LIGHT_SLEEP_CNT_MSB              31
+#define LP_PERF_LIGHT_SLEEP_CNT_LSB              0
+#define LP_PERF_LIGHT_SLEEP_CNT_MASK             0xffffffff
+#define LP_PERF_LIGHT_SLEEP_CNT_GET(x)           (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
+#define LP_PERF_LIGHT_SLEEP_CNT_SET(x)           (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
+
+#define LP_PERF_DEEP_SLEEP_ADDRESS               0x0000028c
+#define LP_PERF_DEEP_SLEEP_OFFSET                0x0000028c
+#define LP_PERF_DEEP_SLEEP_CNT_MSB               31
+#define LP_PERF_DEEP_SLEEP_CNT_LSB               0
+#define LP_PERF_DEEP_SLEEP_CNT_MASK              0xffffffff
+#define LP_PERF_DEEP_SLEEP_CNT_GET(x)            (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
+#define LP_PERF_DEEP_SLEEP_CNT_SET(x)            (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
+
+#define LP_PERF_ON_ADDRESS                       0x00000290
+#define LP_PERF_ON_OFFSET                        0x00000290
+#define LP_PERF_ON_CNT_MSB                       31
+#define LP_PERF_ON_CNT_LSB                       0
+#define LP_PERF_ON_CNT_MASK                      0xffffffff
+#define LP_PERF_ON_CNT_GET(x)                    (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
+#define LP_PERF_ON_CNT_SET(x)                    (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
+
+#define CHIP_MODE_ADDRESS                        0x000002a8
+#define CHIP_MODE_OFFSET                         0x000002a8
+#define CHIP_MODE_BIT_MSB                        1
+#define CHIP_MODE_BIT_LSB                        0
+#define CHIP_MODE_BIT_MASK                       0x00000003
+#define CHIP_MODE_BIT_GET(x)                     (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
+#define CHIP_MODE_BIT_SET(x)                     (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
+
+#define CLK_REQ_FALL_EDGE_ADDRESS                0x000002ac
+#define CLK_REQ_FALL_EDGE_OFFSET                 0x000002ac
+#define CLK_REQ_FALL_EDGE_EN_MSB                 31
+#define CLK_REQ_FALL_EDGE_EN_LSB                 31
+#define CLK_REQ_FALL_EDGE_EN_MASK                0x80000000
+#define CLK_REQ_FALL_EDGE_EN_GET(x)              (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
+#define CLK_REQ_FALL_EDGE_EN_SET(x)              (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
+#define CLK_REQ_FALL_EDGE_DELAY_MSB              7
+#define CLK_REQ_FALL_EDGE_DELAY_LSB              0
+#define CLK_REQ_FALL_EDGE_DELAY_MASK             0x000000ff
+#define CLK_REQ_FALL_EDGE_DELAY_GET(x)           (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
+#define CLK_REQ_FALL_EDGE_DELAY_SET(x)           (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
+
+#define OTP_ADDRESS                              0x000002b0
+#define OTP_OFFSET                               0x000002b0
+#define OTP_LDO25_EN_MSB                         1
+#define OTP_LDO25_EN_LSB                         1
+#define OTP_LDO25_EN_MASK                        0x00000002
+#define OTP_LDO25_EN_GET(x)                      (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
+#define OTP_LDO25_EN_SET(x)                      (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
+#define OTP_VDD12_EN_MSB                         0
+#define OTP_VDD12_EN_LSB                         0
+#define OTP_VDD12_EN_MASK                        0x00000001
+#define OTP_VDD12_EN_GET(x)                      (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
+#define OTP_VDD12_EN_SET(x)                      (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
+
+#define OTP_STATUS_ADDRESS                       0x000002b4
+#define OTP_STATUS_OFFSET                        0x000002b4
+#define OTP_STATUS_LDO25_EN_READY_MSB            1
+#define OTP_STATUS_LDO25_EN_READY_LSB            1
+#define OTP_STATUS_LDO25_EN_READY_MASK           0x00000002
+#define OTP_STATUS_LDO25_EN_READY_GET(x)         (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
+#define OTP_STATUS_LDO25_EN_READY_SET(x)         (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
+#define OTP_STATUS_VDD12_EN_READY_MSB            0
+#define OTP_STATUS_VDD12_EN_READY_LSB            0
+#define OTP_STATUS_VDD12_EN_READY_MASK           0x00000001
+#define OTP_STATUS_VDD12_EN_READY_GET(x)         (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
+#define OTP_STATUS_VDD12_EN_READY_SET(x)         (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
+
+#define PMU_ADDRESS                              0x000002b8
+#define PMU_OFFSET                               0x000002b8
+#define PMU_REG_WAKEUP_TIME_SEL_MSB              1
+#define PMU_REG_WAKEUP_TIME_SEL_LSB              0
+#define PMU_REG_WAKEUP_TIME_SEL_MASK             0x00000003
+#define PMU_REG_WAKEUP_TIME_SEL_GET(x)           (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
+#define PMU_REG_WAKEUP_TIME_SEL_SET(x)           (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
+
+#define PMU_CONFIG_ADDRESS                       0x000002bc
+#define PMU_CONFIG_OFFSET                        0x000002bc
+#define PMU_CONFIG_VALUE_MSB                     4
+#define PMU_CONFIG_VALUE_LSB                     0
+#define PMU_CONFIG_VALUE_MASK                    0x0000001f
+#define PMU_CONFIG_VALUE_GET(x)                  (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
+#define PMU_CONFIG_VALUE_SET(x)                  (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
+
+#define PMU_PAREG_ADDRESS                        0x000002c0
+#define PMU_PAREG_OFFSET                         0x000002c0
+#define PMU_PAREG_LVL_CTR_MSB                    2
+#define PMU_PAREG_LVL_CTR_LSB                    0
+#define PMU_PAREG_LVL_CTR_MASK                   0x00000007
+#define PMU_PAREG_LVL_CTR_GET(x)                 (((x) & PMU_PAREG_LVL_CTR_MASK) >> PMU_PAREG_LVL_CTR_LSB)
+#define PMU_PAREG_LVL_CTR_SET(x)                 (((x) << PMU_PAREG_LVL_CTR_LSB) & PMU_PAREG_LVL_CTR_MASK)
+
+#define PMU_BYPASS_ADDRESS                       0x000002c4
+#define PMU_BYPASS_OFFSET                        0x000002c4
+#define PMU_BYPASS_SWREG_MSB                     2
+#define PMU_BYPASS_SWREG_LSB                     2
+#define PMU_BYPASS_SWREG_MASK                    0x00000004
+#define PMU_BYPASS_SWREG_GET(x)                  (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
+#define PMU_BYPASS_SWREG_SET(x)                  (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
+#define PMU_BYPASS_DREG_MSB                      1
+#define PMU_BYPASS_DREG_LSB                      1
+#define PMU_BYPASS_DREG_MASK                     0x00000002
+#define PMU_BYPASS_DREG_GET(x)                   (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
+#define PMU_BYPASS_DREG_SET(x)                   (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
+#define PMU_BYPASS_PAREG_MSB                     0
+#define PMU_BYPASS_PAREG_LSB                     0
+#define PMU_BYPASS_PAREG_MASK                    0x00000001
+#define PMU_BYPASS_PAREG_GET(x)                  (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
+#define PMU_BYPASS_PAREG_SET(x)                  (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
+
+#define THERM_CTRL1_ADDRESS                      0x000002dc
+#define THERM_CTRL1_OFFSET                       0x000002dc
+#define THERM_CTRL1_BYPASS_MSB                   16
+#define THERM_CTRL1_BYPASS_LSB                   16
+#define THERM_CTRL1_BYPASS_MASK                  0x00010000
+#define THERM_CTRL1_BYPASS_GET(x)                (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
+#define THERM_CTRL1_BYPASS_SET(x)                (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
+#define THERM_CTRL1_WIDTH_ARBITOR_MSB            15
+#define THERM_CTRL1_WIDTH_ARBITOR_LSB            12
+#define THERM_CTRL1_WIDTH_ARBITOR_MASK           0x0000f000
+#define THERM_CTRL1_WIDTH_ARBITOR_GET(x)         (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
+#define THERM_CTRL1_WIDTH_ARBITOR_SET(x)         (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
+#define THERM_CTRL1_WIDTH_MSB                    11
+#define THERM_CTRL1_WIDTH_LSB                    5
+#define THERM_CTRL1_WIDTH_MASK                   0x00000fe0
+#define THERM_CTRL1_WIDTH_GET(x)                 (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
+#define THERM_CTRL1_WIDTH_SET(x)                 (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
+#define THERM_CTRL1_TYPE_MSB                     4
+#define THERM_CTRL1_TYPE_LSB                     3
+#define THERM_CTRL1_TYPE_MASK                    0x00000018
+#define THERM_CTRL1_TYPE_GET(x)                  (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
+#define THERM_CTRL1_TYPE_SET(x)                  (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
+#define THERM_CTRL1_MEASURE_MSB                  2
+#define THERM_CTRL1_MEASURE_LSB                  2
+#define THERM_CTRL1_MEASURE_MASK                 0x00000004
+#define THERM_CTRL1_MEASURE_GET(x)               (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
+#define THERM_CTRL1_MEASURE_SET(x)               (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
+#define THERM_CTRL1_INT_EN_MSB                   1
+#define THERM_CTRL1_INT_EN_LSB                   1
+#define THERM_CTRL1_INT_EN_MASK                  0x00000002
+#define THERM_CTRL1_INT_EN_GET(x)                (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
+#define THERM_CTRL1_INT_EN_SET(x)                (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
+#define THERM_CTRL1_INT_STATUS_MSB               0
+#define THERM_CTRL1_INT_STATUS_LSB               0
+#define THERM_CTRL1_INT_STATUS_MASK              0x00000001
+#define THERM_CTRL1_INT_STATUS_GET(x)            (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
+#define THERM_CTRL1_INT_STATUS_SET(x)            (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
+
+#define THERM_CTRL2_ADDRESS                      0x000002e0
+#define THERM_CTRL2_OFFSET                       0x000002e0
+#define THERM_CTRL2_ADC_OFF_MSB                  25
+#define THERM_CTRL2_ADC_OFF_LSB                  25
+#define THERM_CTRL2_ADC_OFF_MASK                 0x02000000
+#define THERM_CTRL2_ADC_OFF_GET(x)               (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
+#define THERM_CTRL2_ADC_OFF_SET(x)               (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
+#define THERM_CTRL2_ADC_ON_MSB                   24
+#define THERM_CTRL2_ADC_ON_LSB                   24
+#define THERM_CTRL2_ADC_ON_MASK                  0x01000000
+#define THERM_CTRL2_ADC_ON_GET(x)                (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
+#define THERM_CTRL2_ADC_ON_SET(x)                (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
+#define THERM_CTRL2_SAMPLE_MSB                   23
+#define THERM_CTRL2_SAMPLE_LSB                   16
+#define THERM_CTRL2_SAMPLE_MASK                  0x00ff0000
+#define THERM_CTRL2_SAMPLE_GET(x)                (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
+#define THERM_CTRL2_SAMPLE_SET(x)                (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
+#define THERM_CTRL2_HIGH_MSB                     15
+#define THERM_CTRL2_HIGH_LSB                     8
+#define THERM_CTRL2_HIGH_MASK                    0x0000ff00
+#define THERM_CTRL2_HIGH_GET(x)                  (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
+#define THERM_CTRL2_HIGH_SET(x)                  (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
+#define THERM_CTRL2_LOW_MSB                      7
+#define THERM_CTRL2_LOW_LSB                      0
+#define THERM_CTRL2_LOW_MASK                     0x000000ff
+#define THERM_CTRL2_LOW_GET(x)                   (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
+#define THERM_CTRL2_LOW_SET(x)                   (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
+
+#define THERM_CTRL3_ADDRESS                      0x000002e4
+#define THERM_CTRL3_OFFSET                       0x000002e4
+#define THERM_CTRL3_ADC_GAIN_MSB                 16
+#define THERM_CTRL3_ADC_GAIN_LSB                 8
+#define THERM_CTRL3_ADC_GAIN_MASK                0x0001ff00
+#define THERM_CTRL3_ADC_GAIN_GET(x)              (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
+#define THERM_CTRL3_ADC_GAIN_SET(x)              (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
+#define THERM_CTRL3_ADC_OFFSET_MSB               7
+#define THERM_CTRL3_ADC_OFFSET_LSB               0
+#define THERM_CTRL3_ADC_OFFSET_MASK              0x000000ff
+#define THERM_CTRL3_ADC_OFFSET_GET(x)            (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
+#define THERM_CTRL3_ADC_OFFSET_SET(x)            (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
+
+#define LISTEN_MODE1_ADDRESS                     0x000002e8
+#define LISTEN_MODE1_OFFSET                      0x000002e8
+#define LISTEN_MODE1_TIMER_CLEAR_MSB             19
+#define LISTEN_MODE1_TIMER_CLEAR_LSB             19
+#define LISTEN_MODE1_TIMER_CLEAR_MASK            0x00080000
+#define LISTEN_MODE1_TIMER_CLEAR_GET(x)          (((x) & LISTEN_MODE1_TIMER_CLEAR_MASK) >> LISTEN_MODE1_TIMER_CLEAR_LSB)
+#define LISTEN_MODE1_TIMER_CLEAR_SET(x)          (((x) << LISTEN_MODE1_TIMER_CLEAR_LSB) & LISTEN_MODE1_TIMER_CLEAR_MASK)
+#define LISTEN_MODE1_TIMER_THRESH_WAKE_MSB       18
+#define LISTEN_MODE1_TIMER_THRESH_WAKE_LSB       3
+#define LISTEN_MODE1_TIMER_THRESH_WAKE_MASK      0x0007fff8
+#define LISTEN_MODE1_TIMER_THRESH_WAKE_GET(x)    (((x) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK) >> LISTEN_MODE1_TIMER_THRESH_WAKE_LSB)
+#define LISTEN_MODE1_TIMER_THRESH_WAKE_SET(x)    (((x) << LISTEN_MODE1_TIMER_THRESH_WAKE_LSB) & LISTEN_MODE1_TIMER_THRESH_WAKE_MASK)
+#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MSB     2
+#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB     2
+#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK    0x00000004
+#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_GET(x)  (((x) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK) >> LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB)
+#define LISTEN_MODE1_TIMER_OVERFLOW_WAKE_SET(x)  (((x) << LISTEN_MODE1_TIMER_OVERFLOW_WAKE_LSB) & LISTEN_MODE1_TIMER_OVERFLOW_WAKE_MASK)
+#define LISTEN_MODE1_CLOCK_GATE_MSB              1
+#define LISTEN_MODE1_CLOCK_GATE_LSB              1
+#define LISTEN_MODE1_CLOCK_GATE_MASK             0x00000002
+#define LISTEN_MODE1_CLOCK_GATE_GET(x)           (((x) & LISTEN_MODE1_CLOCK_GATE_MASK) >> LISTEN_MODE1_CLOCK_GATE_LSB)
+#define LISTEN_MODE1_CLOCK_GATE_SET(x)           (((x) << LISTEN_MODE1_CLOCK_GATE_LSB) & LISTEN_MODE1_CLOCK_GATE_MASK)
+#define LISTEN_MODE1_ENABLE_MSB                  0
+#define LISTEN_MODE1_ENABLE_LSB                  0
+#define LISTEN_MODE1_ENABLE_MASK                 0x00000001
+#define LISTEN_MODE1_ENABLE_GET(x)               (((x) & LISTEN_MODE1_ENABLE_MASK) >> LISTEN_MODE1_ENABLE_LSB)
+#define LISTEN_MODE1_ENABLE_SET(x)               (((x) << LISTEN_MODE1_ENABLE_LSB) & LISTEN_MODE1_ENABLE_MASK)
+
+#define LISTEN_MODE2_ADDRESS                     0x000002ec
+#define LISTEN_MODE2_OFFSET                      0x000002ec
+#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MSB      15
+#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB      0
+#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK     0x0000ffff
+#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_GET(x)   (((x) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK) >> LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB)
+#define LISTEN_MODE2_TIMER_TRIGGER_WAKE_SET(x)   (((x) << LISTEN_MODE2_TIMER_TRIGGER_WAKE_LSB) & LISTEN_MODE2_TIMER_TRIGGER_WAKE_MASK)
+
+#define AUDIO_PLL_CONFIG_ADDRESS                 0x000002f0
+#define AUDIO_PLL_CONFIG_OFFSET                  0x000002f0
+#define AUDIO_PLL_CONFIG_UPDATING_MSB            31
+#define AUDIO_PLL_CONFIG_UPDATING_LSB            31
+#define AUDIO_PLL_CONFIG_UPDATING_MASK           0x80000000
+#define AUDIO_PLL_CONFIG_UPDATING_GET(x)         (((x) & AUDIO_PLL_CONFIG_UPDATING_MASK) >> AUDIO_PLL_CONFIG_UPDATING_LSB)
+#define AUDIO_PLL_CONFIG_UPDATING_SET(x)         (((x) << AUDIO_PLL_CONFIG_UPDATING_LSB) & AUDIO_PLL_CONFIG_UPDATING_MASK)
+#define AUDIO_PLL_CONFIG_EXT_DIV_MSB             14
+#define AUDIO_PLL_CONFIG_EXT_DIV_LSB             12
+#define AUDIO_PLL_CONFIG_EXT_DIV_MASK            0x00007000
+#define AUDIO_PLL_CONFIG_EXT_DIV_GET(x)          (((x) & AUDIO_PLL_CONFIG_EXT_DIV_MASK) >> AUDIO_PLL_CONFIG_EXT_DIV_LSB)
+#define AUDIO_PLL_CONFIG_EXT_DIV_SET(x)          (((x) << AUDIO_PLL_CONFIG_EXT_DIV_LSB) & AUDIO_PLL_CONFIG_EXT_DIV_MASK)
+#define AUDIO_PLL_CONFIG_POSTPLLDIV_MSB          9
+#define AUDIO_PLL_CONFIG_POSTPLLDIV_LSB          7
+#define AUDIO_PLL_CONFIG_POSTPLLDIV_MASK         0x00000380
+#define AUDIO_PLL_CONFIG_POSTPLLDIV_GET(x)       (((x) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK) >> AUDIO_PLL_CONFIG_POSTPLLDIV_LSB)
+#define AUDIO_PLL_CONFIG_POSTPLLDIV_SET(x)       (((x) << AUDIO_PLL_CONFIG_POSTPLLDIV_LSB) & AUDIO_PLL_CONFIG_POSTPLLDIV_MASK)
+#define AUDIO_PLL_CONFIG_PLLPWD_MSB              5
+#define AUDIO_PLL_CONFIG_PLLPWD_LSB              5
+#define AUDIO_PLL_CONFIG_PLLPWD_MASK             0x00000020
+#define AUDIO_PLL_CONFIG_PLLPWD_GET(x)           (((x) & AUDIO_PLL_CONFIG_PLLPWD_MASK) >> AUDIO_PLL_CONFIG_PLLPWD_LSB)
+#define AUDIO_PLL_CONFIG_PLLPWD_SET(x)           (((x) << AUDIO_PLL_CONFIG_PLLPWD_LSB) & AUDIO_PLL_CONFIG_PLLPWD_MASK)
+#define AUDIO_PLL_CONFIG_BYPASS_MSB              4
+#define AUDIO_PLL_CONFIG_BYPASS_LSB              4
+#define AUDIO_PLL_CONFIG_BYPASS_MASK             0x00000010
+#define AUDIO_PLL_CONFIG_BYPASS_GET(x)           (((x) & AUDIO_PLL_CONFIG_BYPASS_MASK) >> AUDIO_PLL_CONFIG_BYPASS_LSB)
+#define AUDIO_PLL_CONFIG_BYPASS_SET(x)           (((x) << AUDIO_PLL_CONFIG_BYPASS_LSB) & AUDIO_PLL_CONFIG_BYPASS_MASK)
+#define AUDIO_PLL_CONFIG_REFDIV_MSB              3
+#define AUDIO_PLL_CONFIG_REFDIV_LSB              0
+#define AUDIO_PLL_CONFIG_REFDIV_MASK             0x0000000f
+#define AUDIO_PLL_CONFIG_REFDIV_GET(x)           (((x) & AUDIO_PLL_CONFIG_REFDIV_MASK) >> AUDIO_PLL_CONFIG_REFDIV_LSB)
+#define AUDIO_PLL_CONFIG_REFDIV_SET(x)           (((x) << AUDIO_PLL_CONFIG_REFDIV_LSB) & AUDIO_PLL_CONFIG_REFDIV_MASK)
+
+#define AUDIO_PLL_MODULATION_ADDRESS             0x000002f4
+#define AUDIO_PLL_MODULATION_OFFSET              0x000002f4
+#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MSB    28
+#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB    11
+#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK   0x1ffff800
+#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_GET(x) (((x) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB)
+#define AUDIO_PLL_MODULATION_TGT_DIV_FRAC_SET(x) (((x) << AUDIO_PLL_MODULATION_TGT_DIV_FRAC_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_FRAC_MASK)
+#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MSB     6
+#define AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB     1
+#define AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK    0x0000007e
+#define AUDIO_PLL_MODULATION_TGT_DIV_INT_GET(x)  (((x) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK) >> AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB)
+#define AUDIO_PLL_MODULATION_TGT_DIV_INT_SET(x)  (((x) << AUDIO_PLL_MODULATION_TGT_DIV_INT_LSB) & AUDIO_PLL_MODULATION_TGT_DIV_INT_MASK)
+#define AUDIO_PLL_MODULATION_START_MSB           0
+#define AUDIO_PLL_MODULATION_START_LSB           0
+#define AUDIO_PLL_MODULATION_START_MASK          0x00000001
+#define AUDIO_PLL_MODULATION_START_GET(x)        (((x) & AUDIO_PLL_MODULATION_START_MASK) >> AUDIO_PLL_MODULATION_START_LSB)
+#define AUDIO_PLL_MODULATION_START_SET(x)        (((x) << AUDIO_PLL_MODULATION_START_LSB) & AUDIO_PLL_MODULATION_START_MASK)
+
+#define AUDIO_PLL_MOD_STEP_ADDRESS               0x000002f8
+#define AUDIO_PLL_MOD_STEP_OFFSET                0x000002f8
+#define AUDIO_PLL_MOD_STEP_FRAC_MSB              31
+#define AUDIO_PLL_MOD_STEP_FRAC_LSB              14
+#define AUDIO_PLL_MOD_STEP_FRAC_MASK             0xffffc000
+#define AUDIO_PLL_MOD_STEP_FRAC_GET(x)           (((x) & AUDIO_PLL_MOD_STEP_FRAC_MASK) >> AUDIO_PLL_MOD_STEP_FRAC_LSB)
+#define AUDIO_PLL_MOD_STEP_FRAC_SET(x)           (((x) << AUDIO_PLL_MOD_STEP_FRAC_LSB) & AUDIO_PLL_MOD_STEP_FRAC_MASK)
+#define AUDIO_PLL_MOD_STEP_INT_MSB               13
+#define AUDIO_PLL_MOD_STEP_INT_LSB               4
+#define AUDIO_PLL_MOD_STEP_INT_MASK              0x00003ff0
+#define AUDIO_PLL_MOD_STEP_INT_GET(x)            (((x) & AUDIO_PLL_MOD_STEP_INT_MASK) >> AUDIO_PLL_MOD_STEP_INT_LSB)
+#define AUDIO_PLL_MOD_STEP_INT_SET(x)            (((x) << AUDIO_PLL_MOD_STEP_INT_LSB) & AUDIO_PLL_MOD_STEP_INT_MASK)
+#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MSB        3
+#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB        0
+#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK       0x0000000f
+#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_GET(x)     (((x) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK) >> AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB)
+#define AUDIO_PLL_MOD_STEP_UPDATE_CNT_SET(x)     (((x) << AUDIO_PLL_MOD_STEP_UPDATE_CNT_LSB) & AUDIO_PLL_MOD_STEP_UPDATE_CNT_MASK)
+
+#define CURRENT_AUDIO_PLL_MODULATION_ADDRESS     0x000002fc
+#define CURRENT_AUDIO_PLL_MODULATION_OFFSET      0x000002fc
+#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MSB    27
+#define CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB    10
+#define CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK   0x0ffffc00
+#define CURRENT_AUDIO_PLL_MODULATION_FRAC_GET(x) (((x) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK) >> CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB)
+#define CURRENT_AUDIO_PLL_MODULATION_FRAC_SET(x) (((x) << CURRENT_AUDIO_PLL_MODULATION_FRAC_LSB) & CURRENT_AUDIO_PLL_MODULATION_FRAC_MASK)
+#define CURRENT_AUDIO_PLL_MODULATION_INT_MSB     6
+#define CURRENT_AUDIO_PLL_MODULATION_INT_LSB     1
+#define CURRENT_AUDIO_PLL_MODULATION_INT_MASK    0x0000007e
+#define CURRENT_AUDIO_PLL_MODULATION_INT_GET(x)  (((x) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK) >> CURRENT_AUDIO_PLL_MODULATION_INT_LSB)
+#define CURRENT_AUDIO_PLL_MODULATION_INT_SET(x)  (((x) << CURRENT_AUDIO_PLL_MODULATION_INT_LSB) & CURRENT_AUDIO_PLL_MODULATION_INT_MASK)
+
+#define ETH_PLL_CONFIG_ADDRESS                   0x00000300
+#define ETH_PLL_CONFIG_OFFSET                    0x00000300
+#define ETH_PLL_CONFIG_GE0_MASTER_MSB            30
+#define ETH_PLL_CONFIG_GE0_MASTER_LSB            30
+#define ETH_PLL_CONFIG_GE0_MASTER_MASK           0x40000000
+#define ETH_PLL_CONFIG_GE0_MASTER_GET(x)         (((x) & ETH_PLL_CONFIG_GE0_MASTER_MASK) >> ETH_PLL_CONFIG_GE0_MASTER_LSB)
+#define ETH_PLL_CONFIG_GE0_MASTER_SET(x)         (((x) << ETH_PLL_CONFIG_GE0_MASTER_LSB) & ETH_PLL_CONFIG_GE0_MASTER_MASK)
+#define ETH_PLL_CONFIG_GE0_MSB                   29
+#define ETH_PLL_CONFIG_GE0_LSB                   29
+#define ETH_PLL_CONFIG_GE0_MASK                  0x20000000
+#define ETH_PLL_CONFIG_GE0_GET(x)                (((x) & ETH_PLL_CONFIG_GE0_MASK) >> ETH_PLL_CONFIG_GE0_LSB)
+#define ETH_PLL_CONFIG_GE0_SET(x)                (((x) << ETH_PLL_CONFIG_GE0_LSB) & ETH_PLL_CONFIG_GE0_MASK)
+#define ETH_PLL_CONFIG_RANGE_MSB                 28
+#define ETH_PLL_CONFIG_RANGE_LSB                 28
+#define ETH_PLL_CONFIG_RANGE_MASK                0x10000000
+#define ETH_PLL_CONFIG_RANGE_GET(x)              (((x) & ETH_PLL_CONFIG_RANGE_MASK) >> ETH_PLL_CONFIG_RANGE_LSB)
+#define ETH_PLL_CONFIG_RANGE_SET(x)              (((x) << ETH_PLL_CONFIG_RANGE_LSB) & ETH_PLL_CONFIG_RANGE_MASK)
+#define ETH_PLL_CONFIG_FRAC_MSB                  27
+#define ETH_PLL_CONFIG_FRAC_LSB                  18
+#define ETH_PLL_CONFIG_FRAC_MASK                 0x0ffc0000
+#define ETH_PLL_CONFIG_FRAC_GET(x)               (((x) & ETH_PLL_CONFIG_FRAC_MASK) >> ETH_PLL_CONFIG_FRAC_LSB)
+#define ETH_PLL_CONFIG_FRAC_SET(x)               (((x) << ETH_PLL_CONFIG_FRAC_LSB) & ETH_PLL_CONFIG_FRAC_MASK)
+#define ETH_PLL_CONFIG_INT_MSB                   17
+#define ETH_PLL_CONFIG_INT_LSB                   12
+#define ETH_PLL_CONFIG_INT_MASK                  0x0003f000
+#define ETH_PLL_CONFIG_INT_GET(x)                (((x) & ETH_PLL_CONFIG_INT_MASK) >> ETH_PLL_CONFIG_INT_LSB)
+#define ETH_PLL_CONFIG_INT_SET(x)                (((x) << ETH_PLL_CONFIG_INT_LSB) & ETH_PLL_CONFIG_INT_MASK)
+#define ETH_PLL_CONFIG_OUTDIV_MSB                9
+#define ETH_PLL_CONFIG_OUTDIV_LSB                7
+#define ETH_PLL_CONFIG_OUTDIV_MASK               0x00000380
+#define ETH_PLL_CONFIG_OUTDIV_GET(x)             (((x) & ETH_PLL_CONFIG_OUTDIV_MASK) >> ETH_PLL_CONFIG_OUTDIV_LSB)
+#define ETH_PLL_CONFIG_OUTDIV_SET(x)             (((x) << ETH_PLL_CONFIG_OUTDIV_LSB) & ETH_PLL_CONFIG_OUTDIV_MASK)
+#define ETH_PLL_CONFIG_PLLPWD_MSB                6
+#define ETH_PLL_CONFIG_PLLPWD_LSB                6
+#define ETH_PLL_CONFIG_PLLPWD_MASK               0x00000040
+#define ETH_PLL_CONFIG_PLLPWD_GET(x)             (((x) & ETH_PLL_CONFIG_PLLPWD_MASK) >> ETH_PLL_CONFIG_PLLPWD_LSB)
+#define ETH_PLL_CONFIG_PLLPWD_SET(x)             (((x) << ETH_PLL_CONFIG_PLLPWD_LSB) & ETH_PLL_CONFIG_PLLPWD_MASK)
+#define ETH_PLL_CONFIG_BYPASS_MSB                5
+#define ETH_PLL_CONFIG_BYPASS_LSB                5
+#define ETH_PLL_CONFIG_BYPASS_MASK               0x00000020
+#define ETH_PLL_CONFIG_BYPASS_GET(x)             (((x) & ETH_PLL_CONFIG_BYPASS_MASK) >> ETH_PLL_CONFIG_BYPASS_LSB)
+#define ETH_PLL_CONFIG_BYPASS_SET(x)             (((x) << ETH_PLL_CONFIG_BYPASS_LSB) & ETH_PLL_CONFIG_BYPASS_MASK)
+#define ETH_PLL_CONFIG_REFDIV_MSB                4
+#define ETH_PLL_CONFIG_REFDIV_LSB                0
+#define ETH_PLL_CONFIG_REFDIV_MASK               0x0000001f
+#define ETH_PLL_CONFIG_REFDIV_GET(x)             (((x) & ETH_PLL_CONFIG_REFDIV_MASK) >> ETH_PLL_CONFIG_REFDIV_LSB)
+#define ETH_PLL_CONFIG_REFDIV_SET(x)             (((x) << ETH_PLL_CONFIG_REFDIV_LSB) & ETH_PLL_CONFIG_REFDIV_MASK)
+
+#define CPU_PLL_CONFIG_ADDRESS                   0x00000304
+#define CPU_PLL_CONFIG_OFFSET                    0x00000304
+#define CPU_PLL_CONFIG_RANGE_MSB                 28
+#define CPU_PLL_CONFIG_RANGE_LSB                 28
+#define CPU_PLL_CONFIG_RANGE_MASK                0x10000000
+#define CPU_PLL_CONFIG_RANGE_GET(x)              (((x) & CPU_PLL_CONFIG_RANGE_MASK) >> CPU_PLL_CONFIG_RANGE_LSB)
+#define CPU_PLL_CONFIG_RANGE_SET(x)              (((x) << CPU_PLL_CONFIG_RANGE_LSB) & CPU_PLL_CONFIG_RANGE_MASK)
+#define CPU_PLL_CONFIG_FRAC_MSB                  25
+#define CPU_PLL_CONFIG_FRAC_LSB                  20
+#define CPU_PLL_CONFIG_FRAC_MASK                 0x03f00000
+#define CPU_PLL_CONFIG_FRAC_GET(x)               (((x) & CPU_PLL_CONFIG_FRAC_MASK) >> CPU_PLL_CONFIG_FRAC_LSB)
+#define CPU_PLL_CONFIG_FRAC_SET(x)               (((x) << CPU_PLL_CONFIG_FRAC_LSB) & CPU_PLL_CONFIG_FRAC_MASK)
+#define CPU_PLL_CONFIG_INT_MSB                   17
+#define CPU_PLL_CONFIG_INT_LSB                   12
+#define CPU_PLL_CONFIG_INT_MASK                  0x0003f000
+#define CPU_PLL_CONFIG_INT_GET(x)                (((x) & CPU_PLL_CONFIG_INT_MASK) >> CPU_PLL_CONFIG_INT_LSB)
+#define CPU_PLL_CONFIG_INT_SET(x)                (((x) << CPU_PLL_CONFIG_INT_LSB) & CPU_PLL_CONFIG_INT_MASK)
+#define CPU_PLL_CONFIG_OUTDIV_MSB                9
+#define CPU_PLL_CONFIG_OUTDIV_LSB                7
+#define CPU_PLL_CONFIG_OUTDIV_MASK               0x00000380
+#define CPU_PLL_CONFIG_OUTDIV_GET(x)             (((x) & CPU_PLL_CONFIG_OUTDIV_MASK) >> CPU_PLL_CONFIG_OUTDIV_LSB)
+#define CPU_PLL_CONFIG_OUTDIV_SET(x)             (((x) << CPU_PLL_CONFIG_OUTDIV_LSB) & CPU_PLL_CONFIG_OUTDIV_MASK)
+#define CPU_PLL_CONFIG_PLLPWD_MSB                6
+#define CPU_PLL_CONFIG_PLLPWD_LSB                6
+#define CPU_PLL_CONFIG_PLLPWD_MASK               0x00000040
+#define CPU_PLL_CONFIG_PLLPWD_GET(x)             (((x) & CPU_PLL_CONFIG_PLLPWD_MASK) >> CPU_PLL_CONFIG_PLLPWD_LSB)
+#define CPU_PLL_CONFIG_PLLPWD_SET(x)             (((x) << CPU_PLL_CONFIG_PLLPWD_LSB) & CPU_PLL_CONFIG_PLLPWD_MASK)
+#define CPU_PLL_CONFIG_REFDIV_MSB                4
+#define CPU_PLL_CONFIG_REFDIV_LSB                0
+#define CPU_PLL_CONFIG_REFDIV_MASK               0x0000001f
+#define CPU_PLL_CONFIG_REFDIV_GET(x)             (((x) & CPU_PLL_CONFIG_REFDIV_MASK) >> CPU_PLL_CONFIG_REFDIV_LSB)
+#define CPU_PLL_CONFIG_REFDIV_SET(x)             (((x) << CPU_PLL_CONFIG_REFDIV_LSB) & CPU_PLL_CONFIG_REFDIV_MASK)
+
+#define BB_PLL_CONFIG_ADDRESS                    0x00000308
+#define BB_PLL_CONFIG_OFFSET                     0x00000308
+#define BB_PLL_CONFIG_FRAC_MSB                   17
+#define BB_PLL_CONFIG_FRAC_LSB                   0
+#define BB_PLL_CONFIG_FRAC_MASK                  0x0003ffff
+#define BB_PLL_CONFIG_FRAC_GET(x)                (((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
+#define BB_PLL_CONFIG_FRAC_SET(x)                (((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
+
+#define ETH_XMII_ADDRESS                         0x0000030c
+#define ETH_XMII_OFFSET                          0x0000030c
+#define ETH_XMII_TX_INVERT_MSB                   31
+#define ETH_XMII_TX_INVERT_LSB                   31
+#define ETH_XMII_TX_INVERT_MASK                  0x80000000
+#define ETH_XMII_TX_INVERT_GET(x)                (((x) & ETH_XMII_TX_INVERT_MASK) >> ETH_XMII_TX_INVERT_LSB)
+#define ETH_XMII_TX_INVERT_SET(x)                (((x) << ETH_XMII_TX_INVERT_LSB) & ETH_XMII_TX_INVERT_MASK)
+#define ETH_XMII_GIGE_QUAD_MSB                   30
+#define ETH_XMII_GIGE_QUAD_LSB                   30
+#define ETH_XMII_GIGE_QUAD_MASK                  0x40000000
+#define ETH_XMII_GIGE_QUAD_GET(x)                (((x) & ETH_XMII_GIGE_QUAD_MASK) >> ETH_XMII_GIGE_QUAD_LSB)
+#define ETH_XMII_GIGE_QUAD_SET(x)                (((x) << ETH_XMII_GIGE_QUAD_LSB) & ETH_XMII_GIGE_QUAD_MASK)
+#define ETH_XMII_RX_DELAY_MSB                    29
+#define ETH_XMII_RX_DELAY_LSB                    28
+#define ETH_XMII_RX_DELAY_MASK                   0x30000000
+#define ETH_XMII_RX_DELAY_GET(x)                 (((x) & ETH_XMII_RX_DELAY_MASK) >> ETH_XMII_RX_DELAY_LSB)
+#define ETH_XMII_RX_DELAY_SET(x)                 (((x) << ETH_XMII_RX_DELAY_LSB) & ETH_XMII_RX_DELAY_MASK)
+#define ETH_XMII_TX_DELAY_MSB                    27
+#define ETH_XMII_TX_DELAY_LSB                    26
+#define ETH_XMII_TX_DELAY_MASK                   0x0c000000
+#define ETH_XMII_TX_DELAY_GET(x)                 (((x) & ETH_XMII_TX_DELAY_MASK) >> ETH_XMII_TX_DELAY_LSB)
+#define ETH_XMII_TX_DELAY_SET(x)                 (((x) << ETH_XMII_TX_DELAY_LSB) & ETH_XMII_TX_DELAY_MASK)
+#define ETH_XMII_GIGE_MSB                        25
+#define ETH_XMII_GIGE_LSB                        25
+#define ETH_XMII_GIGE_MASK                       0x02000000
+#define ETH_XMII_GIGE_GET(x)                     (((x) & ETH_XMII_GIGE_MASK) >> ETH_XMII_GIGE_LSB)
+#define ETH_XMII_GIGE_SET(x)                     (((x) << ETH_XMII_GIGE_LSB) & ETH_XMII_GIGE_MASK)
+#define ETH_XMII_OFFSET_PHASE_MSB                24
+#define ETH_XMII_OFFSET_PHASE_LSB                24
+#define ETH_XMII_OFFSET_PHASE_MASK               0x01000000
+#define ETH_XMII_OFFSET_PHASE_GET(x)             (((x) & ETH_XMII_OFFSET_PHASE_MASK) >> ETH_XMII_OFFSET_PHASE_LSB)
+#define ETH_XMII_OFFSET_PHASE_SET(x)             (((x) << ETH_XMII_OFFSET_PHASE_LSB) & ETH_XMII_OFFSET_PHASE_MASK)
+#define ETH_XMII_OFFSET_COUNT_MSB                23
+#define ETH_XMII_OFFSET_COUNT_LSB                16
+#define ETH_XMII_OFFSET_COUNT_MASK               0x00ff0000
+#define ETH_XMII_OFFSET_COUNT_GET(x)             (((x) & ETH_XMII_OFFSET_COUNT_MASK) >> ETH_XMII_OFFSET_COUNT_LSB)
+#define ETH_XMII_OFFSET_COUNT_SET(x)             (((x) << ETH_XMII_OFFSET_COUNT_LSB) & ETH_XMII_OFFSET_COUNT_MASK)
+#define ETH_XMII_PHASE1_COUNT_MSB                15
+#define ETH_XMII_PHASE1_COUNT_LSB                8
+#define ETH_XMII_PHASE1_COUNT_MASK               0x0000ff00
+#define ETH_XMII_PHASE1_COUNT_GET(x)             (((x) & ETH_XMII_PHASE1_COUNT_MASK) >> ETH_XMII_PHASE1_COUNT_LSB)
+#define ETH_XMII_PHASE1_COUNT_SET(x)             (((x) << ETH_XMII_PHASE1_COUNT_LSB) & ETH_XMII_PHASE1_COUNT_MASK)
+#define ETH_XMII_PHASE0_COUNT_MSB                7
+#define ETH_XMII_PHASE0_COUNT_LSB                0
+#define ETH_XMII_PHASE0_COUNT_MASK               0x000000ff
+#define ETH_XMII_PHASE0_COUNT_GET(x)             (((x) & ETH_XMII_PHASE0_COUNT_MASK) >> ETH_XMII_PHASE0_COUNT_LSB)
+#define ETH_XMII_PHASE0_COUNT_SET(x)             (((x) << ETH_XMII_PHASE0_COUNT_LSB) & ETH_XMII_PHASE0_COUNT_MASK)
+
+#define USB_PHY_CONFIG_ADDRESS                   0x00000310
+#define USB_PHY_CONFIG_OFFSET                    0x00000310
+#define USB_PHY_CONFIG_REFCLK_SEL_MSB            7
+#define USB_PHY_CONFIG_REFCLK_SEL_LSB            4
+#define USB_PHY_CONFIG_REFCLK_SEL_MASK           0x000000f0
+#define USB_PHY_CONFIG_REFCLK_SEL_GET(x)         (((x) & USB_PHY_CONFIG_REFCLK_SEL_MASK) >> USB_PHY_CONFIG_REFCLK_SEL_LSB)
+#define USB_PHY_CONFIG_REFCLK_SEL_SET(x)         (((x) << USB_PHY_CONFIG_REFCLK_SEL_LSB) & USB_PHY_CONFIG_REFCLK_SEL_MASK)
+#define USB_PHY_CONFIG_REFDIV_MSB                3
+#define USB_PHY_CONFIG_REFDIV_LSB                3
+#define USB_PHY_CONFIG_REFDIV_MASK               0x00000008
+#define USB_PHY_CONFIG_REFDIV_GET(x)             (((x) & USB_PHY_CONFIG_REFDIV_MASK) >> USB_PHY_CONFIG_REFDIV_LSB)
+#define USB_PHY_CONFIG_REFDIV_SET(x)             (((x) << USB_PHY_CONFIG_REFDIV_LSB) & USB_PHY_CONFIG_REFDIV_MASK)
+#define USB_PHY_CONFIG_TESTMODE_MSB              2
+#define USB_PHY_CONFIG_TESTMODE_LSB              2
+#define USB_PHY_CONFIG_TESTMODE_MASK             0x00000004
+#define USB_PHY_CONFIG_TESTMODE_GET(x)           (((x) & USB_PHY_CONFIG_TESTMODE_MASK) >> USB_PHY_CONFIG_TESTMODE_LSB)
+#define USB_PHY_CONFIG_TESTMODE_SET(x)           (((x) << USB_PHY_CONFIG_TESTMODE_LSB) & USB_PHY_CONFIG_TESTMODE_MASK)
+#define USB_PHY_CONFIG_PLL_PWD_MSB               1
+#define USB_PHY_CONFIG_PLL_PWD_LSB               1
+#define USB_PHY_CONFIG_PLL_PWD_MASK              0x00000002
+#define USB_PHY_CONFIG_PLL_PWD_GET(x)            (((x) & USB_PHY_CONFIG_PLL_PWD_MASK) >> USB_PHY_CONFIG_PLL_PWD_LSB)
+#define USB_PHY_CONFIG_PLL_PWD_SET(x)            (((x) << USB_PHY_CONFIG_PLL_PWD_LSB) & USB_PHY_CONFIG_PLL_PWD_MASK)
+#define USB_PHY_CONFIG_HOSTMODE_MSB              0
+#define USB_PHY_CONFIG_HOSTMODE_LSB              0
+#define USB_PHY_CONFIG_HOSTMODE_MASK             0x00000001
+#define USB_PHY_CONFIG_HOSTMODE_GET(x)           (((x) & USB_PHY_CONFIG_HOSTMODE_MASK) >> USB_PHY_CONFIG_HOSTMODE_LSB)
+#define USB_PHY_CONFIG_HOSTMODE_SET(x)           (((x) << USB_PHY_CONFIG_HOSTMODE_LSB) & USB_PHY_CONFIG_HOSTMODE_MASK)
+
+#define USBCORE_CLK60M_ADDRESS                   0x00000314
+#define USBCORE_CLK60M_OFFSET                    0x00000314
+#define USBCORE_CLK60M_SEL_MSB                   0
+#define USBCORE_CLK60M_SEL_LSB                   0
+#define USBCORE_CLK60M_SEL_MASK                  0x00000001
+#define USBCORE_CLK60M_SEL_GET(x)                (((x) & USBCORE_CLK60M_SEL_MASK) >> USBCORE_CLK60M_SEL_LSB)
+#define USBCORE_CLK60M_SEL_SET(x)                (((x) << USBCORE_CLK60M_SEL_LSB) & USBCORE_CLK60M_SEL_MASK)
+
+#define USBPHY_UTMI_CLK_ADDRESS                  0x00000318
+#define USBPHY_UTMI_CLK_OFFSET                   0x00000318
+#define USBPHY_UTMI_CLK_EN_MSB                   0
+#define USBPHY_UTMI_CLK_EN_LSB                   0
+#define USBPHY_UTMI_CLK_EN_MASK                  0x00000001
+#define USBPHY_UTMI_CLK_EN_GET(x)                (((x) & USBPHY_UTMI_CLK_EN_MASK) >> USBPHY_UTMI_CLK_EN_LSB)
+#define USBPHY_UTMI_CLK_EN_SET(x)                (((x) << USBPHY_UTMI_CLK_EN_LSB) & USBPHY_UTMI_CLK_EN_MASK)
+
+#define USB_TXVALID_DLY_CONFIG_ADDRESS           0x0000031c
+#define USB_TXVALID_DLY_CONFIG_OFFSET            0x0000031c
+#define USB_TXVALID_DLY_CONFIG_UTMI16_MSB        7
+#define USB_TXVALID_DLY_CONFIG_UTMI16_LSB        4
+#define USB_TXVALID_DLY_CONFIG_UTMI16_MASK       0x000000f0
+#define USB_TXVALID_DLY_CONFIG_UTMI16_GET(x)     (((x) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI16_LSB)
+#define USB_TXVALID_DLY_CONFIG_UTMI16_SET(x)     (((x) << USB_TXVALID_DLY_CONFIG_UTMI16_LSB) & USB_TXVALID_DLY_CONFIG_UTMI16_MASK)
+#define USB_TXVALID_DLY_CONFIG_UTMI8_MSB         3
+#define USB_TXVALID_DLY_CONFIG_UTMI8_LSB         0
+#define USB_TXVALID_DLY_CONFIG_UTMI8_MASK        0x0000000f
+#define USB_TXVALID_DLY_CONFIG_UTMI8_GET(x)      (((x) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK) >> USB_TXVALID_DLY_CONFIG_UTMI8_LSB)
+#define USB_TXVALID_DLY_CONFIG_UTMI8_SET(x)      (((x) << USB_TXVALID_DLY_CONFIG_UTMI8_LSB) & USB_TXVALID_DLY_CONFIG_UTMI8_MASK)
+
+#define SECOND_HOST_INFT_ADDRESS                 0x00000320
+#define SECOND_HOST_INFT_OFFSET                  0x00000320
+#define SECOND_HOST_INFT_SDIO_MODE_MSB           0
+#define SECOND_HOST_INFT_SDIO_MODE_LSB           0
+#define SECOND_HOST_INFT_SDIO_MODE_MASK          0x00000001
+#define SECOND_HOST_INFT_SDIO_MODE_GET(x)        (((x) & SECOND_HOST_INFT_SDIO_MODE_MASK) >> SECOND_HOST_INFT_SDIO_MODE_LSB)
+#define SECOND_HOST_INFT_SDIO_MODE_SET(x)        (((x) << SECOND_HOST_INFT_SDIO_MODE_LSB) & SECOND_HOST_INFT_SDIO_MODE_MASK)
+
+#define SDIO_HOST_ADDRESS                        0x00000324
+#define SDIO_HOST_OFFSET                         0x00000324
+#define SDIO_HOST_RESET_MSB                      0
+#define SDIO_HOST_RESET_LSB                      0
+#define SDIO_HOST_RESET_MASK                     0x00000001
+#define SDIO_HOST_RESET_GET(x)                   (((x) & SDIO_HOST_RESET_MASK) >> SDIO_HOST_RESET_LSB)
+#define SDIO_HOST_RESET_SET(x)                   (((x) << SDIO_HOST_RESET_LSB) & SDIO_HOST_RESET_MASK)
+
+#define ENTERPRISE_CONFIG_ADDRESS                0x00000328
+#define ENTERPRISE_CONFIG_OFFSET                 0x00000328
+#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MSB 12
+#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB 12
+#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK 0x00001000
+#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_GET(x) (((x) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK) >> ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB)
+#define ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_SET(x) (((x) << ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_LSB) & ENTERPRISE_CONFIG_TPC_LOWER_PERFORMANCE_MASK)
+#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MSB    11
+#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB    11
+#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK   0x00000800
+#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_GET(x) (((x) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK) >> ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB)
+#define ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_SET(x) (((x) << ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_LSB) & ENTERPRISE_CONFIG_SWCOM_IDLE_MODE_MASK)
+#define ENTERPRISE_CONFIG_STBC_DISABLE_MSB       10
+#define ENTERPRISE_CONFIG_STBC_DISABLE_LSB       10
+#define ENTERPRISE_CONFIG_STBC_DISABLE_MASK      0x00000400
+#define ENTERPRISE_CONFIG_STBC_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK) >> ENTERPRISE_CONFIG_STBC_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_STBC_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_STBC_DISABLE_LSB) & ENTERPRISE_CONFIG_STBC_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_LDPC_DISABLE_MSB       9
+#define ENTERPRISE_CONFIG_LDPC_DISABLE_LSB       9
+#define ENTERPRISE_CONFIG_LDPC_DISABLE_MASK      0x00000200
+#define ENTERPRISE_CONFIG_LDPC_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK) >> ENTERPRISE_CONFIG_LDPC_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_LDPC_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_LDPC_DISABLE_LSB) & ENTERPRISE_CONFIG_LDPC_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MSB   8
+#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB   8
+#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK  0x00000100
+#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK) >> ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_GREEN_TX_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_GREEN_TX_DISABLE_LSB) & ENTERPRISE_CONFIG_GREEN_TX_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MSB  7
+#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB  7
+#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK 0x00000080
+#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK) >> ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_LSB) & ENTERPRISE_CONFIG_DUAL_BAND_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MSB     6
+#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB     6
+#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK    0x00000040
+#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_GET(x)  (((x) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK) >> ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_CHAIN1_DISABLE_SET(x)  (((x) << ENTERPRISE_CONFIG_CHAIN1_DISABLE_LSB) & ENTERPRISE_CONFIG_CHAIN1_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MSB    5
+#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB    5
+#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK   0x00000020
+#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_5MHZ_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MSB   4
+#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB   4
+#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK  0x00000010
+#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK) >> ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_LSB) & ENTERPRISE_CONFIG_CH_10MHZ_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_TXBF_DISABLE_MSB       3
+#define ENTERPRISE_CONFIG_TXBF_DISABLE_LSB       3
+#define ENTERPRISE_CONFIG_TXBF_DISABLE_MASK      0x00000008
+#define ENTERPRISE_CONFIG_TXBF_DISABLE_GET(x)    (((x) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK) >> ENTERPRISE_CONFIG_TXBF_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_TXBF_DISABLE_SET(x)    (((x) << ENTERPRISE_CONFIG_TXBF_DISABLE_LSB) & ENTERPRISE_CONFIG_TXBF_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MSB 2
+#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB 2
+#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK 0x00000004
+#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK) >> ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_LSB) & ENTERPRISE_CONFIG_MIN_PKT_SIZE_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MSB   1
+#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB   1
+#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK  0x00000002
+#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_LOOPBACK_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOOPBACK_DISABLE_LSB) & ENTERPRISE_CONFIG_LOOPBACK_DISABLE_MASK)
+#define ENTERPRISE_CONFIG_LOCATION_DISABLE_MSB   0
+#define ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB   0
+#define ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK  0x00000001
+#define ENTERPRISE_CONFIG_LOCATION_DISABLE_GET(x) (((x) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK) >> ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB)
+#define ENTERPRISE_CONFIG_LOCATION_DISABLE_SET(x) (((x) << ENTERPRISE_CONFIG_LOCATION_DISABLE_LSB) & ENTERPRISE_CONFIG_LOCATION_DISABLE_MASK)
+
+#define RTC_DEBUG_BUS_ADDRESS                    0x0000032c
+#define RTC_DEBUG_BUS_OFFSET                     0x0000032c
+#define RTC_DEBUG_BUS_SEL_MSB                    0
+#define RTC_DEBUG_BUS_SEL_LSB                    0
+#define RTC_DEBUG_BUS_SEL_MASK                   0x00000001
+#define RTC_DEBUG_BUS_SEL_GET(x)                 (((x) & RTC_DEBUG_BUS_SEL_MASK) >> RTC_DEBUG_BUS_SEL_LSB)
+#define RTC_DEBUG_BUS_SEL_SET(x)                 (((x) << RTC_DEBUG_BUS_SEL_LSB) & RTC_DEBUG_BUS_SEL_MASK)
+
+#define RTC_EXT_CLK_BUF_ADDRESS                  0x00000330
+#define RTC_EXT_CLK_BUF_OFFSET                   0x00000330
+#define RTC_EXT_CLK_BUF_EN_MSB                   0
+#define RTC_EXT_CLK_BUF_EN_LSB                   0
+#define RTC_EXT_CLK_BUF_EN_MASK                  0x00000001
+#define RTC_EXT_CLK_BUF_EN_GET(x)                (((x) & RTC_EXT_CLK_BUF_EN_MASK) >> RTC_EXT_CLK_BUF_EN_LSB)
+#define RTC_EXT_CLK_BUF_EN_SET(x)                (((x) << RTC_EXT_CLK_BUF_EN_LSB) & RTC_EXT_CLK_BUF_EN_MASK)
+
+#define WLAN_AHB_BRIDGE_TIMEOUT_ADDRESS          0x00000334
+#define WLAN_AHB_BRIDGE_TIMEOUT_OFFSET           0x00000334
+#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MSB       13
+#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB       0
+#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK      0x00003fff
+#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_GET(x)    (((x) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK) >> WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB)
+#define WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_SET(x)    (((x) << WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_LSB) & WLAN_AHB_BRIDGE_TIMEOUT_CONFIG_MASK)
+
+#define WLAN_AHB_CONFIG_ADDRESS                  0x00000338
+#define WLAN_AHB_CONFIG_OFFSET                   0x00000338
+#define WLAN_AHB_CONFIG_MAX_BURST_16_MSB         2
+#define WLAN_AHB_CONFIG_MAX_BURST_16_LSB         2
+#define WLAN_AHB_CONFIG_MAX_BURST_16_MASK        0x00000004
+#define WLAN_AHB_CONFIG_MAX_BURST_16_GET(x)      (((x) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_16_LSB)
+#define WLAN_AHB_CONFIG_MAX_BURST_16_SET(x)      (((x) << WLAN_AHB_CONFIG_MAX_BURST_16_LSB) & WLAN_AHB_CONFIG_MAX_BURST_16_MASK)
+#define WLAN_AHB_CONFIG_MAX_BURST_8_MSB          1
+#define WLAN_AHB_CONFIG_MAX_BURST_8_LSB          1
+#define WLAN_AHB_CONFIG_MAX_BURST_8_MASK         0x00000002
+#define WLAN_AHB_CONFIG_MAX_BURST_8_GET(x)       (((x) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_8_LSB)
+#define WLAN_AHB_CONFIG_MAX_BURST_8_SET(x)       (((x) << WLAN_AHB_CONFIG_MAX_BURST_8_LSB) & WLAN_AHB_CONFIG_MAX_BURST_8_MASK)
+#define WLAN_AHB_CONFIG_MAX_BURST_4_MSB          0
+#define WLAN_AHB_CONFIG_MAX_BURST_4_LSB          0
+#define WLAN_AHB_CONFIG_MAX_BURST_4_MASK         0x00000001
+#define WLAN_AHB_CONFIG_MAX_BURST_4_GET(x)       (((x) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK) >> WLAN_AHB_CONFIG_MAX_BURST_4_LSB)
+#define WLAN_AHB_CONFIG_MAX_BURST_4_SET(x)       (((x) << WLAN_AHB_CONFIG_MAX_BURST_4_LSB) & WLAN_AHB_CONFIG_MAX_BURST_4_MASK)
+
+#define RTC_AXI_AHB_BRIDGE_ADDRESS               0x0000033c
+#define RTC_AXI_AHB_BRIDGE_OFFSET                0x0000033c
+#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MSB 3
+#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB 3
+#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK 0x00000008
+#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB)
+#define RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_WR_ALIGN_EN_MASK)
+#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MSB 2
+#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB 2
+#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK 0x00000004
+#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_GET(x) (((x) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK) >> RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB)
+#define RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_SET(x) (((x) << RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_LSB) & RTC_AXI_AHB_BRIDGE_BURST_RD_ALIGN_EN_MASK)
+#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MSB         1
+#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB         0
+#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK        0x00000003
+#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_GET(x)      (((x) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK) >> RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB)
+#define RTC_AXI_AHB_BRIDGE_MAX_BEATS_SET(x)      (((x) << RTC_AXI_AHB_BRIDGE_MAX_BEATS_LSB) & RTC_AXI_AHB_BRIDGE_MAX_BEATS_MASK)
+
+#define WLAN2BT_CPUCOM_INT_STS_ADDRESS           0x00000400
+#define WLAN2BT_CPUCOM_INT_STS_OFFSET            0x00000400
+#define WLAN2BT_CPUCOM_INT_STS_REG_MSB           31
+#define WLAN2BT_CPUCOM_INT_STS_REG_LSB           0
+#define WLAN2BT_CPUCOM_INT_STS_REG_MASK          0xffffffff
+#define WLAN2BT_CPUCOM_INT_STS_REG_GET(x)        (((x) & WLAN2BT_CPUCOM_INT_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_STS_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_STS_REG_SET(x)        (((x) << WLAN2BT_CPUCOM_INT_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_STS_REG_MASK)
+
+#define WLAN2BT_CPUCOM_INT_MASK_N_ADDRESS        0x00000404
+#define WLAN2BT_CPUCOM_INT_MASK_N_OFFSET         0x00000404
+#define WLAN2BT_CPUCOM_INT_MASK_N_REG_MSB        31
+#define WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB        0
+#define WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK       0xffffffff
+#define WLAN2BT_CPUCOM_INT_MASK_N_REG_GET(x)     (((x) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_MASK_N_REG_SET(x)     (((x) << WLAN2BT_CPUCOM_INT_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_MASK_N_REG_MASK)
+
+#define WLAN2BT_CPUCOM_INT_EOI_ADDRESS           0x00000408
+#define WLAN2BT_CPUCOM_INT_EOI_OFFSET            0x00000408
+#define WLAN2BT_CPUCOM_INT_EOI_REG_MSB           31
+#define WLAN2BT_CPUCOM_INT_EOI_REG_LSB           0
+#define WLAN2BT_CPUCOM_INT_EOI_REG_MASK          0xffffffff
+#define WLAN2BT_CPUCOM_INT_EOI_REG_GET(x)        (((x) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK) >> WLAN2BT_CPUCOM_INT_EOI_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_EOI_REG_SET(x)        (((x) << WLAN2BT_CPUCOM_INT_EOI_REG_LSB) & WLAN2BT_CPUCOM_INT_EOI_REG_MASK)
+
+#define WLAN2BT_CPUCOM_INT_ACK_STS_ADDRESS       0x0000040c
+#define WLAN2BT_CPUCOM_INT_ACK_STS_OFFSET        0x0000040c
+#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MSB       31
+#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB       0
+#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK      0xffffffff
+#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_GET(x)    (((x) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_ACK_STS_REG_SET(x)    (((x) << WLAN2BT_CPUCOM_INT_ACK_STS_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_STS_REG_MASK)
+
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_ADDRESS    0x00000410
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_OFFSET     0x00000410
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MSB    31
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB    0
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK   0xffffffff
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_GET(x) (((x) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_SET(x) (((x) << WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_MASK_N_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_CNT0_ADDRESS             0x00000414
+#define WLAN_CPUCOM_CRD_CNT0_OFFSET              0x00000414
+#define WLAN_CPUCOM_CRD_CNT0_REG_MSB             15
+#define WLAN_CPUCOM_CRD_CNT0_REG_LSB             0
+#define WLAN_CPUCOM_CRD_CNT0_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_CNT0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_CNT0_REG_MASK) >> WLAN_CPUCOM_CRD_CNT0_REG_LSB)
+#define WLAN_CPUCOM_CRD_CNT0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_CNT0_REG_LSB) & WLAN_CPUCOM_CRD_CNT0_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_INC0_ADDRESS             0x00000418
+#define WLAN_CPUCOM_CRD_INC0_OFFSET              0x00000418
+#define WLAN_CPUCOM_CRD_INC0_REG_MSB             15
+#define WLAN_CPUCOM_CRD_INC0_REG_LSB             0
+#define WLAN_CPUCOM_CRD_INC0_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_INC0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_INC0_REG_MASK) >> WLAN_CPUCOM_CRD_INC0_REG_LSB)
+#define WLAN_CPUCOM_CRD_INC0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_INC0_REG_LSB) & WLAN_CPUCOM_CRD_INC0_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_DEC0_ADDRESS             0x0000041c
+#define WLAN_CPUCOM_CRD_DEC0_OFFSET              0x0000041c
+#define WLAN_CPUCOM_CRD_DEC0_REG_MSB             15
+#define WLAN_CPUCOM_CRD_DEC0_REG_LSB             0
+#define WLAN_CPUCOM_CRD_DEC0_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_DEC0_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_DEC0_REG_MASK) >> WLAN_CPUCOM_CRD_DEC0_REG_LSB)
+#define WLAN_CPUCOM_CRD_DEC0_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_DEC0_REG_LSB) & WLAN_CPUCOM_CRD_DEC0_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_CNT1_ADDRESS             0x00000420
+#define WLAN_CPUCOM_CRD_CNT1_OFFSET              0x00000420
+#define WLAN_CPUCOM_CRD_CNT1_REG_MSB             15
+#define WLAN_CPUCOM_CRD_CNT1_REG_LSB             0
+#define WLAN_CPUCOM_CRD_CNT1_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_CNT1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_CNT1_REG_MASK) >> WLAN_CPUCOM_CRD_CNT1_REG_LSB)
+#define WLAN_CPUCOM_CRD_CNT1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_CNT1_REG_LSB) & WLAN_CPUCOM_CRD_CNT1_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_INC1_ADDRESS             0x00000424
+#define WLAN_CPUCOM_CRD_INC1_OFFSET              0x00000424
+#define WLAN_CPUCOM_CRD_INC1_REG_MSB             15
+#define WLAN_CPUCOM_CRD_INC1_REG_LSB             0
+#define WLAN_CPUCOM_CRD_INC1_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_INC1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_INC1_REG_MASK) >> WLAN_CPUCOM_CRD_INC1_REG_LSB)
+#define WLAN_CPUCOM_CRD_INC1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_INC1_REG_LSB) & WLAN_CPUCOM_CRD_INC1_REG_MASK)
+
+#define WLAN_CPUCOM_CRD_DEC1_ADDRESS             0x00000428
+#define WLAN_CPUCOM_CRD_DEC1_OFFSET              0x00000428
+#define WLAN_CPUCOM_CRD_DEC1_REG_MSB             15
+#define WLAN_CPUCOM_CRD_DEC1_REG_LSB             0
+#define WLAN_CPUCOM_CRD_DEC1_REG_MASK            0x0000ffff
+#define WLAN_CPUCOM_CRD_DEC1_REG_GET(x)          (((x) & WLAN_CPUCOM_CRD_DEC1_REG_MASK) >> WLAN_CPUCOM_CRD_DEC1_REG_LSB)
+#define WLAN_CPUCOM_CRD_DEC1_REG_SET(x)          (((x) << WLAN_CPUCOM_CRD_DEC1_REG_LSB) & WLAN_CPUCOM_CRD_DEC1_REG_MASK)
+
+#define WLAN_CPUCOM_SCRATCH0_ADDRESS             0x0000042c
+#define WLAN_CPUCOM_SCRATCH0_OFFSET              0x0000042c
+#define WLAN_CPUCOM_SCRATCH0_REG_MSB             31
+#define WLAN_CPUCOM_SCRATCH0_REG_LSB             0
+#define WLAN_CPUCOM_SCRATCH0_REG_MASK            0xffffffff
+#define WLAN_CPUCOM_SCRATCH0_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH0_REG_MASK) >> WLAN_CPUCOM_SCRATCH0_REG_LSB)
+#define WLAN_CPUCOM_SCRATCH0_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH0_REG_LSB) & WLAN_CPUCOM_SCRATCH0_REG_MASK)
+
+#define WLAN_CPUCOM_SCRATCH1_ADDRESS             0x00000430
+#define WLAN_CPUCOM_SCRATCH1_OFFSET              0x00000430
+#define WLAN_CPUCOM_SCRATCH1_REG_MSB             31
+#define WLAN_CPUCOM_SCRATCH1_REG_LSB             0
+#define WLAN_CPUCOM_SCRATCH1_REG_MASK            0xffffffff
+#define WLAN_CPUCOM_SCRATCH1_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH1_REG_MASK) >> WLAN_CPUCOM_SCRATCH1_REG_LSB)
+#define WLAN_CPUCOM_SCRATCH1_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH1_REG_LSB) & WLAN_CPUCOM_SCRATCH1_REG_MASK)
+
+#define WLAN_CPUCOM_SCRATCH2_ADDRESS             0x00000434
+#define WLAN_CPUCOM_SCRATCH2_OFFSET              0x00000434
+#define WLAN_CPUCOM_SCRATCH2_REG_MSB             31
+#define WLAN_CPUCOM_SCRATCH2_REG_LSB             0
+#define WLAN_CPUCOM_SCRATCH2_REG_MASK            0xffffffff
+#define WLAN_CPUCOM_SCRATCH2_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH2_REG_MASK) >> WLAN_CPUCOM_SCRATCH2_REG_LSB)
+#define WLAN_CPUCOM_SCRATCH2_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH2_REG_LSB) & WLAN_CPUCOM_SCRATCH2_REG_MASK)
+
+#define WLAN_CPUCOM_SCRATCH3_ADDRESS             0x00000438
+#define WLAN_CPUCOM_SCRATCH3_OFFSET              0x00000438
+#define WLAN_CPUCOM_SCRATCH3_REG_MSB             31
+#define WLAN_CPUCOM_SCRATCH3_REG_LSB             0
+#define WLAN_CPUCOM_SCRATCH3_REG_MASK            0xffffffff
+#define WLAN_CPUCOM_SCRATCH3_REG_GET(x)          (((x) & WLAN_CPUCOM_SCRATCH3_REG_MASK) >> WLAN_CPUCOM_SCRATCH3_REG_LSB)
+#define WLAN_CPUCOM_SCRATCH3_REG_SET(x)          (((x) << WLAN_CPUCOM_SCRATCH3_REG_LSB) & WLAN_CPUCOM_SCRATCH3_REG_MASK)
+
+#define WLAN_CPUCOM_DBG_ADDRESS                  0x0000043c
+#define WLAN_CPUCOM_DBG_OFFSET                   0x0000043c
+#define WLAN_CPUCOM_DBG_RESERVE_MSB              7
+#define WLAN_CPUCOM_DBG_RESERVE_LSB              4
+#define WLAN_CPUCOM_DBG_RESERVE_MASK             0x000000f0
+#define WLAN_CPUCOM_DBG_RESERVE_GET(x)           (((x) & WLAN_CPUCOM_DBG_RESERVE_MASK) >> WLAN_CPUCOM_DBG_RESERVE_LSB)
+#define WLAN_CPUCOM_DBG_RESERVE_SET(x)           (((x) << WLAN_CPUCOM_DBG_RESERVE_LSB) & WLAN_CPUCOM_DBG_RESERVE_MASK)
+#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MSB         3
+#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB         3
+#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK        0x00000008
+#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB)
+#define WLAN_CPUCOM_DBG_CRD1_DEC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD1_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_DEC_ERR_MASK)
+#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MSB         2
+#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB         2
+#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK        0x00000004
+#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB)
+#define WLAN_CPUCOM_DBG_CRD1_INC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD1_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD1_INC_ERR_MASK)
+#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MSB         1
+#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB         1
+#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK        0x00000002
+#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB)
+#define WLAN_CPUCOM_DBG_CRD0_DEC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD0_DEC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_DEC_ERR_MASK)
+#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MSB         0
+#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB         0
+#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK        0x00000001
+#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_GET(x)      (((x) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK) >> WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB)
+#define WLAN_CPUCOM_DBG_CRD0_INC_ERR_SET(x)      (((x) << WLAN_CPUCOM_DBG_CRD0_INC_ERR_LSB) & WLAN_CPUCOM_DBG_CRD0_INC_ERR_MASK)
+
+#define WLAN2BT_CPUCOM_INT_ACK_EN_ADDRESS        0x00000440
+#define WLAN2BT_CPUCOM_INT_ACK_EN_OFFSET         0x00000440
+#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MSB        0
+#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB        0
+#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK       0x00000001
+#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_GET(x)     (((x) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK) >> WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB)
+#define WLAN2BT_CPUCOM_INT_ACK_EN_REG_SET(x)     (((x) << WLAN2BT_CPUCOM_INT_ACK_EN_REG_LSB) & WLAN2BT_CPUCOM_INT_ACK_EN_REG_MASK)
+
+#define BT2WLAN_CPUCOM_INT_EN_ADDRESS            0x00000444
+#define BT2WLAN_CPUCOM_INT_EN_OFFSET             0x00000444
+#define BT2WLAN_CPUCOM_INT_EN_REG_MSB            0
+#define BT2WLAN_CPUCOM_INT_EN_REG_LSB            0
+#define BT2WLAN_CPUCOM_INT_EN_REG_MASK           0x00000001
+#define BT2WLAN_CPUCOM_INT_EN_REG_GET(x)         (((x) & BT2WLAN_CPUCOM_INT_EN_REG_MASK) >> BT2WLAN_CPUCOM_INT_EN_REG_LSB)
+#define BT2WLAN_CPUCOM_INT_EN_REG_SET(x)         (((x) << BT2WLAN_CPUCOM_INT_EN_REG_LSB) & BT2WLAN_CPUCOM_INT_EN_REG_MASK)
+
+#ifndef __ASSEMBLER__
+typedef struct rtc_soc_reg_reg_s {
+	volatile unsigned int soc_reset_control;
+	volatile unsigned int soc_tcxo_detect;
+	volatile unsigned int soc_xtal_test;
+	unsigned char pad0[20]; /* pad to 0x20 */
+	volatile unsigned int soc_cpu_clock;
+	unsigned char pad1[4];  /* pad to 0x28 */
+	volatile unsigned int soc_clock_control;
+	unsigned char pad2[4];  /* pad to 0x30 */
+	volatile unsigned int soc_wdt_control;
+	volatile unsigned int soc_wdt_status;
+	volatile unsigned int soc_wdt;
+	volatile unsigned int soc_wdt_count;
+	volatile unsigned int soc_wdt_reset;
+	volatile unsigned int soc_int_status;
+	volatile unsigned int soc_lf_timer0;
+	volatile unsigned int soc_lf_timer_count0;
+	volatile unsigned int soc_lf_timer_control0;
+	volatile unsigned int soc_lf_timer_status0;
+	volatile unsigned int soc_lf_timer1;
+	volatile unsigned int soc_lf_timer_count1;
+	volatile unsigned int soc_lf_timer_control1;
+	volatile unsigned int soc_lf_timer_status1;
+	volatile unsigned int soc_lf_timer2;
+	volatile unsigned int soc_lf_timer_count2;
+	volatile unsigned int soc_lf_timer_control2;
+	volatile unsigned int soc_lf_timer_status2;
+	volatile unsigned int soc_lf_timer3;
+	volatile unsigned int soc_lf_timer_count3;
+	volatile unsigned int soc_lf_timer_control3;
+	volatile unsigned int soc_lf_timer_status3;
+	volatile unsigned int soc_hf_timer;
+	volatile unsigned int soc_hf_timer_count;
+	volatile unsigned int soc_hf_lf_count;
+	volatile unsigned int soc_hf_timer_control;
+	volatile unsigned int soc_hf_timer_status;
+	volatile unsigned int soc_rtc_control;
+	volatile unsigned int soc_rtc_time;
+	volatile unsigned int soc_rtc_date;
+	volatile unsigned int soc_rtc_set_time;
+	volatile unsigned int soc_rtc_set_date;
+	volatile unsigned int soc_rtc_set_alarm;
+	volatile unsigned int soc_rtc_config;
+	volatile unsigned int soc_rtc_alarm_status;
+	volatile unsigned int soc_uart_wakeup;
+	volatile unsigned int soc_reset_cause;
+	volatile unsigned int soc_system_sleep;
+	volatile unsigned int soc_sdio_wrapper;
+	volatile unsigned int soc_int_sleep_mask;
+	unsigned char pad3[4];  /* pad to 0xd4 */
+	volatile unsigned int soc_lpo_cal_time;
+	volatile unsigned int soc_lpo_init_dividend_int;
+	volatile unsigned int soc_lpo_init_dividend_fraction;
+	volatile unsigned int soc_lpo_cal;
+	volatile unsigned int soc_lpo_cal_test_control;
+	volatile unsigned int soc_lpo_cal_test_status;
+	volatile unsigned int legacy_soc_chip_id;
+	volatile unsigned int soc_chip_id;
+	unsigned char pad4[24]; /* pad to 0x10c */
+	volatile unsigned int soc_power_reg;
+	volatile unsigned int soc_core_clk_ctrl;
+	volatile unsigned int soc_gpio_wakeup_control;
+	unsigned char pad5[252];        /* pad to 0x214 */
+	volatile unsigned int sleep_retention;
+	unsigned char pad6[108];        /* pad to 0x284 */
+	volatile unsigned int lp_perf_counter;
+	volatile unsigned int lp_perf_light_sleep;
+	volatile unsigned int lp_perf_deep_sleep;
+	volatile unsigned int lp_perf_on;
+	unsigned char pad7[20]; /* pad to 0x2a8 */
+	volatile unsigned int chip_mode;
+	volatile unsigned int clk_req_fall_edge;
+	volatile unsigned int otp;
+	volatile unsigned int otp_status;
+	volatile unsigned int pmu;
+	volatile unsigned int pmu_config;
+	volatile unsigned int pmu_pareg;
+	volatile unsigned int pmu_bypass;
+	unsigned char pad8[20]; /* pad to 0x2dc */
+	volatile unsigned int therm_ctrl1;
+	volatile unsigned int therm_ctrl2;
+	volatile unsigned int therm_ctrl3;
+	volatile unsigned int listen_mode1;
+	volatile unsigned int listen_mode2;
+	volatile unsigned int audio_pll_config;
+	volatile unsigned int audio_pll_modulation;
+	volatile unsigned int audio_pll_mod_step;
+	volatile unsigned int current_audio_pll_modulation;
+	volatile unsigned int eth_pll_config;
+	volatile unsigned int cpu_pll_config;
+	volatile unsigned int bb_pll_config;
+	volatile unsigned int eth_xmii;
+	volatile unsigned int usb_phy_config;
+	volatile unsigned int usbcore_clk60m;
+	volatile unsigned int usbphy_utmi_clk;
+	volatile unsigned int usb_txvalid_dly_config;
+	volatile unsigned int second_host_inft;
+	volatile unsigned int sdio_host;
+	volatile unsigned int enterprise_config;
+	volatile unsigned int rtc_debug_bus;
+	volatile unsigned int rtc_ext_clk_buf;
+	volatile unsigned int wlan_ahb_bridge_timeout;
+	volatile unsigned int wlan_ahb_config;
+	volatile unsigned int rtc_axi_ahb_bridge;
+	unsigned char pad9[192];        /* pad to 0x400 */
+	volatile unsigned int wlan2bt_cpucom_int_sts;
+	volatile unsigned int wlan2bt_cpucom_int_mask_n;
+	volatile unsigned int wlan2bt_cpucom_int_eoi;
+	volatile unsigned int wlan2bt_cpucom_int_ack_sts;
+	volatile unsigned int wlan2bt_cpucom_int_ack_mask_n;
+	volatile unsigned int wlan_cpucom_crd_cnt0;
+	volatile unsigned int wlan_cpucom_crd_inc0[1];
+	volatile unsigned int wlan_cpucom_crd_dec0[1];
+	volatile unsigned int wlan_cpucom_crd_cnt1;
+	volatile unsigned int wlan_cpucom_crd_inc1[1];
+	volatile unsigned int wlan_cpucom_crd_dec1[1];
+	volatile unsigned int wlan_cpucom_scratch0;
+	volatile unsigned int wlan_cpucom_scratch1;
+	volatile unsigned int wlan_cpucom_scratch2;
+	volatile unsigned int wlan_cpucom_scratch3;
+	volatile unsigned int wlan_cpucom_dbg;
+	volatile unsigned int wlan2bt_cpucom_int_ack_en;
+	volatile unsigned int bt2wlan_cpucom_int_en;
+} rtc_soc_reg_reg_t;
+#endif /* __ASSEMBLER__ */
+
+#endif /* _RTC_SOC_REG_H_ */

fw/targaddrs.h

@@ -42,14 +42,14 @@
  * AR6004: These bits can be set in LOCAL_SCRATCH register 0.
  * AR9888: These bits can be set in soc_core register SCRATCH_0.
  */
-#define SOC_OPTION_BMI_DISABLE      0x01 /* Disable BMI comm with Host */
-#define SOC_OPTION_SERIAL_ENABLE    0x02 /* Enable serial port msgs */
-#define SOC_OPTION_WDT_DISABLE      0x04 /* WatchDog Timer override */
-#define SOC_OPTION_SLEEP_DISABLE    0x08 /* Disable system sleep */
-#define SOC_OPTION_STOP_BOOT        0x10 /* Stop boot processes (for ATE) */
-#define SOC_OPTION_ENABLE_NOANI     0x20 /* Operate without ANI */
-#define SOC_OPTION_DSET_DISABLE     0x40 /* Ignore DataSets */
-#define SOC_OPTION_IGNORE_FLASH     0x80 /* Ignore flash during bootup */
+#define SOC_OPTION_BMI_DISABLE      0x01        /* Disable BMI comm with Host */
+#define SOC_OPTION_SERIAL_ENABLE    0x02        /* Enable serial port msgs */
+#define SOC_OPTION_WDT_DISABLE      0x04        /* WatchDog Timer override */
+#define SOC_OPTION_SLEEP_DISABLE    0x08        /* Disable system sleep */
+#define SOC_OPTION_STOP_BOOT        0x10        /* Stop boot processes (for ATE) */
+#define SOC_OPTION_ENABLE_NOANI     0x20        /* Operate without ANI */
+#define SOC_OPTION_DSET_DISABLE     0x40        /* Ignore DataSets */
+#define SOC_OPTION_IGNORE_FLASH     0x80        /* Ignore flash during bootup */
 
 /*
  * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
@@ -80,10 +80,6 @@
 #endif
 #define AR6006_SOC_RESET_ADDRESS                    0X00004000
 #define AR6006_SOC_RESET_CPU_INIT_RESET_MASK        0X00000800
-#define QCA9984_HOST_INTEREST_ADDRESS               0x00400800
-#define IPQ4019_HOST_INTEREST_ADDRESS               0x00400800
-#define QCA9888_HOST_INTEREST_ADDRESS               0x00400800
-
 
 #define HOST_INTEREST_MAX_SIZE          0x200
 
@@ -103,20 +99,20 @@ struct dbglog_hdr_s;
  * More items may be added at the end.
  */
 PREPACK64 struct host_interest_s {
-    /*
-     * Pointer to application-defined area, if any.
-     * Set by Target application during startup.
-     */
-    A_UINT32               hi_app_host_interest;                      /* 0x00 */
+	/*
+	 * Pointer to application-defined area, if any.
+	 * Set by Target application during startup.
+	 */
+	A_UINT32 hi_app_host_interest;  /* 0x00 */
 
-    /* Pointer to register dump area, valid after Target crash. */
-    A_UINT32               hi_failure_state;                          /* 0x04 */
+	/* Pointer to register dump area, valid after Target crash. */
+	A_UINT32 hi_failure_state;      /* 0x04 */
 
-    /* Pointer to debug logging header */
-    A_UINT32               hi_dbglog_hdr;                             /* 0x08 */
+	/* Pointer to debug logging header */
+	A_UINT32 hi_dbglog_hdr; /* 0x08 */
 
-    /* Save SW ROM version */
-    A_UINT32               hi_sw_rom_version;                         /* 0x0c */
+	/* Save SW ROM version */
+	A_UINT32 hi_sw_rom_version;     /* 0x0c */
 
     /*
      * General-purpose flag bits, similar to SOC_OPTION_* flags.
@@ -124,161 +120,161 @@ PREPACK64 struct host_interest_s {
      */
     volatile A_UINT32      hi_option_flag;                            /* 0x10 */
 
-    /*
-     * Boolean that determines whether or not to
-     * display messages on the serial port.
-     */
-    A_UINT32               hi_serial_enable;                          /* 0x14 */
-
-    /* Start address of DataSet index, if any */
-    A_UINT32               hi_dset_list_head;                         /* 0x18 */
-
-    /* Override Target application start address */
-    A_UINT32               hi_app_start;                              /* 0x1c */
-
-    /* Clock and voltage tuning */
-    A_UINT32               hi_skip_clock_init;                        /* 0x20 */
-    A_UINT32               hi_core_clock_setting;                     /* 0x24 */
-    A_UINT32               hi_cpu_clock_setting;                      /* 0x28 */
-    A_UINT32               hi_system_sleep_setting;                   /* 0x2c */
-    A_UINT32               hi_xtal_control_setting;                   /* 0x30 */
-    A_UINT32               hi_pll_ctrl_setting_24ghz;                 /* 0x34 */
-    A_UINT32               hi_pll_ctrl_setting_5ghz;                  /* 0x38 */
-    A_UINT32               hi_ref_voltage_trim_setting;               /* 0x3c */
-    A_UINT32               hi_clock_info;                             /* 0x40 */
-
-    /* Host uses BE CPU or not */
-    A_UINT32               hi_be;                                     /* 0x44 */
-
-    A_UINT32               hi_stack;  /* normal stack */              /* 0x48 */
-    A_UINT32               hi_err_stack; /* error stack */            /* 0x4c */
-    A_UINT32               hi_desired_cpu_speed_hz;                   /* 0x50 */
-
-    /* Pointer to Board Data  */
-    A_UINT32               hi_board_data;                             /* 0x54 */
-
-    /*
-     * Indication of Board Data state:
-     *    0: board data is not yet initialized.
-     *    1: board data is initialized; unknown size
-     *   >1: number of bytes of initialized board data (varies with board type)
-     */
-    A_UINT32               hi_board_data_initialized;                 /* 0x58 */
-
-    A_UINT32               hi_dset_RAM_index_table;                   /* 0x5c */
-
-    A_UINT32               hi_desired_baud_rate;                      /* 0x60 */
-    A_UINT32               hi_dbglog_config;                          /* 0x64 */
-    A_UINT32               hi_end_RAM_reserve_sz;                     /* 0x68 */
-    A_UINT32               hi_mbox_io_block_sz;                       /* 0x6c */
-
-    A_UINT32               hi_num_bpatch_streams;                     /* 0x70 -- unused */
-    A_UINT32               hi_mbox_isr_yield_limit;                   /* 0x74 */
-
-    A_UINT32               hi_refclk_hz;                              /* 0x78 */
-    A_UINT32               hi_ext_clk_detected;                       /* 0x7c */
-    A_UINT32               hi_dbg_uart_txpin;                         /* 0x80 */
-    A_UINT32               hi_dbg_uart_rxpin;                         /* 0x84 */
-    A_UINT32               hi_hci_uart_baud;                          /* 0x88 */
-    A_UINT32               hi_hci_uart_pin_assignments;               /* 0x8C */
-        /* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
-    A_UINT32               hi_hci_uart_baud_scale_val;                /* 0x90 */
-    A_UINT32               hi_hci_uart_baud_step_val;                 /* 0x94 */
-
-    A_UINT32               hi_allocram_start;                         /* 0x98 */
-    A_UINT32               hi_allocram_sz;                            /* 0x9c */
-    A_UINT32               hi_hci_bridge_flags;                       /* 0xa0 */
-    A_UINT32               hi_hci_uart_support_pins;                  /* 0xa4 */
-        /* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
-    A_UINT32               hi_hci_uart_pwr_mgmt_params;               /* 0xa8 */
-        /* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
-         *        [31:16]: wakeup timeout in ms
-         */
-    /* Pointer to extended board Data  */
-    A_UINT32               hi_board_ext_data;                         /* 0xac */
-    A_UINT32               hi_board_ext_data_config;                  /* 0xb0 */
-        /*
-         * Bit [0]  :   valid
-         * Bit[31:16:   size
-         */
-   /*
-     * hi_reset_flag is used to do some stuff when target reset.
-     * such as restore app_start after warm reset or
-     * preserve host Interest area, or preserve ROM data, literals etc.
-     */
-    A_UINT32                hi_reset_flag;                            /* 0xb4 */
-    /* indicate hi_reset_flag is valid */
-    A_UINT32                hi_reset_flag_valid;                      /* 0xb8 */
-    A_UINT32               hi_hci_uart_pwr_mgmt_params_ext;           /* 0xbc */
-        /* 0xbc - [31:0]: idle timeout in ms
-         */
-        /* ACS flags */
-    A_UINT32               hi_acs_flags;                              /* 0xc0 */
-    A_UINT32               hi_console_flags;                          /* 0xc4 */
-    A_UINT32               hi_nvram_state;                            /* 0xc8 */
-    volatile A_UINT32      hi_option_flag2;                           /* 0xcc */
-
-    /* If non-zero, override values sent to Host in WMI_READY event. */
-    A_UINT32               hi_sw_version_override;                    /* 0xd0 */
-    A_UINT32               hi_abi_version_override;                   /* 0xd4 */
-
-    /* Percentage of high priority RX traffic to total expected RX traffic -
-     * applicable only to ar6004 */
-    A_UINT32               hi_hp_rx_traffic_ratio;                    /* 0xd8 */
-
-    /* test applications flags */
-    A_UINT32               hi_test_apps_related    ;                  /* 0xdc */
-    /* location of test script */
-    A_UINT32               hi_ota_testscript;                         /* 0xe0 */
-    /* location of CAL data */
-    A_UINT32               hi_cal_data;                               /* 0xe4 */
+	/*
+	 * Boolean that determines whether or not to
+	 * display messages on the serial port.
+	 */
+	A_UINT32 hi_serial_enable;      /* 0x14 */
+
+	/* Start address of DataSet index, if any */
+	A_UINT32 hi_dset_list_head;     /* 0x18 */
+
+	/* Override Target application start address */
+	A_UINT32 hi_app_start;  /* 0x1c */
+
+	/* Clock and voltage tuning */
+	A_UINT32 hi_skip_clock_init;    /* 0x20 */
+	A_UINT32 hi_core_clock_setting; /* 0x24 */
+	A_UINT32 hi_cpu_clock_setting;  /* 0x28 */
+	A_UINT32 hi_system_sleep_setting;       /* 0x2c */
+	A_UINT32 hi_xtal_control_setting;       /* 0x30 */
+	A_UINT32 hi_pll_ctrl_setting_24ghz;     /* 0x34 */
+	A_UINT32 hi_pll_ctrl_setting_5ghz;      /* 0x38 */
+	A_UINT32 hi_ref_voltage_trim_setting;   /* 0x3c */
+	A_UINT32 hi_clock_info; /* 0x40 */
+
+	/* Host uses BE CPU or not */
+	A_UINT32 hi_be;         /* 0x44 */
+
+	A_UINT32 hi_stack;      /* normal stack *//* 0x48 */
+	A_UINT32 hi_err_stack;  /* error stack *//* 0x4c */
+	A_UINT32 hi_desired_cpu_speed_hz;       /* 0x50 */
+
+	/* Pointer to Board Data  */
+	A_UINT32 hi_board_data; /* 0x54 */
+
+	/*
+	 * Indication of Board Data state:
+	 *    0: board data is not yet initialized.
+	 *    1: board data is initialized; unknown size
+	 *   >1: number of bytes of initialized board data (varies with board type)
+	 */
+	A_UINT32 hi_board_data_initialized;     /* 0x58 */
+
+	A_UINT32 hi_dset_RAM_index_table;       /* 0x5c */
+
+	A_UINT32 hi_desired_baud_rate;  /* 0x60 */
+	A_UINT32 hi_dbglog_config;      /* 0x64 */
+	A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
+	A_UINT32 hi_mbox_io_block_sz;   /* 0x6c */
+
+	A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
+	A_UINT32 hi_mbox_isr_yield_limit;       /* 0x74 */
+
+	A_UINT32 hi_refclk_hz;  /* 0x78 */
+	A_UINT32 hi_ext_clk_detected;   /* 0x7c */
+	A_UINT32 hi_dbg_uart_txpin;     /* 0x80 */
+	A_UINT32 hi_dbg_uart_rxpin;     /* 0x84 */
+	A_UINT32 hi_hci_uart_baud;      /* 0x88 */
+	A_UINT32 hi_hci_uart_pin_assignments;   /* 0x8C */
+	/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
+	A_UINT32 hi_hci_uart_baud_scale_val;    /* 0x90 */
+	A_UINT32 hi_hci_uart_baud_step_val;     /* 0x94 */
+
+	A_UINT32 hi_allocram_start;     /* 0x98 */
+	A_UINT32 hi_allocram_sz;        /* 0x9c */
+	A_UINT32 hi_hci_bridge_flags;   /* 0xa0 */
+	A_UINT32 hi_hci_uart_support_pins;      /* 0xa4 */
+	/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
+	A_UINT32 hi_hci_uart_pwr_mgmt_params;   /* 0xa8 */
+	/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
+	 *        [31:16]: wakeup timeout in ms
+	 */
+	/* Pointer to extended board Data  */
+	A_UINT32 hi_board_ext_data;     /* 0xac */
+	A_UINT32 hi_board_ext_data_config;      /* 0xb0 */
+	/*
+	 * Bit [0]  :   valid
+	 * Bit[31:16:   size
+	 */
+	/*
+	 * hi_reset_flag is used to do some stuff when target reset.
+	 * such as restore app_start after warm reset or
+	 * preserve host Interest area, or preserve ROM data, literals etc.
+	 */
+	A_UINT32 hi_reset_flag; /* 0xb4 */
+	/* indicate hi_reset_flag is valid */
+	A_UINT32 hi_reset_flag_valid;   /* 0xb8 */
+	A_UINT32 hi_hci_uart_pwr_mgmt_params_ext;       /* 0xbc */
+	/* 0xbc - [31:0]: idle timeout in ms
+	 */
+	/* ACS flags */
+	A_UINT32 hi_acs_flags;  /* 0xc0 */
+	A_UINT32 hi_console_flags;      /* 0xc4 */
+	A_UINT32 hi_nvram_state;        /* 0xc8 */
+	volatile A_UINT32 hi_option_flag2;       /* 0xcc */
+
+	/* If non-zero, override values sent to Host in WMI_READY event. */
+	A_UINT32 hi_sw_version_override;        /* 0xd0 */
+	A_UINT32 hi_abi_version_override;       /* 0xd4 */
+
+	/* Percentage of high priority RX traffic to total expected RX traffic -
+	 * applicable only to ar6004 */
+	A_UINT32 hi_hp_rx_traffic_ratio;        /* 0xd8 */
+
+	/* test applications flags */
+	A_UINT32 hi_test_apps_related;  /* 0xdc */
+	/* location of test script */
+	A_UINT32 hi_ota_testscript;     /* 0xe0 */
+	/* location of CAL data */
+	A_UINT32 hi_cal_data;   /* 0xe4 */
 
     /* Number of packet log buffers */
     volatile A_UINT32      hi_pktlog_num_buffers;                     /* 0xe8 */
 
-    /* wow extension configuration */
-    A_UINT32               hi_wow_ext_config;                         /* 0xec */
-    A_UINT32               hi_pwr_save_flags;                         /* 0xf0 */
+	/* wow extension configuration */
+	A_UINT32 hi_wow_ext_config;     /* 0xec */
+	A_UINT32 hi_pwr_save_flags;     /* 0xf0 */
 
-    /* Spatial Multiplexing Power Save (SMPS) options */
-    A_UINT32               hi_smps_options;                           /* 0xf4 */
+	/* Spatial Multiplexing Power Save (SMPS) options */
+	A_UINT32 hi_smps_options;       /* 0xf4 */
 
-    /* Interconnect-specific state */
-    A_UINT32               hi_interconnect_state;                     /* 0xf8 */
+	/* Interconnect-specific state */
+	A_UINT32 hi_interconnect_state; /* 0xf8 */
 
-    /* Coex configuration flags */
-    A_UINT32               hi_coex_config;                           /* 0xfc */
+	/* Coex configuration flags */
+	A_UINT32 hi_coex_config;        /* 0xfc */
 
-    /* Early allocation support */
-    A_UINT32               hi_early_alloc;                            /* 0x100 */
+	/* Early allocation support */
+	A_UINT32 hi_early_alloc;        /* 0x100 */
 
-    /* FW swap field */
-    /* Bits of this 32bit word will be used to pass specific swap
-        instruction to FW */
-    /* Bit 0 -- AP Nart descriptor no swap. When this bit is set
-            FW will not swap TX descriptor. Meaning packets are formed
-            on the target processor.*/
-    /* Bit 1 -- TBD */
+	/* FW swap field */
+	/* Bits of this 32bit word will be used to pass specific swap
+	   instruction to FW */
+	/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
+	   FW will not swap TX descriptor. Meaning packets are formed
+	   on the target processor. */
+	/* Bit 1 -- TBD */
 
-    A_UINT32               hi_fw_swap;                               /* 0x104 */
+	A_UINT32 hi_fw_swap;    /* 0x104 */
 
-    /* global arenas pointer address, used by host driver debug */
-    A_UINT32               hi_dynamic_mem_arenas_addr;              /* 0x108 */
+	/* global arenas pointer address, used by host driver debug */
+	A_UINT32 hi_dynamic_mem_arenas_addr;    /* 0x108 */
 
-    /* allocated bytes of DRAM use by allocated */
-    A_UINT32               hi_dynamic_mem_allocated;                /* 0x10C */
+	/* allocated bytes of DRAM use by allocated */
+	A_UINT32 hi_dynamic_mem_allocated;      /* 0x10C */
 
-    /* remaining bytes of DRAM */
-    A_UINT32               hi_dynamic_mem_remaining;                /* 0x110 */
+	/* remaining bytes of DRAM */
+	A_UINT32 hi_dynamic_mem_remaining;      /* 0x110 */
 
-    /* memory track count, configured by host */
-    A_UINT32               hi_dynamic_mem_track_max;                /* 0x114 */
+	/* memory track count, configured by host */
+	A_UINT32 hi_dynamic_mem_track_max;      /* 0x114 */
 
-    /* minidump buffer */
-    A_UINT32               hi_minidump;                             /* 0x118 */
+	/* minidump buffer */
+	A_UINT32 hi_minidump;   /* 0x118 */
 
-    /* bdata's sig and key addr */
-    A_UINT32               hi_bd_sig_key;                           /* 0x11c */
+	/* bdata's sig and key addr */
+	A_UINT32 hi_bd_sig_key; /* 0x11c */
 
 } POSTPACK64;
 
@@ -287,38 +283,38 @@ PREPACK64 struct host_interest_s {
 #define HI_TEST_APPS_CAL_DATA_AVAIL      0x00000002
 
 /* Bits defined in hi_option_flag */
-#define HI_OPTION_TIMER_WAR         0x01 /* Enable timer workaround */
-#define HI_OPTION_BMI_CRED_LIMIT    0x02 /* Limit BMI command credits */
-#define HI_OPTION_RELAY_DOT11_HDR   0x04 /* Relay Dot11 hdr to/from host */
-#define HI_OPTION_MAC_ADDR_METHOD   0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
-#define HI_OPTION_FW_BRIDGE         0x10 /* Firmware Bridging */
-#define HI_OPTION_ENABLE_PROFILE    0x20 /* Enable CPU profiling */
-#define HI_OPTION_DISABLE_DBGLOG    0x40 /* Disable debug logging */
-#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
-#define HI_OPTION_PAPRD_DISABLE     0x100 /* Disable PAPRD (debug) */
+#define HI_OPTION_TIMER_WAR         0x01        /* Enable timer workaround */
+#define HI_OPTION_BMI_CRED_LIMIT    0x02        /* Limit BMI command credits */
+#define HI_OPTION_RELAY_DOT11_HDR   0x04        /* Relay Dot11 hdr to/from host */
+#define HI_OPTION_MAC_ADDR_METHOD   0x08        /* MAC addr method 0-locally administred 1-globally unique addrs */
+#define HI_OPTION_FW_BRIDGE         0x10        /* Firmware Bridging */
+#define HI_OPTION_ENABLE_PROFILE    0x20        /* Enable CPU profiling */
+#define HI_OPTION_DISABLE_DBGLOG    0x40        /* Disable debug logging */
+#define HI_OPTION_SKIP_ERA_TRACKING 0x80        /* Skip Era Tracking */
+#define HI_OPTION_PAPRD_DISABLE     0x100       /* Disable PAPRD (debug) */
 #define HI_OPTION_NUM_DEV_LSB       0x200
 #define HI_OPTION_NUM_DEV_MSB       0x800
 #define HI_OPTION_DEV_MODE_LSB      0x1000
 #define HI_OPTION_DEV_MODE_MSB      0x8000000
-#define HI_OPTION_NO_LFT_STBL       0x10000000 /* Disable LowFreq Timer Stabilization */
-#define HI_OPTION_SKIP_REG_SCAN     0x20000000 /* Skip regulatory scan */
-#define HI_OPTION_INIT_REG_SCAN     0x40000000 /* Do regulatory scan during init before
-                                                * sending WMI ready event to host */
-#define HI_OPTION_SKIP_MEMMAP       0x80000000 /* REV6: Do not adjust memory map */
+#define HI_OPTION_NO_LFT_STBL       0x10000000  /* Disable LowFreq Timer Stabilization */
+#define HI_OPTION_SKIP_REG_SCAN     0x20000000  /* Skip regulatory scan */
+#define HI_OPTION_INIT_REG_SCAN     0x40000000  /* Do regulatory scan during init before
+	                                         * sending WMI ready event to host */
+#define HI_OPTION_SKIP_MEMMAP       0x80000000  /* REV6: Do not adjust memory map */
 
 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
 
 /* 2 bits of hi_option_flag are used to represent 3 modes */
-#define HI_OPTION_FW_MODE_IBSS    0x0 /* IBSS Mode */
-#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
-#define HI_OPTION_FW_MODE_AP      0x2 /* AP Mode */
-#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
+#define HI_OPTION_FW_MODE_IBSS    0x0   /* IBSS Mode */
+#define HI_OPTION_FW_MODE_BSS_STA 0x1   /* STA Mode */
+#define HI_OPTION_FW_MODE_AP      0x2   /* AP Mode */
+#define HI_OPTION_FW_MODE_BT30AMP 0x3   /* BT30 AMP Mode */
 
 /* 2 bits of hi_option flag are usedto represent 4 submodes */
-#define HI_OPTION_FW_SUBMODE_NONE    0x0  /* Normal mode */
-#define HI_OPTION_FW_SUBMODE_P2PDEV  0x1  /* p2p device mode */
-#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
-#define HI_OPTION_FW_SUBMODE_P2PGO   0x3 /* p2p go mode */
+#define HI_OPTION_FW_SUBMODE_NONE    0x0        /* Normal mode */
+#define HI_OPTION_FW_SUBMODE_P2PDEV  0x1        /* p2p device mode */
+#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2      /* p2p client mode */
+#define HI_OPTION_FW_SUBMODE_P2PGO   0x3        /* p2p go mode */
 
 /* Num dev Mask */
 #define HI_OPTION_NUM_DEV_MASK    0x7
@@ -328,12 +324,12 @@ PREPACK64 struct host_interest_s {
 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04
 
 /* Fw Mode/SubMode Mask
-|-------------------------------------------------------------------------------|
-|   SUB   |   SUB   |   SUB   |  SUB    |         |         |         |         |
-| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
-|   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |
-|-------------------------------------------------------------------------------|
-*/
+   |-------------------------------------------------------------------------------|
+ |   SUB   |   SUB   |   SUB   |  SUB    |         |         |         |         |
+ | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
+ |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |
+ |||-------------------------------------------------------------------------------|
+ */
 #define HI_OPTION_FW_MODE_BITS         0x2
 #define HI_OPTION_FW_MODE_MASK         0x3
 #define HI_OPTION_FW_MODE_SHIFT        0xC
@@ -345,13 +341,12 @@ PREPACK64 struct host_interest_s {
 #define HI_OPTION_ALL_FW_SUBMODE_MASK  0xFF00
 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
 
-
 /* hi_option_flag2 options */
 #define HI_OPTION_OFFLOAD_AMSDU     0x01
-#define HI_OPTION_DFS_SUPPORT       0x02 /* Enable DFS support */
-#define HI_OPTION_ENABLE_RFKILL     0x04 /* RFKill Enable Feature*/
-#define HI_OPTION_RADIO_RETENTION_DISABLE     0x08 /* Disable radio retention */
-#define HI_OPTION_EARLY_CFG_DONE    0x10 /* Early configuration is complete */
+#define HI_OPTION_DFS_SUPPORT       0x02        /* Enable DFS support */
+#define HI_OPTION_ENABLE_RFKILL     0x04        /* RFKill Enable Feature */
+#define HI_OPTION_RADIO_RETENTION_DISABLE     0x08      /* Disable radio retention */
+#define HI_OPTION_EARLY_CFG_DONE    0x10        /* Early configuration is complete */
 
 #define HI_OPTION_RF_KILL_SHIFT     0x2
 #define HI_OPTION_RF_KILL_MASK      0x1
@@ -359,68 +354,71 @@ PREPACK64 struct host_interest_s {
 #define HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX 0x20
 
 #define HTT_TGT_DEBUG_TX_COMPL_IDX_VALUE()    \
-        ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
+	((HOST_INTEREST->hi_option_flag2 & HI_OPTION_HTT_TGT_DEBUG_TX_COMPL_IDX))
 
 /* AR9888 1.0 only. Enable/disable CDC max perf support from host */
 #define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR  0x20
 #define CDC_MAX_PERF_WAR_ENABLED()    \
-        (!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
+	(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
 #define HI_OPTION_USE_EXT_LDO       0x40 /* use LDO27 for 1.1V instead of PMU. */
 #define HI_OPTION_DBUART_SUPPORT    0x80 /* Enable uart debug support */
-#define HI_OPTION_BE_LATENCY_OPTIMIZE    0x100 /* This bit is to enable BE low latency for some customers. The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).*/
+/* This bit is to enable BE low latency for some customers.
+ * The side effect is TCP DL will be 8Mbps decreased (673Mbps -> 665Mbps).
+ */
+#define HI_OPTION_BE_LATENCY_OPTIMIZE    0x100
 #define HT_OPTION_GPIO_WAKEUP_SUPPORT    0x200 /* GPIO wake up support */
-
 #define GPIO_WAKEUP_ENABLED() \
-    (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
-
+			 (HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
 
 /* hi_reset_flag */
-#define HI_RESET_FLAG_PRESERVE_APP_START         0x01  /* preserve App Start address */
-#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST     0x02  /* preserve host interest */
-#define HI_RESET_FLAG_PRESERVE_ROMDATA           0x04  /* preserve ROM data */
+#define HI_RESET_FLAG_PRESERVE_APP_START         0x01   /* preserve App Start address */
+#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST     0x02   /* preserve host interest */
+#define HI_RESET_FLAG_PRESERVE_ROMDATA           0x04   /* preserve ROM data */
 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE       0x08
 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO         0x10
-#define HI_RESET_FLAG_WARM_RESET	0x20
+#define HI_RESET_FLAG_WARM_RESET        0x20
 
 /* define hi_fw_swap bits */
 #define HI_DESC_IN_FW_BIT       0x01
 
-#define HI_RESET_FLAG_IS_VALID  0x12345678  /* indicate the reset flag is valid */
+#define HI_RESET_FLAG_IS_VALID  0x12345678      /* indicate the reset flag is valid */
 
 #define ON_RESET_FLAGS_VALID() \
-        (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
+	(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
 
-#define RESET_FLAGS_VALIDATE()  \
-        (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
+#define RESET_FLAGS_VALIDATE()	\
+	(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
 
 #define RESET_FLAGS_INVALIDATE() \
-        (HOST_INTEREST->hi_reset_flag_valid = 0)
+	(HOST_INTEREST->hi_reset_flag_valid = 0)
 
 #define ON_RESET_PRESERVE_APP_START() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
 
-#define ON_RESET_PRESERVE_NVRAM_STATE() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
+#define ON_RESET_PRESERVE_NVRAM_STATE()	\
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
 
 #define ON_RESET_PRESERVE_HOST_INTEREST() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
 
 #define ON_RESET_PRESERVE_ROMDATA() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
 
 #define ON_RESET_PRESERVE_BOOT_INFO() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
 
 #define ON_RESET_WARM_RESET() \
-        (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
+	(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
 
 /* host CPU endianness */
 #define HOST_ON_BE_CPU() \
-        (HOST_INTEREST->hi_be)
+	(HOST_INTEREST->hi_be)
 
-/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
+/* AP nart no swap descriptor flag. Decsriptors are created
+ * on the target processor.
+ */
 #define DESC_IN_FW() \
-        (HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
+	(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
 
 
 /* redefine for hi_acs_flags since no product ever use it
@@ -434,15 +432,20 @@ PREPACK64 struct host_interest_s {
  *     1      HOST supports HTT reduced tx completion
  *     2      HOST supports HTT alternate credit size for data frames
  *   15..3    reserved for HOST
- *    16      FW set it before sending HTC_Ready to HOST to indicate MBOX swap is done
+ *    16      FW set it before sending HTC_Ready to indicate MBOX swap is done
  *    17      same as above but to indicate HTT reduced tx completion capability
  *  31..18    reserved for FW
  */
-#define HI_ACS_FLAGS_HOST_SWAP_MBOX     (1 << 0)   /* HOST require to swap MBOX */
-#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1) /* HOST supports HTT reduced tx completion */
-#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2) /* HOST supports alternate credit size for data frames */
-#define HI_ACS_FLAGS_FW_SWAPPED_MBOX    (1 << 16)  /* FW swapped MBOX */
-#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)  /* FW support HTT reduced tx completion */
+/* HOST require to swap MBOX */
+#define HI_ACS_FLAGS_HOST_SWAP_MBOX     (1 << 0)
+/* HOST supports HTT reduced tx completion */
+#define HI_ACS_FLAGS_HOST_REDUCE_TX_COMPL (1 << 1)
+/* HOST supports alternate credit size for data frames */
+#define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE (1 << 2)
+/* FW swapped MBOX */
+#define HI_ACS_FLAGS_FW_SWAPPED_MBOX    (1 << 16)
+/* FW support HTT reduced tx completion */
+#define HI_ACS_FLAGS_FW_REDUCE_TX_COMPL (1 << 17)
 
 /* CONSOLE FLAGS
  *
@@ -484,7 +487,6 @@ PREPACK64 struct host_interest_s {
 #define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
 #define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
 
-
 /* WOW Extension configuration
  *
  * Bit Range  Meaning
@@ -508,16 +510,16 @@ PREPACK64 struct host_interest_s {
 #define HI_WOW_EXT_PATTERN_SIZE_MASK   (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
 
 #define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
-    ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK)     | \
-    (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK)  | \
-    (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
+	((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK)     | \
+	 (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK)  |	\
+	 (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
 
 #define HI_WOW_EXT_GET_NUM_LISTS(config)     \
-                        (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
+	(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
 #define HI_WOW_EXT_GET_NUM_PATTERNS(config)  \
-                        (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
+	(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
 #define HI_WOW_EXT_GET_PATTERN_SIZE(config)  \
-                        (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
+	(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
 
 /*
  * Early allocation configuration
@@ -546,57 +548,57 @@ PREPACK64 struct host_interest_s {
 #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT        0
 
 #define HI_EARLY_ALLOC_VALID() \
-               ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
-                               == (HI_EARLY_ALLOC_MAGIC))
-#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
-               (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
+	((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
+	 == (HI_EARLY_ALLOC_MAGIC))
+#define HI_EARLY_ALLOC_GET_IRAM_BANKS()	\
+	(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
 
 /*
  * Intended for use by Host software, this macro returns the Target RAM
  * address of any item in the host_interest structure.
  * Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
  */
-#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
+#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
+#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
+#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
+#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
+#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
+#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
 
-#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
-    (A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
+#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item)	\
+	(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
 
 #define HOST_INTEREST_DBGLOG_IS_ENABLED() \
-        (!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
+	(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
 
 #define HOST_INTEREST_PKTLOG_IS_ENABLED() \
-        ((HOST_INTEREST->hi_pktlog_num_buffers))
+	((HOST_INTEREST->hi_pktlog_num_buffers))
 
 #define HOST_INTEREST_PROFILE_IS_ENABLED() \
-        (HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
+	(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
 
 #define LF_TIMER_STABILIZATION_IS_ENABLED() \
-        (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
+	(!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
 
 #define IS_AMSDU_OFFLAOD_ENABLED() \
-        ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
+	((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
 
 #define HOST_INTEREST_DFS_IS_ENABLED() \
-        ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
+	((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
 
 #define HOST_INTEREST_EARLY_CFG_DONE() \
-        ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
+	((HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
 
 /*power save flag bit definitions*/
 #define HI_PWR_SAVE_LPL_ENABLED   0x1
@@ -609,15 +611,15 @@ PREPACK64 struct host_interest_s {
 #define HI_PWR_SAVE_LPL_DEV_MASK   0x3
 /*power save related utility macros*/
 #define HI_LPL_ENABLED() \
-        ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
+	((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
 #define HI_DEV_LPL_TYPE_GET(_devix)   \
-        (HOST_INTEREST->hi_pwr_save_flags & \
-          ((HI_PWR_SAVE_LPL_DEV_MASK) << \
-           (HI_PWR_SAVE_LPL_DEV0_LSB + \
-            (_devix)*2)))
+	(HOST_INTEREST->hi_pwr_save_flags & \
+	 ((HI_PWR_SAVE_LPL_DEV_MASK) <<	\
+	  (HI_PWR_SAVE_LPL_DEV0_LSB + \
+	   (_devix)*2)))
 
-#define HOST_INTEREST_SMPS_IS_ALLOWED() \
-        ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
+#define HOST_INTEREST_SMPS_IS_ALLOWED()	\
+	((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
 
 /* Convert a Target virtual address into a Target physical address */
 #define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
@@ -628,24 +630,24 @@ PREPACK64 struct host_interest_s {
 #define AR6320_VTOP(vaddr) (vaddr)
 #define AR900B_VTOP(vaddr) (vaddr)
 #define TARG_VTOP(TargetType, vaddr) \
-        (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
-        (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
-           0)))))))
+	(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
+	 (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
+	  (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
+	   (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) :	\
+	    (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
+	    (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
+	    (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
+	    0)))))))
 
 #define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
-        (((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
-        (((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
-           0)))))))
+	(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
+	0)))))))
 
 #define AR6002_BOARD_DATA_SZ 768
 #define AR6002_BOARD_EXT_DATA_SZ 0
@@ -664,23 +666,8 @@ PREPACK64 struct host_interest_s {
 #define AR6320_BOARD_EXT_DATA_SZ 0
 #define QCA9377_BOARD_DATA_SZ     8192
 #define QCA9377_BOARD_EXT_DATA_SZ 0
-#define AR900B_BOARD_DATA_SZ      (14 * 1024)
+#define AR900B_BOARD_DATA_SZ     7168
 #define AR900B_BOARD_EXT_DATA_SZ 0
-#define QCA9984_BOARD_DATA_SZ     (14 * 1024)
-#define QCA9984_BOARD_EXT_DATA_SZ 0
-#define QCA9888_BOARD_DATA_SZ     (14 * 1024)
-#define QCA9888_BOARD_EXT_DATA_SZ 0
-#define IPQ4019_BOARD_DATA_SZ     (14 * 1024)
-#define IPQ4019_BOARD_EXT_DATA_SZ 0
-
-/* Allocate board data right at the begining of AXI SRAM,
- * Current size for beeliner is 14K.
- * Allocate it towards the end of DRAM, until AXI SRAM is functional.
- */
-#define AR900B_BOARD_DATA_ADDR    0xc0000
-#define QCA9984_BOARD_DATA_ADDR   0xc0000
-#define QCA9888_BOARD_DATA_ADDR   0xc0000
-#define IPQ4019_BOARD_DATA_ADDR   0xc0000
 
 #define AR6003_REV3_APP_START_OVERRIDE          0x946100
 #define AR6003_REV3_APP_LOAD_ADDRESS            0x545000

fw/targcfg.h

@@ -29,25 +29,25 @@
 #define __TARGCFG_H__
 
 #if defined(ATH_TARGET)
-#include <osapi.h>   /* A_UINT32 */
+#include <osapi.h>              /* A_UINT32 */
 #else
-#include <a_types.h> /* A_UINT32 */
+#include <a_types.h>            /* A_UINT32 */
 #endif
 
 typedef struct _targcfg_t {
-    A_UINT32 num_vdev;
-    A_UINT32 num_peers;
-    A_UINT32 num_peer_ast;
-    A_UINT32 num_peer_keys;
-    A_UINT32 num_peer_tid;
-    A_UINT32 num_mcast_keys;
-    A_UINT32 num_tx;
-    A_UINT32 num_rx;
-    A_UINT32 num_mgmt_tx;
-    A_UINT32 num_mgmt_rx;
-    A_UINT32 tx_chain_mask;
-    A_UINT32 rx_chain_mask;
-    A_UINT32 override; /* Override target with the values supplied above */
+	A_UINT32 num_vdev;
+	A_UINT32 num_peers;
+	A_UINT32 num_peer_ast;
+	A_UINT32 num_peer_keys;
+	A_UINT32 num_peer_tid;
+	A_UINT32 num_mcast_keys;
+	A_UINT32 num_tx;
+	A_UINT32 num_rx;
+	A_UINT32 num_mgmt_tx;
+	A_UINT32 num_mgmt_rx;
+	A_UINT32 tx_chain_mask;
+	A_UINT32 rx_chain_mask;
+	A_UINT32 override;      /* Override target with the values supplied above */
 } targcfg_t;
 
 #endif /* __TARGCFG_H__ */

fw/wal_rx_desc.h

@@ -28,11 +28,10 @@
 #ifndef _WAL_RX_DESC__H_
 #define _WAL_RX_DESC__H_
 
-
 #if defined(ATH_TARGET)
-#include <athdefs.h> /* A_UINT8 */
+#include <athdefs.h>            /* A_UINT8 */
 #else
-#include <a_types.h> /* A_UINT8 */
+#include <a_types.h>            /* A_UINT8 */
 #endif
 
 /*
@@ -42,7 +41,7 @@
  *
  */
 #if !defined(ATH_PERF_PWR_OFFLOAD)
-#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) //FIXME_WIFI2 beeliner enbled by default (will be removed once we have target aware HTT)
+#if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B)
 #include <hw/interface/rx_location_info.h>
 #include <hw/interface/rx_pkt_end.h>
 #include <hw/interface/rx_phy_ppdu_end.h>
@@ -73,33 +72,36 @@
  * ring.
  */
 struct hw_rx_desc_base {
-    struct rx_attention  attention;
-    struct rx_frag_info  frag_info;
-    struct rx_mpdu_start mpdu_start;
-    struct rx_msdu_start msdu_start;
-    struct rx_msdu_end   msdu_end;
-    struct rx_mpdu_end   mpdu_end;
-    struct rx_ppdu_start ppdu_start;
-    struct rx_ppdu_end   ppdu_end;
+	struct rx_attention attention;
+	struct rx_frag_info frag_info;
+	struct rx_mpdu_start mpdu_start;
+	struct rx_msdu_start msdu_start;
+	struct rx_msdu_end msdu_end;
+	struct rx_mpdu_end mpdu_end;
+	struct rx_ppdu_start ppdu_start;
+	struct rx_ppdu_end ppdu_end;
 };
 #endif
 
+#define FW_MSDU_INFO_FIRST_WAKEUP_M 0x40
+#define FW_MSDU_INFO_FIRST_WAKEUP_S 6
+
 /*
  * This struct defines the basic MSDU rx descriptor created by FW.
  */
 struct fw_rx_desc_base {
-    union {
-        struct {
-            A_UINT8 discard  : 1,
-                    forward  : 1,
-                    any_err  : 1,
-                    dup_err  : 1,
-                    ipa_ind  : 1,
-                    inspect  : 1,
-                    extension: 2;
-        }bits;
-        A_UINT8     val;
-    }u;
+	union {
+		struct {
+			A_UINT8 discard:1,
+				forward:1,
+				any_err:1,
+				dup_err:1,
+				ipa_ind:1,
+				inspect:1,
+				extension:2;
+		} bits;
+		A_UINT8 val;
+	} u;
 };
 
 #define FW_RX_DESC_DISCARD_M 0x1
@@ -118,62 +120,61 @@ struct fw_rx_desc_base {
 #define FW_RX_DESC_CNT_2_BYTES(_fw_desc_cnt)    (_fw_desc_cnt)
 
 enum {
-    FW_RX_DESC_EXT_NONE          = 0,
-    FW_RX_DESC_EXT_LRO_ONLY,
-    FW_RX_DESC_EXT_LRO_AND_OTHER,
-    FW_RX_DESC_EXT_OTHER
+	FW_RX_DESC_EXT_NONE = 0,
+	FW_RX_DESC_EXT_LRO_ONLY,
+	FW_RX_DESC_EXT_LRO_AND_OTHER,
+	FW_RX_DESC_EXT_OTHER
 };
 
 #define FW_RX_DESC_DISCARD_GET(_var) \
-    (((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
+	(((_var) & FW_RX_DESC_DISCARD_M) >> FW_RX_DESC_DISCARD_S)
 #define FW_RX_DESC_DISCARD_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
+	((_var) |= ((_val) << FW_RX_DESC_DISCARD_S))
 
 #define FW_RX_DESC_FORWARD_GET(_var) \
-    (((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
+	(((_var) & FW_RX_DESC_FORWARD_M) >> FW_RX_DESC_FORWARD_S)
 #define FW_RX_DESC_FORWARD_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
+	((_var) |= ((_val) << FW_RX_DESC_FORWARD_S))
 
 #define FW_RX_DESC_INSPECT_GET(_var) \
-    (((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
+	(((_var) & FW_RX_DESC_INSPECT_M) >> FW_RX_DESC_INSPECT_S)
 #define FW_RX_DESC_INSPECT_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
+	((_var) |= ((_val) << FW_RX_DESC_INSPECT_S))
 
 #define FW_RX_DESC_EXT_GET(_var) \
-    (((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
+	(((_var) & FW_RX_DESC_EXT_M) >> FW_RX_DESC_EXT_S)
 #define FW_RX_DESC_EXT_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_DESC_EXT_S))
-
+	((_var) |= ((_val) << FW_RX_DESC_EXT_S))
 
 /*
  * This struct defines TCP_CHKSUM_OFFLOAD bit fields which are needed by host.
  */
 struct fw_rx_msdu_info {
-    union {
-        /*
-         * The "bits" struct defines the flags in fw_rx_msdu_info used
-         * during regular operation.
-         */
-        struct {
-            A_UINT8 tcp_udp_chksum_fail : 1, /* for tcp checksum offload use */
-                    ip_chksum_fail      : 1,
-                    ipv6_proto          : 1,
-                    tcp_proto           : 1,
-                    udp_proto           : 1,
-                    ip_frag             : 1,
-                    first_wakeup        : 1,
-                    reserved            : 1;
-        } bits;
-        /*
-         * The "mon" struct defines the flags in fw_rx_msdu_info used
-         * during monitor mode.
-         */
-        struct {
-            A_UINT8 last_frag           : 1,
-                    reserved            : 7;
-        } mon;
-        A_UINT8     val;
-    } u;
+	union {
+	/*
+	* The "bits" struct defines the flags in fw_rx_msdu_info used
+	* during regular operation.
+	*/
+	struct {
+	A_UINT8 tcp_udp_chksum_fail:1, /* for tcp checksum offload use */
+		ip_chksum_fail:1,
+		ipv6_proto:1,
+		tcp_proto:1,
+		udp_proto:1,
+		ip_frag:1,
+		first_wakeup:1,
+		reserved:1;
+	} bits;
+	/*
+	 * The "mon" struct defines the flags in fw_rx_msdu_info used
+	 * during monitor mode.
+	 */
+	struct {
+		A_UINT8 last_frag:1,
+		reserved:7;
+	} mon;
+	A_UINT8     val;
+	} u;
 };
 
 /* regular operation flags */
@@ -194,39 +195,39 @@ struct fw_rx_msdu_info {
 #define FW_RX_MSDU_INFO_FIRST_WAKEUP_S        6
 
 #define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
+	(((_var) & FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S)
 #define FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_UDP_CHKSUM_FAIL_S))
 
 #define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
+	(((_var) & FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_M) >> FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S)
 #define FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_CHKSUM_FAIL_S))
 
 #define FW_RX_MSDU_INFO_IPV6_PROTO_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
+	(((_var) & FW_RX_MSDU_INFO_IPV6_PROTO_M) >> FW_RX_MSDU_INFO_IPV6_PROTO_S)
 #define FW_RX_MSDU_INFO_IPV6_PROTO_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_IPV6_PROTO_S))
 
 #define FW_RX_MSDU_INFO_TCP_PROTO_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
+	(((_var) & FW_RX_MSDU_INFO_TCP_PROTO_M) >> FW_RX_MSDU_INFO_TCP_PROTO_S)
 #define FW_RX_MSDU_INFO_TCP_PROTO_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_TCP_PROTO_S))
 
 #define FW_RX_MSDU_INFO_UDP_PROTO_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
+	(((_var) & FW_RX_MSDU_INFO_UDP_PROTO_M) >> FW_RX_MSDU_INFO_UDP_PROTO_S)
 #define FW_RX_MSDU_INFO_UDP_PROTO_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_UDP_PROTO_S))
 
 #define FW_RX_MSDU_INFO_IP_FRAG_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
+	(((_var) & FW_RX_MSDU_INFO_IP_FRAG_M) >> FW_RX_MSDU_INFO_IP_FRAG_S)
 #define FW_RX_MSDU_INFO_IP_FRAG_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_IP_FRAG_S))
 
 #define FW_RX_MSDU_INFO_FIRST_WAKEUP_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
+	(((_var) & FW_RX_MSDU_INFO_FIRST_WAKEUP_M) >> FW_RX_MSDU_INFO_FIRST_WAKEUP_S)
 #define FW_RX_MSDU_INFO_FIRST_WAKEUP_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_FIRST_WAKEUP_S))
 
 
 /* monitor mode flags */
@@ -236,9 +237,7 @@ struct fw_rx_msdu_info {
 
 
 #define FW_RX_MSDU_INFO_MON_LAST_FRAG_GET(_var) \
-    (((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
+	(((_var) & FW_RX_MSDU_INFO_MON_LAST_FRAG_M) >> FW_RX_MSDU_INFO_MON_LAST_FRAG_S)
 #define FW_RX_MSDU_INFO_MON_LAST_FRAG_SET(_var, _val) \
-    ((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
-
-
+	((_var) |= ((_val) << FW_RX_MSDU_INFO_MON_LAST_FRAG_S))
 #endif /* _WAL_RX_DESC__H_ */

fw/wlan_module_ids.h

@@ -1,3 +1,23 @@
+/*
+ * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
 
 /*
  * This file was originally distributed by Qualcomm Atheros, Inc.
@@ -10,79 +30,79 @@
 
 /* Wlan module ids , global across all the modules */
 typedef enum {
-  WLAN_MODULE_ID_MIN = 0,
-  WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
-  WLAN_MODULE_WMI,                      /* 0x1 */
-  WLAN_MODULE_STA_PWRSAVE,              /* 0x2 */
-  WLAN_MODULE_WHAL,                     /* 0x3 */
-  WLAN_MODULE_COEX,                     /* 0x4 */
-  WLAN_MODULE_ROAM,                     /* 0x5 */
-  WLAN_MODULE_RESMGR_CHAN_MANAGER,      /* 0x6 */
-  WLAN_MODULE_RESMGR,                   /* 0x7 */
-  WLAN_MODULE_VDEV_MGR,                 /* 0x8 */
-  WLAN_MODULE_SCAN,                     /* 0x9 */
-  WLAN_MODULE_RATECTRL,                 /* 0xa */
-  WLAN_MODULE_AP_PWRSAVE,               /* 0xb */
-  WLAN_MODULE_BLOCKACK,                 /* 0xc */
-  WLAN_MODULE_MGMT_TXRX,                /* 0xd */
-  WLAN_MODULE_DATA_TXRX,                /* 0xe */
-  WLAN_MODULE_HTT,                      /* 0xf */
-  WLAN_MODULE_HOST,                     /* 0x10 */
-  WLAN_MODULE_BEACON,                   /* 0x11 */
-  WLAN_MODULE_OFFLOAD,                  /* 0x12 */
-  WLAN_MODULE_WAL,                      /* 0x13 */
-  WAL_MODULE_DE,                        /* 0x14 */
-  WLAN_MODULE_PCIELP,                   /* 0x15 */
-  WLAN_MODULE_RTT,                      /* 0x16 */
-  WLAN_MODULE_RESOURCE,                 /* 0x17 */
-  WLAN_MODULE_DCS,                      /* 0x18 */
-  WLAN_MODULE_CACHEMGR,                 /* 0x19 */
-  WLAN_MODULE_ANI,                      /* 0x1a */
-  WLAN_MODULE_P2P,                      /* 0x1b */
-  WLAN_MODULE_CSA,                      /* 0x1c */
-  WLAN_MODULE_NLO,                      /* 0x1d */
-  WLAN_MODULE_CHATTER,                  /* 0x1e */
-  WLAN_MODULE_WOW,                      /* 0x1f */
-  WLAN_MODULE_WAL_VDEV,                 /* 0x20 */
-  WLAN_MODULE_WAL_PDEV,                 /* 0x21 */
-  WLAN_MODULE_TEST,                     /* 0x22 */
-  WLAN_MODULE_STA_SMPS,                 /* 0x23 */
-  WLAN_MODULE_SWBMISS,                  /* 0x24 */
-  WLAN_MODULE_WMMAC,                    /* 0x25 */
-  WLAN_MODULE_TDLS,                     /* 0x26 */
-  WLAN_MODULE_HB,                       /* 0x27 */
-  WLAN_MODULE_TXBF,                     /* 0x28 */
-  WLAN_MODULE_BATCH_SCAN,               /* 0x29 */
-  WLAN_MODULE_THERMAL_MGR,              /* 0x2a */
-  WLAN_MODULE_PHYERR_DFS,               /* 0x2b */
-  WLAN_MODULE_RMC,                      /* 0x2c */
-  WLAN_MODULE_STATS,                    /* 0x2d */
-  WLAN_MODULE_NAN,                      /* 0x2e */
-  WLAN_MODULE_IBSS_PWRSAVE,             /* 0x2f */
-  WLAN_MODULE_HIF_UART,                 /* 0x30 */
-  WLAN_MODULE_LPI,                      /* 0x31 */
-  WLAN_MODULE_EXTSCAN,                  /* 0x32 */
-  WLAN_MODULE_UNIT_TEST,                /* 0x33 */
-  WLAN_MODULE_MLME,                     /* 0x34 */
-  WLAN_MODULE_SUPPL,                    /* 0x35 */
-  WLAN_MODULE_ERE,                      /* 0x36 */
-  WLAN_MODULE_OCB,                      /* 0x37 */
-  WLAN_MODULE_RSSI_MONITOR,             /* 0x38 */
-  WLAN_MODULE_WPM,                      /* 0x39 */
-  WLAN_MODULE_CSS,                      /* 0x3a */
-  WLAN_MODULE_PPS,                      /* 0x3b */
-  WLAN_MODULE_SCAN_CH_PREDICT,          /* 0x3c */
-  WLAN_MODULE_MAWC,                     /* 0x3d */
-  WLAN_MODULE_CMC_QMIC,                 /* 0x3e */
-  WLAN_MODULE_EGAP,                     /* 0x3f */
-  WLAN_MODULE_NAN20,                    /* 0x40 */
-  WLAN_MODULE_QBOOST,                   /* 0x41 */
-  WLAN_MODULE_P2P_LISTEN_OFFLOAD,       /* 0x42 */
-  WLAN_MODULE_HALPHY,                   /* 0x43 */
-  WAL_MODULE_ENQ,                       /* 0x44 */
+	WLAN_MODULE_ID_MIN = 0,
+	WLAN_MODULE_INF = WLAN_MODULE_ID_MIN, /* 0x0 */
+	WLAN_MODULE_WMI,                      /* 0x1 */
+	WLAN_MODULE_STA_PWRSAVE,              /* 0x2 */
+	WLAN_MODULE_WHAL,                     /* 0x3 */
+	WLAN_MODULE_COEX,                     /* 0x4 */
+	WLAN_MODULE_ROAM,                     /* 0x5 */
+	WLAN_MODULE_RESMGR_CHAN_MANAGER,      /* 0x6 */
+	WLAN_MODULE_RESMGR,                   /* 0x7 */
+	WLAN_MODULE_VDEV_MGR,                 /* 0x8 */
+	WLAN_MODULE_SCAN,                     /* 0x9 */
+	WLAN_MODULE_RATECTRL,                 /* 0xa */
+	WLAN_MODULE_AP_PWRSAVE,               /* 0xb */
+	WLAN_MODULE_BLOCKACK,                 /* 0xc */
+	WLAN_MODULE_MGMT_TXRX,                /* 0xd */
+	WLAN_MODULE_DATA_TXRX,                /* 0xe */
+	WLAN_MODULE_HTT,                      /* 0xf */
+	WLAN_MODULE_HOST,                     /* 0x10 */
+	WLAN_MODULE_BEACON,                   /* 0x11 */
+	WLAN_MODULE_OFFLOAD,                  /* 0x12 */
+	WLAN_MODULE_WAL,                      /* 0x13 */
+	WAL_MODULE_DE,                        /* 0x14 */
+	WLAN_MODULE_PCIELP,                   /* 0x15 */
+	WLAN_MODULE_RTT,                      /* 0x16 */
+	WLAN_MODULE_RESOURCE,                 /* 0x17 */
+	WLAN_MODULE_DCS,                      /* 0x18 */
+	WLAN_MODULE_CACHEMGR,                 /* 0x19 */
+	WLAN_MODULE_ANI,                      /* 0x1a */
+	WLAN_MODULE_P2P,                      /* 0x1b */
+	WLAN_MODULE_CSA,                      /* 0x1c */
+	WLAN_MODULE_NLO,                      /* 0x1d */
+	WLAN_MODULE_CHATTER,                  /* 0x1e */
+	WLAN_MODULE_WOW,                      /* 0x1f */
+	WLAN_MODULE_WAL_VDEV,                 /* 0x20 */
+	WLAN_MODULE_WAL_PDEV,                 /* 0x21 */
+	WLAN_MODULE_TEST,                     /* 0x22 */
+	WLAN_MODULE_STA_SMPS,                 /* 0x23 */
+	WLAN_MODULE_SWBMISS,                  /* 0x24 */
+	WLAN_MODULE_WMMAC,                    /* 0x25 */
+	WLAN_MODULE_TDLS,                     /* 0x26 */
+	WLAN_MODULE_HB,                       /* 0x27 */
+	WLAN_MODULE_TXBF,                     /* 0x28 */
+	WLAN_MODULE_BATCH_SCAN,               /* 0x29 */
+	WLAN_MODULE_THERMAL_MGR,              /* 0x2a */
+	WLAN_MODULE_PHYERR_DFS,               /* 0x2b */
+	WLAN_MODULE_RMC,                      /* 0x2c */
+	WLAN_MODULE_STATS,                    /* 0x2d */
+	WLAN_MODULE_NAN,                      /* 0x2e */
+	WLAN_MODULE_IBSS_PWRSAVE,             /* 0x2f */
+	WLAN_MODULE_HIF_UART,                 /* 0x30 */
+	WLAN_MODULE_LPI,                      /* 0x31 */
+	WLAN_MODULE_EXTSCAN,                  /* 0x32 */
+	WLAN_MODULE_UNIT_TEST,                /* 0x33 */
+	WLAN_MODULE_MLME,                     /* 0x34 */
+	WLAN_MODULE_SUPPL,                    /* 0x35 */
+	WLAN_MODULE_ERE,                      /* 0x36 */
+	WLAN_MODULE_OCB,                      /* 0x37 */
+	WLAN_MODULE_RSSI_MONITOR,             /* 0x38 */
+	WLAN_MODULE_WPM,                      /* 0x39 */
+	WLAN_MODULE_CSS,                      /* 0x3a */
+	WLAN_MODULE_PPS,                      /* 0x3b */
+	WLAN_MODULE_SCAN_CH_PREDICT,          /* 0x3c */
+	WLAN_MODULE_MAWC,                     /* 0x3d */
+	WLAN_MODULE_CMC_QMIC,                 /* 0x3e */
+	WLAN_MODULE_EGAP,                     /* 0x3f */
+	WLAN_MODULE_NAN20,                    /* 0x40 */
+	WLAN_MODULE_QBOOST,                   /* 0x41 */
+	WLAN_MODULE_P2P_LISTEN_OFFLOAD,       /* 0x42 */
+	WLAN_MODULE_HALPHY,                   /* 0x43 */
+	WAL_MODULE_ENQ,                       /* 0x44 */
 
-  WLAN_MODULE_ID_MAX,
-  WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
+	WLAN_MODULE_ID_MAX,
+	WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX,
 } WLAN_MODULE_ID;
 
 

fw/wlan_tgt_def_config.h

@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2011, 2014-2016 The Linux Foundation. All rights reserved.
+ *
+ * Previously licensed under the ISC license by Qualcomm Atheros, Inc.
+ *
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*
+ * This file was originally distributed by Qualcomm Atheros, Inc.
+ * under proprietary terms before Copyright ownership was assigned
+ * to the Linux Foundation.
+ */
+
+#ifndef __WLAN_TGT_DEF_CONFIG_H__
+#define __WLAN_TGT_DEF_CONFIG_H__
+
+/*
+ * set of default target config , that can be over written by platform
+ */
+
+/*
+ * default limit of 8 VAPs per device.
+ */
+/* Rome PRD support 4 vdevs */
+#define CFG_TGT_NUM_VDEV                4
+
+/*
+ * We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize hash collisions.
+ * TODO: This scaling factor would be taken care inside the WAL in the future.
+ */
+#define CFG_TGT_NUM_PEER_AST            2
+
+/* # of WDS entries to support.
+ */
+#define CFG_TGT_WDS_ENTRIES             0
+
+/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
+ */
+#define CFG_TGT_DEFAULT_DMA_BURST_SIZE   0
+
+/* Fixed delimiters to be inserted after every MPDU
+ */
+#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM   0
+
+/*
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_AST_SKID_LIMIT          16
+
+/*
+ * total number of peers per device.
+ */
+#define CFG_TGT_NUM_PEERS               14
+
+/*
+ * In offload mode target supports features like WOW, chatter and other
+ * protocol offloads. In order to support them some functionalities like
+ * reorder buffering, PN checking need to be done in target. This determines
+ * maximum number of peers suported by target in offload mode
+ */
+
+/*
+ * The current firmware implementation requires the number of offload peers
+ * should be (number of vdevs + 1).
+
+ * The reason for this is the firmware clubbed the self peer and offload peer
+ * in the same pool. So if the firmware wanted to support n vdevs then the
+ * number of offload peer must be n+1 of which n buffers will be used for
+ * self peer and the remaining 1 is used for offload peer to support chatter
+ * mode for single STA.
+
+ * Technically the macro should be 1 however the current firmware requires n+1.
+
+ * TODO: This MACRO need to be modified in the future, if the firmware modified
+ * to allocate buffers for self peer and offload peer independently.
+ */
+
+#define CFG_TGT_NUM_OFFLOAD_PEERS       (CFG_TGT_NUM_VDEV+1)
+
+/*
+ * Number of reorder buffers used in offload mode
+ */
+#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS   4
+
+/*
+ * keys per peer node
+ */
+#define CFG_TGT_NUM_PEER_KEYS           2
+/*
+ * total number of data TX and RX TIDs
+ */
+#define CFG_TGT_NUM_TIDS       (2 * (CFG_TGT_NUM_PEERS + CFG_TGT_NUM_VDEV + 2))
+/*
+ * set this to 0x7 (Peregrine = 3 chains).
+ * need to be set dynamically based on the HW capability.
+ */
+#define CFG_TGT_DEFAULT_TX_CHAIN_MASK   0x7
+/*
+ * set this to 0x7 (Peregrine = 3 chains).
+ * need to be set dynamically based on the HW capability.
+ */
+#define CFG_TGT_DEFAULT_RX_CHAIN_MASK   0x7
+/* 100 ms for video, best-effort, and background */
+#define CFG_TGT_RX_TIMEOUT_LO_PRI       100
+/* 40 ms for voice*/
+#define CFG_TGT_RX_TIMEOUT_HI_PRI       40
+
+/* AR9888 unified is default in ethernet mode */
+#define CFG_TGT_RX_DECAP_MODE (0x2)
+/* Decap to native Wifi header */
+#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
+/* Decap to raw mode header */
+#define CFG_TGT_RX_DECAP_MODE_RAW   (0x0)
+
+/* maximum number of pending scan requests */
+#define CFG_TGT_DEFAULT_SCAN_MAX_REQS   0x4
+
+/* maximum number of VDEV that could use BMISS offload */
+#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV   0x3
+
+/* maximum number of VDEV offload Roaming to support */
+#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV   0x3
+
+/* maximum number of AP profiles pushed to offload Roaming */
+#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES   0x8
+
+/* maximum number of VDEV offload GTK to support */
+#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV   0x3
+
+/* default: mcast->ucast disabled if ATH_SUPPORT_MCAST2UCAST not defined */
+#ifndef ATH_SUPPORT_MCAST2UCAST
+#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
+#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
+#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0      /* disabled */
+#else
+/* (for testing) small multicast group membership table enabled */
+#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 4
+#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 16
+#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 2
+#endif
+
+#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 32
+/*
+ * Specify how much memory the target should allocate for a debug log of
+ * tx PPDU meta-information (how large the PPDU was, when it was sent,
+ * whether it was successful, etc.)
+ * The size of the log records is configurable, from a minimum of 28 bytes
+ * to a maximum of about 300 bytes.  A typical configuration would result
+ * in each log record being about 124 bytes.
+ * Thus, 1KB of log space can hold about 30 small records, 3 large records,
+ * or about 8 typical-sized records.
+ */
+#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024    /* bytes */
+
+/* target based fragment timeout and MPDU duplicate detection */
+#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
+
+/*  Default VoW configuration
+ */
+#define CFG_TGT_DEFAULT_VOW_CONFIG   0
+
+/*
+ * total number of descriptors to use in the target
+ */
+#define CFG_TGT_NUM_MSDU_DESC    (1024 + 32)
+
+/*
+ * Maximum number of frag table entries
+ */
+#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 10
+
+/*
+ * Maximum number of VDEV that beacon tx offload will support
+ */
+#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 3
+
+/*
+ * number of vdevs that can support tdls
+ */
+#define CFG_TGT_NUM_TDLS_VDEVS    1
+
+/*
+ * number of peers that each Tdls vdev can track
+ */
+#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES    32
+
+/*
+ * number of TDLS concurrent sleep STAs
+ */
+#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS    1
+
+/*
+ * number of TDLS concurrent buffer STAs
+ */
+#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS    1
+
+/*
+ * ht enable highest MCS by default
+ */
+#define CFG_TGT_DEFAULT_GTX_HT_MASK             0x8080
+/*
+ * vht enable highest MCS by default
+ */
+#define CFG_TGT_DEFAULT_GTX_VHT_MASK            0x80200
+/*
+ * threshold to enable GTX
+ */
+#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD       3
+/*
+ * margin to move back when per > margin + threshold
+ */
+#define CFG_TGT_DEFAULT_GTX_PER_MARGIN          2
+/*
+ * step for every move
+ */
+#define CFG_TGT_DEFAULT_GTX_TPC_STEP            1
+/*
+ * lowest TPC
+ */
+#define CFG_TGT_DEFAULT_GTX_TPC_MIN             0
+/*
+ * enable all BW 20/40/80/160
+ */
+#define CFG_TGT_DEFAULT_GTX_BW_MASK             0xf
+
+/*
+ * number of vdevs that can support OCB
+ */
+#define CFG_TGT_NUM_OCB_VDEVS			1
+
+/*
+ * maximum number of channels that can do OCB
+ */
+#define CFG_TGT_NUM_OCB_CHANNELS		2
+
+/*
+ * maximum number of channels in an OCB schedule
+ */
+#define CFG_TGT_NUM_OCB_SCHEDULES		2
+
+#endif /*__WLAN_TGT_DEF_CONFIG_H__ */

fw/wlan_tgt_def_config_hl.h

@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef __WLAN_TGT_DEF_CONFIG_H__
+#define __WLAN_TGT_DEF_CONFIG_H__
+
+/*
+ * TODO: please help to consider if we need a seperate config file from LL case.
+ */
+
+/*
+ * set of default target config , that can be over written by platform
+ */
+
+#ifdef QCA_SUPPORT_INTEGRATED_SOC
+#define CFG_TGT_NUM_VDEV                3 /*STA, P2P device, P2P GO/Cli*/
+#else
+/*
+ * default limit of VAPs per device.
+ */
+#define CFG_TGT_NUM_VDEV                3
+#endif
+/*
+ * We would need 1 AST entry per peer. Scale it by a factor of 2 to minimize
+ * hash collisions.
+ * TODO: This scaling factor would be taken care inside the WAL in the future.
+ */
+#define CFG_TGT_NUM_PEER_AST            2
+
+/* # of WDS entries to support.
+ */
+#define CFG_TGT_WDS_ENTRIES             2
+
+/* MAC DMA burst size. 0: 128B - default, 1: 256B, 2: 64B
+ */
+#define CFG_TGT_DEFAULT_DMA_BURST_SIZE   0
+
+/* Fixed delimiters to be inserted after every MPDU
+ */
+#define CFG_TGT_DEFAULT_MAC_AGGR_DELIM   0
+
+/*
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_AST_SKID_LIMIT          6
+/*
+ * total number of peers per device.
+ * currently set to 8 to bring up IP3.9 for memory size problem
+ */
+#define CFG_TGT_NUM_PEERS               8
+/*
+ *  max number of peers per device.
+ */
+#define CFG_TGT_NUM_PEERS_MAX           8
+/*
+ * In offload mode target supports features like WOW, chatter and other
+ * protocol offloads. In order to support them some functionalities like
+ * reorder buffering, PN checking need to be done in target. This determines
+ * maximum number of peers suported by target in offload mode
+ */
+#define CFG_TGT_NUM_OFFLOAD_PEERS       0
+/*
+ * Number of reorder buffers used in offload mode
+ */
+#define CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS   0
+/*
+ * keys per peer node
+ */
+#define CFG_TGT_NUM_PEER_KEYS           2
+/*
+ * total number of TX/RX data TIDs
+ */
+#define CFG_TGT_NUM_TIDS      (2 * (CFG_TGT_NUM_PEERS + \
+					CFG_TGT_NUM_VDEV))
+/*
+ * max number of Tx TIDS
+ */
+#define CFG_TGT_NUM_TIDS_MAX   (2 * (CFG_TGT_NUM_PEERS_MAX + \
+					CFG_TGT_NUM_VDEV))
+/*
+ * number of multicast keys.
+ */
+#define CFG_TGT_NUM_MCAST_KEYS          8
+/*
+ * A value of 3 would probably suffice - one for the control stack, one for
+ * the data stack, and one for debugging.
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_NUM_PDEV_HANDLERS       8
+/*
+ * A value of 3 would probably suffice - one for the control stack, one for
+ * the data stack, and one for debugging.
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_NUM_VDEV_HANDLERS       4
+/*
+ * set this to 8:
+ *     one for WAL interals (connection pause)
+ *     one for the control stack,
+ *     one for the data stack
+ *     and one for debugging
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_NUM_HANDLERS            14
+/*
+ * set this to 3: one for the control stack, one for
+ * the data stack, and one for debugging.
+ * This value may need to be fine tuned, but a constant value will
+ * probably always be appropriate; it is probably not necessary to
+ * determine this value dynamically.
+ */
+#define CFG_TGT_NUM_PEER_HANDLERS       32
+/*
+ * set this to 0x7 (Peregrine = 3 chains).
+ * need to be set dynamically based on the HW capability.
+ * this is rome
+ */
+#define CFG_TGT_DEFAULT_TX_CHAIN_MASK   0x3
+/*
+ * set this to 0x7 (Peregrine = 3 chains).
+ * need to be set dynamically based on the HW capability.
+ * this is rome
+ */
+#define CFG_TGT_DEFAULT_RX_CHAIN_MASK   0x3
+/* 100 ms for video, best-effort, and background */
+#define CFG_TGT_RX_TIMEOUT_LO_PRI       100
+/* 40 ms for voice*/
+#define CFG_TGT_RX_TIMEOUT_HI_PRI       40
+
+/* AR9888 unified is default in ethernet mode */
+#define CFG_TGT_RX_DECAP_MODE (0x2)
+/* Decap to native Wifi header */
+#define CFG_TGT_RX_DECAP_MODE_NWIFI (0x1)
+
+/* Decap to raw mode header */
+#define CFG_TGT_RX_DECAP_MODE_RAW   (0x0)
+
+/* maximum number of pending scan requests */
+#define CFG_TGT_DEFAULT_SCAN_MAX_REQS   0x4
+
+/* maximum number of scan event handlers */
+#define CFG_TGT_DEFAULT_SCAN_MAX_HANDLERS   0x4
+
+/* maximum number of VDEV that could use BMISS offload */
+#define CFG_TGT_DEFAULT_BMISS_OFFLOAD_MAX_VDEV   0x2
+
+/* maximum number of VDEV offload Roaming to support */
+#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_VDEV   0x2
+
+/* maximum number of AP profiles pushed to offload Roaming */
+#define CFG_TGT_DEFAULT_ROAM_OFFLOAD_MAX_PROFILES   0x8
+
+/* maximum number of VDEV offload GTK to support */
+#define CFG_TGT_DEFAULT_GTK_OFFLOAD_MAX_VDEV   0x2
+/* default: mcast->ucast disabled */
+
+#define CFG_TGT_DEFAULT_NUM_MCAST_GROUPS 0
+#define CFG_TGT_DEFAULT_NUM_MCAST_TABLE_ELEMS 0
+#define CFG_TGT_DEFAULT_MCAST2UCAST_MODE 0 /* disabled */
+
+/*
+ * Specify how much memory the target should allocate for a debug log of
+ * tx PPDU meta-information (how large the PPDU was, when it was sent,
+ * whether it was successful, etc.)
+ * The size of the log records is configurable, from a minimum of 28 bytes
+ * to a maximum of about 300 bytes.  A typical configuration would result
+ * in each log record being about 124 bytes.
+ * Thus, 1KB of log space can hold about 30 small records, 3 large records,
+ * or about 8 typical-sized records.
+ */
+#define CFG_TGT_DEFAULT_TX_DBG_LOG_SIZE 1024 /* bytes */
+
+/* target based fragment timeout and MPDU duplicate detection */
+#define CFG_TGT_DEFAULT_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
+/*  Default VoW configuration
+ */
+#define CFG_TGT_DEFAULT_VOW_CONFIG   0
+
+/*
+ * total number of descriptors to use in the target
+ */
+#ifndef HIF_SDIO
+#define CFG_TGT_NUM_MSDU_DESC    (32)
+#else
+#define CFG_TGT_NUM_MSDU_DESC    (0)
+#endif
+/*
+ * Maximum number of frag table entries
+ */
+#define CFG_TGT_MAX_FRAG_TABLE_ENTRIES 2
+
+/*
+ * number of vdevs that can support tdls
+ */
+#define CFG_TGT_NUM_TDLS_VDEVS    1
+
+/*
+ * number of peers that each Tdls vdev can track
+ */
+#define CFG_TGT_NUM_TDLS_CONN_TABLE_ENTRIES    32
+/*
+ * number of TDLS concurrent sleep STAs
+ */
+#define CFG_TGT_NUM_TDLS_CONC_SLEEP_STAS    1
+
+/*
+ * number of TDLS concurrent buffer STAs
+ */
+#define CFG_TGT_NUM_TDLS_CONC_BUFFER_STAS    1
+
+#define CFG_TGT_MAX_MULTICAST_FILTER_ENTRIES 16
+/*
+ * Maximum number of VDEV that beacon tx offload will support
+ */
+#ifdef HIF_SDIO
+#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 2
+#else
+#define CFG_TGT_DEFAULT_BEACON_TX_OFFLOAD_MAX_VDEV 1
+#endif
+
+/*
+ * ht enable highest MCS by default
+ */
+#define CFG_TGT_DEFAULT_GTX_HT_MASK     0x8080
+/*
+ * vht enable highest MCS by default
+ */
+#define CFG_TGT_DEFAULT_GTX_VHT_MASK        0x80200
+/*
+ * threshold to enable GTX
+ */
+#define CFG_TGT_DEFAULT_GTX_PER_THRESHOLD   3
+/*
+ * margin to move back when per > margin + threshold
+ */
+#define CFG_TGT_DEFAULT_GTX_PER_MARGIN      2
+/*
+ * step for every move
+ */
+#define CFG_TGT_DEFAULT_GTX_TPC_STEP        1
+/*
+ * lowest TPC
+ */
+#define CFG_TGT_DEFAULT_GTX_TPC_MIN     0
+/*
+ * enable all BW 20/40/80/160
+ */
+#define CFG_TGT_DEFAULT_GTX_BW_MASK     0xf
+
+/*
+ * number of vdevs that can support OCB
+ */
+#define CFG_TGT_NUM_OCB_VDEVS			1
+
+/*
+ * maximum number of channels that can do OCB
+ */
+#define CFG_TGT_NUM_OCB_CHANNELS		2
+
+/*
+ * maximum number of channels in an OCB schedule
+ */
+#define CFG_TGT_NUM_OCB_SCHEDULES		2
+
+#endif  /*__WLAN_TGT_DEF_CONFIG_H__ */

fw/wmi.h

@@ -50,7 +50,6 @@
 extern "C" {
 #endif
 
-
 #define HTC_PROTOCOL_VERSION    0x0002
 
 #define WMI_PROTOCOL_VERSION    0x0002
@@ -58,37 +57,38 @@ extern "C" {
 #define WMI_MODE_MAX              8
 #define WMI_MAX_RATE_MASK         6
 
-
 PREPACK struct host_app_area_s {
-    A_UINT32 wmi_protocol_ver;
+	A_UINT32 wmi_protocol_ver;
 } POSTPACK;
 
-
 #undef MS
-#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
+#define MS(_v, _f) (((_v) & _f ## _MASK) >> _f ## _LSB)
 #undef SM
-#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
+#define SM(_v, _f) (((_v) << _f ## _LSB) & _f ## _MASK)
 #undef WO
-#define WO(_f)      ((_f##_OFFSET) >> 2)
+#define WO(_f)      ((_f ## _OFFSET) >> 2)
 
 #undef GET_FIELD
 #define GET_FIELD(_addr, _f) MS(*((A_UINT32 *)(_addr) + WO(_f)), _f)
 #undef SET_FIELD
 #define SET_FIELD(_addr, _f, _val)  \
-    (*((A_UINT32 *)(_addr) + WO(_f)) = \
-     (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f##_MASK) | SM(_val, _f))
+	(*((A_UINT32 *)(_addr) + WO(_f)) = \
+		 (*((A_UINT32 *)(_addr) + WO(_f)) & ~_f ## _MASK) | SM(_val, _f))
 
 #define WMI_GET_FIELD(_msg_buf, _msg_type, _f) \
-    GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
+	GET_FIELD(_msg_buf, _msg_type ## _ ## _f)
 
 #define WMI_SET_FIELD(_msg_buf, _msg_type, _f, _val) \
-    SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
+	SET_FIELD(_msg_buf, _msg_type ## _ ## _f, _val)
 
-#define WMI_EP_APASS WMI_EP_APSS /* TYPO: leave incorrect name as an alias for the correct name */
-#define WMI_EP_APSS            0x0 /* WLAN driver running on apps processor sub-system */
+/* TYPO: leave incorrect name as an alias for the correct name */
+#define WMI_EP_APASS WMI_EP_APSS
+/* WLAN driver running on apps processor sub-system */
+#define WMI_EP_APSS            0x0
 #define WMI_EP_LPASS           0x1
 #define WMI_EP_SENSOR          0x2
-#define WMI_EP_NANOHUB         0x3 /* WLAN driver running on NANO Hub */
+/* WLAN driver running on NANO Hub */
+#define WMI_EP_NANOHUB         0x3
 #define WMI_EP_MODEM           0x4
 #define WMI_EP_LOCATION        0x5
 
@@ -96,37 +96,35 @@ PREPACK struct host_app_area_s {
  * Control Path
  */
 typedef PREPACK struct {
-    A_UINT32    commandId : 24,
-                reserved  : 2, /* used for WMI endpoint ID */
-                plt_priv  : 6; /* platform private */
-} POSTPACK WMI_CMD_HDR;        /* used for commands and events */
+	A_UINT32 commandId : 24, reserved : 2,          /* used for WMI endpoint ID */
+		 plt_priv : 6;    /* platform private */
+} POSTPACK WMI_CMD_HDR;         /* used for commands and events */
 
 #define WMI_CMD_HDR_COMMANDID_LSB           0
 #define WMI_CMD_HDR_COMMANDID_MASK          0x00ffffff
 #define WMI_CMD_HDR_COMMANDID_OFFSET        0x00000000
-#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK        0x03000000
-#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET      24
-#define WMI_CMD_HDR_PLT_PRIV_LSB               24
-#define WMI_CMD_HDR_PLT_PRIV_MASK              0xff000000
-#define WMI_CMD_HDR_PLT_PRIV_OFFSET            0x00000000
+#define WMI_CMD_HDR_WMI_ENDPOINTID_MASK     0x03000000
+#define WMI_CMD_HDR_WMI_ENDPOINTID_OFFSET   24
+#define WMI_CMD_HDR_PLT_PRIV_LSB            24
+#define WMI_CMD_HDR_PLT_PRIV_MASK           0xff000000
+#define WMI_CMD_HDR_PLT_PRIV_OFFSET         0x00000000
 
 /*
  * List of Commnands
  */
 typedef enum {
-    WMI_EXTENSION_CMDID,                     //used in wmi_svc.c   /* Non-wireless extensions */
-    WMI_IGNORE_CMDID,				//used in wlan_wmi.c
+	WMI_EXTENSION_CMDID,            /* used in wmi_svc.c   / * Non-wireless extensions * / */
+	WMI_IGNORE_CMDID,               /* used in wlan_wmi.c */
 } WMI_COMMAND_ID;
 
-
 typedef enum {
-    NONE_CRYPT          = 0x01,
-    WEP_CRYPT           = 0x02,
-    TKIP_CRYPT          = 0x04,
-    AES_CRYPT           = 0x08,
+	NONE_CRYPT = 0x01,
+	WEP_CRYPT = 0x02,
+	TKIP_CRYPT = 0x04,
+	AES_CRYPT = 0x08,
 #ifdef WAPI_ENABLE
-    WAPI_CRYPT          = 0x10,
-#endif /*WAPI_ENABLE*/
+	WAPI_CRYPT = 0x10,
+#endif /*WAPI_ENABLE */
 } CRYPTO_TYPE;
 
 #define WMI_MAX_SSID_LEN    32
@@ -136,63 +134,63 @@ typedef enum {
  */
 #define WMI_PMK_LEN     32
 
-
 /*
  * WMI_ADD_CIPHER_KEY_CMDID
  */
 typedef enum {
-    PAIRWISE_USAGE      = 0x00,
-    GROUP_USAGE         = 0x01,
-    TX_USAGE            = 0x02,     /* default Tx Key - Static WEP only */
+	PAIRWISE_USAGE = 0x00,
+	GROUP_USAGE = 0x01,
+	TX_USAGE = 0x02,                /* default Tx Key - Static WEP only */
 } KEY_USAGE;
+
 /*
  * List of Events (target to host)
  */
 typedef enum {
-    WMI_EXTENSION_EVENTID			//wmi_profhook.c and umac_wmi_events.c
+	WMI_EXTENSION_EVENTID,          /* wmi_profhook.c and umac_wmi_events.c */
 } WMI_EVENT_ID;
 
 typedef enum {
-    WMI_11A_CAPABILITY   = 1,
-    WMI_11G_CAPABILITY   = 2,
-    WMI_11AG_CAPABILITY  = 3,
-    WMI_11NA_CAPABILITY  = 4,
-    WMI_11NG_CAPABILITY  = 5,
-    WMI_11NAG_CAPABILITY = 6,
-    WMI_11AC_CAPABILITY  = 7,
-    WMI_11AX_CAPABILITY  = 8,
-    // END CAPABILITY
-    WMI_11N_CAPABILITY_OFFSET = (WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
+	WMI_11A_CAPABILITY = 1,
+	WMI_11G_CAPABILITY = 2,
+	WMI_11AG_CAPABILITY = 3,
+	WMI_11NA_CAPABILITY = 4,
+	WMI_11NG_CAPABILITY = 5,
+	WMI_11NAG_CAPABILITY = 6,
+	WMI_11AC_CAPABILITY = 7,
+	WMI_11AX_CAPABILITY = 8,
+	/* END CAPABILITY */
+	WMI_11N_CAPABILITY_OFFSET =
+		(WMI_11NA_CAPABILITY - WMI_11A_CAPABILITY),
 } WMI_PHY_CAPABILITY;
 
-
 /* Deprectated, need clean up */
 #define WMI_MAX_RX_META_SZ  (12)
 
 typedef PREPACK struct {
-    A_INT8      rssi;
-    A_UINT8     info;               /* usage of 'info' field(8-bit):
-                                     *  b1:b0       - WMI_MSG_TYPE
-                                     *  b4:b3:b2    - UP(tid)
-                                     *  b5          - Used in AP mode. More-data in tx dir, PS in rx.
-                                     *  b7:b6       -  Dot3 header(0),
-                                     *                 Dot11 Header(1),
-                                     *                 ACL data(2)
-                                     */
-
-    A_UINT16    info2;              /* usage of 'info2' field(16-bit):
-                                     * b11:b0       - seq_no
-                                     * b12          - A-MSDU?
-                                     * b15:b13      - META_DATA_VERSION 0 - 7
-                                     */
-    A_UINT16    info3;              /* b3:b2:b1:b0  - device id
-                                     * b4           - Used in AP mode. uAPSD trigger in rx, EOSP in tx
-                                     * b7:b5        - unused?
-                                     * b15:b8       - pad before data start(irrespective of meta version)
-                                     */
+	A_INT8 rssi;
+	A_UINT8 info;           /* usage of 'info' field(8-bit):
+	                         *  b1:b0       - WMI_MSG_TYPE
+	                         *  b4:b3:b2    - UP(tid)
+	                         *  b5          - Used in AP mode. More-data in tx dir, PS in rx.
+	                         *  b7:b6       -  Dot3 header(0),
+	                         *                 Dot11 Header(1),
+	                         *                 ACL data(2)
+	                         */
+
+	A_UINT16 info2;         /* usage of 'info2' field(16-bit):
+	                         * b11:b0       - seq_no
+	                         * b12          - A-MSDU?
+	                         * b15:b13      - META_DATA_VERSION 0 - 7
+	                         */
+	A_UINT16 info3;         /* b3:b2:b1:b0  - device id
+	                         * b4           - Used in AP mode. uAPSD trigger in rx, EOSP in tx
+	                         * b7:b5        - unused?
+	                         * b15:b8       - pad before data start(irrespective of meta version)
+	                         */
 } POSTPACK WMI_DATA_HDR;
+
 #ifdef __cplusplus
 }
 #endif
-
 #endif /* _WMI_H_ */

fw/wmi_services.h

@@ -35,170 +35,262 @@
 #ifndef _WMI_SERVICES_H_
 #define _WMI_SERVICES_H_
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 
 
-typedef  enum  {
-    WMI_SERVICE_BEACON_OFFLOAD=0,           /* beacon offload */
-    WMI_SERVICE_SCAN_OFFLOAD=1,             /* scan offload */
-    WMI_SERVICE_ROAM_SCAN_OFFLOAD=2,        /* roam scan offload */
-    WMI_SERVICE_BCN_MISS_OFFLOAD=3,         /* beacon miss offload */
-    WMI_SERVICE_STA_PWRSAVE=4,              /* fake sleep + basic power save */
-    WMI_SERVICE_STA_ADVANCED_PWRSAVE=5,     /* uapsd, pspoll, force sleep */
-    WMI_SERVICE_AP_UAPSD=6,                 /* uapsd on AP */
-    WMI_SERVICE_AP_DFS=7,                   /* DFS on AP */
-    WMI_SERVICE_11AC=8,                     /* supports 11ac */
-    WMI_SERVICE_BLOCKACK=9,                 /* Supports triggering ADDBA/DELBA from host*/
-    WMI_SERVICE_PHYERR=10,                  /* PHY error */
-    WMI_SERVICE_BCN_FILTER=11,              /* Beacon filter support */
-    WMI_SERVICE_RTT=12,                     /* RTT (round trip time) support */
-    WMI_SERVICE_WOW=13,                     /* WOW Support */
-    WMI_SERVICE_RATECTRL_CACHE=14,          /* Rate-control caching */
-    WMI_SERVICE_IRAM_TIDS=15,               /* TIDs in IRAM */
-    WMI_SERVICE_ARPNS_OFFLOAD=16,           /* ARP NS Offload support for STA vdev */
-    WMI_SERVICE_NLO=17,                     /* Network list offload service */
-    WMI_SERVICE_GTK_OFFLOAD=18,             /* GTK offload */
-    WMI_SERVICE_SCAN_SCH=19,                /* Scan Scheduler Service */
-    WMI_SERVICE_CSA_OFFLOAD=20,             /* CSA offload service */
-    WMI_SERVICE_CHATTER=21,                 /* Chatter service */
-    WMI_SERVICE_COEX_FREQAVOID=22,          /* FW report freq range to avoid */
-    WMI_SERVICE_PACKET_POWER_SAVE=23,       /* packet power save service */
-    WMI_SERVICE_FORCE_FW_HANG=24,           /* Service to test the firmware recovery mechanism */
-    WMI_SERVICE_GPIO=25,                    /* GPIO service */
-    WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM=26, /* Modulated DTIM support */
-    WMI_STA_UAPSD_BASIC_AUTO_TRIG=27,       /* Basic version of station UAPSD AC Trigger Generation Method with
-                                             * variable tigger periods (service, delay, and suspend intervals) */
-    WMI_STA_UAPSD_VAR_AUTO_TRIG=28,         /* Station UAPSD AC Trigger Generation Method with variable
-                                             * trigger periods (service, delay, and suspend intervals) */
-    WMI_SERVICE_STA_KEEP_ALIVE=29,          /* Serivce to support the STA KEEP ALIVE mechanism */
-    WMI_SERVICE_TX_ENCAP=30,                /* Packet type for TX encapsulation */
-    WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC=31, /* detect out-of-sync sleeping stations */
-    WMI_SERVICE_EARLY_RX=32,                /* adaptive early-rx feature */
-    WMI_SERVICE_STA_SMPS=33,                /* STA MIMO-PS */
-    WMI_SERVICE_FWTEST=34,                  /* Firmware test service */
-    WMI_SERVICE_STA_WMMAC=35,               /* STA WMMAC */
-    WMI_SERVICE_TDLS=36,                    /* TDLS support */
-    WMI_SERVICE_BURST=37,                   /* SIFS spaced burst support */
-    WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE=38, /* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
-    WMI_SERVICE_ADAPTIVE_OCS=39,            /* Service to support adaptive off-channel scheduler */
-    WMI_SERVICE_BA_SSN_SUPPORT=40,          /* target will provide Sequence number for the peer/tid combo */
-    WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE=41,
-    WMI_SERVICE_WLAN_HB=42,                 /* wlan HB service */
-    WMI_SERVICE_LTE_ANT_SHARE_SUPPORT=43,   /* support LTE/WLAN antenna sharing */
-    WMI_SERVICE_BATCH_SCAN=44,              /* Service to support batch scan */
-    WMI_SERVICE_QPOWER=45,                  /* QPower service */
-    WMI_SERVICE_PLMREQ=46,
-    WMI_SERVICE_THERMAL_MGMT=47,            /* thermal throttling support */
-    WMI_SERVICE_RMC=48,                     /* RMC support */
-    WMI_SERVICE_MHF_OFFLOAD=49,             /* multi-hop forwarding offload */
-    WMI_SERVICE_COEX_SAR=50,                /* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
-    WMI_SERVICE_BCN_TXRATE_OVERRIDE=51,     /* Will support the bcn/prb rsp rate override */
-    WMI_SERVICE_NAN=52,                     /* Neighbor Awareness Network */
-    WMI_SERVICE_L1SS_STAT=53,               /* L1SS statistics counter report */
-    WMI_SERVICE_ESTIMATE_LINKSPEED=54,      /* Linkspeed Estimation per peer */
-    WMI_SERVICE_OBSS_SCAN=55,               /* Service to support OBSS scan */
-    WMI_SERVICE_TDLS_OFFCHAN=56,            /* TDLS off channel support */
-    WMI_SERVICE_TDLS_UAPSD_BUFFER_STA=57,   /* TDLS UAPSD Buffer STA support */
-    WMI_SERVICE_TDLS_UAPSD_SLEEP_STA=58,    /* TDLS UAPSD Sleep STA support */
-    WMI_SERVICE_IBSS_PWRSAVE=59,            /* IBSS power save support */
-    WMI_SERVICE_LPASS=60,                   /* Service to support LPASS */
-    WMI_SERVICE_EXTSCAN=61,                 /* Extended Scans */
-    WMI_SERVICE_D0WOW=62,                   /* D0-WOW Support */
-    WMI_SERVICE_HSOFFLOAD=63,               /* Hotspot offload feature Support */
-    WMI_SERVICE_ROAM_HO_OFFLOAD=64,         /* roam handover offload */
-    WMI_SERVICE_RX_FULL_REORDER=65,         /* target-based Rx full reorder */
-    WMI_SERVICE_DHCP_OFFLOAD=66,            /* DHCP offload support */
-    WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT=67, /* STA RX DATA offload to IPA support */
-    WMI_SERVICE_MDNS_OFFLOAD=68,            /* mDNS responder offload support */
-    WMI_SERVICE_SAP_AUTH_OFFLOAD=69,        /* softap auth offload */
-    WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT=70, /* Dual Band Simultaneous support */
-    WMI_SERVICE_OCB=71,                     /* OCB mode support */
-    WMI_SERVICE_AP_ARPNS_OFFLOAD=72,        /* arp offload support for ap mode vdev */
-    WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT=73, /* Per band chainmask support */
-    WMI_SERVICE_PACKET_FILTER_OFFLOAD=74,   /* Per vdev packet filters */
-    WMI_SERVICE_MGMT_TX_HTT=75,             /* Mgmt Tx via HTT interface */
-    WMI_SERVICE_MGMT_TX_WMI=76,             /* Mgmt Tx via WMI interface */
-    WMI_SERVICE_EXT_MSG=77,                 /* WMI_SERVICE_READY_EXT msg follows */
-    WMI_SERVICE_MAWC=78,                    /* Motion Aided WiFi Connectivity (MAWC)*/
-    WMI_SERVICE_PEER_ASSOC_CONF=79,         /* target will send ASSOC_CONF after ASSOC_CMD is processed */
-    WMI_SERVICE_EGAP=80,                    /* enhanced green ap support */
-    WMI_SERVICE_STA_PMF_OFFLOAD=81,         /* FW supports 11W PMF Offload for STA */
-    WMI_SERVICE_UNIFIED_WOW_CAPABILITY=82,  /* FW supports unified D0 and D3 wow */
-    WMI_SERVICE_ENHANCED_PROXY_STA=83,      /* Enhanced ProxySTA mode support */
-    WMI_SERVICE_ATF=84,                     /* Air Time Fairness support */
-    WMI_SERVICE_COEX_GPIO=85,               /* BTCOEX GPIO support */
-    WMI_SERVICE_AUX_SPECTRAL_INTF=86,       /* Aux Radio enhancement support for ignoring spectral scan intf from main radios */
-    WMI_SERVICE_AUX_CHAN_LOAD_INTF=87,      /* Aux Radio enhancement support for ignoring chan load intf from main radios*/
-    WMI_SERVICE_BSS_CHANNEL_INFO_64=88,     /* BSS channel info (freq, noise floor, 64-bit counters) event support */
-    WMI_SERVICE_ENTERPRISE_MESH=89,         /* Enterprise MESH Service Support */
-    WMI_SERVICE_RESTRT_CHNL_SUPPORT=90,     /* Restricted Channel Support */
-    WMI_SERVICE_BPF_OFFLOAD=91,             /* FW supports bpf offload */
-    WMI_SERVICE_SYNC_DELETE_CMDS=92,        /* FW sends response event for Peer, Vdev delete commands */
-    WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT=93,
-    WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT=94,
-    WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES=95, /* allow per-peer tx MCS min/max limits by host */
-    WMI_SERVICE_NAN_DATA=96,                /* FW supports NAN data */
-    WMI_SERVICE_NAN_RTT=97,                 /* FW supports NAN RTT */
-    WMI_SERVICE_11AX=98,                    /* FW supports 802.11ax */
-    /* WMI_SERVICE_DEPRECATED_REPLACE
-     * FW supports these new WMI commands, to be used rather than
-     * deprecated matching commands:
-     * - WMI_PDEV_SET_PCL_CMDID          (vs. WMI_SOC_SET_PCL_CMDID)
-     * - WMI_PDEV_SET_HW_MODE_CMDID      (vs. WMI_SOC_SET_HW_MODE_CMDID)
-     * - WMI_PDEV_SET_MAC_CONFIG_CMDID   (vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
-     * - WMI_PDEV_SET_ANTENNA_MODE_CMDID (vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
-     * - WMI_VDEV_SET_DSCP_TID_MAP_CMDID (vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
-     */
-    WMI_SERVICE_DEPRECATED_REPLACE=99,
-    WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE=100, /* FW supports a new mode that allows to run connection tracker in host */
-    WMI_SERVICE_ENHANCED_MCAST_FILTER=101,  /* FW supports enhanced multicast filtering (of mcast IP inside ucast WLAN) */
-    WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT=102, /* periodic channel stats service */
-    WMI_SERVICE_MESH_11S=103,               /* 11s mesh service support */
-    WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT=104, /* FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate) channel bandwidth */
-    WMI_SERVICE_VDEV_RX_FILTER=105,         /* Support per-vdev specs of which rx frames to filter out */
-    WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT=106,
-    WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET=107, /* FW supports marking the first data packet which wakes the host from suspend */
-    WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET=108, /* FW supports command that can add/delete multiple mcast filters */
-    /* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
-     * FW supports host-managed RX reorder.
-     * Host managed RX reorder involves RX BA state machine handling
-     * on peer/TID basis, REO configuration for HW based reordering/PN
-     * check and processing reorder exceptions generated by HW.
-     */
-    WMI_SERVICE_HOST_MANAGED_RX_REORDER=109,
-    /* Specify whether the target supports the following WMI messages for
-     * reading / writing its flash memory:
-     *     WMI_READ_DATA_FROM_FLASH_CMDID,
-     *     WMI_READ_DATA_FROM_FLASH_EVENTID,
-     *     WMI_TRANSFER_DATA_TO_FLASH_CMDID,
-     *     WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
-     */
-    WMI_SERVICE_FLASH_RDWR_SUPPORT=110,
-    WMI_SERVICE_WLAN_STATS_REPORT=111, /* support WLAN stats report */
+typedef enum {
+	WMI_SERVICE_BEACON_OFFLOAD = 0,       /* beacon offload */
+	WMI_SERVICE_SCAN_OFFLOAD = 1,         /* scan offload */
+	WMI_SERVICE_ROAM_SCAN_OFFLOAD = 2,    /* roam scan offload */
+	WMI_SERVICE_BCN_MISS_OFFLOAD = 3,     /* beacon miss offload */
+	/* fake sleep + basic power save */
+	WMI_SERVICE_STA_PWRSAVE = 4,
+	WMI_SERVICE_STA_ADVANCED_PWRSAVE = 5, /* uapsd, pspoll, force sleep */
+	WMI_SERVICE_AP_UAPSD = 6,             /* uapsd on AP */
+	WMI_SERVICE_AP_DFS = 7,               /* DFS on AP */
+	WMI_SERVICE_11AC = 8,                 /* supports 11ac */
+	/* Supports triggering ADDBA/DELBA from host*/
+	WMI_SERVICE_BLOCKACK = 9,
+	WMI_SERVICE_PHYERR = 10,              /* PHY error */
+	WMI_SERVICE_BCN_FILTER = 11,          /* Beacon filter support */
+	/* RTT (round trip time) support */
+	WMI_SERVICE_RTT = 12,
+	WMI_SERVICE_WOW = 13,                 /* WOW Support */
+	WMI_SERVICE_RATECTRL_CACHE = 14,      /* Rate-control caching */
+	WMI_SERVICE_IRAM_TIDS = 15,           /* TIDs in IRAM */
+	/* ARP NS Offload support for STA vdev */
+	WMI_SERVICE_ARPNS_OFFLOAD = 16,
+	/* Network list offload service */
+	WMI_SERVICE_NLO = 17,
+	WMI_SERVICE_GTK_OFFLOAD = 18,         /* GTK offload */
+	WMI_SERVICE_SCAN_SCH = 19,            /* Scan Scheduler Service */
+	WMI_SERVICE_CSA_OFFLOAD = 20,         /* CSA offload service */
+	WMI_SERVICE_CHATTER = 21,             /* Chatter service */
+	/* FW report freq range to avoid */
+	WMI_SERVICE_COEX_FREQAVOID = 22,
+	WMI_SERVICE_PACKET_POWER_SAVE = 23,   /* packet power save service */
+	/* Service to test the firmware recovery mechanism */
+	WMI_SERVICE_FORCE_FW_HANG = 24,
+	WMI_SERVICE_GPIO = 25,                /* GPIO service */
+	/* Modulated DTIM support */
+	WMI_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26,
+	/**
+	 * Basic version of station UAPSD AC Trigger Generation Method with
+	 * variable tigger periods (service, delay, and suspend intervals)
+	 */
+	WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27,
+	/**
+	 * Station UAPSD AC Trigger Generation Method with variable
+	 * trigger periods (service, delay, and suspend intervals)
+	 */
+	WMI_STA_UAPSD_VAR_AUTO_TRIG = 28,
+	/* Serivce to support the STA KEEP ALIVE mechanism */
+	WMI_SERVICE_STA_KEEP_ALIVE = 29,
+	/* Packet type for TX encapsulation */
+	WMI_SERVICE_TX_ENCAP = 30,
+	/* detect out-of-sync sleeping stations */
+	WMI_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31,
+	WMI_SERVICE_EARLY_RX = 32,            /* adaptive early-rx feature */
+	WMI_SERVICE_STA_SMPS = 33,            /* STA MIMO-PS */
+	WMI_SERVICE_FWTEST = 34,              /* Firmware test service */
+	WMI_SERVICE_STA_WMMAC = 35,           /* STA WMMAC */
+	WMI_SERVICE_TDLS = 36,                /* TDLS support */
+	WMI_SERVICE_BURST = 37,               /* SIFS spaced burst support */
+	/* Dynamic beaocn interval change for SAP/P2p GO in MCC scenario */
+	WMI_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38,
+	/* Service to support adaptive off-channel scheduler */
+	WMI_SERVICE_ADAPTIVE_OCS = 39,
+	/* target will provide Sequence number for the peer/tid combo */
+	WMI_SERVICE_BA_SSN_SUPPORT = 40,
+	WMI_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41,
+	WMI_SERVICE_WLAN_HB = 42,             /* wlan HB service */
+	/* support LTE/WLAN antenna sharing */
+	WMI_SERVICE_LTE_ANT_SHARE_SUPPORT = 43,
+	WMI_SERVICE_BATCH_SCAN = 44,          /*Service to support batch scan*/
+	WMI_SERVICE_QPOWER = 45,              /* QPower service */
+	WMI_SERVICE_PLMREQ = 46,
+	WMI_SERVICE_THERMAL_MGMT = 47,        /* thermal throttling support */
+	WMI_SERVICE_RMC = 48,                 /* RMC support */
+	/* multi-hop forwarding offload */
+	WMI_SERVICE_MHF_OFFLOAD = 49,
+	/* target support SAR tx limit from WMI_PDEV_PARAM_TXPOWER_LIMITxG */
+	WMI_SERVICE_COEX_SAR = 50,
+	/* Will support the bcn/prb rsp rate override */
+	WMI_SERVICE_BCN_TXRATE_OVERRIDE = 51,
+	WMI_SERVICE_NAN = 52,                 /* Neighbor Awareness Network */
+	/* L1SS statistics counter report */
+	WMI_SERVICE_L1SS_STAT = 53,
+	/* Linkspeed Estimation per peer */
+	WMI_SERVICE_ESTIMATE_LINKSPEED = 54,
+	/* Service to support OBSS scan */
+	WMI_SERVICE_OBSS_SCAN = 55,
+	WMI_SERVICE_TDLS_OFFCHAN = 56,        /* TDLS off channel support */
+	/* TDLS UAPSD Buffer STA support */
+	WMI_SERVICE_TDLS_UAPSD_BUFFER_STA = 57,
+	/* TDLS UAPSD Sleep STA support */
+	WMI_SERVICE_TDLS_UAPSD_SLEEP_STA = 58,
+	WMI_SERVICE_IBSS_PWRSAVE = 59,        /* IBSS power save support */
+	WMI_SERVICE_LPASS = 60,               /*Service to support LPASS*/
+	WMI_SERVICE_EXTSCAN = 61,             /* Extended Scans */
+	WMI_SERVICE_D0WOW = 62,               /* D0-WOW Support */
+	/* Hotspot offload feature Support */
+	WMI_SERVICE_HSOFFLOAD = 63,
+	WMI_SERVICE_ROAM_HO_OFFLOAD = 64,     /* roam handover offload */
+	/* target-based Rx full reorder */
+	WMI_SERVICE_RX_FULL_REORDER = 65,
+	WMI_SERVICE_DHCP_OFFLOAD = 66,        /* DHCP offload support */
+	/* STA RX DATA offload to IPA support */
+	WMI_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67,
+	/* mDNS responder offload support */
+	WMI_SERVICE_MDNS_OFFLOAD = 68,
+	WMI_SERVICE_SAP_AUTH_OFFLOAD = 69,    /* softap auth offload */
+	/* Dual Band Simultaneous support */
+	WMI_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70,
+	WMI_SERVICE_OCB = 71,                 /* OCB mode support */
+	/* arp offload support for ap mode vdev */
+	WMI_SERVICE_AP_ARPNS_OFFLOAD = 72,
+	/* Per band chainmask support */
+	WMI_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73,
+	WMI_SERVICE_PACKET_FILTER_OFFLOAD = 74, /* Per vdev packet filters */
+	WMI_SERVICE_MGMT_TX_HTT = 75,         /* Mgmt Tx via HTT interface */
+	WMI_SERVICE_MGMT_TX_WMI = 76,         /* Mgmt Tx via WMI interface */
+	/* WMI_SERVICE_READY_EXT msg follows */
+	WMI_SERVICE_EXT_MSG = 77,
+	/* Motion Aided WiFi Connectivity (MAWC)*/
+	WMI_SERVICE_MAWC = 78,
+	/* target will send ASSOC_CONF after ASSOC_CMD is processed */
+	WMI_SERVICE_PEER_ASSOC_CONF = 79,
+	WMI_SERVICE_EGAP = 80,                /* enhanced green ap support */
+	/* FW supports 11W PMF Offload for STA */
+	WMI_SERVICE_STA_PMF_OFFLOAD = 81,
+	/* FW supports unified D0 and D3 wow */
+	WMI_SERVICE_UNIFIED_WOW_CAPABILITY = 82,
+	/* Enhanced ProxySTA mode support */
+	WMI_SERVICE_ENHANCED_PROXY_STA = 83,
+	WMI_SERVICE_ATF = 84,                 /* Air Time Fairness support */
+	WMI_SERVICE_COEX_GPIO = 85,           /* BTCOEX GPIO support */
+	/**
+	 * Aux Radio enhancement support for ignoring spectral scan intf
+	 * from main radios
+	 */
+	WMI_SERVICE_AUX_SPECTRAL_INTF = 86,
+	/**
+	 * Aux Radio enhancement support for ignoring chan load intf
+	 * from main radios
+	 */
+	WMI_SERVICE_AUX_CHAN_LOAD_INTF = 87,
+	/**
+	 * BSS channel info (freq, noise floor, 64-bit counters)
+	 * event support
+	 */
+	WMI_SERVICE_BSS_CHANNEL_INFO_64 = 88,
+	/* Enterprise MESH Service Support */
+	WMI_SERVICE_ENTERPRISE_MESH = 89,
+	WMI_SERVICE_RESTRT_CHNL_SUPPORT = 90, /* Restricted Channel Support */
+	WMI_SERVICE_BPF_OFFLOAD = 91,         /* FW supports bpf offload */
+	/* FW sends response event for Peer, Vdev delete commands */
+	WMI_SERVICE_SYNC_DELETE_CMDS = 92,
+	WMI_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93,
+	WMI_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94,
+	/* allow per-peer tx MCS min/max limits by host */
+	WMI_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95,
+	WMI_SERVICE_NAN_DATA = 96,            /* FW supports NAN data */
+	WMI_SERVICE_NAN_RTT = 97,             /* FW supports NAN RTT */
+	WMI_SERVICE_11AX = 98,                /* FW supports 802.11ax */
+
+	/* WMI_SERVICE_DEPRECATED_REPLACE
+	 * FW supports these new WMI commands, to be used rather than
+	 * deprecated matching commands:
+	 * - WMI_PDEV_SET_PCL_CMDID          (vs. WMI_SOC_SET_PCL_CMDID)
+	 * - WMI_PDEV_SET_HW_MODE_CMDID
+	 *			(vs. WMI_SOC_SET_HW_MODE_CMDID)
+	 * - WMI_PDEV_SET_MAC_CONFIG_CMDID
+	 *			(vs. WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID)
+	 * - WMI_PDEV_SET_ANTENNA_MODE_CMDID
+	 *			(vs. WMI_SOC_SET_ANTENNA_MODE_CMDID)
+	 * - WMI_VDEV_SET_DSCP_TID_MAP_CMDID
+	 *			(vs. WMI_VDEV_SET_WMM_PARAMS_CMDID)
+	 */
+	WMI_SERVICE_DEPRECATED_REPLACE = 99,
+	/**
+	 * FW supports a new mode that allows to run connection tracker
+	 * in host
+	 */
+	WMI_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100,
+	/**
+	 * FW supports enhanced multicast filtering (of mcast IP inside
+	 * ucast WLAN)
+	 */
+	WMI_SERVICE_ENHANCED_MCAST_FILTER = 101,
+	/* periodic channel stats service */
+	WMI_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102,
+	WMI_SERVICE_MESH_11S = 103,
+	/**
+	 * FW+HW supports 10 MHz (half rate) and 5 MHz (quarter rate)
+	 * channel bandwidth
+	 */
+	WMI_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104,
+	/* Support per-vdev specs of which rx frames to filter out */
+	WMI_SERVICE_VDEV_RX_FILTER = 105,
+	WMI_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106,
+	/**
+	 * FW supports marking the first data packet which wakes
+	 * the host from suspend
+	 */
+	WMI_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107,
+	/* FW supports command that can add/delete multiple mcast filters */
+	WMI_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108,
+	/* WMI_SERVICE_HOST_MANAGED_RX_REORDER -
+	 * FW supports host-managed RX reorder.
+	 * Host managed RX reorder involves RX BA state machine handling
+	 * on peer/TID basis, REO configuration for HW based reordering/PN
+	 * check and processing reorder exceptions generated by HW.
+	 */
+	WMI_SERVICE_HOST_MANAGED_RX_REORDER = 109,
+	/* Specify whether the target supports the following WMI messages
+	 * for reading / writing its flash memory:
+	 *     WMI_READ_DATA_FROM_FLASH_CMDID,
+	 *     WMI_READ_DATA_FROM_FLASH_EVENTID,
+	 *     WMI_TRANSFER_DATA_TO_FLASH_CMDID,
+	 *     WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID,
+	 */
+	WMI_SERVICE_FLASH_RDWR_SUPPORT = 110,
+	WMI_SERVICE_WLAN_STATS_REPORT = 111, /* support WLAN stats report */
 
+	/* WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT -
+	 * FW supports bigger MSDU ID partition which is defined as
+	 * HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. When both host and FW support
+	 * new partition, FW uses HTT_TX_IPA_NEW_MSDU_ID_SPACE_BEGIN. If host
+	 * doesn't support, FW falls back to HTT_TX_IPA_MSDU_ID_SPACE_BEGIN
+	 * Handshaking is done through WMI_INIT and WMI service ready
+	 *
+	 * support bigger MSDU ID partition
+	 */
+	WMI_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112,
+	WMI_SERVICE_DFS_PHYERR_OFFLOAD = 113,
 
-    /******* ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED *******/
+	/*** ADD NEW SERVICES HERE UNTIL ALL VALUES UP TO 128 ARE USED ***/
 
-    WMI_MAX_SERVICE=128, /* max service */
+	WMI_MAX_SERVICE = 128, /* max service */
 
-    /* NOTE:
-     * The above service flags are delivered in the wmi_service_bitmap field
-     * of the WMI_SERVICE_READY_EVENT message.
-     * The below service flags are delivered in a WMI_SERVICE_AVAILABLE_EVENT
-     * message rather than in the WMI_SERVICE_READY_EVENT message's
-     * wmi_service_bitmap field.
-     * The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
-     * WMI_SERVICE_READY_EVENT message.
-     */
+	/**
+	 * NOTE:
+	 * The above service flags are delivered in the wmi_service_bitmap
+	 * field of the WMI_SERVICE_READY_EVENT message.
+	 * The below service flags are delivered in a
+	 * WMI_SERVICE_AVAILABLE_EVENT message rather than in the
+	 * WMI_SERVICE_READY_EVENT message's wmi_service_bitmap field.
+	 * The WMI_SERVICE_AVAILABLE_EVENT message immediately precedes the
+	 * WMI_SERVICE_READY_EVENT message.
+	 */
 
-    /*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/
-    /*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/
+	/*PUT 1ST EXT SERVICE HERE:*//*WMI_SERVICE_xxxxxxxx=128,*/
+	/*PUT 2ND EXT SERVICE HERE:*//*WMI_SERVICE_yyyyyyyy=129,*/
 
-    WMI_MAX_EXT_SERVICE
+	WMI_MAX_EXT_SERVICE
 
 } WMI_SERVICE;
 
@@ -207,59 +299,61 @@ typedef  enum  {
 #define WMI_NUM_EXT_SERVICES (WMI_MAX_EXT_SERVICE - WMI_MAX_SERVICE)
 #define WMI_SERVICE_EXT_BM_SIZE32 ((WMI_NUM_EXT_SERVICES + 31) / 32)
 
-#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD /* depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help compiling with old host driver */
+/**
+ * depreciated the name WMI_SERVICE_ROAM_OFFLOAD, but here to help
+ * compiling with old host driver
+ */
+#define WMI_SERVICE_ROAM_OFFLOAD WMI_SERVICE_ROAM_SCAN_OFFLOAD
 
 /*
  * turn on the WMI service bit corresponding to  the WMI service.
  */
 #define WMI_SERVICE_ENABLE(pwmi_svc_bmap,svc_id) \
-    ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
-         (1 << ((svc_id)%(sizeof(A_UINT32)))) )
+	( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] |= \
+		  (1 << ((svc_id)%(sizeof(A_UINT32)))) )
 
 #define WMI_SERVICE_DISABLE(pwmi_svc_bmap,svc_id) \
-    ( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &=  \
-      ( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
+	( (pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &=  \
+		  ( ~(1 << ((svc_id)%(sizeof(A_UINT32)))) ) )
 
 #define WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap,svc_id) \
-    ( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &  \
-       (1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
-
+	( ((pwmi_svc_bmap)[(svc_id)/(sizeof(A_UINT32))] &  \
+	   (1 << ((svc_id)%(sizeof(A_UINT32)))) ) != 0)
 
 #define WMI_SERVICE_EXT_ENABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
-    do { \
-        if (svc_id < WMI_MAX_SERVICE) { \
-            WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
-        } else { \
-            int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
-            int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
-            (pwmi_svc_ext_bmap)[word] |= (1 << bit); \
-        } \
-    } while (0)
+	do { \
+		if (svc_id < WMI_MAX_SERVICE) { \
+			WMI_SERVICE_ENABLE(pwmi_svc_bmap, svc_id); \
+		} else { \
+			int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
+			int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
+			(pwmi_svc_ext_bmap)[word] |= (1 << bit); \
+		} \
+	} while (0)
 
 #define WMI_SERVICE_EXT_DISABLE(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
-    do { \
-        if (svc_id < WMI_MAX_SERVICE) { \
-            WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
-        } else { \
-            int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
-            int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
-            (pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
-        } \
-    } while (0)
+	do { \
+		if (svc_id < WMI_MAX_SERVICE) { \
+			WMI_SERVICE_DISABLE(pwmi_svc_bmap, svc_id); \
+		} else { \
+			int word = ((svc_id) - WMI_MAX_SERVICE) / 32; \
+			int bit = (svc_id) & 0x1f; /* svc_id mod 32 */ \
+			(pwmi_svc_ext_bmap)[word] &= ~(1 << bit); \
+		} \
+	} while (0)
 
 #define WMI_SERVICE_EXT_IS_ENABLED(pwmi_svc_bmap, pwmi_svc_ext_bmap, svc_id) \
-    /* If the service ID is beyond the known limit, treat it as disabled */ \
-    ((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
-        /* If service ID is in the non-extension range, use the old check */ \
-        (svc_id) < WMI_MAX_SERVICE ? \
-            WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
-            /* If service ID is in the extended range, check ext_bmap */ \
-            (pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
-                ((svc_id) & 0x1f))
+	/* If the service ID is beyond the known limit, treat it as disabled */ \
+	((svc_id) >= WMI_MAX_EXT_SERVICE ? 0 : \
+		/* If service ID is in the non-extension range, use the old check */ \
+		(svc_id) < WMI_MAX_SERVICE ? \
+			WMI_SERVICE_IS_ENABLED(pwmi_svc_bmap, svc_id) : \
+			/* If service ID is in the extended range, check ext_bmap */ \
+			(pwmi_svc_ext_bmap)[((svc_id) - WMI_MAX_SERVICE) / 32] >> \
+				((svc_id) & 0x1f))
 
 
 #ifdef __cplusplus
 }
 #endif
-
 #endif /*_WMI_SERVICES_H_*/

fw/wmi_tlv_helper.h

@@ -24,6 +24,7 @@
  * under proprietary terms before Copyright ownership was assigned
  * to the Linux Foundation.
  */
+
 #ifndef _WMI_TLV_HELPER_H_
 #define _WMI_TLV_HELPER_H_
 
@@ -42,7 +43,7 @@
  * (5) Either WMITLV_SIZE_FIX or WMITLV_SIZE_VAR to indicate if this TLV is variable size.
  *
  * Note: It is important that the last TLV_ELEM does not have the "\" character.
-*/
+ */
 
 /* Size of the TLV Header which is the Tag and Length fields */
 #define WMI_TLV_HDR_SIZE   (1 * sizeof(A_UINT32))
@@ -75,20 +76,19 @@ typedef struct {
 	A_UINT32 tag_struct_size;
 	A_UINT32 tag_varied_size;
 	A_UINT32 tag_array_size;
-    A_UINT32 cmd_num_tlv;
+	A_UINT32 cmd_num_tlv;
 } wmitlv_attributes_struc;
 
-
 /* Template structure definition for a variable size array of UINT32 */
 typedef struct {
-    A_UINT32    tlv_header;     /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
-    A_UINT32    uint32_array[1]; /* variable length Array of UINT32 */
+	A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_UINT32 */
+	A_UINT32 uint32_array[1];       /* variable length Array of UINT32 */
 } wmitlv_array_uint32;
 
 /* Template structure definition for a variable size array of unknown structure */
 typedef struct {
-    A_UINT32    tlv_header;     /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
-    A_UINT32    struc_array[1]; /* variable length Array of structures */
+	A_UINT32 tlv_header;    /* TLV tag and len; tag equals WMI_TLVTAG_ARRAY_STRUC */
+	A_UINT32 struc_array[1];        /* variable length Array of structures */
 } wmitlv_array_struc;
 
 /*
@@ -97,60 +97,64 @@ typedef struct {
  */
 #define WMITLV_ARR_SIZE_INVALID  0x1FE
 
-#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id)      \
-       WMI_TLV_HLPR_NUM_TLVS_FOR_##wmi_cmd_event_id
-
+#define WMITLV_GET_TAG_NUM_TLV_ATTRIB(wmi_cmd_event_id)	     \
+	WMI_TLV_HLPR_NUM_TLVS_FOR_ ## wmi_cmd_event_id
 
 void
-wmitlv_set_static_param_tlv_buf(void *param_tlv_buf, A_UINT32 max_tlvs_accomodated);
+wmitlv_set_static_param_tlv_buf(void *param_tlv_buf,
+				A_UINT32 max_tlvs_accomodated);
 
 void
-wmitlv_free_allocated_command_tlvs(
-    A_UINT32 cmd_id,
-    void **wmi_cmd_struct_ptr);
+wmitlv_free_allocated_command_tlvs(A_UINT32 cmd_id, void **wmi_cmd_struct_ptr);
 
 void
-wmitlv_free_allocated_event_tlvs(
-    A_UINT32 event_id,
-    void **wmi_cmd_struct_ptr);
+wmitlv_free_allocated_event_tlvs(A_UINT32 event_id, void **wmi_cmd_struct_ptr);
 
 int
-wmitlv_check_command_tlv_params(
-    void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
+wmitlv_check_command_tlv_params(void *os_ctx, void *param_struc_ptr,
+				A_UINT32 param_buf_len,
+				A_UINT32 wmi_cmd_event_id);
 
 int
-wmitlv_check_event_tlv_params(
-    void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id);
+wmitlv_check_event_tlv_params(void *os_ctx, void *param_struc_ptr,
+			      A_UINT32 param_buf_len,
+			      A_UINT32 wmi_cmd_event_id);
 
 int
-wmitlv_check_and_pad_command_tlvs(
-    void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
+wmitlv_check_and_pad_command_tlvs(void *os_ctx, void *param_struc_ptr,
+				  A_UINT32 param_buf_len,
+				  A_UINT32 wmi_cmd_event_id,
+				  void **wmi_cmd_struct_ptr);
 
 int
-wmitlv_check_and_pad_event_tlvs(
-    void *os_ctx, void *param_struc_ptr, A_UINT32 param_buf_len, A_UINT32 wmi_cmd_event_id, void **wmi_cmd_struct_ptr);
+wmitlv_check_and_pad_event_tlvs(void *os_ctx, void *param_struc_ptr,
+				A_UINT32 param_buf_len,
+				A_UINT32 wmi_cmd_event_id,
+				void **wmi_cmd_struct_ptr);
 
 /** This structure is the element for the Version WhiteList
  *  table. */
 typedef struct {
-    A_UINT32      major;
-    A_UINT32      minor;
-    A_UINT32      namespace_0;
-    A_UINT32      namespace_1;
-    A_UINT32      namespace_2;
-    A_UINT32      namespace_3;
+	A_UINT32 major;
+	A_UINT32 minor;
+	A_UINT32 namespace_0;
+	A_UINT32 namespace_1;
+	A_UINT32 namespace_2;
+	A_UINT32 namespace_3;
 } wmi_whitelist_version_info;
 
-struct _wmi_abi_version;   /* Forward declaration to make the ARM compiler happy */
+struct _wmi_abi_version;        /* Forward declaration to make the ARM compiler happy */
 
 int
-wmi_cmp_and_set_abi_version(int num_whitelist, wmi_whitelist_version_info *version_whitelist_table,
-                            struct _wmi_abi_version *my_vers,
-                            struct _wmi_abi_version *opp_vers,
-                            struct _wmi_abi_version *out_vers);
+wmi_cmp_and_set_abi_version(int num_whitelist,
+			    wmi_whitelist_version_info *
+			    version_whitelist_table,
+			    struct _wmi_abi_version *my_vers,
+			    struct _wmi_abi_version *opp_vers,
+			    struct _wmi_abi_version *out_vers);
 
 int
-wmi_versions_are_compatible(struct _wmi_abi_version *vers1, struct _wmi_abi_version *vers2);
+wmi_versions_are_compatible(struct _wmi_abi_version *vers1,
+			    struct _wmi_abi_version *vers2);
 
 #endif /*_WMI_TLV_HELPER_H_*/
-

fw/wmi_version.h

@@ -35,8 +35,8 @@
  *  compatibility. */
 #define __WMI_VER_MINOR_    0
 /** WMI revision number has to be incremented when there is a
- *  change that may or may not break compatibility. */
-#define __WMI_REVISION_ 290
+ *  change that may or may not break compatibility */
+#define __WMI_REVISION_ 309
 
 /** The Version Namespace should not be normally changed. Only
  *  host and firmware of the same WMI namespace will work
@@ -78,4 +78,3 @@
 #define WMI_ABI_VERSION_NS_1 __NAMESPACE_1_
 #define WMI_ABI_VERSION_NS_2 __NAMESPACE_2_
 #define WMI_ABI_VERSION_NS_3 __NAMESPACE_3_
-

fw/wmix.h

@@ -53,29 +53,29 @@ extern "C" {
  * WMI_EVENT_ID=WMI_EXTENSION_EVENTID.
  */
 typedef struct {
-    A_UINT32    commandId;
+	A_UINT32 commandId;
 } POSTPACK WMIX_CMD_HDR;
 
 typedef enum {
-    WMIX_DSETOPEN_REPLY_CMDID           = 0x2001,
-    WMIX_DSETDATA_REPLY_CMDID,
-    WMIX_HB_CHALLENGE_RESP_CMDID,
-    WMIX_DBGLOG_CFG_MODULE_CMDID,
-    WMIX_PROF_CFG_CMDID,                 /* 0x200a */
-    WMIX_PROF_ADDR_SET_CMDID,
-    WMIX_PROF_START_CMDID,
-    WMIX_PROF_STOP_CMDID,
-    WMIX_PROF_COUNT_GET_CMDID,
+	WMIX_DSETOPEN_REPLY_CMDID = 0x2001,
+	WMIX_DSETDATA_REPLY_CMDID,
+	WMIX_HB_CHALLENGE_RESP_CMDID,
+	WMIX_DBGLOG_CFG_MODULE_CMDID,
+	WMIX_PROF_CFG_CMDID,            /* 0x200a */
+	WMIX_PROF_ADDR_SET_CMDID,
+	WMIX_PROF_START_CMDID,
+	WMIX_PROF_STOP_CMDID,
+	WMIX_PROF_COUNT_GET_CMDID,
 } WMIX_COMMAND_ID;
 
 typedef enum {
-    WMIX_DSETOPENREQ_EVENTID            = 0x3001,
-    WMIX_DSETCLOSE_EVENTID,
-    WMIX_DSETDATAREQ_EVENTID,
-    WMIX_HB_CHALLENGE_RESP_EVENTID,
-    WMIX_DBGLOG_EVENTID,
-    WMIX_PROF_COUNT_EVENTID,
-    WMIX_PKTLOG_EVENTID,
+	WMIX_DSETOPENREQ_EVENTID = 0x3001,
+	WMIX_DSETCLOSE_EVENTID,
+	WMIX_DSETDATAREQ_EVENTID,
+	WMIX_HB_CHALLENGE_RESP_EVENTID,
+	WMIX_DBGLOG_EVENTID,
+	WMIX_PROF_COUNT_EVENTID,
+	WMIX_PKTLOG_EVENTID,
 } WMIX_EVENT_ID;
 
 /*
@@ -87,10 +87,10 @@ typedef enum {
  * DataSet Open Request Event
  */
 typedef struct {
-    A_UINT32 dset_id;
-    A_UINT32 targ_dset_handle;  /* echo'ed, not used by Host, */
-    A_UINT32 targ_reply_fn;     /* echo'ed, not used by Host, */
-    A_UINT32 targ_reply_arg;    /* echo'ed, not used by Host, */
+	A_UINT32 dset_id;
+	A_UINT32 targ_dset_handle;              /* echo'ed, not used by Host, */
+	A_UINT32 targ_reply_fn;         /* echo'ed, not used by Host, */
+	A_UINT32 targ_reply_arg;                /* echo'ed, not used by Host, */
 } POSTPACK WMIX_DSETOPENREQ_EVENT;
 
 /*
@@ -98,7 +98,7 @@ typedef struct {
  * DataSet Close Event
  */
 typedef struct {
-    A_UINT32 access_cookie;
+	A_UINT32 access_cookie;
 } POSTPACK WMIX_DSETCLOSE_EVENT;
 
 /*
@@ -106,33 +106,32 @@ typedef struct {
  * DataSet Data Request Event
  */
 typedef struct {
-    A_UINT32 access_cookie;
-    A_UINT32 offset;
-    A_UINT32 length;
-    A_UINT32 targ_buf;         /* echo'ed, not used by Host, */
-    A_UINT32 targ_reply_fn;    /* echo'ed, not used by Host, */
-    A_UINT32 targ_reply_arg;   /* echo'ed, not used by Host, */
+	A_UINT32 access_cookie;
+	A_UINT32 offset;
+	A_UINT32 length;
+	A_UINT32 targ_buf;              /* echo'ed, not used by Host, */
+	A_UINT32 targ_reply_fn;         /* echo'ed, not used by Host, */
+	A_UINT32 targ_reply_arg;                /* echo'ed, not used by Host, */
 } WMIX_DSETDATAREQ_EVENT;
 
 typedef struct {
-    A_UINT32              status;
-    A_UINT32              targ_dset_handle;
-    A_UINT32              targ_reply_fn;
-    A_UINT32              targ_reply_arg;
-    A_UINT32              access_cookie;
-    A_UINT32              size;
-    A_UINT32              version;
-}  WMIX_DSETOPEN_REPLY_CMD;
+	A_UINT32 status;
+	A_UINT32 targ_dset_handle;
+	A_UINT32 targ_reply_fn;
+	A_UINT32 targ_reply_arg;
+	A_UINT32 access_cookie;
+	A_UINT32 size;
+	A_UINT32 version;
+} WMIX_DSETOPEN_REPLY_CMD;
 
 typedef struct {
-    A_UINT32              status;
-    A_UINT32              targ_buf;
-    A_UINT32              targ_reply_fn;
-    A_UINT32              targ_reply_arg;
-    A_UINT32              length;
-    A_UINT8               buf[1];
-}  WMIX_DSETDATA_REPLY_CMD;
-
+	A_UINT32 status;
+	A_UINT32 targ_buf;
+	A_UINT32 targ_reply_fn;
+	A_UINT32 targ_reply_arg;
+	A_UINT32 length;
+	A_UINT8 buf[1];
+} WMIX_DSETDATA_REPLY_CMD;
 
 /*
  * =============Error Detection support=================
@@ -143,9 +142,9 @@ typedef struct {
  * Heartbeat Challenge Response command
  */
 typedef struct {
-    A_UINT32              cookie;
-    A_UINT32              source;
-}  WMIX_HB_CHALLENGE_RESP_CMD;
+	A_UINT32 cookie;
+	A_UINT32 source;
+} WMIX_HB_CHALLENGE_RESP_CMD;
 
 /*
  * WMIX_HB_CHALLENGE_RESP_EVENTID
@@ -158,13 +157,13 @@ typedef struct {
  */
 
 typedef struct {
-    A_UINT32 period; /* Time (in 30.5us ticks) between samples */
-    A_UINT32 nbins;
-}  WMIX_PROF_CFG_CMD;
+	A_UINT32 period;                /* Time (in 30.5us ticks) between samples */
+	A_UINT32 nbins;
+} WMIX_PROF_CFG_CMD;
 
 typedef struct {
-    A_UINT32 addr;
-}  WMIX_PROF_ADDR_SET_CMD;
+	A_UINT32 addr;
+} WMIX_PROF_ADDR_SET_CMD;
 
 /*
  * Target responds to Hosts's earlier WMIX_PROF_COUNT_GET_CMDID request
@@ -173,13 +172,11 @@ typedef struct {
  *   count set to the corresponding count
  */
 typedef struct {
-    A_UINT32              addr;
-    A_UINT32              count;
-}  WMIX_PROF_COUNT_EVENT;
-
+	A_UINT32 addr;
+	A_UINT32 count;
+} WMIX_PROF_COUNT_EVENT;
 
 #ifdef __cplusplus
 }
 #endif
-
 #endif /* _WMIX_H_ */

hw/qca6290/v1/HALcomdef.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+/*
+==============================================================================
+
+FILE:         HALcomdef.h
+
+DESCRIPTION:
+
+==============================================================================
+
+                             Edit History
+
+$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $
+
+when       who     what, where, why
+--------   ---     -----------------------------------------------------------
+06/17/10   sc      Included com_dtypes.h and cleaned up typedefs
+05/15/08   gfr     Added HAL_ENUM_32BITS macro.
+02/14/08   gfr     Added bool32 type.
+11/13/07   gfr     Removed dependency on comdef.h
+01/08/07   hxw     Created
+
+*/
+
+
+/*
+ * Assembly wrapper
+ */
+#ifndef _ARM_ASM_
+
+/*
+ * C++ wrapper
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+/* -----------------------------------------------------------------------
+** Types
+** ----------------------------------------------------------------------- */
+
+/*
+ * Standard integer types.
+ *
+ * bool32  - boolean, 32 bit (TRUE or FALSE)
+ */
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+/*
+ * Macro to allow forcing an enum to 32 bits.  The argument should be
+ * an identifier in the namespace of the enumeration in question, i.e.
+ * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
+ */
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+/*===========================================================================
+
+FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
+
+DESCRIPTION
+  IN/OUT port macros for byte and word ports, typically inlined by compilers
+  which support these routines
+
+PARAMETERS
+  inp(   xx_addr )
+  inpw(  xx_addr )
+  inpdw( xx_addr )
+  outp(   xx_addr, xx_byte_val  )
+  outpw(  xx_addr, xx_word_val  )
+  outpdw( xx_addr, xx_dword_val )
+      xx_addr      - Address of port to read or write (may be memory mapped)
+      xx_byte_val  - 8 bit value to write
+      xx_word_val  - 16 bit value to write
+      xx_dword_val - 32 bit value to write
+
+DEPENDENCIES
+  None
+
+RETURN VALUE
+  inp/inpw/inpdw: the byte, word or dword read from the given address
+  outp/outpw/outpdw: the byte, word or dword written to the given address
+
+SIDE EFFECTS
+  None.
+
+===========================================================================*/
+
+  /* ARM based targets use memory mapped i/o, so the inp/outp calls are
+  ** macroized to access memory directly
+  */
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ARM_ASM_ */
+
+#endif /* HAL_COMDEF_H */
+

hw/qca6290/v1/HALhwio.h

@@ -0,0 +1,490 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+/*
+===========================================================================
+*/
+/**
+  @file HALhwio.h 
+  
+  Public interface include file for accessing the HWIO HAL definitions.
+  
+  The HALhwio.h file is the public API interface to the HW I/O (HWIO)
+  register access definitions.
+*/
+
+/*=========================================================================
+      Include Files
+==========================================================================*/
+
+
+/*
+ * Common types.
+ */
+#include "HALcomdef.h"
+
+
+
+/* -----------------------------------------------------------------------
+** Macros
+** ----------------------------------------------------------------------- */
+
+/** 
+  @addtogroup macros
+  @{ 
+*/ 
+
+/**
+ * Map a base name to the pointer to access the base.
+ *
+ * This macro maps a base name to the pointer to access the base.
+ * This is generally just used internally.
+ *
+ */
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+
+/**
+ * Declare a HWIO base pointer.
+ *
+ * This macro will declare a HWIO base pointer data structure.  The pointer
+ * will always be declared as a weak symbol so multiple declarations will
+ * resolve correctly to the same data at link-time.
+ */
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+/**
+  @}
+*/
+
+
+/** 
+  @addtogroup hwio_macros
+  @{ 
+*/ 
+
+/**
+ * @name Address Macros
+ *
+ * Macros for getting register addresses.
+ * These macros are used for retrieving the address of a register.
+ * HWIO_ADDR* will return the directly accessible address (virtual or physical based
+ * on environment), HWIO_PHYS* will always return the physical address.
+ * The offset from the base region can be retrieved using HWIO_OFFS*.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * @{
+ */
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+/** @} */
+
+/**
+ * @name Input Macros
+ *
+ * These macros are used for reading from a named hardware register.  Register
+ * arrays ("indexed") use the macros with the "I" suffix.  The "M" suffix
+ * indicates that the input will be masked with the supplied mask.  The HWIO_INF*
+ * macros take a field name and will do the appropriate masking and shifting
+ * to return just the value of that field.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Output Macros
+ *
+ * These macros are used for writing to a named hardware register.  Register
+ * arrays ("indexed") use the macros with the "I" suffix.  The "M" suffix
+ * indicates that the output will be masked with the supplied mask (meaning these
+ * macros do a read first, mask in the supplied data, then write it back).
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ * The HWIO_OUTF* macros take a field name and will do the appropriate masking
+ * and shifting to output just the value of that field.
+ * HWIO_OUTV* registers take a named value instead of a numeric value and
+ * do the same masking/shifting as HWIO_OUTF.
+ *
+ * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Shift and Mask Macros
+ *
+ * Macros for getting shift and mask values for fields and registers.
+ *  HWIO_RMSK: The mask value for accessing an entire register.  For example:
+ *             @code
+ *             HWIO_RMSK(REG) -> 0xFFFFFFFF
+ *             @endcode
+ *  HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
+ *  HWIO_SHFT: The right-shift value for accessing a field in a register.  For example:
+ *             @code
+ *             HWIO_SHFT(REG, FLD) -> 8
+ *             @endcode
+ *  HWIO_FMSK: The mask value for accessing a field in a register.  For example:
+ *             @code
+ *             HWIO_FMSK(REG, FLD) -> 0xFF00
+ *             @endcode
+ *  HWIO_VAL:  The value for a field in a register.  For example:
+ *             @code
+ *             HWIO_VAL(REG, FLD, ON) -> 0x1
+ *             @endcode
+ *  HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
+ *             the given field position.  For example:
+ *             @code
+ *             HWIO_FVAL(REG, FLD, 0x1) -> 0x100
+ *             @endcode
+ *  HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
+ *              into the given field position.  For example:
+ *              @code
+ *              HWIO_FVALV(REG, FLD, ON) -> 0x100
+ *              @endcode
+ *
+ * @{
+ */
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+/** @} */
+
+/**
+ * @name Shadow Register Macros
+ *
+ * These macros are used for directly reading the value stored in a 
+ * shadow register.
+ * Shadow registers are defined for write-only registers.  Generally these
+ * macros should not be necessary as HWIO_OUTM* macros will automatically use
+ * the shadow values internally.
+ *
+ * @{
+ */
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+/** @} */
+
+/** 
+  @}
+*/ /* end_group */
+
+
+/** @cond */
+
+/*
+ * Map to final symbols.  This remapping is done to allow register 
+ * redefinitions.  If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
+ * then remappings like "#define xreg xregnew" do not work as expected.
+ */
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS 
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  {	\
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                               }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                               }  
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+                                                                               } 
+
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+
+/*
+ * HWIO_INTLOCK
+ *
+ * Macro used by autogenerated code for mutual exclusion around
+ * read-mask-write operations.  This is not supported in HAL
+ * code but can be overridden by non-HAL code.
+ */
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+
+/*
+ * Input/output port macros for memory mapped IO.
+ */
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+
+#ifdef HAL_HWIO_EXTERNAL
+
+/*
+ * Replace macros with externally supplied functions.
+ */
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)         
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif /* HAL_HWIO_EXTERNAL */
+
+
+/*
+ * Base 8-bit byte accessing macros.
+ */
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask)) 
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 16-bit word accessing macros.
+ */
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 32-bit double-word accessing macros.
+ */
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+/** @endcond */
+
+#endif /* HAL_HWIO_H */
+

hw/qca6290/v1/buffer_addr_info.h

@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	buffer_addr_31_0[31:0]
+//	1	buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+             uint32_t buffer_addr_31_0                : 32; //[31:0]
+             uint32_t buffer_addr_39_32               :  8, //[7:0]
+                      return_buffer_manager           :  3, //[10:8]
+                      sw_buffer_cookie                : 21; //[31:11]
+};
+
+/*
+
+buffer_addr_31_0
+			
+			Address (lower 32 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+
+buffer_addr_39_32
+			
+			Address (upper 8 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+
+return_buffer_manager
+			
+			Consumer: WBM
+			
+			Producer: SW/FW
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			Indicates to which buffer manager the buffer OR
+			MSDU_EXTENSION descriptor OR link descriptor that is being
+			pointed to shall be returned after the frame has been
+			processed. It is used by WBM for routing purposes.
+			
+			
+			
+			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+			to the WMB buffer idle list
+			
+			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+			returned to the WMB idle link descriptor idle list
+			
+			<enum 2 FW_BM> This buffer shall be returned to the FW
+			
+			<enum 3 SW0_BM> This buffer shall be returned to the SW,
+			ring 0
+			
+			<enum 4 SW1_BM> This buffer shall be returned to the SW,
+			ring 1
+			
+			<enum 5 SW2_BM> This buffer shall be returned to the SW,
+			ring 2
+			
+			<enum 6 SW3_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			
+			
+			<legal 0-6>
+
+sw_buffer_cookie
+			
+			Cookie field exclusively used by SW. 
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			HW ignores the contents, accept that it passes the
+			programmed value on to other descriptors together with the
+			physical address 
+			
+			
+			
+			Field can be used by SW to for example associate the
+			buffers physical address with the virtual address
+			
+			The bit definitions as used by SW are within SW HLD
+			specification
+			
+			
+			
+			NOTE:
+			
+			The two most significant bits can have a special meaning
+			in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
+			and field transmit_bw_restriction is set
+			
+			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+			
+			
+			
+			<legal all>
+*/
+
+
+/* Description		BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
+			
+			Address (lower 32 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET                   0x00000000
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB                      0
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK                     0xffffffff
+
+/* Description		BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
+			
+			Address (upper 8 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET                  0x00000004
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB                     0
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK                    0x000000ff
+
+/* Description		BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
+			
+			Consumer: WBM
+			
+			Producer: SW/FW
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			Indicates to which buffer manager the buffer OR
+			MSDU_EXTENSION descriptor OR link descriptor that is being
+			pointed to shall be returned after the frame has been
+			processed. It is used by WBM for routing purposes.
+			
+			
+			
+			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+			to the WMB buffer idle list
+			
+			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+			returned to the WMB idle link descriptor idle list
+			
+			<enum 2 FW_BM> This buffer shall be returned to the FW
+			
+			<enum 3 SW0_BM> This buffer shall be returned to the SW,
+			ring 0
+			
+			<enum 4 SW1_BM> This buffer shall be returned to the SW,
+			ring 1
+			
+			<enum 5 SW2_BM> This buffer shall be returned to the SW,
+			ring 2
+			
+			<enum 6 SW3_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			
+			
+			<legal 0-6>
+*/
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET              0x00000004
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB                 8
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK                0x00000700
+
+/* Description		BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
+			
+			Cookie field exclusively used by SW. 
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			HW ignores the contents, accept that it passes the
+			programmed value on to other descriptors together with the
+			physical address 
+			
+			
+			
+			Field can be used by SW to for example associate the
+			buffers physical address with the virtual address
+			
+			The bit definitions as used by SW are within SW HLD
+			specification
+			
+			
+			
+			NOTE:
+			
+			The two most significant bits can have a special meaning
+			in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
+			and field transmit_bw_restriction is set
+			
+			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+			
+			
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET                   0x00000004
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB                      11
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK                     0xfffff800
+
+
+#endif // _BUFFER_ADDR_INFO_H_

hw/qca6290/v1/ce_src_desc.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	src_buffer_low[31:0]
+//	1	src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
+//	2	fw_metadata[15:0], ce_res_1[31:16]
+//	3	ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+             uint32_t src_buffer_low                  : 32; //[31:0]
+             uint32_t src_buffer_high                 :  8, //[7:0]
+                      toeplitz_en                     :  1, //[8]
+                      src_swap                        :  1, //[9]
+                      dest_swap                       :  1, //[10]
+                      gather                          :  1, //[11]
+                      ce_res_0                        :  4, //[15:12]
+                      length                          : 16; //[31:16]
+             uint32_t fw_metadata                     : 16, //[15:0]
+                      ce_res_1                        : 16; //[31:16]
+             uint32_t ce_res_2                        : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+src_buffer_low
+			
+			LSB 32 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+
+src_buffer_high
+			
+			MSB 8 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+
+toeplitz_en
+			
+			Enable generation of 32-bit Toeplitz-LFSR hash for the
+			data transfer
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+src_swap
+			
+			Treats source memory organization as big-endian. For
+			each dword read (4 bytes), the byte 0 is swapped with byte 3
+			and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+dest_swap
+			
+			Treats destination memory organization as big-endian.
+			For each dword write (4 bytes), the byte 0 is swapped with
+			byte 3 and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+gather
+			
+			Enables gather of multiple copy engine source
+			descriptors to one destination.
+			
+			<legal all>
+
+ce_res_0
+			
+			Reserved
+			
+			<legal all>
+
+length
+			
+			Length of the buffer in units of octets of the current
+			descriptor
+			
+			<legal all>
+
+fw_metadata
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+ce_res_1
+			
+			Reserved
+			
+			<legal all>
+
+ce_res_2
+			
+			Reserved 
+			
+			<legal all>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		CE_SRC_DESC_0_SRC_BUFFER_LOW
+			
+			LSB 32 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET                          0x00000000
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB                             0
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK                            0xffffffff
+
+/* Description		CE_SRC_DESC_1_SRC_BUFFER_HIGH
+			
+			MSB 8 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET                         0x00000004
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB                            0
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK                           0x000000ff
+
+/* Description		CE_SRC_DESC_1_TOEPLITZ_EN
+			
+			Enable generation of 32-bit Toeplitz-LFSR hash for the
+			data transfer
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET                             0x00000004
+#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB                                8
+#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK                               0x00000100
+
+/* Description		CE_SRC_DESC_1_SRC_SWAP
+			
+			Treats source memory organization as big-endian. For
+			each dword read (4 bytes), the byte 0 is swapped with byte 3
+			and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_SRC_SWAP_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_SRC_SWAP_LSB                                   9
+#define CE_SRC_DESC_1_SRC_SWAP_MASK                                  0x00000200
+
+/* Description		CE_SRC_DESC_1_DEST_SWAP
+			
+			Treats destination memory organization as big-endian.
+			For each dword write (4 bytes), the byte 0 is swapped with
+			byte 3 and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_DEST_SWAP_OFFSET                               0x00000004
+#define CE_SRC_DESC_1_DEST_SWAP_LSB                                  10
+#define CE_SRC_DESC_1_DEST_SWAP_MASK                                 0x00000400
+
+/* Description		CE_SRC_DESC_1_GATHER
+			
+			Enables gather of multiple copy engine source
+			descriptors to one destination.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_GATHER_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_GATHER_LSB                                     11
+#define CE_SRC_DESC_1_GATHER_MASK                                    0x00000800
+
+/* Description		CE_SRC_DESC_1_CE_RES_0
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_CE_RES_0_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_CE_RES_0_LSB                                   12
+#define CE_SRC_DESC_1_CE_RES_0_MASK                                  0x0000f000
+
+/* Description		CE_SRC_DESC_1_LENGTH
+			
+			Length of the buffer in units of octets of the current
+			descriptor
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_LENGTH_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_LENGTH_LSB                                     16
+#define CE_SRC_DESC_1_LENGTH_MASK                                    0xffff0000
+
+/* Description		CE_SRC_DESC_2_FW_METADATA
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_2_FW_METADATA_OFFSET                             0x00000008
+#define CE_SRC_DESC_2_FW_METADATA_LSB                                0
+#define CE_SRC_DESC_2_FW_METADATA_MASK                               0x0000ffff
+
+/* Description		CE_SRC_DESC_2_CE_RES_1
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_2_CE_RES_1_OFFSET                                0x00000008
+#define CE_SRC_DESC_2_CE_RES_1_LSB                                   16
+#define CE_SRC_DESC_2_CE_RES_1_MASK                                  0xffff0000
+
+/* Description		CE_SRC_DESC_3_CE_RES_2
+			
+			Reserved 
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_CE_RES_2_OFFSET                                0x0000000c
+#define CE_SRC_DESC_3_CE_RES_2_LSB                                   0
+#define CE_SRC_DESC_3_CE_RES_2_MASK                                  0x000fffff
+
+/* Description		CE_SRC_DESC_3_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_RING_ID_OFFSET                                 0x0000000c
+#define CE_SRC_DESC_3_RING_ID_LSB                                    20
+#define CE_SRC_DESC_3_RING_ID_MASK                                   0x0ff00000
+
+/* Description		CE_SRC_DESC_3_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET                           0x0000000c
+#define CE_SRC_DESC_3_LOOPING_COUNT_LSB                              28
+#define CE_SRC_DESC_3_LOOPING_COUNT_MASK                             0xf0000000
+
+
+#endif // _CE_SRC_DESC_H_

hw/qca6290/v1/ce_stat_desc.h

@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
+//	1	toeplitz_hash_0[31:0]
+//	2	toeplitz_hash_1[31:0]
+//	3	fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+             uint32_t ce_res_5                        :  8, //[7:0]
+                      toeplitz_en                     :  1, //[8]
+                      src_swap                        :  1, //[9]
+                      dest_swap                       :  1, //[10]
+                      gather                          :  1, //[11]
+                      ce_res_6                        :  4, //[15:12]
+                      length                          : 16; //[31:16]
+             uint32_t toeplitz_hash_0                 : 32; //[31:0]
+             uint32_t toeplitz_hash_1                 : 32; //[31:0]
+             uint32_t fw_metadata                     : 16, //[15:0]
+                      ce_res_7                        :  4, //[19:16]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+ce_res_5
+			
+			Reserved
+			
+			<legal all>
+
+toeplitz_en
+			
+			
+			<legal all>
+
+src_swap
+			
+			Source memory buffer swapped
+			
+			<legal all>
+
+dest_swap
+			
+			Destination  memory buffer swapped
+			
+			<legal all>
+
+gather
+			
+			Gather of multiple copy engine source descriptors to one
+			destination enabled
+			
+			<legal all>
+
+ce_res_6
+			
+			Reserved
+			
+			<legal all>
+
+length
+			
+			Sum of all the Lengths of the source descriptor in the
+			gather chain
+			
+			<legal all>
+
+toeplitz_hash_0
+			
+			32 LS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+
+toeplitz_hash_1
+			
+			32 MS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+
+fw_metadata
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+ce_res_7
+			
+			Reserved 
+			
+			<legal all>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		CE_STAT_DESC_0_CE_RES_5
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_5_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_5_LSB                                  0
+#define CE_STAT_DESC_0_CE_RES_5_MASK                                 0x000000ff
+
+/* Description		CE_STAT_DESC_0_TOEPLITZ_EN
+			
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET                            0x00000000
+#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB                               8
+#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK                              0x00000100
+
+/* Description		CE_STAT_DESC_0_SRC_SWAP
+			
+			Source memory buffer swapped
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_SRC_SWAP_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_SRC_SWAP_LSB                                  9
+#define CE_STAT_DESC_0_SRC_SWAP_MASK                                 0x00000200
+
+/* Description		CE_STAT_DESC_0_DEST_SWAP
+			
+			Destination  memory buffer swapped
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_DEST_SWAP_OFFSET                              0x00000000
+#define CE_STAT_DESC_0_DEST_SWAP_LSB                                 10
+#define CE_STAT_DESC_0_DEST_SWAP_MASK                                0x00000400
+
+/* Description		CE_STAT_DESC_0_GATHER
+			
+			Gather of multiple copy engine source descriptors to one
+			destination enabled
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_GATHER_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_GATHER_LSB                                    11
+#define CE_STAT_DESC_0_GATHER_MASK                                   0x00000800
+
+/* Description		CE_STAT_DESC_0_CE_RES_6
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_6_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_6_LSB                                  12
+#define CE_STAT_DESC_0_CE_RES_6_MASK                                 0x0000f000
+
+/* Description		CE_STAT_DESC_0_LENGTH
+			
+			Sum of all the Lengths of the source descriptor in the
+			gather chain
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_LENGTH_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_LENGTH_LSB                                    16
+#define CE_STAT_DESC_0_LENGTH_MASK                                   0xffff0000
+
+/* Description		CE_STAT_DESC_1_TOEPLITZ_HASH_0
+			
+			32 LS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET                        0x00000004
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB                           0
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK                          0xffffffff
+
+/* Description		CE_STAT_DESC_2_TOEPLITZ_HASH_1
+			
+			32 MS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET                        0x00000008
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB                           0
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK                          0xffffffff
+
+/* Description		CE_STAT_DESC_3_FW_METADATA
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_FW_METADATA_OFFSET                            0x0000000c
+#define CE_STAT_DESC_3_FW_METADATA_LSB                               0
+#define CE_STAT_DESC_3_FW_METADATA_MASK                              0x0000ffff
+
+/* Description		CE_STAT_DESC_3_CE_RES_7
+			
+			Reserved 
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_CE_RES_7_OFFSET                               0x0000000c
+#define CE_STAT_DESC_3_CE_RES_7_LSB                                  16
+#define CE_STAT_DESC_3_CE_RES_7_MASK                                 0x000f0000
+
+/* Description		CE_STAT_DESC_3_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_RING_ID_OFFSET                                0x0000000c
+#define CE_STAT_DESC_3_RING_ID_LSB                                   20
+#define CE_STAT_DESC_3_RING_ID_MASK                                  0x0ff00000
+
+/* Description		CE_STAT_DESC_3_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET                          0x0000000c
+#define CE_STAT_DESC_3_LOOPING_COUNT_LSB                             28
+#define CE_STAT_DESC_3_LOOPING_COUNT_MASK                            0xf0000000
+
+
+#endif // _CE_STAT_DESC_H_

hw/qca6290/v1/com_dtypes.h

@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+/**
+  @file com_dtypes.h
+  @brief This header file contains general data types that are of use to all 
+  modules.  
+
+*/
+/*===========================================================================
+NOTE: The @brief description and any detailed descriptions above do not appear 
+      in the PDF. 
+
+      The Utility_Services_API_mainpage.dox file contains all file/group 
+      descriptions that are in the output PDF generated using Doxygen and 
+      Latex. To edit or update any of the file/group text in the PDF, edit 
+      the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
+
+      The above description for this file is part of the "utils_services" 
+	  group description in the Utility_Services_API_mainpage.dox file. 
+===========================================================================*/
+/*===========================================================================
+
+                   S T A N D A R D    D E C L A R A T I O N S
+
+DESCRIPTION
+  This header file contains general data types that are of use to all modules.  
+  The values or definitions are dependent on the specified
+  target.  T_WINNT specifies Windows NT based targets, otherwise the
+  default is for ARM targets.
+
+  T_WINNT  Software is hosted on an NT platforn, triggers macro and
+           type definitions, unlike definition above which triggers
+           actual OS calls
+
+===========================================================================*/
+
+
+/*===========================================================================
+
+                      EDIT HISTORY FOR FILE
+
+This section contains comments describing changes made to this file.
+Notice that changes are listed in reverse chronological order.
+
+$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $
+
+when       who     what, where, why
+--------   ---     ----------------------------------------------------------
+03/21/11   llg     (Tech Pubs) Edited/added Doxygen comments and markup.
+11/09/10   EBR     Doxygenated file.
+09/15/09   pc      Created file.
+===========================================================================*/
+
+
+/*===========================================================================
+
+                            Data Declarations
+
+===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For NT apps we want to use the Win32 definitions and/or those
+ supplied by the Win32 compiler for things like NULL, MAX, MIN
+ abs, labs, etc.
+*/
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+/* ------------------------------------------------------------------------
+** Constants
+** ------------------------------------------------------------------------ */
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+/** @addtogroup utils_services
+@{ */
+
+/** @name Macros for Common Data Types
+@{ */
+#define TRUE   1   /**< Boolean TRUE value. */
+#define FALSE  0   /**< Boolean FALSE value. */
+
+#define  ON   1    /**< ON value. */
+#define  OFF  0    /**< OFF value. */
+
+#ifndef NULL
+  #define NULL  0  /**< NULL value. */  
+#endif
+/** @} */ /* end_name_group Macros for Common Data Types */
+
+/* -----------------------------------------------------------------------
+** Standard Types
+** ----------------------------------------------------------------------- */
+
+/** @} */ /* end_addtogroup utils_services */
+
+/* The following definitions are the same across platforms.  This first
+ group are the sanctioned types.
+*/
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+/** @addtogroup utils_services
+@{ */
+/** Boolean value type. 
+*/
+typedef  unsigned char      boolean;     
+#define _BOOLEAN_DEFINED
+#endif
+
+/** @cond 
+*/
+#if defined(DALSTDDEF_H) /* guards against a known re-definer */
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif /* #if !defined(DALSTDDEF_H) */
+/** @endcond */
+
+#ifndef _UINT32_DEFINED
+/** Unsigned 32-bit value.
+*/
+typedef  unsigned long int  uint32;      
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+/** Unsigned 16-bit value.
+*/
+typedef  unsigned short     uint16;      
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+/** Unsigned 8-bit value. 
+*/
+typedef  unsigned char      uint8;       
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+/** Signed 32-bit value.
+*/
+typedef  signed long int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+/** Signed 16-bit value.
+*/
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+/** Signed 8-bit value.
+*/
+typedef  signed char        int8;        
+#define _INT8_DEFINED
+#endif
+
+/** @cond
+*/
+/* This group are the deprecated types.  Their use should be
+** discontinued and new code should use the types above
+*/
+#ifndef _BYTE_DEFINED
+/** DEPRECATED: Unsigned 8  bit value type.
+*/
+typedef  unsigned char      byte;         
+#define  _BYTE_DEFINED
+#endif
+
+/** DEPRECATED: Unsinged 16 bit value type.
+*/
+typedef  unsigned short     word;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef  unsigned long      dword;        
+
+/** DEPRECATED: Unsigned 8  bit value type.
+*/
+typedef  unsigned char      uint1;
+/** DEPRECATED: Unsigned 16 bit value type.
+*/
+typedef  unsigned short     uint2;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef  unsigned long      uint4;        
+
+/** DEPRECATED: Signed 8  bit value type. 
+*/
+typedef  signed char        int1;
+/** DEPRECATED: Signed 16 bit value type.
+*/         
+typedef  signed short       int2;
+/** DEPRECATED: Signed 32 bit value type. 
+*/     
+typedef  long int           int4;         
+
+/** DEPRECATED: Signed 32 bit value.
+*/
+typedef  signed long        sint31;
+/** DEPRECATED: Signed 16 bit value. 
+*/       
+typedef  signed short       sint15;
+/** DEPRECATED: Signed 8  bit value.
+*/       
+typedef  signed char        sint7; 
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+/** @endcond */
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+  /* Non WinNT Targets */
+  #ifndef _INT64_DEFINED
+    /** Signed 64-bit value.
+	*/
+    typedef long long     int64;       
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+    /** Unsigned 64-bit value.
+	*/
+    typedef  unsigned long long  uint64;      
+    #define _UINT64_DEFINED
+  #endif
+#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
+  /* WINNT or SOLARIS based targets */
+  #if (defined __GNUC__) 
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;       /* Signed 64-bit value */
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;      /* Unsigned 64-bit value */
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif /* T_WINNT */
+
+#endif /* _ARM_ASM_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */ /* end_addtogroup utils_services */
+#endif  /* COM_DTYPES_H */

hw/qca6290/v1/lithium_top_reg.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//////////////////////////////////////////////////////////////////////////////
+// lithium_top_reg.h generated by: GenArmCHeader.pl
+//////////////////////////////////////////////////////////////////////////////
+// **** W A R N I N G ****  THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
+//////////////////////////////////////////////////////////////////////////////
+// RCS File        : -USE CVS LOG-
+// Revision        : -USE CVS LOG-
+// Last Check In   : -USE CVS LOG-
+//////////////////////////////////////////////////////////////////////////////
+// Description     : Constants related to Hardware Registers
+//
+// Byte Addresses are used for all BASES and ADDRESSES
+//////////////////////////////////////////////////////////////////////////////
+#ifndef LITHIUM_TOP_REG_H
+#define LITHIUM_TOP_REG_H
+
+#define UMAC_CE_COMMON_CE_HOST_IE_0               (0x00A18034)
+#define UMAC_CE_COMMON_CE_HOST_IE_1               (0x00A18038)
+
+#endif

hw/qca6290/v1/mac_tcl_reg_seq_hwiobase.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_BASE_H__
+#define __MAC_TCL_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+#endif
+

hw/qca6290/v1/mac_tcl_reg_seq_hwioreg.h

@@ -0,0 +1,6821 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_REG_H__
+#define __MAC_TCL_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "mac_tcl_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block MAC_TCL_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register TCL_R0_SW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x)                        (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x)                        (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x)                        (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x)                        (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x)                        (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x)                        (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x)                        (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x)                        (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x)                     (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x)                     (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK                        0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT                                 0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK          0x00040000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT                0x12
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK            0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT                   0x6
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK               0x00000020
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT                      0x5
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK               0x00000001
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT                      0x0
+
+//// Register TCL_R0_CONS_RING_CMN_CTRL_REG ////
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                   (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x)                   (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK                      0x00000007
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT                               0
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK           0x00000004
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT                  0x2
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK     0x00000002
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT            0x1
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK             0x00000001
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT                    0x0
+
+//// Register TCL_R0_TCL2TQM_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x)                        (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x)                        (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK                           0x00000fff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK               0x00000fff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT                      0x0
+
+//// Register TCL_R0_TCL2FW_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x)                         (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x)                         (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK                            0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT                                     0
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK                0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT                       0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x)                    (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x)                    (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK                       0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK           0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT                  0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x)                    (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x)                    (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK                       0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK           0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT                  0x0
+
+//// Register TCL_R0_GEN_CTRL ////
+
+#define HWIO_TCL_R0_GEN_CTRL_ADDR(x)                                 (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_PHYS(x)                                 (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_RMSK                                    0xffff7e1d
+#define HWIO_TCL_R0_GEN_CTRL_SHFT                                             0
+#define HWIO_TCL_R0_GEN_CTRL_IN(x)                                   \
+	in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK)
+#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask)                            \
+	in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val)                             \
+	out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val)                      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK           0xffff0000
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT                 0x10
+
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK            0x00004000
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT                   0xe
+
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK                0x00002000
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT                       0xd
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK                    0x00001000
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT                           0xc
+
+#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK                             0x00000e00
+#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT                                    0x9
+
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK                             0x00000010
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT                                    0x4
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK                             0x00000008
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT                                    0x3
+
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK                         0x00000004
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT                                0x2
+
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK                            0x00000001
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT                                   0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_0 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x)                          (x+0x0000002c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x)                          (x+0x0000002c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK                      0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT                            0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK                      0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT                            0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK                      0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT                            0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK                      0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT                            0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_1 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x)                          (x+0x00000030)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x)                          (x+0x00000030)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_2 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x)                          (x+0x00000034)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x)                          (x+0x00000034)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_3 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x)                          (x+0x00000038)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x)                          (x+0x00000038)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_4 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x)                          (x+0x0000003c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x)                          (x+0x0000003c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_5 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x)                          (x+0x00000040)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x)                          (x+0x00000040)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_6 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x)                          (x+0x00000044)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x)                          (x+0x00000044)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK                             0x00000fff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_0 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x)                          (x+0x00000048)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x)                          (x+0x00000048)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK                      0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT                            0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK                      0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT                            0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK                      0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT                            0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK                      0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT                            0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_1 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x)                          (x+0x0000004c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x)                          (x+0x0000004c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_2 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x)                          (x+0x00000050)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x)                          (x+0x00000050)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_3 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x)                          (x+0x00000054)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x)                          (x+0x00000054)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_4 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x)                          (x+0x00000058)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x)                          (x+0x00000058)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_5 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x)                          (x+0x0000005c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x)                          (x+0x0000005c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_6 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x)                          (x+0x00000060)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x)                          (x+0x00000060)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK                             0x00000fff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT                            0x0
+
+//// Register TCL_R0_PCP_TID_MAP ////
+
+#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)                              (x+0x00000064)
+#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x)                              (x+0x00000064)
+#define HWIO_TCL_R0_PCP_TID_MAP_RMSK                                 0x00ffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_SHFT                                          0
+#define HWIO_TCL_R0_PCP_TID_MAP_IN(x)                                \
+	in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK)
+#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask)                         \
+	in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 
+#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val)                          \
+	out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val)
+#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK                           0x00e00000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT                                 0x15
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK                           0x001c0000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT                                 0x12
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK                           0x00038000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT                                  0xf
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK                           0x00007000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT                                  0xc
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK                           0x00000e00
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT                                  0x9
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK                           0x000001c0
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT                                  0x6
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK                           0x00000038
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT                                  0x3
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK                           0x00000007
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT                                  0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_31_0 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x)                        (x+0x00000068)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x)                        (x+0x00000068)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK                           0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT                                    0
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK                       0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT                              0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_63_32 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x)                       (x+0x0000006c)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x)                       (x+0x0000006c)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK                          0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT                                   0
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT                             0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_64 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x)                          (x+0x00000070)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x)                          (x+0x00000070)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK                             0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT                                      0
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK                         0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT                                0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_31_0 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x)                        (x+0x00000074)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x)                        (x+0x00000074)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK                           0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT                                    0
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK                       0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT                              0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_63_32 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x)                       (x+0x00000078)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x)                       (x+0x00000078)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK                          0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT                                   0
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT                             0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_95_64 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x)                       (x+0x0000007c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x)                       (x+0x0000007c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK                          0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT                                   0
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT                             0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_127_96 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x)                      (x+0x00000080)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x)                      (x+0x00000080)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT                                  0
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT                            0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_159_128 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x)                     (x+0x00000084)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x)                     (x+0x00000084)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_191_160 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x)                     (x+0x00000088)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x)                     (x+0x00000088)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_223_192 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x)                     (x+0x0000008c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x)                     (x+0x0000008c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_255_224 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x)                     (x+0x00000090)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x)                     (x+0x00000090)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_287_256 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x)                     (x+0x00000094)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x)                     (x+0x00000094)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_314_288 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x)                     (x+0x00000098)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x)                     (x+0x00000098)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK                        0x07ffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK                    0x07ffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT                           0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_QUEUE ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x)                      (x+0x0000009c)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x)                      (x+0x0000009c)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK                         0x00003dfc
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT                                  2
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK           0x00002000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT                  0xd
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK           0x00001000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT                  0xc
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK           0x00000800
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT                  0xb
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK           0x00000400
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT                  0xa
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK                0x000001c0
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT                       0x6
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK        0x00000030
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT               0x4
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK        0x0000000c
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT               0x2
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x)                   (x+0x000000a0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x)                   (x+0x000000a0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT                               0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK                  0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT                         0x0
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x)                  (x+0x000000a4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x)                  (x+0x000000a4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK                     0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT                              0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK                 0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT                        0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x)                   (x+0x000000a8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x)                   (x+0x000000a8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK                      0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT                               0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK                  0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT                         0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x)                  (x+0x000000ac)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x)                  (x+0x000000ac)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK                     0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT                              0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK                 0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT                        0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_METADATA ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x)                   (x+0x000000b0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x)                   (x+0x000000b0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT                               0
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK         0xffff0000
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT               0x10
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK         0x0000ffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT                0x0
+
+//// Register TCL_R0_TID_MAP_PRTY ////
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)                             (x+0x000000b4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x)                             (x+0x000000b4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK                                0x000000ef
+#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT                                         0
+#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK)
+#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val)
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK                        0x000000e0
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT                               0x5
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK                            0x0000000f
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_INVALID_APB_ACC_ADDR ////
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x)                     (x+0x000000b8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x)                     (x+0x000000b8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK                        0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT                                 0
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT                           0x0
+
+//// Register TCL_R0_WATCHDOG ////
+
+#define HWIO_TCL_R0_WATCHDOG_ADDR(x)                                 (x+0x000000bc)
+#define HWIO_TCL_R0_WATCHDOG_PHYS(x)                                 (x+0x000000bc)
+#define HWIO_TCL_R0_WATCHDOG_RMSK                                    0xffffffff
+#define HWIO_TCL_R0_WATCHDOG_SHFT                                             0
+#define HWIO_TCL_R0_WATCHDOG_IN(x)                                   \
+	in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_WATCHDOG_INM(x, mask)                            \
+	in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_WATCHDOG_OUT(x, val)                             \
+	out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val)                      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK                             0xffff0000
+#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT                                   0x10
+
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK                              0x0000ffff
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT                                     0x0
+
+//// Register TCL_R0_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x)                          (x+0x000000c0)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x)                          (x+0x000000c0)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK                             0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT                                      0
+#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK                         0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT                                0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                    (x+0x000000c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x)                    (x+0x000000c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                    (x+0x000000c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x)                    (x+0x000000c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                          (x+0x000000cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x)                          (x+0x000000cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x)                      (x+0x000000d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x)                      (x+0x000000d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                        (x+0x000000d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x)                        (x+0x000000d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x000000e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x000000e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x000000e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x000000e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000000f4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000000f4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000000f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000000f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000000fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000000fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000100)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000100)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x00000104)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x00000104)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000108)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000108)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000010c)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000010c)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000110)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000110)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                   (x+0x00000114)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x)                   (x+0x00000114)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000118)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000118)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                    (x+0x0000011c)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x)                    (x+0x0000011c)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x)                    (x+0x00000120)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x)                    (x+0x00000120)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL2_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x)                          (x+0x00000124)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x)                          (x+0x00000124)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL2_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x)                      (x+0x00000128)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x)                      (x+0x00000128)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x)                        (x+0x0000012c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x)                        (x+0x0000012c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000138)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000138)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x0000013c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x0000013c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x0000014c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x0000014c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x00000150)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x00000150)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x00000154)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x00000154)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000158)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000158)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x0000015c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x0000015c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000160)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000160)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x00000164)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x00000164)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000168)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000168)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x)                   (x+0x0000016c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x)                   (x+0x0000016c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000170)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000170)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x)                    (x+0x00000174)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x)                    (x+0x00000174)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x)                    (x+0x00000178)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x)                    (x+0x00000178)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL3_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x)                          (x+0x0000017c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x)                          (x+0x0000017c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL3_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x)                      (x+0x00000180)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x)                      (x+0x00000180)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x)                        (x+0x00000184)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x)                        (x+0x00000184)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000190)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000190)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x00000194)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x00000194)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000001a4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000001a4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000001a8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000001a8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000001ac)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000001ac)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x000001b0)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x000001b0)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x000001b4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x000001b4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x000001b8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x000001b8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000001bc)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000001bc)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000001c0)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000001c0)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x)                   (x+0x000001c4)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x)                   (x+0x000001c4)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000001c8)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000001c8)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x)                 (x+0x000001cc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x)                 (x+0x000001cc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x)                 (x+0x000001d0)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x)                 (x+0x000001d0)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x)                       (x+0x000001d4)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x)                       (x+0x000001d4)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK                          0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT                                   0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x)                   (x+0x000001d8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x)                   (x+0x000001d8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x)                     (x+0x000001dc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x)                     (x+0x000001dc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK                        0x0000003f
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT                                 0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x)              (x+0x000001e8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x)              (x+0x000001e8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x)              (x+0x000001ec)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x)              (x+0x000001ec)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x000001fc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x000001fc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000200)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000200)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x00000204)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x00000204)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000208)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000208)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x0000020c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x0000020c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000214)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000214)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000218)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000218)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x)                (x+0x0000021c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x)                (x+0x0000021c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT                            0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000220)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000220)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x)                    (x+0x00000224)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x)                    (x+0x00000224)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x)                    (x+0x00000228)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x)                    (x+0x00000228)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_FW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x)                          (x+0x0000022c)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x)                          (x+0x0000022c)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_FW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x)                      (x+0x00000230)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x)                      (x+0x00000230)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x)                        (x+0x00000234)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x)                        (x+0x00000234)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000240)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000240)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x00000244)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x00000244)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x00000254)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x00000254)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x00000258)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x00000258)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x0000025c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x0000025c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000260)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000260)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x00000264)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x00000264)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000268)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000268)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000026c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000026c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000270)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000270)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x)                   (x+0x00000274)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x)                   (x+0x00000274)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000278)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000278)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)                    (x+0x0000027c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x)                    (x+0x0000027c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)                    (x+0x00000280)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x)                    (x+0x00000280)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_TCL2TQM_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x)                          (x+0x00000284)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x)                          (x+0x00000284)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_TCL2TQM_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x)                      (x+0x00000288)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x)                      (x+0x00000288)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x)                        (x+0x0000028c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x)                        (x+0x0000028c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000290)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000290)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x00000294)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x00000294)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x000002a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x000002a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x000002a4)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x000002a4)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x000002a8)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x000002a8)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000002d0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000002d0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)                (x+0x000002d4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x)                (x+0x000002d4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x)                (x+0x000002d8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x)                (x+0x000002d8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x)                      (x+0x000002dc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x)                      (x+0x000002dc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT                                  0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x)                  (x+0x000002e0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x)                  (x+0x000002e0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT                              0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x)                    (x+0x000002e4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x)                    (x+0x000002e4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK                       0x0000003f
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x)             (x+0x000002e8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x)             (x+0x000002e8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x)             (x+0x000002ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x)             (x+0x000002ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x000002f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x000002f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x000002fc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x000002fc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000300)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000300)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x0000031c)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x0000031c)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x00000320)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x00000320)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x)               (x+0x00000324)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x)               (x+0x00000324)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT                           0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000328)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000328)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x)                (x+0x0000032c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x)                (x+0x0000032c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x)                (x+0x00000330)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x)                (x+0x00000330)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x)                      (x+0x00000334)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x)                      (x+0x00000334)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT                                  0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x)                  (x+0x00000338)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x)                  (x+0x00000338)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT                              0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x)                    (x+0x0000033c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x)                    (x+0x0000033c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK                       0x0000003f
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x)             (x+0x00000340)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x)             (x+0x00000340)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x)             (x+0x00000344)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x)             (x+0x00000344)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x00000350)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x00000350)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x00000354)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x00000354)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000358)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000358)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x00000374)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x00000374)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x00000378)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x00000378)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x)               (x+0x0000037c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x)               (x+0x0000037c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT                           0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000380)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000380)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x)                     (x+0x00000384)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x)                     (x+0x00000384)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK                        0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT                                 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x)                     (x+0x00000388)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x)                     (x+0x00000388)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK                        0x00ffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT                                 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK              0x00ffff00
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT                     0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0
+
+//// Register TCL_R0_TCL2FW_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x)                           (x+0x0000038c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x)                           (x+0x0000038c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK                              0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT                                       0
+#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK                      0x0000ff00
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT                             0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT                          0x0
+
+//// Register TCL_R0_TCL2FW_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x)                       (x+0x00000390)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x)                       (x+0x00000390)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK                          0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT                                   0
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x)                         (x+0x00000394)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x)                         (x+0x00000394)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK                            0x0000003f
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT                                     0
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK               0x00000004
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT                      0x2
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT                   0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x)                  (x+0x00000398)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x)                  (x+0x00000398)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT                              0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x)                  (x+0x0000039c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x)                  (x+0x0000039c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK                     0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT                              0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x)           (x+0x000003a8)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x)           (x+0x000003a8)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT                       0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x)          (x+0x000003ac)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x)          (x+0x000003ac)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK             0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT                      0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)        (x+0x000003b0)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x)        (x+0x000003b0)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK           0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT                    0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x000003d8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x000003d8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK                 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT                          0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x)                        (x+0x000003dc)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x)                        (x+0x000003dc)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK                           0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT                                    0
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK                     0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT                            0x0
+
+//// Register TCL_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x)                        (x+0x000003e0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x)                        (x+0x000003e0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK                           0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT                                    0
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK                     0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT                            0x0
+
+//// Register TCL_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x)                       (x+0x000003e4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x)                       (x+0x000003e4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK                          0x00000fff
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT                                   0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK         0x00000e00
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                0x9
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK         0x000001f0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                0x4
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK         0x0000000f
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                0x0
+
+//// Register TCL_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000003e8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000003e8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x)                   (x+0x000003ec)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x)                   (x+0x000003ec)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK                      0x80000fff
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT                               0
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK    0x80000000
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT          0x1f
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK   0x00000fff
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT          0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x)                         (x+0x000003f0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x)                         (x+0x000003f0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK                            0x01010101
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT                                     0
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK        0x01000000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT              0x18
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK         0x00010000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT               0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK         0x00000100
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK          0x00000001
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                 0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x)                        (x+0x000003f4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x)                        (x+0x000003f4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK                           0x003f3f3f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT                                    0
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK      0x003f0000
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT            0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK           0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                  0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK           0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                  0x0
+
+//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                  (x+0x000003f8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                  (x+0x000003f8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT                              0
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x)                  (x+0x000003fc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x)                  (x+0x000003fc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT                              0
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register TCL_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x)                     (x+0x00000400)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x)                     (x+0x00000400)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK                        0x007fffff
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT                                 0
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK   0x00700000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT         0x14
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK    0x000e0000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT          0x11
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK        0x00000001
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT               0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x)                     (x+0x00000404)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x)                     (x+0x00000404)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK                        0xffff0001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT                                 0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK         0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT               0x10
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x)                      (x+0x00000408)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x)                      (x+0x00000408)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                0x0
+
+//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x)                    (x+0x0000040c)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x)                    (x+0x0000040c)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK                       0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT                                0
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK     0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT           0x10
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK    0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT           0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x)                    (x+0x00000410)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x)                    (x+0x00000410)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK                       0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT                                0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK                   0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT                          0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x)                   (x+0x00000414)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x)                   (x+0x00000414)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK                      0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT                               0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK                  0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT                         0x0
+
+//// Register TCL_R0_ASE_GST_SIZE ////
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x)                             (x+0x00000418)
+#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x)                             (x+0x00000418)
+#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK                                0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT                                         0
+#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK)
+#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK                            0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_ASE_SEARCH_CTRL ////
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x)                          (x+0x0000041c)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x)                          (x+0x0000041c)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK                             0xffff03ff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT                                      0
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK              0xffff0000
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT                    0x10
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK               0x00000200
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT                      0x9
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK                 0x00000100
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT                        0x8
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK                  0x000000ff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT                         0x0
+
+//// Register TCL_R0_ASE_WATCHDOG ////
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x)                             (x+0x00000420)
+#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x)                             (x+0x00000420)
+#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK                                0xffffffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT                                         0
+#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK                         0xffff0000
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT                               0x10
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK                          0x0000ffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT                                 0x0
+
+//// Register TCL_R0_ASE_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x)                      (x+0x00000424)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x)                      (x+0x00000424)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK                         0xffffffff
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT                                  0
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT                            0x0
+
+//// Register TCL_R0_ASE_WRITE_BACK_PENDING ////
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x)                   (x+0x00000428)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x)                   (x+0x00000428)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK                      0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT                               0
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK               0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT                      0x0
+
+//// Register TCL_R0_FSE_GST_BASE_ADDR_LOW ////
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x)                    (x+0x0000042c)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x)                    (x+0x0000042c)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK                       0xffffffff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT                                0
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK                   0xffffffff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT                          0x0
+
+//// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH ////
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x)                   (x+0x00000430)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x)                   (x+0x00000430)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK                      0x000000ff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT                               0
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT                         0x0
+
+//// Register TCL_R0_FSE_GST_SIZE ////
+
+#define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x)                             (x+0x00000434)
+#define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x)                             (x+0x00000434)
+#define HWIO_TCL_R0_FSE_GST_SIZE_RMSK                                0x000fffff
+#define HWIO_TCL_R0_FSE_GST_SIZE_SHFT                                         0
+#define HWIO_TCL_R0_FSE_GST_SIZE_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK)
+#define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK                            0x000fffff
+#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_FSE_SEARCH_CTRL ////
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x)                          (x+0x00000438)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x)                          (x+0x00000438)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK                             0xffff03ff
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT                                      0
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK              0xffff0000
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT                    0x10
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK               0x00000200
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT                      0x9
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK                 0x00000100
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT                        0x8
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT                         0x0
+
+//// Register TCL_R0_FSE_WATCHDOG ////
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x)                             (x+0x0000043c)
+#define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x)                             (x+0x0000043c)
+#define HWIO_TCL_R0_FSE_WATCHDOG_RMSK                                0xffffffff
+#define HWIO_TCL_R0_FSE_WATCHDOG_SHFT                                         0
+#define HWIO_TCL_R0_FSE_WATCHDOG_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK                         0xffff0000
+#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT                               0x10
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK                          0x0000ffff
+#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT                                 0x0
+
+//// Register TCL_R0_FSE_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x)                      (x+0x00000440)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x)                      (x+0x00000440)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT                                  0
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT                            0x0
+
+//// Register TCL_R0_FSE_WRITE_BACK_PENDING ////
+
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x)                   (x+0x00000444)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x)                   (x+0x00000444)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK                      0x00000001
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT                               0
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK               0x00000001
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT                      0x0
+
+//// Register TCL_R1_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00001000)
+#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00001000)
+#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK                              0x07ffffff
+#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT                                       0
+#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK                     0x07000000
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT                           0x18
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK                      0x00e00000
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT                            0x15
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK              0x001c0000
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT                    0x12
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK                   0x00038000
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT                          0xf
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK              0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT                     0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK                 0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT                        0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK                 0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT                        0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK                 0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT                        0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK                 0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT                        0x0
+
+//// Register TCL_R1_SM_STATES_IX_1 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK                              0x00007fff
+#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT                                       0
+#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK                    0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT                           0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK                  0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT                         0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK                  0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT                         0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK                       0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT                              0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK                      0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT                             0x0
+
+//// Register TCL_R1_TESTBUS_CTRL_0 ////
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x)                           (x+0x00001008)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x)                           (x+0x00001008)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK                              0x1fffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT                                       0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK              0x1f800000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT                    0x17
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK                   0x007c0000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT                         0x12
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK                   0x0003c000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT                          0xe
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK                   0x00003c00
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT                          0xa
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK                0x000003e0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT                       0x5
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK                   0x0000001f
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT                          0x0
+
+//// Register TCL_R1_TESTBUS_LOW ////
+
+#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x)                              (x+0x0000100c)
+#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x)                              (x+0x0000100c)
+#define HWIO_TCL_R1_TESTBUS_LOW_RMSK                                 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_SHFT                                          0
+#define HWIO_TCL_R1_TESTBUS_LOW_IN(x)                                \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK)
+#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask)                         \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val)                          \
+	out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT                                    0x0
+
+//// Register TCL_R1_TESTBUS_HIGH ////
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x)                             (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x)                             (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK                                0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT                                         0
+#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK)
+#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK                            0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT                                   0x0
+
+//// Register TCL_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x)                           (x+0x00001014)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x)                           (x+0x00001014)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x)                           (x+0x00001018)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x)                           (x+0x00001018)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_2 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x)                           (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x)                           (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_3 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x)                           (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x)                           (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)                (x+0x00001024)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x)                (x+0x00001024)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK                   0xffffffff
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT                            0
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val)            \
+	out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT       0x11
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT        0x2
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT        0x1
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT        0x0
+
+//// Register TCL_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00001028)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00001028)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT                                    0
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK    0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT           0x0
+
+//// Register TCL_R1_ASE_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x)                    (x+0x0000102c)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x)                    (x+0x0000102c)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x)                 (x+0x00001030)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x)                 (x+0x00001030)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK                    0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT                             0
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val)             \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK                 0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT                        0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)         (x+0x00001034)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x)         (x+0x00001034)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK            0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT                     0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val)     \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK        0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT               0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)           (x+0x00001038)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x)           (x+0x00001038)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK              0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT                       0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val)       \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK          0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT                 0x0
+
+//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)        (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x)        (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK           0x000fffff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT                    0
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK      0x000ffc00
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT             0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK      0x000003ff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT             0x0
+
+//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)            (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x)            (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK               0x03ffffff
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT                        0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val)        \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT        0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT        0x5
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT        0x0
+
+//// Register TCL_R1_ASE_SM_STATES ////
+
+#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x)                            (x+0x00001044)
+#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x)                            (x+0x00001044)
+#define HWIO_TCL_R1_ASE_SM_STATES_RMSK                               0x003fffff
+#define HWIO_TCL_R1_ASE_SM_STATES_SHFT                                        0
+#define HWIO_TCL_R1_ASE_SM_STATES_IN(x)                              \
+	in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK)
+#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask)                       \
+	in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val)                        \
+	out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK                0x00300000
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT                      0x14
+
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK               0x000c0000
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT                     0x12
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK                0x00030000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT                      0x10
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK                0x0000c000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT                       0xe
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK               0x00003800
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT                      0xb
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK               0x00000700
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT                      0x8
+
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK                0x000000c0
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT                       0x6
+
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK               0x00000030
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT                      0x4
+
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK              0x0000000f
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT                     0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x)                          (x+0x00001048)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x)                          (x+0x00001048)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK                             0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT                                      0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK                    0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT                           0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)              (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x)              (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK                 0x007fffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT                          0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val)          \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK         0x007ffff8
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT                0x3
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK      0x00000004
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT             0x2
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK           0x00000002
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT                  0x1
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK           0x00000001
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT                  0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n)            (base+0x1050+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n)            (base+0x1050+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK                     0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT                              0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn                             31
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)             \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val)       \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK                 0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT                        0x0
+
+//// Register TCL_R1_FSE_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000010d0)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000010d0)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x)                 (x+0x000010d4)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x)                 (x+0x000010d4)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK                    0x00000001
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT                             0
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val)             \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK                 0x00000001
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT                        0x0
+
+//// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)         (x+0x000010d8)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x)         (x+0x000010d8)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK            0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT                     0
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val)     \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK        0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT               0x0
+
+//// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)           (x+0x000010dc)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x)           (x+0x000010dc)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK              0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT                       0
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val)       \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK          0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT                 0x0
+
+//// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)        (x+0x000010e0)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x)        (x+0x000010e0)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK           0x000fffff
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT                    0
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK      0x000ffc00
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT             0xa
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK      0x000003ff
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT             0x0
+
+//// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)            (x+0x000010e4)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x)            (x+0x000010e4)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK               0x03ffffff
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT                        0
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val)        \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT        0xa
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT        0x5
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT        0x0
+
+//// Register TCL_R1_FSE_SM_STATES ////
+
+#define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x)                            (x+0x000010e8)
+#define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x)                            (x+0x000010e8)
+#define HWIO_TCL_R1_FSE_SM_STATES_RMSK                               0x003fffff
+#define HWIO_TCL_R1_FSE_SM_STATES_SHFT                                        0
+#define HWIO_TCL_R1_FSE_SM_STATES_IN(x)                              \
+	in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK)
+#define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask)                       \
+	in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val)                        \
+	out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK                0x00300000
+#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT                      0x14
+
+#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK               0x000c0000
+#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT                     0x12
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK                0x00030000
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT                      0x10
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK                0x0000c000
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT                       0xe
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK               0x00003800
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT                      0xb
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK               0x00000700
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT                      0x8
+
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK                0x000000c0
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT                       0x6
+
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK               0x00000030
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT                      0x4
+
+#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK              0x0000000f
+#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT                     0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x)                          (x+0x000010ec)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x)                          (x+0x000010ec)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK                             0x000003ff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT                                      0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK                    0x000003ff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT                           0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)              (x+0x000010f0)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x)              (x+0x000010f0)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK                 0x007fffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT                          0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val)          \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK         0x007ffff8
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT                0x3
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK      0x00000004
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT             0x2
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK           0x00000002
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT                  0x1
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK           0x00000001
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT                  0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n)            (base+0x10F4+0x4*n)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n)            (base+0x10F4+0x4*n)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK                     0xffffffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT                              0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn                             31
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)             \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val)       \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK                 0xffffffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT                        0x0
+
+//// Register TCL_R2_SW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                          (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x)                          (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                          (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x)                          (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL2_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                          (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x)                          (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL2_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x)                          (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x)                          (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL3_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x)                          (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x)                          (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL3_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x)                          (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x)                          (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL_CMD_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x)                       (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x)                       (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK                          0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT                                   0
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register TCL_R2_SW2TCL_CMD_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x)                       (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x)                       (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK                          0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT                                   0
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register TCL_R2_FW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x)                          (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x)                          (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_FW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x)                          (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x)                          (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL2TQM_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x)                          (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x)                          (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL2TQM_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x)                          (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x)                          (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)                      (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x)                      (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x)                      (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x)                      (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x)                      (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x)                      (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x)                      (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x)                      (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL2FW_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x)                           (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x)                           (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK                              0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT                                       0
+#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK                     0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT                            0x0
+
+//// Register TCL_R2_TCL2FW_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x)                           (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x)                           (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK                              0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT                                       0
+#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK                     0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT                            0x0
+
+
+#endif
+

hw/qca6290/v1/msmhwio.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef MSMHWIO_H
+#define MSMHWIO_H
+/*
+===========================================================================
+*/
+/**
+  @file msmhwio.h 
+
+  Deprecated public interface include file for accessing the HWIO macro
+  definitions.
+
+  The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO)
+  register access definitions.  See HALhwio.h and DDIHWIO.h for the new
+  interfaces.
+*/
+/*  
+  ==================================================================== 
+  $Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $
+  ====================================================================
+*/ 
+
+/*=========================================================================
+      Include Files
+==========================================================================*/
+
+/*
+ * Include main HWIO macros.
+ */
+#include "HALhwio.h"
+
+
+#endif /* MSMHWIO_H */
+

hw/qca6290/v1/reo_destination_ring.h

@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_msdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info buf_or_link_desc_addr_info;
+//	2-3	struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+//	4-5	struct rx_msdu_desc_info rx_msdu_desc_info_details;
+//	6	rx_reo_queue_desc_addr_31_0[31:0]
+//	7	rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
+//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
+
+struct reo_destination_ring {
+    struct            buffer_addr_info                       buf_or_link_desc_addr_info;
+    struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
+    struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      reo_dest_buffer_type            :  1, //[8]
+                      reo_push_reason                 :  2, //[10:9]
+                      reo_error_code                  :  5, //[15:11]
+                      receive_queue_number            : 16; //[31:16]
+             uint32_t soft_reorder_info_valid         :  1, //[0]
+                      reorder_opcode                  :  4, //[4:1]
+                      reorder_slot_index              :  8, //[12:5]
+                      reserved_8a                     : 19; //[31:13]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info buf_or_link_desc_addr_info
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Details of the physical address of the a buffer or MSDU
+			link descriptor
+
+struct rx_mpdu_desc_info rx_mpdu_desc_info_details
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			General information related to the MPDU that is passed
+			on from REO entrance ring to the REO destination ring
+
+struct rx_msdu_desc_info rx_msdu_desc_info_details
+			
+			General information related to the MSDU that is passed
+			on from RXDMA all the way to to the REO destination ring.
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+reo_dest_buffer_type
+			
+			Indicates the type of address provided in the
+			'Buf_or_link_desc_addr_info'
+			
+			
+			
+			<enum 0 MSDU_buf_address> The address of an MSDU buffer
+			
+			<enum 1 MSDU_link_desc_address> The address of the MSDU
+			link descriptor. 
+			
+			
+			
+			<legal all>
+
+reo_push_reason
+			
+			Indicates why REO pushed the frame to this exit ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			
+			
+			<legal 0 - 1>
+
+reo_error_code
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+
+receive_queue_number
+			
+			This field indicates the REO MPDU reorder queue ID from
+			which this frame originated. This field is populated from a
+			field with the same name in the RX_REO_QUEUE descriptor.
+			
+			<legal all>
+
+soft_reorder_info_valid
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes
+			
+			<legal all>
+
+reorder_opcode
+			
+			Field is valid when 'Soft_reorder_info_valid' is set.
+			This field is always valid for debug purpose as well.
+			
+			Details are in the MLD.
+			
+			
+			
+			<enum 0 invalid>
+			
+			<enum 1 fwdcur_fwdbuf>
+			
+			<enum 2 fwdbuf_fwdcur>
+			
+			<enum 3 qcur>
+			
+			<enum 4 fwdbuf_qcur>
+			
+			<enum 5 fwdbuf_drop>
+			
+			<enum 6 fwdall_drop>
+			
+			<enum 7 fwdall_qcur>
+			
+			<enum 8 reserved_reo_opcode_1>
+			
+			<enum 9 dropcur>  the error reason code is in
+			reo_error_code field.
+			
+			<enum 10 reserved_reo_opcode_2>
+			
+			<enum 11 reserved_reo_opcode_3>
+			
+			<enum 12 reserved_reo_opcode_4>
+			
+			<enum 13 reserved_reo_opcode_5>
+			
+			<enum 14 reserved_reo_opcode_6>
+			
+			<enum 15 reserved_reo_opcode_7>
+			
+			
+			
+			<legal all>
+
+reorder_slot_index
+			
+			Field only valid when 'Soft_reorder_info_valid' is set.
+			
+			
+			
+			TODO: add description
+			
+			
+			
+			<legal all>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15
+			
+			<legal 0>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+
+/* Description		REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET    0x00000018
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB       0
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK      0xffffffff
+
+/* Description		REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET   0x0000001c
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB      0
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK     0x000000ff
+
+/* Description		REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE
+			
+			Indicates the type of address provided in the
+			'Buf_or_link_desc_addr_info'
+			
+			
+			
+			<enum 0 MSDU_buf_address> The address of an MSDU buffer
+			
+			<enum 1 MSDU_link_desc_address> The address of the MSDU
+			link descriptor. 
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB              8
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK             0x00000100
+
+/* Description		REO_DESTINATION_RING_7_REO_PUSH_REASON
+			
+			Indicates why REO pushed the frame to this exit ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			
+			
+			<legal 0 - 1>
+*/
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB                   9
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK                  0x00000600
+
+/* Description		REO_DESTINATION_RING_7_REO_ERROR_CODE
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+*/
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB                    11
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK                   0x0000f800
+
+/* Description		REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
+			
+			This field indicates the REO MPDU reorder queue ID from
+			which this frame originated. This field is populated from a
+			field with the same name in the RX_REO_QUEUE descriptor.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB              16
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK             0xffff0000
+
+/* Description		REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET        0x00000020
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB           0
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK          0x00000001
+
+/* Description		REO_DESTINATION_RING_8_REORDER_OPCODE
+			
+			Field is valid when 'Soft_reorder_info_valid' is set.
+			This field is always valid for debug purpose as well.
+			
+			Details are in the MLD.
+			
+			
+			
+			<enum 0 invalid>
+			
+			<enum 1 fwdcur_fwdbuf>
+			
+			<enum 2 fwdbuf_fwdcur>
+			
+			<enum 3 qcur>
+			
+			<enum 4 fwdbuf_qcur>
+			
+			<enum 5 fwdbuf_drop>
+			
+			<enum 6 fwdall_drop>
+			
+			<enum 7 fwdall_qcur>
+			
+			<enum 8 reserved_reo_opcode_1>
+			
+			<enum 9 dropcur>  the error reason code is in
+			reo_error_code field.
+			
+			<enum 10 reserved_reo_opcode_2>
+			
+			<enum 11 reserved_reo_opcode_3>
+			
+			<enum 12 reserved_reo_opcode_4>
+			
+			<enum 13 reserved_reo_opcode_5>
+			
+			<enum 14 reserved_reo_opcode_6>
+			
+			<enum 15 reserved_reo_opcode_7>
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET                 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB                    1
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK                   0x0000001e
+
+/* Description		REO_DESTINATION_RING_8_REORDER_SLOT_INDEX
+			
+			Field only valid when 'Soft_reorder_info_valid' is set.
+			
+			
+			
+			TODO: add description
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET             0x00000020
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB                5
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK               0x00001fe0
+
+/* Description		REO_DESTINATION_RING_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET                    0x00000020
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       13
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xffffe000
+
+/* Description		REO_DESTINATION_RING_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET                    0x00000024
+#define REO_DESTINATION_RING_9_RESERVED_9A_LSB                       0
+#define REO_DESTINATION_RING_9_RESERVED_9A_MASK                      0xffffffff
+
+/* Description		REO_DESTINATION_RING_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET                  0x00000028
+#define REO_DESTINATION_RING_10_RESERVED_10A_LSB                     0
+#define REO_DESTINATION_RING_10_RESERVED_10A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET                  0x0000002c
+#define REO_DESTINATION_RING_11_RESERVED_11A_LSB                     0
+#define REO_DESTINATION_RING_11_RESERVED_11A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET                  0x00000030
+#define REO_DESTINATION_RING_12_RESERVED_12A_LSB                     0
+#define REO_DESTINATION_RING_12_RESERVED_12A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET                  0x00000034
+#define REO_DESTINATION_RING_13_RESERVED_13A_LSB                     0
+#define REO_DESTINATION_RING_13_RESERVED_13A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET                  0x00000038
+#define REO_DESTINATION_RING_14_RESERVED_14A_LSB                     0
+#define REO_DESTINATION_RING_14_RESERVED_14A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_15_RESERVED_15
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET                   0x0000003c
+#define REO_DESTINATION_RING_15_RESERVED_15_LSB                      0
+#define REO_DESTINATION_RING_15_RESERVED_15_MASK                     0x000fffff
+
+/* Description		REO_DESTINATION_RING_15_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_15_RING_ID_OFFSET                       0x0000003c
+#define REO_DESTINATION_RING_15_RING_ID_LSB                          20
+#define REO_DESTINATION_RING_15_RING_ID_MASK                         0x0ff00000
+
+/* Description		REO_DESTINATION_RING_15_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET                 0x0000003c
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB                    28
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK                   0xf0000000
+
+
+#endif // _REO_DESTINATION_RING_H_

hw/qca6290/v1/reo_entrance_ring.h

@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
+//	4	rx_reo_queue_desc_addr_31_0[31:0]
+//	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
+//	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7]
+//	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+    struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      rounded_mpdu_byte_count         : 14, //[21:8]
+                      reo_destination_indication      :  5, //[26:22]
+                      frameless_bar                   :  1, //[27]
+                      reserved_5a                     :  4; //[31:28]
+             uint32_t rxdma_push_reason               :  2, //[1:0]
+                      rxdma_error_code                :  5, //[6:2]
+                      reserved_6a                     : 25; //[31:7]
+             uint32_t reserved_7a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct rx_mpdu_details reo_level_mpdu_frame_info
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Details related to the MPDU being pushed into the REO
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rounded_mpdu_byte_count
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+
+reo_destination_indication
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+frameless_bar
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+
+reserved_5a
+			
+			<legal 0>
+
+rxdma_push_reason
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			This field is ignored by REO. 
+			
+			<legal 0 - 1>
+
+rxdma_error_code
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+ring_id
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+
+looping_count
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+
+/* Description		REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
+
+/* Description		REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
+
+/* Description		REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
+
+/* Description		REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
+
+/* Description		REO_ENTRANCE_RING_5_FRAMELESS_BAR
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
+
+/* Description		REO_ENTRANCE_RING_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			This field is ignored by REO. 
+			
+			<legal 0 - 1>
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
+
+/* Description		REO_ENTRANCE_RING_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          7
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xffffff80
+
+/* Description		REO_ENTRANCE_RING_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
+
+/* Description		REO_ENTRANCE_RING_7_RING_ID
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+*/
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
+
+/* Description		REO_ENTRANCE_RING_7_LOOPING_COUNT
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
+
+
+#endif // _REO_ENTRANCE_RING_H_

hw/qca6290/v1/reo_get_queue_stats.h

@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_GET_QUEUE_STATS_H_
+#define _REO_GET_QUEUE_STATS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_cmd_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_reo_cmd_header cmd_header;
+//	1	rx_reo_queue_desc_addr_31_0[31:0]
+//	2	rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9]
+//	3	reserved_3a[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[31:0]
+//	8	reserved_8a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9
+
+struct reo_get_queue_stats {
+    struct            uniform_reo_cmd_header                       cmd_header;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      clear_stats                     :  1, //[8]
+                      reserved_2a                     : 23; //[31:9]
+             uint32_t reserved_3a                     : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 32; //[31:0]
+             uint32_t reserved_8a                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_reo_cmd_header cmd_header
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Details for command execution tracking purposes.
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor
+			
+			<legal all>
+
+clear_stats
+			
+			Clear stat settings....
+			
+			
+			
+			<enum 0 no_clear> Do NOT clear the stats after
+			generating the status
+			
+			<enum 1 clear_the_stats> Clear the stats after
+			generating the status. 
+			
+			
+			
+			The stats actually cleared are:
+			
+			Timeout_count
+			
+			Forward_due_to_bar_count
+			
+			Duplicate_count
+			
+			Frames_in_order_count
+			
+			BAR_received_count
+			
+			MPDU_Frames_processed_count
+			
+			MSDU_Frames_processed_count
+			
+			Total_processed_byte_count
+			
+			Late_receive_MPDU_count
+			
+			window_jump_2k
+			
+			Hole_count
+			
+			<legal 0-1>
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+reserved_8a
+			
+			<legal 0>
+*/
+
+#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_LSB  0
+#define REO_GET_QUEUE_STATS_0_UNIFORM_REO_CMD_HEADER_CMD_HEADER_MASK 0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET     0x00000004
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB        0
+#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: SW
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET    0x00000008
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB       0
+#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK      0x000000ff
+
+/* Description		REO_GET_QUEUE_STATS_2_CLEAR_STATS
+			
+			Clear stat settings....
+			
+			
+			
+			<enum 0 no_clear> Do NOT clear the stats after
+			generating the status
+			
+			<enum 1 clear_the_stats> Clear the stats after
+			generating the status. 
+			
+			
+			
+			The stats actually cleared are:
+			
+			Timeout_count
+			
+			Forward_due_to_bar_count
+			
+			Duplicate_count
+			
+			Frames_in_order_count
+			
+			BAR_received_count
+			
+			MPDU_Frames_processed_count
+			
+			MSDU_Frames_processed_count
+			
+			Total_processed_byte_count
+			
+			Late_receive_MPDU_count
+			
+			window_jump_2k
+			
+			Hole_count
+			
+			<legal 0-1>
+*/
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET                     0x00000008
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB                        8
+#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK                       0x00000100
+
+/* Description		REO_GET_QUEUE_STATS_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET                     0x00000008
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB                        9
+#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK                       0xfffffe00
+
+/* Description		REO_GET_QUEUE_STATS_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET                     0x0000000c
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB                        0
+#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK                       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET                     0x00000010
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB                        0
+#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK                       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET                     0x00000014
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB                        0
+#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK                       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET                     0x00000018
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB                        0
+#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK                       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET                     0x0000001c
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB                        0
+#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK                       0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET                     0x00000020
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB                        0
+#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK                       0xffffffff
+
+
+#endif // _REO_GET_QUEUE_STATS_H_

hw/qca6290/v1/reo_get_queue_stats_status.h

@@ -0,0 +1,868 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_GET_QUEUE_STATS_STATUS_H_
+#define _REO_GET_QUEUE_STATS_STATUS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_reo_status_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct uniform_reo_status_header status_header;
+//	2	ssn[11:0], current_index[19:12], reserved_2[31:20]
+//	3	pn_31_0[31:0]
+//	4	pn_63_32[31:0]
+//	5	pn_95_64[31:0]
+//	6	pn_127_96[31:0]
+//	7	last_rx_enqueue_timestamp[31:0]
+//	8	last_rx_dequeue_timestamp[31:0]
+//	9	rx_bitmap_31_0[31:0]
+//	10	rx_bitmap_63_32[31:0]
+//	11	rx_bitmap_95_64[31:0]
+//	12	rx_bitmap_127_96[31:0]
+//	13	rx_bitmap_159_128[31:0]
+//	14	rx_bitmap_191_160[31:0]
+//	15	rx_bitmap_223_192[31:0]
+//	16	rx_bitmap_255_224[31:0]
+//	17	current_mpdu_count[6:0], current_msdu_count[31:7]
+//	18	reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
+//	19	frames_in_order_count[23:0], bar_received_count[31:24]
+//	20	mpdu_frames_processed_count[31:0]
+//	21	msdu_frames_processed_count[31:0]
+//	22	total_processed_byte_count[31:0]
+//	23	late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
+//	24	reserved_24a[27:0], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25
+
+struct reo_get_queue_stats_status {
+    struct            uniform_reo_status_header                       status_header;
+             uint32_t ssn                             : 12, //[11:0]
+                      current_index                   :  8, //[19:12]
+                      reserved_2                      : 12; //[31:20]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+             uint32_t last_rx_enqueue_timestamp       : 32; //[31:0]
+             uint32_t last_rx_dequeue_timestamp       : 32; //[31:0]
+             uint32_t rx_bitmap_31_0                  : 32; //[31:0]
+             uint32_t rx_bitmap_63_32                 : 32; //[31:0]
+             uint32_t rx_bitmap_95_64                 : 32; //[31:0]
+             uint32_t rx_bitmap_127_96                : 32; //[31:0]
+             uint32_t rx_bitmap_159_128               : 32; //[31:0]
+             uint32_t rx_bitmap_191_160               : 32; //[31:0]
+             uint32_t rx_bitmap_223_192               : 32; //[31:0]
+             uint32_t rx_bitmap_255_224               : 32; //[31:0]
+             uint32_t current_mpdu_count              :  7, //[6:0]
+                      current_msdu_count              : 25; //[31:7]
+             uint32_t reserved_18                     :  4, //[3:0]
+                      timeout_count                   :  6, //[9:4]
+                      forward_due_to_bar_count        :  6, //[15:10]
+                      duplicate_count                 : 16; //[31:16]
+             uint32_t frames_in_order_count           : 24, //[23:0]
+                      bar_received_count              :  8; //[31:24]
+             uint32_t mpdu_frames_processed_count     : 32; //[31:0]
+             uint32_t msdu_frames_processed_count     : 32; //[31:0]
+             uint32_t total_processed_byte_count      : 32; //[31:0]
+             uint32_t late_receive_mpdu_count         : 12, //[11:0]
+                      window_jump_2k                  :  4, //[15:12]
+                      hole_count                      : 16; //[31:16]
+             uint32_t reserved_24a                    : 28, //[27:0]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct uniform_reo_status_header status_header
+			
+			Consumer: SW
+			
+			Producer: REO
+			
+			
+			
+			Details that can link this status with the original
+			command. It also contains info on how long REO took to
+			execute this command.
+
+ssn
+			
+			Starting Sequence number of the session, this changes
+			whenever window moves. (can be filled by SW then maintained
+			by REO)
+			
+			<legal all>
+
+current_index
+			
+			Points to last forwarded packet
+			
+			<legal all>
+
+reserved_2
+			
+			<legal 0>
+
+pn_31_0
+			
+			
+			<legal all>
+
+pn_63_32
+			
+			Bits [63:32] of the PN number.  
+			
+			<legal all> 
+
+pn_95_64
+			
+			Bits [95:64] of the PN number.  
+			
+			<legal all>
+
+pn_127_96
+			
+			Bits [127:96] of the PN number.  
+			
+			<legal all>
+
+last_rx_enqueue_timestamp
+			
+			Timestamp of arrival of the last MPDU for this queue
+			
+			<legal all>
+
+last_rx_dequeue_timestamp
+			
+			Timestamp of forwarding an MPDU
+			
+			
+			
+			If the queue is empty when a frame gets received, this
+			time shall be initialized to the 'enqueue' timestamp
+			
+			
+			
+			Used for aging
+			
+			<legal all>
+
+rx_bitmap_31_0
+			
+			When a bit is set, the corresponding frame is currently
+			held in the re-order queue.
+			
+			The bitmap  is Fully managed by HW. 
+			
+			SW shall init this to 0, and then never ever change it
+			
+			<legal all>
+
+rx_bitmap_63_32
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_95_64
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_127_96
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_159_128
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_191_160
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_223_192
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_255_224
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+current_mpdu_count
+			
+			The number of MPDUs in the queue.
+			
+			
+			
+			<legal all>
+
+current_msdu_count
+			
+			The number of MSDUs in the queue.
+			
+			<legal all>
+
+reserved_18
+			
+			<legal 0>
+
+timeout_count
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is Timeout
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+
+forward_due_to_bar_count
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is reception of BAR frame.
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+
+duplicate_count
+			
+			The number of duplicate frames that have been detected
+			
+			<legal all>
+
+frames_in_order_count
+			
+			The number of frames that have been received in order
+			(without a hole that prevented them from being forwarded
+			immediately)
+			
+			
+			
+			This corresponds to the Reorder opcodes:
+			
+			'FWDCUR' and 'FWD BUF'
+			
+			
+			
+			<legal all>
+
+bar_received_count
+			
+			The number of times a BAR frame is received.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'DROP'
+			
+			
+			
+			The counter saturates and freezes at 0xFF
+			
+			<legal all>
+
+mpdu_frames_processed_count
+			
+			The total number of MPDU frames that have been processed
+			by REO. This includes the duplicates.
+			
+			
+			
+			<legal all>
+
+msdu_frames_processed_count
+			
+			The total number of MSDU frames that have been processed
+			by REO. This includes the duplicates.
+			
+			
+			
+			<legal all>
+
+total_processed_byte_count
+			
+			An approximation of the number of bytes received for
+			this queue. 
+			
+			
+			
+			In 64 byte units
+			
+			<legal all>
+
+late_receive_mpdu_count
+			
+			The number of MPDUs received after the window had
+			already moved on. The 'late' sequence window is defined as
+			(Window SSN - 256) - (Window SSN - 1)
+			
+			
+			
+			This corresponds with Out of order detection in
+			duplicate detect FSM
+			
+			
+			
+			The counter saturates and freezes at 0xFFF
+			
+			
+			
+			<legal all>
+
+window_jump_2k
+			
+			The number of times the window moved more then 2K
+			
+			
+			
+			The counter saturates and freezes at 0xF
+			
+			
+			
+			(Note: field name can not start with number: previous
+			2k_window_jump)
+			
+			
+			
+			<legal all>
+
+hole_count
+			
+			The number of times a hole was created in the receive
+			bitmap.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'QCUR'
+			
+			
+			
+			<legal all>
+
+reserved_24a
+			
+			<legal 0>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000000
+#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_0_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_OFFSET 0x00000004
+#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_LSB 28
+#define REO_GET_QUEUE_STATS_STATUS_1_UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_MASK 0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_2_SSN
+			
+			Starting Sequence number of the session, this changes
+			whenever window moves. (can be filled by SW then maintained
+			by REO)
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET                      0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB                         0
+#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK                        0x00000fff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX
+			
+			Points to last forwarded packet
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET            0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB               12
+#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK              0x000ff000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET               0x00000008
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB                  20
+#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK                 0xfff00000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_3_PN_31_0
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET                  0x0000000c
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB                     0
+#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK                    0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_4_PN_63_32
+			
+			Bits [63:32] of the PN number.  
+			
+			<legal all> 
+*/
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET                 0x00000010
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK                   0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_5_PN_95_64
+			
+			Bits [95:64] of the PN number.  
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET                 0x00000014
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB                    0
+#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK                   0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_6_PN_127_96
+			
+			Bits [127:96] of the PN number.  
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET                0x00000018
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB                   0
+#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK                  0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP
+			
+			Timestamp of arrival of the last MPDU for this queue
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB   0
+#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK  0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP
+			
+			Timestamp of forwarding an MPDU
+			
+			
+			
+			If the queue is empty when a frame gets received, this
+			time shall be initialized to the 'enqueue' timestamp
+			
+			
+			
+			Used for aging
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB   0
+#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK  0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0
+			
+			When a bit is set, the corresponding frame is currently
+			held in the re-order queue.
+			
+			The bitmap  is Fully managed by HW. 
+			
+			SW shall init this to 0, and then never ever change it
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET           0x00000024
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB              0
+#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK             0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET         0x00000028
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB            0
+#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK           0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET         0x0000002c
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB            0
+#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK           0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET        0x00000030
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB           0
+#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK          0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET       0x00000034
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK         0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET       0x00000038
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK         0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET       0x0000003c
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK         0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET       0x00000040
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB          0
+#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK         0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT
+			
+			The number of MPDUs in the queue.
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET      0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB         0
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK        0x0000007f
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT
+			
+			The number of MSDUs in the queue.
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET      0x00000044
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB         7
+#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK        0xffffff80
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET             0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB                0
+#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK               0x0000000f
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is Timeout
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET           0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB              4
+#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK             0x000003f0
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is reception of BAR frame.
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB   10
+#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK  0x0000fc00
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT
+			
+			The number of duplicate frames that have been detected
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET         0x00000048
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB            16
+#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK           0xffff0000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT
+			
+			The number of frames that have been received in order
+			(without a hole that prevented them from being forwarded
+			immediately)
+			
+			
+			
+			This corresponds to the Reorder opcodes:
+			
+			'FWDCUR' and 'FWD BUF'
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET   0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB      0
+#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK     0x00ffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT
+			
+			The number of times a BAR frame is received.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'DROP'
+			
+			
+			
+			The counter saturates and freezes at 0xFF
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET      0x0000004c
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB         24
+#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK        0xff000000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT
+			
+			The total number of MPDU frames that have been processed
+			by REO. This includes the duplicates.
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT
+			
+			The total number of MSDU frames that have been processed
+			by REO. This includes the duplicates.
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT
+			
+			An approximation of the number of bytes received for
+			this queue. 
+			
+			
+			
+			In 64 byte units
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0
+#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT
+			
+			The number of MPDUs received after the window had
+			already moved on. The 'late' sequence window is defined as
+			(Window SSN - 256) - (Window SSN - 1)
+			
+			
+			
+			This corresponds with Out of order detection in
+			duplicate detect FSM
+			
+			
+			
+			The counter saturates and freezes at 0xFFF
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB    0
+#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK   0x00000fff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K
+			
+			The number of times the window moved more then 2K
+			
+			
+			
+			The counter saturates and freezes at 0xF
+			
+			
+			
+			(Note: field name can not start with number: previous
+			2k_window_jump)
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET          0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB             12
+#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK            0x0000f000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT
+			
+			The number of times a hole was created in the receive
+			bitmap.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'QCUR'
+			
+			
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET              0x0000005c
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB                 16
+#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK                0xffff0000
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A
+			
+			<legal 0>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET            0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB               0
+#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK              0x0fffffff
+
+/* Description		REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET           0x00000060
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB              28
+#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK             0xf0000000
+
+
+#endif // _REO_GET_QUEUE_STATS_STATUS_H_

hw/qca6290/v1/reo_reg_seq_hwiobase.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// reo_reg_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __REO_REG_SEQ_BASE_H__
+#define __REO_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+#endif
+

hw/qca6290/v1/reo_reg_seq_hwioreg.h

@@ -0,0 +1,8639 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// reo_reg_seq_hwioreg.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __REO_REG_SEQ_REG_H__
+#define __REO_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "reo_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block REO_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register REO_R0_GENERAL_ENABLE ////
+
+#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x)                           (x+0x00000000)
+#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x)                           (x+0x00000000)
+#define HWIO_REO_R0_GENERAL_ENABLE_RMSK                              0x1fffffff
+#define HWIO_REO_R0_GENERAL_ENABLE_SHFT                                       0
+#define HWIO_REO_R0_GENERAL_ENABLE_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK)
+#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) 
+#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val)
+#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK           0x10000000
+#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT                 0x1c
+
+#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK       0x0e000000
+#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT             0x19
+
+#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_BMSK           0x01c00000
+#define HWIO_REO_R0_GENERAL_ENABLE_FRAGMENT_DEST_RING_SHFT                 0x16
+
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK           0x00200000
+#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT                 0x15
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK          0x00100000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT                0x14
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK       0x00080000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT             0x13
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK      0x00040000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT            0x12
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK          0x00020000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT                0x11
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK           0x00010000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT                 0x10
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK          0x00008000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT                 0xf
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK          0x00004000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT                 0xe
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK          0x00002000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT                 0xd
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK          0x00001000
+#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT                 0xc
+
+#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK     0x00000800
+#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT            0xb
+
+#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK        0x00000700
+#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT               0x8
+
+#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK                0x00000080
+#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT                       0x7
+
+#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK                0x00000070
+#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT                       0x4
+
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK           0x00000008
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT                  0x3
+
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK            0x00000004
+#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT                   0x2
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK        0x00000002
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT               0x1
+
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK                   0x00000001
+#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT                          0x0
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x)               (x+0x00000004)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x)               (x+0x00000004)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK                  0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT                           8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x)               (x+0x00000008)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x)               (x+0x00000008)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK                  0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT                           8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x)               (x+0x0000000c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x)               (x+0x0000000c)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK                  0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT                           8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x)               (x+0x00000010)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x)               (x+0x00000010)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK                  0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT                           8
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x)           (x+0x00000014)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x)           (x+0x00000014)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK              0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT                       8
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x)           (x+0x00000018)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x)           (x+0x00000018)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK              0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT                       8
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x)           (x+0x0000001c)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x)           (x+0x0000001c)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK              0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT                       8
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT        0x8
+
+//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 ////
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x)           (x+0x00000020)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x)           (x+0x00000020)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK              0xffffff00
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT                       8
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xe0000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT       0x1d
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x1c000000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT       0x1a
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x03800000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT       0x17
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x00700000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT       0x14
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x000e0000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT       0x11
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x0001c000
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT        0xe
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x00003800
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT        0xb
+
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x00000700
+#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT        0x8
+
+//// Register REO_R0_TIMESTAMP ////
+
+#define HWIO_REO_R0_TIMESTAMP_ADDR(x)                                (x+0x00000024)
+#define HWIO_REO_R0_TIMESTAMP_PHYS(x)                                (x+0x00000024)
+#define HWIO_REO_R0_TIMESTAMP_RMSK                                   0xffffffff
+#define HWIO_REO_R0_TIMESTAMP_SHFT                                            0
+#define HWIO_REO_R0_TIMESTAMP_IN(x)                                  \
+	in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK)
+#define HWIO_REO_R0_TIMESTAMP_INM(x, mask)                           \
+	in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) 
+#define HWIO_REO_R0_TIMESTAMP_OUT(x, val)                            \
+	out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val)
+#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val)                     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK                         0xffffffff
+#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT                                0x0
+
+//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 ////
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x)           (x+0x00000028)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x)           (x+0x00000028)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK              0x3fffffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT                       0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_BMSK 0x38000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_9_SHFT       0x1b
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_BMSK 0x07000000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_8_SHFT       0x18
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0x00e00000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT       0x15
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x001c0000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT       0x12
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00038000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT        0xf
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x00007000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT        0xc
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x00000e00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT        0x9
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x000001c0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT        0x6
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x00000038
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT        0x3
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x00000007
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT        0x0
+
+//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 ////
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x)           (x+0x0000002c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x)           (x+0x0000002c)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK              0x0003ffff
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT                       0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0x00038000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT        0xf
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x00007000
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT        0xc
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00000e00
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT        0x9
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000001c0
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT        0x6
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x00000038
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT        0x3
+
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000007
+#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT        0x0
+
+//// Register REO_R0_IDLE_REQ_CTRL ////
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x)                            (x+0x00000030)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x)                            (x+0x00000030)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK                               0x00000003
+#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT                                        0
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)                              \
+	in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask)                       \
+	in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val)                        \
+	out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK          0x00000002
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT                 0x1
+
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK       0x00000001
+#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT              0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x)                 (x+0x00000034)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x)                 (x+0x00000034)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x)                 (x+0x00000038)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x)                 (x+0x00000038)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_ID ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x)                       (x+0x0000003c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x)                       (x+0x0000003c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK                          0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT                                   0
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x)                   (x+0x00000040)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x)                   (x+0x00000040)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT                               0
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MISC ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x)                     (x+0x00000044)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x)                     (x+0x00000044)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK                        0x0000003f
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT                                 0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x)              (x+0x00000050)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x)              (x+0x00000050)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x)              (x+0x00000054)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x)              (x+0x00000054)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x00000064)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x00000064)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000068)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000068)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x0000006c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x0000006c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000070)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000070)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x00000074)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x00000074)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x0000007c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x0000007c)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000080)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000080)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x)                (x+0x00000084)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x)                (x+0x00000084)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT                            0
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000088)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000088)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x)                 (x+0x0000008c)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_PHYS(x)                 (x+0x0000008c)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x)                 (x+0x00000090)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_PHYS(x)                 (x+0x00000090)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_ID ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x)                       (x+0x00000094)
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_PHYS(x)                       (x+0x00000094)
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK                          0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_SHFT                                   0
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_ID_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x)                   (x+0x00000098)
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_PHYS(x)                   (x+0x00000098)
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_SHFT                               0
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_MISC ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x)                     (x+0x0000009c)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_PHYS(x)                     (x+0x0000009c)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK                        0x0000003f
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SHFT                                 0
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MISC_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_REO_R0_RXDMA2REO1_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x)              (x+0x000000a8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_PHYS(x)              (x+0x000000a8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x)              (x+0x000000ac)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_PHYS(x)              (x+0x000000ac)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x000000bc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x000000bc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x000000c0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x000000c0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x000000c4)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x000000c4)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x000000c8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x000000c8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x000000cc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x000000cc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x000000d4)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x000000d4)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x000000d8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x000000d8)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x)                (x+0x000000dc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_PHYS(x)                (x+0x000000dc)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_SHFT                            0
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x000000e0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x000000e0)
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x)                 (x+0x000000e4)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_PHYS(x)                 (x+0x000000e4)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x)                 (x+0x000000e8)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_PHYS(x)                 (x+0x000000e8)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_SHFT                             0
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_ID ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x)                       (x+0x000000ec)
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_PHYS(x)                       (x+0x000000ec)
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK                          0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_SHFT                                   0
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_ID_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x)                   (x+0x000000f0)
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_PHYS(x)                   (x+0x000000f0)
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_SHFT                               0
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_MISC ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x)                     (x+0x000000f4)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_PHYS(x)                     (x+0x000000f4)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK                        0x0000003f
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SHFT                                 0
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MISC_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_REO_R0_RXDMA2REO2_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x)              (x+0x00000100)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_PHYS(x)              (x+0x00000100)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x)              (x+0x00000104)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_PHYS(x)              (x+0x00000104)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x00000114)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x00000114)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000118)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000118)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x0000011c)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x0000011c)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000120)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000120)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x00000124)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x00000124)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x0000012c)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x0000012c)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000130)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000130)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x)                (x+0x00000134)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_PHYS(x)                (x+0x00000134)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_SHFT                            0
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000138)
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000138)
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_RXDMA2REO2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)               (x+0x0000013c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x)               (x+0x0000013c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)               (x+0x00000140)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x)               (x+0x00000140)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK                  0x00ffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK        0x00ffff00
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT               0x8
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_ID ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x)                     (x+0x00000144)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x)                     (x+0x00000144)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK                        0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT                                 0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK                0x0000ff00
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT                       0x8
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK             0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT                    0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)                 (x+0x00000148)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x)                 (x+0x00000148)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK                    0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT                             0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK    0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT          0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK    0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT           0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_MISC ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x)                   (x+0x0000014c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x)                   (x+0x0000014c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK                      0x0000003f
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT                               0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK    0x00000020
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT           0x5
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK     0x00000010
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT            0x4
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK         0x00000008
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                0x3
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK         0x00000004
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT                0x2
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK      0x00000002
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT             0x1
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK      0x00000001
+#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT             0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x)            (x+0x00000158)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x)            (x+0x00000158)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK               0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT                        0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x)            (x+0x0000015c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x)            (x+0x0000015c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK               0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT                        0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK    0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT             0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK    0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT             0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)    (x+0x00000174)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x)    (x+0x00000174)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK       0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT                0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK    0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT             0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)   \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK   0x00000007
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT            0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)  \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK  0x00ffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT           0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)        (x+0x00000190)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)        (x+0x00000190)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK           0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT                    0
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x)                    (x+0x00000194)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x)                    (x+0x00000194)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO_CMD_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x)                    (x+0x00000198)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x)                    (x+0x00000198)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO_CMD_RING_ID ////
+
+#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x)                          (x+0x0000019c)
+#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x)                          (x+0x0000019c)
+#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO_CMD_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO_CMD_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x)                      (x+0x000001a0)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x)                      (x+0x000001a0)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO_CMD_RING_MISC ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x)                        (x+0x000001a4)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x)                        (x+0x000001a4)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x000001b0)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x000001b0)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x000001b4)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x000001b4)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000001c4)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000001c4)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000001c8)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000001c8)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000001cc)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000001cc)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x000001d0)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x000001d0)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x000001d4)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x000001d4)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x000001d8)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x000001d8)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000001dc)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000001dc)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000001e0)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000001e0)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO_CMD_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x)                   (x+0x000001e4)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x)                   (x+0x000001e4)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000001e8)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000001e8)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x)                     (x+0x000001ec)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x)                     (x+0x000001ec)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK                        0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT                                 0
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0
+
+//// Register REO_R0_SW2REO_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x)                     (x+0x000001f0)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x)                     (x+0x000001f0)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK                        0x00ffffff
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT                                 0
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK              0x00ffff00
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT                     0x8
+
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0
+
+//// Register REO_R0_SW2REO_RING_ID ////
+
+#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x)                           (x+0x000001f4)
+#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x)                           (x+0x000001f4)
+#define HWIO_REO_R0_SW2REO_RING_ID_RMSK                              0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_ID_SHFT                                       0
+#define HWIO_REO_R0_SW2REO_RING_ID_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_BMSK                      0x0000ff00
+#define HWIO_REO_R0_SW2REO_RING_ID_RING_ID_SHFT                             0x8
+
+#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT                          0x0
+
+//// Register REO_R0_SW2REO_RING_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x)                       (x+0x000001f8)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x)                       (x+0x000001f8)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK                          0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT                                   0
+#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10
+
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0
+
+//// Register REO_R0_SW2REO_RING_MISC ////
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x)                         (x+0x000001fc)
+#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x)                         (x+0x000001fc)
+#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK                            0x0000003f
+#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT                                     0
+#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val)                     \
+	out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
+#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
+#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
+#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK               0x00000004
+#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT                      0x2
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
+#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1
+
+#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
+#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT                   0x0
+
+//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x)                  (x+0x00000208)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x)                  (x+0x00000208)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK                     0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT                              0
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x)                  (x+0x0000020c)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x)                  (x+0x0000020c)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK                     0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT                              0
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)       (x+0x0000021c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)       (x+0x0000021c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK          0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT                   0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)       (x+0x00000220)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)       (x+0x00000220)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK          0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT                   0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x)          (x+0x00000224)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x)          (x+0x00000224)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK             0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT                      0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)       (x+0x00000228)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)       (x+0x00000228)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT                   0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)      (x+0x0000022c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)      (x+0x0000022c)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK         0x00000007
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT                  0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK    0x00000007
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT           0x0
+
+//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)     (x+0x00000230)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)     (x+0x00000230)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK        0x00ffffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT                 0
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x)                (x+0x00000234)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x)                (x+0x00000234)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT                            0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK              0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT                     0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x)                (x+0x00000238)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x)                (x+0x00000238)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK                   0x000001ff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT                            0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK       0x00000100
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT              0x8
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK              0x000000ff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT                     0x0
+
+//// Register REO_R0_SW2REO_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x)                    (x+0x0000023c)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x)                    (x+0x0000023c)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK                       0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT                                0
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK                 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT                        0x0
+
+//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x00000240)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x00000240)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK                 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT                          0
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x)                    (x+0x00000244)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x)                    (x+0x00000244)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW1_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x)                    (x+0x00000248)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x)                    (x+0x00000248)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW1_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x)                          (x+0x0000024c)
+#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x)                          (x+0x0000024c)
+#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO2SW1_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x)                      (x+0x00000250)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x)                      (x+0x00000250)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO2SW1_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x)                        (x+0x00000254)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x)                        (x+0x00000254)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000258)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000258)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x0000025c)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x0000025c)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000268)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000268)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x0000026c)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x0000026c)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000270)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000270)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000028c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000028c)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000290)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000290)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW1_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x)                   (x+0x00000294)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x)                   (x+0x00000294)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000298)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000298)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x)                    (x+0x0000029c)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x)                    (x+0x0000029c)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW2_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x)                    (x+0x000002a0)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x)                    (x+0x000002a0)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW2_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x)                          (x+0x000002a4)
+#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x)                          (x+0x000002a4)
+#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO2SW2_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x)                      (x+0x000002a8)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x)                      (x+0x000002a8)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO2SW2_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x)                        (x+0x000002ac)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x)                        (x+0x000002ac)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x000002b0)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x000002b0)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x000002b4)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x000002b4)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x000002c0)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x000002c0)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x000002c4)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x000002c4)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x000002c8)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x000002c8)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000002e4)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000002e4)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000002e8)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000002e8)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW2_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x)                   (x+0x000002ec)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x)                   (x+0x000002ec)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000002f0)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000002f0)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x)                    (x+0x000002f4)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x)                    (x+0x000002f4)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW3_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x)                    (x+0x000002f8)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x)                    (x+0x000002f8)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW3_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x)                          (x+0x000002fc)
+#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x)                          (x+0x000002fc)
+#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO2SW3_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x)                      (x+0x00000300)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x)                      (x+0x00000300)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO2SW3_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x)                        (x+0x00000304)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x)                        (x+0x00000304)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000308)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000308)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x0000030c)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x0000030c)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000318)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000318)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x0000031c)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x0000031c)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000320)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000320)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000033c)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000033c)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000340)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000340)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW3_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x)                   (x+0x00000344)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x)                   (x+0x00000344)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000348)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000348)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x)                    (x+0x0000034c)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x)                    (x+0x0000034c)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW4_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x)                    (x+0x00000350)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x)                    (x+0x00000350)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO2SW4_RING_ID ////
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x)                          (x+0x00000354)
+#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x)                          (x+0x00000354)
+#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO2SW4_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x)                      (x+0x00000358)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x)                      (x+0x00000358)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO2SW4_RING_MISC ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x)                        (x+0x0000035c)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x)                        (x+0x0000035c)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000360)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000360)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x00000364)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x00000364)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x00000370)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x00000370)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x00000374)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x00000374)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x00000378)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x00000378)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x00000394)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x00000394)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000398)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000398)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2SW4_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x)                   (x+0x0000039c)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x)                   (x+0x0000039c)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000003a0)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000003a0)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x)                    (x+0x000003a4)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x)                    (x+0x000003a4)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT                                0
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register REO_R0_REO2TCL_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x)                    (x+0x000003a8)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x)                    (x+0x000003a8)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT                                0
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register REO_R0_REO2TCL_RING_ID ////
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x)                          (x+0x000003ac)
+#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x)                          (x+0x000003ac)
+#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK                             0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT                                      0
+#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register REO_R0_REO2TCL_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x)                      (x+0x000003b0)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x)                      (x+0x000003b0)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT                                  0
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register REO_R0_REO2TCL_RING_MISC ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x)                        (x+0x000003b4)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x)                        (x+0x000003b4)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK                           0x0000003f
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT                                    0
+#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x000003b8)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x000003b8)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x000003bc)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x000003bc)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x000003c8)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x000003c8)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x000003cc)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x000003cc)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x000003d0)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x000003d0)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000003ec)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000003ec)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000003f0)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000003f0)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register REO_R0_REO2TCL_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x)                   (x+0x000003f4)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x)                   (x+0x000003f4)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT                               0
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000003f8)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000003f8)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x)                     (x+0x000003fc)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x)                     (x+0x000003fc)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK                        0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT                                 0
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0
+
+//// Register REO_R0_REO2FW_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x)                     (x+0x00000400)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x)                     (x+0x00000400)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK                        0x00ffffff
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT                                 0
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK              0x00ffff00
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT                     0x8
+
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0
+
+//// Register REO_R0_REO2FW_RING_ID ////
+
+#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x)                           (x+0x00000404)
+#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x)                           (x+0x00000404)
+#define HWIO_REO_R0_REO2FW_RING_ID_RMSK                              0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_ID_SHFT                                       0
+#define HWIO_REO_R0_REO2FW_RING_ID_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK                      0x0000ff00
+#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT                             0x8
+
+#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT                          0x0
+
+//// Register REO_R0_REO2FW_RING_STATUS ////
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x)                       (x+0x00000408)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x)                       (x+0x00000408)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK                          0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT                                   0
+#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10
+
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0
+
+//// Register REO_R0_REO2FW_RING_MISC ////
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x)                         (x+0x0000040c)
+#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x)                         (x+0x0000040c)
+#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK                            0x0000003f
+#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT                                     0
+#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val)                     \
+	out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
+#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
+#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
+#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK               0x00000004
+#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT                      0x2
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
+#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1
+
+#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
+#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT                   0x0
+
+//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x)                  (x+0x00000410)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x)                  (x+0x00000410)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK                     0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT                              0
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x)                  (x+0x00000414)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x)                  (x+0x00000414)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK                     0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT                              0
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x)           (x+0x00000420)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x)           (x+0x00000420)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK              0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT                       0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)             \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val)       \
+	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x)          (x+0x00000424)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x)          (x+0x00000424)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK             0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT                      0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)        (x+0x00000428)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x)        (x+0x00000428)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK           0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT                    0
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x)                (x+0x00000444)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x)                (x+0x00000444)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT                            0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK              0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT                     0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x)                (x+0x00000448)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x)                (x+0x00000448)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK                   0x000001ff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT                            0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK       0x00000100
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT              0x8
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK              0x000000ff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT                     0x0
+
+//// Register REO_R0_REO2FW_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x)                    (x+0x0000044c)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x)                    (x+0x0000044c)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK                       0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT                                0
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK                 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT                        0x0
+
+//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x00000450)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x00000450)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK                 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT                          0
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)                (x+0x00000454)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x)                (x+0x00000454)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT                            0
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)                (x+0x00000458)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x)                (x+0x00000458)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT                            0
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_ID ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x)                      (x+0x0000045c)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x)                      (x+0x0000045c)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK                         0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT                                  0
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register REO_R0_REO_RELEASE_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x)                  (x+0x00000460)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x)                  (x+0x00000460)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT                              0
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register REO_R0_REO_RELEASE_RING_MISC ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x)                    (x+0x00000464)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x)                    (x+0x00000464)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK                       0x0000003f
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT                                0
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x)             (x+0x00000468)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x)             (x+0x00000468)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x)             (x+0x0000046c)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x)             (x+0x0000046c)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x00000478)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x00000478)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x0000047c)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x0000047c)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000480)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000480)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x000004a8)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x000004a8)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x)                 (x+0x000004ac)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x)                 (x+0x000004ac)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT                             0
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x)                 (x+0x000004b0)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x)                 (x+0x000004b0)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT                             0
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_ID ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x)                       (x+0x000004b4)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x)                       (x+0x000004b4)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK                          0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT                                   0
+#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register REO_R0_REO_STATUS_RING_STATUS ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x)                   (x+0x000004b8)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x)                   (x+0x000004b8)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT                               0
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register REO_R0_REO_STATUS_RING_MISC ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x)                     (x+0x000004bc)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x)                     (x+0x000004bc)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK                        0x0000003f
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT                                 0
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x)              (x+0x000004c0)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x)              (x+0x000004c0)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT                          0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x)              (x+0x000004c4)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x)              (x+0x000004c4)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT                          0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x)       (x+0x000004d0)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x)       (x+0x000004d0)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK          0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT                   0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x)      (x+0x000004d4)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x)      (x+0x000004d4)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT                  0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x)    (x+0x000004d8)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x)    (x+0x000004d8)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK       0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT                0
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)      \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x000004f4)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x000004f4)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x000004f8)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x000004f8)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register REO_R0_REO_STATUS_RING_MSI1_DATA ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x)                (x+0x000004fc)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x)                (x+0x000004fc)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT                            0
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000500)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000500)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register REO_R0_WATCHDOG_TIMEOUT ////
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x)                         (x+0x00000504)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x)                         (x+0x00000504)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK                            0x0fff0fff
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT                                     0
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val)                     \
+	out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val)
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_BMSK                0x0fff0000
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_GXI_TIMEOUT_SHFT                      0x10
+
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK               0x00000fff
+#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT                      0x0
+
+//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 ////
+
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x)              (x+0x00000508)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x)              (x+0x00000508)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK                 0xffffffff
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT                          0
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK      0xffffffff
+#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT             0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_0 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x)                     (x+0x0000050c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x)                     (x+0x0000050c)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT                                 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT           0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_1 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x)                     (x+0x00000510)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x)                     (x+0x00000510)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT                                 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT           0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_2 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x)                     (x+0x00000514)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x)                     (x+0x00000514)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT                                 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT           0x0
+
+//// Register REO_R0_AGING_THRESHOLD_IX_3 ////
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x)                     (x+0x00000518)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x)                     (x+0x00000518)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT                                 0
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT           0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x)               (x+0x0000051c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x)               (x+0x0000051c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x)               (x+0x00000520)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x)               (x+0x00000520)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x)               (x+0x00000524)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x)               (x+0x00000524)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x)               (x+0x00000528)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x)               (x+0x00000528)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x)               (x+0x0000052c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x)               (x+0x0000052c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x)               (x+0x00000530)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x)               (x+0x00000530)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x)               (x+0x00000534)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x)               (x+0x00000534)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x)               (x+0x00000538)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x)               (x+0x00000538)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x)               (x+0x0000053c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x)               (x+0x0000053c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x)               (x+0x00000540)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x)               (x+0x00000540)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x)               (x+0x00000544)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x)               (x+0x00000544)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x)               (x+0x00000548)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x)               (x+0x00000548)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x)               (x+0x0000054c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x)               (x+0x0000054c)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x)               (x+0x00000550)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x)               (x+0x00000550)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x)               (x+0x00000554)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x)               (x+0x00000554)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK                  0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 ////
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x)               (x+0x00000558)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x)               (x+0x00000558)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK                  0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT                           0
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val)           \
+	out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_0 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x)                    (x+0x0000055c)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x)                    (x+0x0000055c)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK                       0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT                                0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK  0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT         0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_1 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x)                    (x+0x00000560)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x)                    (x+0x00000560)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK                       0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT                                0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK  0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT         0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_2 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x)                    (x+0x00000564)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x)                    (x+0x00000564)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK                       0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT                                0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK  0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT         0x0
+
+//// Register REO_R0_AGING_NUM_QUEUES_IX_3 ////
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x)                    (x+0x00000568)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x)                    (x+0x00000568)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK                       0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT                                0
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK  0x0000ffff
+#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT         0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_0 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x)                     (x+0x0000056c)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x)                     (x+0x0000056c)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT                                 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT           0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_1 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x)                     (x+0x00000570)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x)                     (x+0x00000570)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT                                 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT           0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_2 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x)                     (x+0x00000574)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x)                     (x+0x00000574)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT                                 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT           0x0
+
+//// Register REO_R0_AGING_TIMESTAMP_IX_3 ////
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x)                     (x+0x00000578)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x)                     (x+0x00000578)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK                        0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT                                 0
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK    0xffffffff
+#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT           0x0
+
+//// Register REO_R0_AGING_CONTROL ////
+
+#define HWIO_REO_R0_AGING_CONTROL_ADDR(x)                            (x+0x0000057c)
+#define HWIO_REO_R0_AGING_CONTROL_PHYS(x)                            (x+0x0000057c)
+#define HWIO_REO_R0_AGING_CONTROL_RMSK                               0x0000001f
+#define HWIO_REO_R0_AGING_CONTROL_SHFT                                        0
+#define HWIO_REO_R0_AGING_CONTROL_IN(x)                              \
+	in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK)
+#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask)                       \
+	in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val)                        \
+	out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK      0x0000001f
+#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT             0x0
+
+//// Register REO_R0_HIGH_MEMORY_THRESHOLD ////
+
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x)                    (x+0x00000580)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x)                    (x+0x00000580)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK                       0xffffffff
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT                                0
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) 
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val)
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff
+#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_0 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x)                     (x+0x00000584)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x)                     (x+0x00000584)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK                        0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT                                 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK           0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT                  0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_1 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x)                     (x+0x00000588)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x)                     (x+0x00000588)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK                        0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT                                 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK           0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT                  0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_2 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x)                     (x+0x0000058c)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x)                     (x+0x0000058c)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK                        0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT                                 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK           0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT                  0x0
+
+//// Register REO_R0_AC_BUFFERS_USED_IX_3 ////
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x)                     (x+0x00000590)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x)                     (x+0x00000590)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK                        0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT                                 0
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK           0xffffffff
+#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT                  0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x)       (x+0x00000594)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x)       (x+0x00000594)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK          0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT                   0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x)       (x+0x00000598)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x)       (x+0x00000598)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK          0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT                   0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x)       (x+0x0000059c)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x)       (x+0x0000059c)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK          0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT                   0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask)  \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val)   \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x)      (x+0x000005a0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x)      (x+0x000005a0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK         0x03ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT                  0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)        \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val)  \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT        0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x)              (x+0x000005a4)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x)              (x+0x000005a4)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK                 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT                          0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK           0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT                  0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x)              (x+0x000005a8)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x)              (x+0x000005a8)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK                 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT                          0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK           0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT                  0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x)              (x+0x000005ac)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x)              (x+0x000005ac)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK                 0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT                          0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK           0x00ffffff
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT                  0x0
+
+//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL ////
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x)              (x+0x000005b0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x)              (x+0x000005b0)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK                 0x00000001
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT                          0
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)                \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val)          \
+	out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001
+#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x)            (x+0x000005b4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x)            (x+0x000005b4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK               0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x)            (x+0x000005b8)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x)            (x+0x000005b8)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK               0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x)            (x+0x000005bc)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x)            (x+0x000005bc)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK               0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x)            (x+0x000005c0)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x)            (x+0x000005c0)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK               0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x)            (x+0x000005c4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x)            (x+0x000005c4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK               0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x)            (x+0x000005c8)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x)            (x+0x000005c8)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK               0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x)            (x+0x000005cc)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x)            (x+0x000005cc)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK               0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x)            (x+0x000005d0)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x)            (x+0x000005d0)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK               0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT                        0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)              \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val)        \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT        0x0
+
+//// Register REO_R0_QUEUE_DESC_BLOCK_INFO ////
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x)                    (x+0x000005d4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x)                    (x+0x000005d4)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK                       0x0000001f
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT                                0
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) 
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val)
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK  0x00000010
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT         0x4
+
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK         0x0000000f
+#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT                0x0
+
+//// Register REO_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x)                        (x+0x000005d8)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x)                        (x+0x000005d8)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK                           0xffffffff
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT                                    0
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK                     0xffffffff
+#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT                            0x0
+
+//// Register REO_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x)                        (x+0x000005dc)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x)                        (x+0x000005dc)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK                           0x000000ff
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT                                    0
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK                     0x000000ff
+#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT                            0x0
+
+//// Register REO_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x)                       (x+0x000005e0)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x)                       (x+0x000005e0)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK                          0x00000fff
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT                                   0
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val)                   \
+	out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK         0x00000e00
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                0x9
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK         0x000001f0
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                0x4
+
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK         0x0000000f
+#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                0x0
+
+//// Register REO_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000005e4)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000005e4)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register REO_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x)                   (x+0x000005e8)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x)                   (x+0x000005e8)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK                      0x80000fff
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT                               0
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)                     \
+	in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask)              \
+	in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val)               \
+	out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK    0x80000000
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT          0x1f
+
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK   0x00000fff
+#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT          0x0
+
+//// Register REO_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x)                         (x+0x000005ec)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x)                         (x+0x000005ec)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK                            0x01010101
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT                                     0
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val)                     \
+	out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK        0x01000000
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT              0x18
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK         0x00010000
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT               0x10
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK         0x00000100
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                0x8
+
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK          0x00000001
+#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                 0x0
+
+//// Register REO_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x)                        (x+0x000005f0)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x)                        (x+0x000005f0)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK                           0x003f3f3f
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT                                    0
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK      0x003f0000
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT            0x10
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK           0x00003f00
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                  0x8
+
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK           0x0000003f
+#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                  0x0
+
+//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                  (x+0x000005f4)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                  (x+0x000005f4)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT                              0
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register REO_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x)                  (x+0x000005f8)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x)                  (x+0x000005f8)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT                              0
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register REO_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x)                     (x+0x000005fc)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x)                     (x+0x000005fc)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK                        0x007fffff
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT                                 0
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK   0x00700000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT         0x14
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK    0x000e0000
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT          0x11
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1
+
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK        0x00000001
+#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT               0x0
+
+//// Register REO_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x)                     (x+0x00000600)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x)                     (x+0x00000600)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK                        0xffff0001
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT                                 0
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK         0xffff0000
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT               0x10
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK       0x00000001
+#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT              0x0
+
+//// Register REO_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x)                      (x+0x00000604)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x)                      (x+0x00000604)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK                         0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT                                  0
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK         0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                0x0
+
+//// Register REO_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x)                    (x+0x00000608)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x)                    (x+0x00000608)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK                       0xffffffff
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT                                0
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)                      \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask)               \
+	in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val)                \
+	out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK     0xffff0000
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT           0x10
+
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK    0x0000ffff
+#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT           0x0
+
+//// Register REO_R0_CACHE_CTL_CONFIG ////
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x)                         (x+0x0000060c)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x)                         (x+0x0000060c)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK                            0x003f7fff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT                                     0
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) 
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val)                     \
+	out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK          0x00200000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT                0x15
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK           0x00100000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT                 0x14
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK             0x00080000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT                   0x13
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK              0x00040000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT                    0x12
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK        0x00020000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT              0x11
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK    0x00010000
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT          0x10
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK      0x00007f00
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT             0x8
+
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK         0x000000ff
+#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT                0x0
+
+//// Register REO_R0_CACHE_CTL_CONTROL ////
+
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x)                        (x+0x00000610)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x)                        (x+0x00000610)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK                           0x00000001
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT                                    0
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val)                    \
+	out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val)
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK               0x00000001
+#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT                      0x0
+
+//// Register REO_R0_CLK_GATE_CTRL ////
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x)                            (x+0x00000614)
+#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x)                            (x+0x00000614)
+#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK                               0x0007ffff
+#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT                                        0
+#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x)                              \
+	in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK)
+#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask)                       \
+	in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val)                        \
+	out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val)
+#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK                     0x00040000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT                           0x12
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK                     0x00020000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT                           0x11
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK                     0x00010000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT                           0x10
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK                     0x00008000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT                            0xf
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK                     0x00004000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT                            0xe
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK                     0x00002000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT                            0xd
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_BMSK                     0x00001000
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_1_SHFT                            0xc
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_BMSK                     0x00000800
+#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_0_SHFT                            0xb
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK              0x00000400
+#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT                     0xa
+
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK           0x000003ff
+#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT                  0x0
+
+//// Register REO_R0_EVENTMASK_IX_0 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x)                           (x+0x00000618)
+#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x)                           (x+0x00000618)
+#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK                              0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT                                       0
+#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK                         0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT                                0x0
+
+//// Register REO_R0_EVENTMASK_IX_1 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x)                           (x+0x0000061c)
+#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x)                           (x+0x0000061c)
+#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK                              0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT                                       0
+#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK                         0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT                                0x0
+
+//// Register REO_R0_EVENTMASK_IX_2 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x)                           (x+0x00000620)
+#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x)                           (x+0x00000620)
+#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK                              0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT                                       0
+#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK                         0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT                                0x0
+
+//// Register REO_R0_EVENTMASK_IX_3 ////
+
+#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x)                           (x+0x00000624)
+#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x)                           (x+0x00000624)
+#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK                              0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT                                       0
+#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK)
+#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val)                       \
+	out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK                         0xffffffff
+#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT                                0x0
+
+//// Register REO_R1_MISC_DEBUG_CTRL ////
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x)                          (x+0x00002000)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x)                          (x+0x00002000)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK                             0x3fffffff
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT                                      0
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val)                      \
+	out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK      0x3ff00000
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT            0x14
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK        0x000ffc00
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT               0xa
+
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK       0x000003ff
+#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT              0x0
+
+//// Register REO_R1_MISC_PERF_DEBUG_CTRL ////
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x)                     (x+0x00002004)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x)                     (x+0x00002004)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK                        0x00ffffff
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT                                 0
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val)                 \
+	out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT        0xc
+
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK  0x00000fff
+#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT         0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x)                  (x+0x00002008)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x)                  (x+0x00002008)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK                     0x000003ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT                              0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK  0x00000200
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT         0x9
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK      0x00000100
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT             0x8
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK    0x00000080
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT           0x7
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK       0x0000007f
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT              0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x)                (x+0x0000200c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x)                (x+0x0000200c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK                   0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT                            0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val)            \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK   0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT          0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x)               (x+0x00002010)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x)               (x+0x00002010)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK                  0x00ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT                           0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)                 \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask)          \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val)           \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT        0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x)            (x+0x00002014)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x)            (x+0x00002014)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK               0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT                        0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)              \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask)       \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val)        \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK     0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT            0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x)           (x+0x00002018)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x)           (x+0x00002018)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK              0x03ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT                       0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)             \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask)      \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val)       \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK    0x03ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT           0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_STM ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x)                      (x+0x0000201c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x)                      (x+0x0000201c)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK                         0x01ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT                                  0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val)                  \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK                   0x01ffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT                          0x0
+
+//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST ////
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x)                (x+0x00002020)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x)                (x+0x00002020)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK                   0xffffffff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT                            0
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)                  \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask)           \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val)            \
+	out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_BMSK         0xff000000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_HEAD_FLAG_SHFT               0x18
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_BMSK         0x00ff0000
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_TAIL_FLAG_SHFT               0x10
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK          0x0000ff00
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT                 0x8
+
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK          0x000000ff
+#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT                 0x0
+
+//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x)              (x+0x00002024)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x)              (x+0x00002024)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK                 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT                          0
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)                \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask)         \
+	in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val)          \
+	out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register REO_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00002028)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00002028)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
+#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT                                    0
+#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)                          \
+	in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask)                   \
+	in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val)                    \
+	out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK    0x00000001
+#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT           0x0
+
+//// Register REO_R1_SM_ALL_IDLE ////
+
+#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x)                              (x+0x0000202c)
+#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x)                              (x+0x0000202c)
+#define HWIO_REO_R1_SM_ALL_IDLE_RMSK                                 0x00000007
+#define HWIO_REO_R1_SM_ALL_IDLE_SHFT                                          0
+#define HWIO_REO_R1_SM_ALL_IDLE_IN(x)                                \
+	in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK)
+#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask)                         \
+	in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val)                          \
+	out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val)
+#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK    0x00000004
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT           0x2
+
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK                     0x00000002
+#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT                            0x1
+
+#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK              0x00000001
+#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT                     0x0
+
+//// Register REO_R1_TESTBUS_CTRL ////
+
+#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x)                             (x+0x00002030)
+#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x)                             (x+0x00002030)
+#define HWIO_REO_R1_TESTBUS_CTRL_RMSK                                0x0000007f
+#define HWIO_REO_R1_TESTBUS_CTRL_SHFT                                         0
+#define HWIO_REO_R1_TESTBUS_CTRL_IN(x)                               \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask)                        \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) 
+#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val)                         \
+	out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK                 0x0000007f
+#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT                        0x0
+
+//// Register REO_R1_TESTBUS_LOWER ////
+
+#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x)                            (x+0x00002034)
+#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x)                            (x+0x00002034)
+#define HWIO_REO_R1_TESTBUS_LOWER_RMSK                               0xffffffff
+#define HWIO_REO_R1_TESTBUS_LOWER_SHFT                                        0
+#define HWIO_REO_R1_TESTBUS_LOWER_IN(x)                              \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK)
+#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask)                       \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val)                        \
+	out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK                         0xffffffff
+#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT                                0x0
+
+//// Register REO_R1_TESTBUS_HIGHER ////
+
+#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x)                           (x+0x00002038)
+#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x)                           (x+0x00002038)
+#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK                              0x000000ff
+#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT                                       0
+#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK)
+#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) 
+#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val)
+#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK                        0x000000ff
+#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT                               0x0
+
+//// Register REO_R1_SM_STATES_IX_0 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x0000203c)
+#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x0000203c)
+#define HWIO_REO_R1_SM_STATES_IX_0_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_0_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_1 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00002040)
+#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00002040)
+#define HWIO_REO_R1_SM_STATES_IX_1_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_1_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_2 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x)                           (x+0x00002044)
+#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x)                           (x+0x00002044)
+#define HWIO_REO_R1_SM_STATES_IX_2_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_2_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_2_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_3 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x)                           (x+0x00002048)
+#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x)                           (x+0x00002048)
+#define HWIO_REO_R1_SM_STATES_IX_3_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_3_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_3_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_4 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x)                           (x+0x0000204c)
+#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x)                           (x+0x0000204c)
+#define HWIO_REO_R1_SM_STATES_IX_4_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_4_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_4_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_5 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x)                           (x+0x00002050)
+#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x)                           (x+0x00002050)
+#define HWIO_REO_R1_SM_STATES_IX_5_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_5_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_5_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_SM_STATES_IX_6 ////
+
+#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x)                           (x+0x00002054)
+#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x)                           (x+0x00002054)
+#define HWIO_REO_R1_SM_STATES_IX_6_RMSK                              0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_6_SHFT                                       0
+#define HWIO_REO_R1_SM_STATES_IX_6_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK)
+#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) 
+#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val)                       \
+	out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val)
+#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK                     0xffffffff
+#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT                            0x0
+
+//// Register REO_R1_IDLE_STATES_IX_0 ////
+
+#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x)                         (x+0x00002058)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x)                         (x+0x00002058)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK                            0xffffffff
+#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT                                     0
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)                           \
+	in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask)                    \
+	in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val)                     \
+	out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val)
+#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK                 0xffffffff
+#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT                        0x0
+
+//// Register REO_R1_INVALID_APB_ACCESS ////
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x)                       (x+0x0000205c)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x)                       (x+0x0000205c)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK                          0x0007ffff
+#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT                                   0
+#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) 
+#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val)                   \
+	out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val)
+#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK                 0x00060000
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT                       0x11
+
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK                 0x0001ffff
+#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO0_RING_HP ////
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x)                       (x+0x00003000)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x)                       (x+0x00003000)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO0_RING_TP ////
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x)                       (x+0x00003004)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x)                       (x+0x00003004)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO1_RING_HP ////
+
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x)                       (x+0x00003008)
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_PHYS(x)                       (x+0x00003008)
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_HP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO1_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO1_RING_TP ////
+
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x)                       (x+0x0000300c)
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_PHYS(x)                       (x+0x0000300c)
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO1_RING_TP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO1_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO2_RING_HP ////
+
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x)                       (x+0x00003010)
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_PHYS(x)                       (x+0x00003010)
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_HP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO2_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register REO_R2_RXDMA2REO2_RING_TP ////
+
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x)                       (x+0x00003014)
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_PHYS(x)                       (x+0x00003014)
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_SHFT                                   0
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO2_RING_TP_RMSK)
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_RXDMA2REO2_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register REO_R2_WBM2REO_LINK_RING_HP ////
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x)                     (x+0x00003018)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x)                     (x+0x00003018)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK                        0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT                                 0
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val)                 \
+	out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK               0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT                      0x0
+
+//// Register REO_R2_WBM2REO_LINK_RING_TP ////
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x)                     (x+0x0000301c)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x)                     (x+0x0000301c)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK                        0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT                                 0
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)                       \
+	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask)                \
+	in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val)                 \
+	out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK               0x0000ffff
+#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT                      0x0
+
+//// Register REO_R2_REO_CMD_RING_HP ////
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x)                          (x+0x00003020)
+#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x)                          (x+0x00003020)
+#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO_CMD_RING_TP ////
+
+#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x)                          (x+0x00003024)
+#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x)                          (x+0x00003024)
+#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_SW2REO_RING_HP ////
+
+#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x)                           (x+0x00003028)
+#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x)                           (x+0x00003028)
+#define HWIO_REO_R2_SW2REO_RING_HP_RMSK                              0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_HP_SHFT                                       0
+#define HWIO_REO_R2_SW2REO_RING_HP_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK)
+#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val)                       \
+	out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK                     0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT                            0x0
+
+//// Register REO_R2_SW2REO_RING_TP ////
+
+#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x)                           (x+0x0000302c)
+#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x)                           (x+0x0000302c)
+#define HWIO_REO_R2_SW2REO_RING_TP_RMSK                              0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_TP_SHFT                                       0
+#define HWIO_REO_R2_SW2REO_RING_TP_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK)
+#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val)                       \
+	out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK                     0x0000ffff
+#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT                            0x0
+
+//// Register REO_R2_REO2SW1_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x)                          (x+0x00003030)
+#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x)                          (x+0x00003030)
+#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW1_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x)                          (x+0x00003034)
+#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x)                          (x+0x00003034)
+#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW2_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x)                          (x+0x00003038)
+#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x)                          (x+0x00003038)
+#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW2_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x)                          (x+0x0000303c)
+#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x)                          (x+0x0000303c)
+#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW3_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x)                          (x+0x00003040)
+#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x)                          (x+0x00003040)
+#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW3_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x)                          (x+0x00003044)
+#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x)                          (x+0x00003044)
+#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW4_RING_HP ////
+
+#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x)                          (x+0x00003048)
+#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x)                          (x+0x00003048)
+#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2SW4_RING_TP ////
+
+#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x)                          (x+0x0000304c)
+#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x)                          (x+0x0000304c)
+#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2TCL_RING_HP ////
+
+#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x)                          (x+0x00003050)
+#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x)                          (x+0x00003050)
+#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT                                      0
+#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2TCL_RING_TP ////
+
+#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x)                          (x+0x00003054)
+#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x)                          (x+0x00003054)
+#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK                             0x0000ffff
+#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT                                      0
+#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register REO_R2_REO2FW_RING_HP ////
+
+#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x)                           (x+0x00003058)
+#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x)                           (x+0x00003058)
+#define HWIO_REO_R2_REO2FW_RING_HP_RMSK                              0x0000ffff
+#define HWIO_REO_R2_REO2FW_RING_HP_SHFT                                       0
+#define HWIO_REO_R2_REO2FW_RING_HP_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK)
+#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val)                       \
+	out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK                     0x0000ffff
+#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT                            0x0
+
+//// Register REO_R2_REO2FW_RING_TP ////
+
+#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x)                           (x+0x0000305c)
+#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x)                           (x+0x0000305c)
+#define HWIO_REO_R2_REO2FW_RING_TP_RMSK                              0x0000ffff
+#define HWIO_REO_R2_REO2FW_RING_TP_SHFT                                       0
+#define HWIO_REO_R2_REO2FW_RING_TP_IN(x)                             \
+	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK)
+#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val)                       \
+	out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK                     0x0000ffff
+#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT                            0x0
+
+//// Register REO_R2_REO_RELEASE_RING_HP ////
+
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x)                      (x+0x00003060)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x)                      (x+0x00003060)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK                         0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT                                  0
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register REO_R2_REO_RELEASE_RING_TP ////
+
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x)                      (x+0x00003064)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x)                      (x+0x00003064)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK                         0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT                                  0
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register REO_R2_REO_STATUS_RING_HP ////
+
+#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x)                       (x+0x00003068)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x)                       (x+0x00003068)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT                                   0
+#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val)
+#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register REO_R2_REO_STATUS_RING_TP ////
+
+#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x)                       (x+0x0000306c)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x)                       (x+0x0000306c)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK                          0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT                                   0
+#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) 
+#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val)
+#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT                        0x0
+
+
+#endif
+

hw/qca6290/v1/rx_attention.h

@@ -0,0 +1,1168 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_ATTENTION_H_
+#define _RX_ATTENTION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+//	1	first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31]
+//	2	flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_ATTENTION 3
+
+struct rx_attention {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
+                      sw_frame_group_id               :  7, //[8:2]
+                      reserved_0                      :  7, //[15:9]
+                      phy_ppdu_id                     : 16; //[31:16]
+             uint32_t first_mpdu                      :  1, //[0]
+                      reserved_1a                     :  1, //[1]
+                      mcast_bcast                     :  1, //[2]
+                      ast_index_not_found             :  1, //[3]
+                      ast_index_timeout               :  1, //[4]
+                      power_mgmt                      :  1, //[5]
+                      non_qos                         :  1, //[6]
+                      null_data                       :  1, //[7]
+                      mgmt_type                       :  1, //[8]
+                      ctrl_type                       :  1, //[9]
+                      more_data                       :  1, //[10]
+                      eosp                            :  1, //[11]
+                      a_msdu_error                    :  1, //[12]
+                      fragment_flag                   :  1, //[13]
+                      order                           :  1, //[14]
+                      cce_match                       :  1, //[15]
+                      overflow_err                    :  1, //[16]
+                      msdu_length_err                 :  1, //[17]
+                      tcp_udp_chksum_fail             :  1, //[18]
+                      ip_chksum_fail                  :  1, //[19]
+                      sa_idx_invalid                  :  1, //[20]
+                      da_idx_invalid                  :  1, //[21]
+                      reserved_1b                     :  1, //[22]
+                      rx_in_tx_decrypt_byp            :  1, //[23]
+                      encrypt_required                :  1, //[24]
+                      directed                        :  1, //[25]
+                      buffer_fragment                 :  1, //[26]
+                      mpdu_length_err                 :  1, //[27]
+                      tkip_mic_err                    :  1, //[28]
+                      decrypt_err                     :  1, //[29]
+                      unencrypted_frame_err           :  1, //[30]
+                      fcs_err                         :  1; //[31]
+             uint32_t flow_idx_timeout                :  1, //[0]
+                      flow_idx_invalid                :  1, //[1]
+                      wifi_parser_error               :  1, //[2]
+                      amsdu_parser_error              :  1, //[3]
+                      sa_idx_timeout                  :  1, //[4]
+                      da_idx_timeout                  :  1, //[5]
+                      msdu_limit_error                :  1, //[6]
+                      da_is_valid                     :  1, //[7]
+                      da_is_mcbc                      :  1, //[8]
+                      sa_is_valid                     :  1, //[9]
+                      decrypt_status_code             :  3, //[12:10]
+                      rx_bitmap_not_updated           :  1, //[13]
+                      reserved_2                      : 17, //[30:14]
+                      msdu_done                       :  1; //[31]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+
+sw_frame_group_id
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+
+reserved_0
+			
+			<legal 0>
+
+phy_ppdu_id
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+
+first_mpdu
+			
+			Indicates the first MSDU of the PPDU.  If both
+			first_mpdu and last_mpdu are set in the MSDU then this is a
+			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
+			in an A-MPDU shall have both first_mpdu and last_mpdu bits
+			set to 0.  The PPDU start status will only be valid when
+			this bit is set.
+
+reserved_1a
+			
+			<legal 0>
+
+mcast_bcast
+			
+			Multicast / broadcast indicator.  Only set when the MAC
+			address 1 bit 0 is set indicating mcast/bcast and the BSSID
+			matches one of the 4 BSSID registers. Only set when
+			first_msdu is set.
+
+ast_index_not_found
+			
+			Only valid when first_msdu is set.
+			
+			
+			
+			Indicates no AST matching entries within the the max
+			search count.  
+
+ast_index_timeout
+			
+			Only valid when first_msdu is set.
+			
+			
+			
+			Indicates an unsuccessful search in the address seach
+			table due to timeout.  
+
+power_mgmt
+			
+			Power management bit set in the 802.11 header.  Only set
+			when first_msdu is set.
+
+non_qos
+			
+			Set if packet is not a non-QoS data frame.  Only set
+			when first_msdu is set.
+
+null_data
+			
+			Set if frame type indicates either null data or QoS null
+			data format.  Only set when first_msdu is set.
+
+mgmt_type
+			
+			Set if packet is a management packet.  Only set when
+			first_msdu is set.
+
+ctrl_type
+			
+			Set if packet is a control packet.  Only set when
+			first_msdu is set.
+
+more_data
+			
+			Set if more bit in frame control is set.  Only set when
+			first_msdu is set.
+
+eosp
+			
+			Set if the EOSP (end of service period) bit in the QoS
+			control field is set.  Only set when first_msdu is set.
+
+a_msdu_error
+			
+			Set if number of MSDUs in A-MSDU is above a threshold or
+			if the size of the MSDU is invalid.  This receive buffer
+			will contain all of the remainder of the MSDUs in this MPDU
+			without decapsulation.
+
+fragment_flag
+			
+			Indicates that this is an 802.11 fragment frame.  This
+			is set when either the more_frag bit is set in the frame
+			control or the fragment number is not zero.  Only set when
+			first_msdu is set.
+
+order
+			
+			Set if the order bit in the frame control is set.  Only
+			set when first_msdu is set.
+
+cce_match
+			
+			Indicates that this status has a corresponding MSDU that
+			requires FW processing.  The OLE will have classification
+			ring mask registers which will indicate the ring(s) for
+			packets and descriptors which need FW attention.
+
+overflow_err
+			
+			RXPCU Receive FIFO ran out of space to receive the full
+			MPDU. Therefor this MPDU is terminated early and is thus
+			corrupted.  
+			
+			
+			
+			This MPDU will not be ACKed.
+			
+			RXPCU might still be able to correctly receive the
+			following MPDUs in the PPDU if enough fifo space became
+			available in time
+
+msdu_length_err
+			
+			Indicates that the MSDU length from the 802.3
+			encapsulated length field extends beyond the MPDU boundary
+			or if the length is less than 14 bytes.
+			
+			Merged with original other_msdu_err: Indicates that the
+			MSDU threshold was exceeded and thus all the rest of the
+			MSDUs will not be scattered and will not be decasulated but
+			will be DMA'ed in RAW format as a single MSDU buffer
+
+tcp_udp_chksum_fail
+			
+			Indicates that the computed checksum (tcp_udp_chksum)
+			did not match the checksum in the TCP/UDP header.
+
+ip_chksum_fail
+			
+			Indicates that the computed checksum did not match the
+			checksum in the IP header.
+
+sa_idx_invalid
+			
+			Indicates no matching entry was found in the address
+			search table for the source MAC address.
+
+da_idx_invalid
+			
+			Indicates no matching entry was found in the address
+			search table for the destination MAC address.
+
+reserved_1b
+			
+
+rx_in_tx_decrypt_byp
+			
+			Indicates that RX packet is not decrypted as Crypto is
+			busy with TX packet processing.
+
+encrypt_required
+			
+			Indicates that this data type frame is not encrypted
+			even if the policy for this MPDU requires encryption as
+			indicated in the peer entry key type.
+
+directed
+			
+			MPDU is a directed packet which means that the RA
+			matched our STA addresses.  In proxySTA it means that the TA
+			matched an entry in our address search table with the
+			corresponding no_ack bit is the address search entry
+			cleared.
+
+buffer_fragment
+			
+			Indicates that at least one of the rx buffers has been
+			fragmented.  If set the FW should look at the rx_frag_info
+			descriptor described below.
+
+mpdu_length_err
+			
+			Indicates that the MPDU was pre-maturely terminated
+			resulting in a truncated MPDU.  Don't trust the MPDU length
+			field.
+
+tkip_mic_err
+			
+			Indicates that the MPDU Michael integrity check failed
+
+decrypt_err
+			
+			Indicates that the MPDU decrypt integrity check failed
+
+unencrypted_frame_err
+			
+			Copied here by RX OLE from the RX_MPDU_END TLV
+
+fcs_err
+			
+			Indicates that the MPDU FCS check failed
+
+flow_idx_timeout
+			
+			Indicates an unsuccessful flow search due to the
+			expiring of the search timer.
+			
+			<legal all>
+
+flow_idx_invalid
+			
+			flow id is not valid
+			
+			<legal all>
+
+wifi_parser_error
+			
+			TODO: add details to the description
+			
+			<legal all>
+
+amsdu_parser_error
+			
+			A-MSDU could not be properly de-agregated.
+			
+			<legal all>
+
+sa_idx_timeout
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer.
+
+da_idx_timeout
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer.
+
+msdu_limit_error
+			
+			Indicates that the MSDU threshold was exceeded and thus
+			all the rest of the MSDUs will not be scattered and will not
+			be decasulated but will be DMA'ed in RAW format as a single
+			MSDU buffer
+
+da_is_valid
+			
+			Indicates that OLE found a valid DA entry
+
+da_is_mcbc
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address.
+
+sa_is_valid
+			
+			Indicates that OLE found a valid SA entry
+
+decrypt_status_code
+			
+			Field provides insight into the decryption performed
+			
+			
+			
+			<enum 0 decrypt_ok> Frame had protection enabled and
+			decrypted properly 
+			
+			<enum 1 decrypt_unprotected_frame > Frame is unprotected
+			and hence bypassed 
+			
+			<enum 2 decrypt_data_err > Frame has protection enabled
+			and could not be properly decrypted due to MIC/ICV mismatch
+			etc. 
+			
+			<enum 3 decrypt_key_invalid > Frame has protection
+			enabled but the key that was required to decrypt this frame
+			was not valid 
+			
+			<enum 4 decrypt_peer_entry_invalid > Frame has
+			protection enabled but the key that was required to decrypt
+			this frame was not valid
+			
+			<enum 5 decrypt_other > Reserved for other indications
+			
+			
+			
+			<legal 0 - 5>
+
+rx_bitmap_not_updated
+			
+			Frame is received, but RXPCU could not update the
+			receive bitmap due to (temporary) fifo contraints.
+			
+			<legal all>
+
+reserved_2
+			
+			<legal 0>
+
+msdu_done
+			
+			If set indicates that the RX packet data, RX header
+			data, RX PPDU start descriptor, RX MPDU start/end
+			descriptor, RX MSDU start/end descriptors and RX Attention
+			descriptor are all valid.  This bit must be in the last
+			octet of the descriptor.
+*/
+
+
+/* Description		RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+*/
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
+#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
+
+/* Description		RX_ATTENTION_0_SW_FRAME_GROUP_ID
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+*/
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB                         2
+#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
+
+/* Description		RX_ATTENTION_0_RESERVED_0
+			
+			<legal 0>
+*/
+#define RX_ATTENTION_0_RESERVED_0_OFFSET                             0x00000000
+#define RX_ATTENTION_0_RESERVED_0_LSB                                9
+#define RX_ATTENTION_0_RESERVED_0_MASK                               0x0000fe00
+
+/* Description		RX_ATTENTION_0_PHY_PPDU_ID
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+*/
+#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET                            0x00000000
+#define RX_ATTENTION_0_PHY_PPDU_ID_LSB                               16
+#define RX_ATTENTION_0_PHY_PPDU_ID_MASK                              0xffff0000
+
+/* Description		RX_ATTENTION_1_FIRST_MPDU
+			
+			Indicates the first MSDU of the PPDU.  If both
+			first_mpdu and last_mpdu are set in the MSDU then this is a
+			not an A-MPDU frame but a stand alone MPDU.  Interior MPDU
+			in an A-MPDU shall have both first_mpdu and last_mpdu bits
+			set to 0.  The PPDU start status will only be valid when
+			this bit is set.
+*/
+#define RX_ATTENTION_1_FIRST_MPDU_OFFSET                             0x00000004
+#define RX_ATTENTION_1_FIRST_MPDU_LSB                                0
+#define RX_ATTENTION_1_FIRST_MPDU_MASK                               0x00000001
+
+/* Description		RX_ATTENTION_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define RX_ATTENTION_1_RESERVED_1A_OFFSET                            0x00000004
+#define RX_ATTENTION_1_RESERVED_1A_LSB                               1
+#define RX_ATTENTION_1_RESERVED_1A_MASK                              0x00000002
+
+/* Description		RX_ATTENTION_1_MCAST_BCAST
+			
+			Multicast / broadcast indicator.  Only set when the MAC
+			address 1 bit 0 is set indicating mcast/bcast and the BSSID
+			matches one of the 4 BSSID registers. Only set when
+			first_msdu is set.
+*/
+#define RX_ATTENTION_1_MCAST_BCAST_OFFSET                            0x00000004
+#define RX_ATTENTION_1_MCAST_BCAST_LSB                               2
+#define RX_ATTENTION_1_MCAST_BCAST_MASK                              0x00000004
+
+/* Description		RX_ATTENTION_1_AST_INDEX_NOT_FOUND
+			
+			Only valid when first_msdu is set.
+			
+			
+			
+			Indicates no AST matching entries within the the max
+			search count.  
+*/
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET                    0x00000004
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB                       3
+#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK                      0x00000008
+
+/* Description		RX_ATTENTION_1_AST_INDEX_TIMEOUT
+			
+			Only valid when first_msdu is set.
+			
+			
+			
+			Indicates an unsuccessful search in the address seach
+			table due to timeout.  
+*/
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET                      0x00000004
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB                         4
+#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK                        0x00000010
+
+/* Description		RX_ATTENTION_1_POWER_MGMT
+			
+			Power management bit set in the 802.11 header.  Only set
+			when first_msdu is set.
+*/
+#define RX_ATTENTION_1_POWER_MGMT_OFFSET                             0x00000004
+#define RX_ATTENTION_1_POWER_MGMT_LSB                                5
+#define RX_ATTENTION_1_POWER_MGMT_MASK                               0x00000020
+
+/* Description		RX_ATTENTION_1_NON_QOS
+			
+			Set if packet is not a non-QoS data frame.  Only set
+			when first_msdu is set.
+*/
+#define RX_ATTENTION_1_NON_QOS_OFFSET                                0x00000004
+#define RX_ATTENTION_1_NON_QOS_LSB                                   6
+#define RX_ATTENTION_1_NON_QOS_MASK                                  0x00000040
+
+/* Description		RX_ATTENTION_1_NULL_DATA
+			
+			Set if frame type indicates either null data or QoS null
+			data format.  Only set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_NULL_DATA_OFFSET                              0x00000004
+#define RX_ATTENTION_1_NULL_DATA_LSB                                 7
+#define RX_ATTENTION_1_NULL_DATA_MASK                                0x00000080
+
+/* Description		RX_ATTENTION_1_MGMT_TYPE
+			
+			Set if packet is a management packet.  Only set when
+			first_msdu is set.
+*/
+#define RX_ATTENTION_1_MGMT_TYPE_OFFSET                              0x00000004
+#define RX_ATTENTION_1_MGMT_TYPE_LSB                                 8
+#define RX_ATTENTION_1_MGMT_TYPE_MASK                                0x00000100
+
+/* Description		RX_ATTENTION_1_CTRL_TYPE
+			
+			Set if packet is a control packet.  Only set when
+			first_msdu is set.
+*/
+#define RX_ATTENTION_1_CTRL_TYPE_OFFSET                              0x00000004
+#define RX_ATTENTION_1_CTRL_TYPE_LSB                                 9
+#define RX_ATTENTION_1_CTRL_TYPE_MASK                                0x00000200
+
+/* Description		RX_ATTENTION_1_MORE_DATA
+			
+			Set if more bit in frame control is set.  Only set when
+			first_msdu is set.
+*/
+#define RX_ATTENTION_1_MORE_DATA_OFFSET                              0x00000004
+#define RX_ATTENTION_1_MORE_DATA_LSB                                 10
+#define RX_ATTENTION_1_MORE_DATA_MASK                                0x00000400
+
+/* Description		RX_ATTENTION_1_EOSP
+			
+			Set if the EOSP (end of service period) bit in the QoS
+			control field is set.  Only set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_EOSP_OFFSET                                   0x00000004
+#define RX_ATTENTION_1_EOSP_LSB                                      11
+#define RX_ATTENTION_1_EOSP_MASK                                     0x00000800
+
+/* Description		RX_ATTENTION_1_A_MSDU_ERROR
+			
+			Set if number of MSDUs in A-MSDU is above a threshold or
+			if the size of the MSDU is invalid.  This receive buffer
+			will contain all of the remainder of the MSDUs in this MPDU
+			without decapsulation.
+*/
+#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_A_MSDU_ERROR_LSB                              12
+#define RX_ATTENTION_1_A_MSDU_ERROR_MASK                             0x00001000
+
+/* Description		RX_ATTENTION_1_FRAGMENT_FLAG
+			
+			Indicates that this is an 802.11 fragment frame.  This
+			is set when either the more_frag bit is set in the frame
+			control or the fragment number is not zero.  Only set when
+			first_msdu is set.
+*/
+#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET                          0x00000004
+#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB                             13
+#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK                            0x00002000
+
+/* Description		RX_ATTENTION_1_ORDER
+			
+			Set if the order bit in the frame control is set.  Only
+			set when first_msdu is set.
+*/
+#define RX_ATTENTION_1_ORDER_OFFSET                                  0x00000004
+#define RX_ATTENTION_1_ORDER_LSB                                     14
+#define RX_ATTENTION_1_ORDER_MASK                                    0x00004000
+
+/* Description		RX_ATTENTION_1_CCE_MATCH
+			
+			Indicates that this status has a corresponding MSDU that
+			requires FW processing.  The OLE will have classification
+			ring mask registers which will indicate the ring(s) for
+			packets and descriptors which need FW attention.
+*/
+#define RX_ATTENTION_1_CCE_MATCH_OFFSET                              0x00000004
+#define RX_ATTENTION_1_CCE_MATCH_LSB                                 15
+#define RX_ATTENTION_1_CCE_MATCH_MASK                                0x00008000
+
+/* Description		RX_ATTENTION_1_OVERFLOW_ERR
+			
+			RXPCU Receive FIFO ran out of space to receive the full
+			MPDU. Therefor this MPDU is terminated early and is thus
+			corrupted.  
+			
+			
+			
+			This MPDU will not be ACKed.
+			
+			RXPCU might still be able to correctly receive the
+			following MPDUs in the PPDU if enough fifo space became
+			available in time
+*/
+#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_OVERFLOW_ERR_LSB                              16
+#define RX_ATTENTION_1_OVERFLOW_ERR_MASK                             0x00010000
+
+/* Description		RX_ATTENTION_1_MSDU_LENGTH_ERR
+			
+			Indicates that the MSDU length from the 802.3
+			encapsulated length field extends beyond the MPDU boundary
+			or if the length is less than 14 bytes.
+			
+			Merged with original other_msdu_err: Indicates that the
+			MSDU threshold was exceeded and thus all the rest of the
+			MSDUs will not be scattered and will not be decasulated but
+			will be DMA'ed in RAW format as a single MSDU buffer
+*/
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET                        0x00000004
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB                           17
+#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK                          0x00020000
+
+/* Description		RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL
+			
+			Indicates that the computed checksum (tcp_udp_chksum)
+			did not match the checksum in the TCP/UDP header.
+*/
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET                    0x00000004
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB                       18
+#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK                      0x00040000
+
+/* Description		RX_ATTENTION_1_IP_CHKSUM_FAIL
+			
+			Indicates that the computed checksum did not match the
+			checksum in the IP header.
+*/
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET                         0x00000004
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB                            19
+#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK                           0x00080000
+
+/* Description		RX_ATTENTION_1_SA_IDX_INVALID
+			
+			Indicates no matching entry was found in the address
+			search table for the source MAC address.
+*/
+#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET                         0x00000004
+#define RX_ATTENTION_1_SA_IDX_INVALID_LSB                            20
+#define RX_ATTENTION_1_SA_IDX_INVALID_MASK                           0x00100000
+
+/* Description		RX_ATTENTION_1_DA_IDX_INVALID
+			
+			Indicates no matching entry was found in the address
+			search table for the destination MAC address.
+*/
+#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET                         0x00000004
+#define RX_ATTENTION_1_DA_IDX_INVALID_LSB                            21
+#define RX_ATTENTION_1_DA_IDX_INVALID_MASK                           0x00200000
+
+/* Description		RX_ATTENTION_1_RESERVED_1B
+			
+*/
+#define RX_ATTENTION_1_RESERVED_1B_OFFSET                            0x00000004
+#define RX_ATTENTION_1_RESERVED_1B_LSB                               22
+#define RX_ATTENTION_1_RESERVED_1B_MASK                              0x00400000
+
+/* Description		RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP
+			
+			Indicates that RX packet is not decrypted as Crypto is
+			busy with TX packet processing.
+*/
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET                   0x00000004
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB                      23
+#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK                     0x00800000
+
+/* Description		RX_ATTENTION_1_ENCRYPT_REQUIRED
+			
+			Indicates that this data type frame is not encrypted
+			even if the policy for this MPDU requires encryption as
+			indicated in the peer entry key type.
+*/
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET                       0x00000004
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB                          24
+#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK                         0x01000000
+
+/* Description		RX_ATTENTION_1_DIRECTED
+			
+			MPDU is a directed packet which means that the RA
+			matched our STA addresses.  In proxySTA it means that the TA
+			matched an entry in our address search table with the
+			corresponding no_ack bit is the address search entry
+			cleared.
+*/
+#define RX_ATTENTION_1_DIRECTED_OFFSET                               0x00000004
+#define RX_ATTENTION_1_DIRECTED_LSB                                  25
+#define RX_ATTENTION_1_DIRECTED_MASK                                 0x02000000
+
+/* Description		RX_ATTENTION_1_BUFFER_FRAGMENT
+			
+			Indicates that at least one of the rx buffers has been
+			fragmented.  If set the FW should look at the rx_frag_info
+			descriptor described below.
+*/
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET                        0x00000004
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB                           26
+#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK                          0x04000000
+
+/* Description		RX_ATTENTION_1_MPDU_LENGTH_ERR
+			
+			Indicates that the MPDU was pre-maturely terminated
+			resulting in a truncated MPDU.  Don't trust the MPDU length
+			field.
+*/
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET                        0x00000004
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB                           27
+#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK                          0x08000000
+
+/* Description		RX_ATTENTION_1_TKIP_MIC_ERR
+			
+			Indicates that the MPDU Michael integrity check failed
+*/
+#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET                           0x00000004
+#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB                              28
+#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK                             0x10000000
+
+/* Description		RX_ATTENTION_1_DECRYPT_ERR
+			
+			Indicates that the MPDU decrypt integrity check failed
+*/
+#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET                            0x00000004
+#define RX_ATTENTION_1_DECRYPT_ERR_LSB                               29
+#define RX_ATTENTION_1_DECRYPT_ERR_MASK                              0x20000000
+
+/* Description		RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR
+			
+			Copied here by RX OLE from the RX_MPDU_END TLV
+*/
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET                  0x00000004
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB                     30
+#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK                    0x40000000
+
+/* Description		RX_ATTENTION_1_FCS_ERR
+			
+			Indicates that the MPDU FCS check failed
+*/
+#define RX_ATTENTION_1_FCS_ERR_OFFSET                                0x00000004
+#define RX_ATTENTION_1_FCS_ERR_LSB                                   31
+#define RX_ATTENTION_1_FCS_ERR_MASK                                  0x80000000
+
+/* Description		RX_ATTENTION_2_FLOW_IDX_TIMEOUT
+			
+			Indicates an unsuccessful flow search due to the
+			expiring of the search timer.
+			
+			<legal all>
+*/
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET                       0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB                          0
+#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK                         0x00000001
+
+/* Description		RX_ATTENTION_2_FLOW_IDX_INVALID
+			
+			flow id is not valid
+			
+			<legal all>
+*/
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET                       0x00000008
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB                          1
+#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK                         0x00000002
+
+/* Description		RX_ATTENTION_2_WIFI_PARSER_ERROR
+			
+			TODO: add details to the description
+			
+			<legal all>
+*/
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET                      0x00000008
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB                         2
+#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK                        0x00000004
+
+/* Description		RX_ATTENTION_2_AMSDU_PARSER_ERROR
+			
+			A-MSDU could not be properly de-agregated.
+			
+			<legal all>
+*/
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET                     0x00000008
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB                        3
+#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK                       0x00000008
+
+/* Description		RX_ATTENTION_2_SA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer.
+*/
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET                         0x00000008
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB                            4
+#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK                           0x00000010
+
+/* Description		RX_ATTENTION_2_DA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer.
+*/
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET                         0x00000008
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB                            5
+#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK                           0x00000020
+
+/* Description		RX_ATTENTION_2_MSDU_LIMIT_ERROR
+			
+			Indicates that the MSDU threshold was exceeded and thus
+			all the rest of the MSDUs will not be scattered and will not
+			be decasulated but will be DMA'ed in RAW format as a single
+			MSDU buffer
+*/
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET                       0x00000008
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB                          6
+#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK                         0x00000040
+
+/* Description		RX_ATTENTION_2_DA_IS_VALID
+			
+			Indicates that OLE found a valid DA entry
+*/
+#define RX_ATTENTION_2_DA_IS_VALID_OFFSET                            0x00000008
+#define RX_ATTENTION_2_DA_IS_VALID_LSB                               7
+#define RX_ATTENTION_2_DA_IS_VALID_MASK                              0x00000080
+
+/* Description		RX_ATTENTION_2_DA_IS_MCBC
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address.
+*/
+#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET                             0x00000008
+#define RX_ATTENTION_2_DA_IS_MCBC_LSB                                8
+#define RX_ATTENTION_2_DA_IS_MCBC_MASK                               0x00000100
+
+/* Description		RX_ATTENTION_2_SA_IS_VALID
+			
+			Indicates that OLE found a valid SA entry
+*/
+#define RX_ATTENTION_2_SA_IS_VALID_OFFSET                            0x00000008
+#define RX_ATTENTION_2_SA_IS_VALID_LSB                               9
+#define RX_ATTENTION_2_SA_IS_VALID_MASK                              0x00000200
+
+/* Description		RX_ATTENTION_2_DECRYPT_STATUS_CODE
+			
+			Field provides insight into the decryption performed
+			
+			
+			
+			<enum 0 decrypt_ok> Frame had protection enabled and
+			decrypted properly 
+			
+			<enum 1 decrypt_unprotected_frame > Frame is unprotected
+			and hence bypassed 
+			
+			<enum 2 decrypt_data_err > Frame has protection enabled
+			and could not be properly decrypted due to MIC/ICV mismatch
+			etc. 
+			
+			<enum 3 decrypt_key_invalid > Frame has protection
+			enabled but the key that was required to decrypt this frame
+			was not valid 
+			
+			<enum 4 decrypt_peer_entry_invalid > Frame has
+			protection enabled but the key that was required to decrypt
+			this frame was not valid
+			
+			<enum 5 decrypt_other > Reserved for other indications
+			
+			
+			
+			<legal 0 - 5>
+*/
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET                    0x00000008
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB                       10
+#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK                      0x00001c00
+
+/* Description		RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED
+			
+			Frame is received, but RXPCU could not update the
+			receive bitmap due to (temporary) fifo contraints.
+			
+			<legal all>
+*/
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET                  0x00000008
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB                     13
+#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK                    0x00002000
+
+/* Description		RX_ATTENTION_2_RESERVED_2
+			
+			<legal 0>
+*/
+#define RX_ATTENTION_2_RESERVED_2_OFFSET                             0x00000008
+#define RX_ATTENTION_2_RESERVED_2_LSB                                14
+#define RX_ATTENTION_2_RESERVED_2_MASK                               0x7fffc000
+
+/* Description		RX_ATTENTION_2_MSDU_DONE
+			
+			If set indicates that the RX packet data, RX header
+			data, RX PPDU start descriptor, RX MPDU start/end
+			descriptor, RX MSDU start/end descriptors and RX Attention
+			descriptor are all valid.  This bit must be in the last
+			octet of the descriptor.
+*/
+#define RX_ATTENTION_2_MSDU_DONE_OFFSET                              0x00000008
+#define RX_ATTENTION_2_MSDU_DONE_LSB                                 31
+#define RX_ATTENTION_2_MSDU_DONE_MASK                                0x80000000
+
+
+#endif // _RX_ATTENTION_H_

hw/qca6290/v1/rx_mpdu_desc_info.h

@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_DESC_INFO_H_
+#define _RX_MPDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], reserved[31]
+//	1	peer_meta_data[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2
+
+struct rx_mpdu_desc_info {
+             uint32_t msdu_count                      :  8, //[7:0]
+                      mpdu_sequence_number            : 12, //[19:8]
+                      fragment_flag                   :  1, //[20]
+                      mpdu_retry_bit                  :  1, //[21]
+                      ampdu_flag                      :  1, //[22]
+                      bar_frame                       :  1, //[23]
+                      pn_fields_contain_valid_info    :  1, //[24]
+                      sa_is_valid                     :  1, //[25]
+                      sa_idx_timeout                  :  1, //[26]
+                      da_is_valid                     :  1, //[27]
+                      da_is_mcbc                      :  1, //[28]
+                      da_idx_timeout                  :  1, //[29]
+                      raw_mpdu                        :  1, //[30]
+                      reserved                        :  1; //[31]
+             uint32_t peer_meta_data                  : 32; //[31:0]
+};
+
+/*
+
+msdu_count
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The number of MSDUs within the MPDU 
+			
+			<legal all>
+
+mpdu_sequence_number
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The field can have two different meanings based on the
+			setting of field 'BAR_frame':
+			
+			
+			
+			'BAR_frame' is NOT set:
+			
+			The MPDU sequence number of the received frame.
+			
+			
+			
+			'BAR_frame' is set.
+			
+			The MPDU Start sequence number from the BAR frame
+			
+			<legal all>
+
+fragment_flag
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, this MPDU is a fragment and REO should forward
+			this fragment MPDU to the REO destination ring without any
+			reorder checks, pn checks or bitmap update. This implies
+			that REO is forwarding the pointer to the MSDU link
+			descriptor. The destination ring is coming from a
+			programmable register setting in REO
+			
+			
+			
+			<legal all>
+
+mpdu_retry_bit
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The retry bit setting from the MPDU header of the
+			received frame
+			
+			<legal all>
+
+ampdu_flag
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the MPDU was received as part of an A-MPDU.
+			
+			<legal all>
+
+bar_frame
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the received frame is a BAR frame. After
+			processing, this frame shall be pushed to SW or deleted.
+			
+			<legal all>
+
+pn_fields_contain_valid_info
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Copied here by RXDMA from RX_MPDU_END
+			
+			When not set, REO will Not perform a PN sequence number
+			check
+
+sa_is_valid
+			
+			When set, OLE found a valid SA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+
+sa_idx_timeout
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC source address search due to the expiration
+			of the search timer.
+			
+			<legal all>
+
+da_is_valid
+			
+			When set, OLE found a valid DA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+
+da_is_mcbc
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			When set, at least one of the DA addresses is a
+			Multicast or Broadcast address.
+			
+			<legal all>
+
+da_idx_timeout
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC destination address search due to the
+			expiration of the search timer.
+			
+			<legal all>
+
+raw_mpdu
+			
+			Field only valid when first_msdu_in_mpdu_flag is set.
+			
+			
+			
+			When set, the contents in the MSDU buffer contains a
+			'RAW' MPDU. This 'RAW' MPDU might be spread out over
+			multiple MSDU buffers.
+			
+			<legal all>
+
+reserved
+			
+			<legal 0>
+
+peer_meta_data
+			
+			Meta data that SW has programmed in the Peer table entry
+			of the transmitting STA.
+			
+			<legal all>
+*/
+
+
+/* Description		RX_MPDU_DESC_INFO_0_MSDU_COUNT
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The number of MSDUs within the MPDU 
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB                           0
+#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK                          0x000000ff
+
+/* Description		RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The field can have two different meanings based on the
+			setting of field 'BAR_frame':
+			
+			
+			
+			'BAR_frame' is NOT set:
+			
+			The MPDU sequence number of the received frame.
+			
+			
+			
+			'BAR_frame' is set.
+			
+			The MPDU Start sequence number from the BAR frame
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET              0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB                 8
+#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK                0x000fff00
+
+/* Description		RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, this MPDU is a fragment and REO should forward
+			this fragment MPDU to the REO destination ring without any
+			reorder checks, pn checks or bitmap update. This implies
+			that REO is forwarding the pointer to the MSDU link
+			descriptor. The destination ring is coming from a
+			programmable register setting in REO
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET                     0x00000000
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB                        20
+#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK                       0x00100000
+
+/* Description		RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			The retry bit setting from the MPDU header of the
+			received frame
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB                       21
+#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK                      0x00200000
+
+/* Description		RX_MPDU_DESC_INFO_0_AMPDU_FLAG
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the MPDU was received as part of an A-MPDU.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB                           22
+#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK                          0x00400000
+
+/* Description		RX_MPDU_DESC_INFO_0_BAR_FRAME
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			When set, the received frame is a BAR frame. After
+			processing, this frame shall be pushed to SW or deleted.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET                         0x00000000
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB                            23
+#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK                           0x00800000
+
+/* Description		RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Copied here by RXDMA from RX_MPDU_END
+			
+			When not set, REO will Not perform a PN sequence number
+			check
+*/
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET      0x00000000
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB         24
+#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK        0x01000000
+
+/* Description		RX_MPDU_DESC_INFO_0_SA_IS_VALID
+			
+			When set, OLE found a valid SA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB                          25
+#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK                         0x02000000
+
+/* Description		RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC source address search due to the expiration
+			of the search timer.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB                       26
+#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK                      0x04000000
+
+/* Description		RX_MPDU_DESC_INFO_0_DA_IS_VALID
+			
+			When set, OLE found a valid DA entry for all MSDUs in
+			this MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET                       0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB                          27
+#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK                         0x08000000
+
+/* Description		RX_MPDU_DESC_INFO_0_DA_IS_MCBC
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			When set, at least one of the DA addresses is a
+			Multicast or Broadcast address.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET                        0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB                           28
+#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK                          0x10000000
+
+/* Description		RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT
+			
+			When set, at least 1 MSDU within the MPDU has an
+			unsuccessful MAC destination address search due to the
+			expiration of the search timer.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB                       29
+#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK                      0x20000000
+
+/* Description		RX_MPDU_DESC_INFO_0_RAW_MPDU
+			
+			Field only valid when first_msdu_in_mpdu_flag is set.
+			
+			
+			
+			When set, the contents in the MSDU buffer contains a
+			'RAW' MPDU. This 'RAW' MPDU might be spread out over
+			multiple MSDU buffers.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET                          0x00000000
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB                             30
+#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK                            0x40000000
+
+/* Description		RX_MPDU_DESC_INFO_0_RESERVED
+			
+			<legal 0>
+*/
+#define RX_MPDU_DESC_INFO_0_RESERVED_OFFSET                          0x00000000
+#define RX_MPDU_DESC_INFO_0_RESERVED_LSB                             31
+#define RX_MPDU_DESC_INFO_0_RESERVED_MASK                            0x80000000
+
+/* Description		RX_MPDU_DESC_INFO_1_PEER_META_DATA
+			
+			Meta data that SW has programmed in the Peer table entry
+			of the transmitting STA.
+			
+			<legal all>
+*/
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET                    0x00000004
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB                       0
+#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK                      0xffffffff
+
+
+#endif // _RX_MPDU_DESC_INFO_H_

hw/qca6290/v1/rx_mpdu_details.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_DETAILS_H_
+#define _RX_MPDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info msdu_link_desc_addr_info;
+//	2-3	struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4
+
+struct rx_mpdu_details {
+    struct            buffer_addr_info                       msdu_link_desc_addr_info;
+    struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
+};
+
+/*
+
+struct buffer_addr_info msdu_link_desc_addr_info
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Details of the physical address of the MSDU link
+			descriptor that contains pointers to MSDUs related to this
+			MPDU
+
+struct rx_mpdu_desc_info rx_mpdu_desc_info_details
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			General information related to the MPDU that should be
+*/
+
+#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
+#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MPDU_DETAILS_0_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
+#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MPDU_DETAILS_1_BUFFER_ADDR_INFO_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0
+#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 0
+#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_DETAILS_H_

hw/qca6290/v1/rx_mpdu_end.h

@@ -0,0 +1,753 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_END_H_
+#define _RX_MPDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+//	1	reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_END 2
+
+struct rx_mpdu_end {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
+                      sw_frame_group_id               :  7, //[8:2]
+                      reserved_0                      :  7, //[15:9]
+                      phy_ppdu_id                     : 16; //[31:16]
+             uint32_t reserved_1a                     : 11, //[10:0]
+                      unsup_ktype_short_frame         :  1, //[11]
+                      rx_in_tx_decrypt_byp            :  1, //[12]
+                      overflow_err                    :  1, //[13]
+                      mpdu_length_err                 :  1, //[14]
+                      tkip_mic_err                    :  1, //[15]
+                      decrypt_err                     :  1, //[16]
+                      unencrypted_frame_err           :  1, //[17]
+                      pn_fields_contain_valid_info    :  1, //[18]
+                      fcs_err                         :  1, //[19]
+                      msdu_length_err                 :  1, //[20]
+                      rxdma0_destination_ring         :  2, //[22:21]
+                      rxdma1_destination_ring         :  2, //[24:23]
+                      decrypt_status_code             :  3, //[27:25]
+                      rx_bitmap_not_updated           :  1, //[28]
+                      reserved_1b                     :  3; //[31:29]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+
+sw_frame_group_id
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+
+reserved_0
+			
+			<legal 0>
+
+phy_ppdu_id
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+
+reserved_1a
+			
+			<legal 0>
+
+unsup_ktype_short_frame
+			
+			This bit will be '1' when WEP or TKIP or WAPI key type
+			is received for 11ah short frame.  Crypto will bypass the
+			received packet without decryption to RxOLE after setting
+			this bit.
+
+rx_in_tx_decrypt_byp
+			
+			Indicates that RX packet is not decrypted as Crypto is
+			busy with TX packet processing.
+
+overflow_err
+			
+			RXPCU Receive FIFO ran out of space to receive the full
+			MPDU. Therefor this MPDU is terminated early and is thus
+			corrupted.  
+			
+			
+			
+			This MPDU will not be ACKed.
+			
+			RXPCU might still be able to correctly receive the
+			following MPDUs in the PPDU if enough fifo space became
+			available in time
+
+mpdu_length_err
+			
+			Set by RXPCU if the expected MPDU length does not
+			correspond with the actually received number of bytes in the
+			MPDU.
+
+tkip_mic_err
+			
+			Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
+			for this MPDU
+
+decrypt_err
+			
+			Set by RX CRYPTO when CRYPTO detected a decrypt error
+			for this MPDU.
+
+unencrypted_frame_err
+			
+			Set by RX CRYPTO when CRYPTO detected an unencrypted
+			frame while in the peer entry field
+			'All_frames_shall_be_encrypted' is set.
+
+pn_fields_contain_valid_info
+			
+			Set by RX CRYPTO to indicate that there is a valid PN
+			field present in this MPDU
+
+fcs_err
+			
+			Set by RXPCU when there is an FCS error detected for
+			this MPDU
+
+msdu_length_err
+			
+			Set by RXOLE when there is an msdu length error detected
+			in at least 1 of the MSDUs embedded within the MPDU
+
+rxdma0_destination_ring
+			
+			The ring to which RXDMA0 shall push the frame, assuming
+			no MPDU level errors are detected. In case of MPDU level
+			errors, RXDMA0 might change the RXDMA0 destination
+			
+			
+			
+			<enum 0  rxdma_release_ring >  RXDMA0 shall push the
+			frame to the Release ring. Effectively this means the frame
+			needs to be dropped.
+			
+			
+			
+			<enum 1  rxdma2fw_ring >  RXDMA0 shall push the frame to
+			the FW ring 
+			
+			
+			
+			<enum 2  rxdma2sw_ring >  RXDMA0 shall push the frame to
+			the SW ring 
+			
+			
+			
+			<enum 3  rxdma2reo_ring >  RXDMA0 shall push the frame
+			to the REO entrance ring 
+			
+			
+			
+			<legal all>
+
+rxdma1_destination_ring
+			
+			The ring to which RXDMA1 shall push the frame, assuming
+			no MPDU level errors are detected. In case of MPDU level
+			errors, RXDMA1 might change the RXDMA destination
+			
+			
+			
+			<enum 0  rxdma_release_ring >  RXDMA1 shall push the
+			frame to the Release ring. Effectively this means the frame
+			needs to be dropped.
+			
+			
+			
+			<enum 1  rxdma2fw_ring >  RXDMA1 shall push the frame to
+			the FW ring 
+			
+			
+			
+			<enum 2  rxdma2sw_ring >  RXDMA1 shall push the frame to
+			the SW ring 
+			
+			
+			
+			<enum 3  rxdma2reo_ring >  RXDMA1 shall push the frame
+			to the REO entrance ring 
+			
+			
+			
+			<legal all>
+
+decrypt_status_code
+			
+			Field provides insight into the decryption performed
+			
+			
+			
+			<enum 0 decrypt_ok> Frame had protection enabled and
+			decrypted properly 
+			
+			<enum 1 decrypt_unprotected_frame > Frame is unprotected
+			and hence bypassed 
+			
+			<enum 2 decrypt_data_err > Frame has protection enabled
+			and could not be properly decrypted due to MIC/ICV mismatch
+			etc. 
+			
+			<enum 3 decrypt_key_invalid > Frame has protection
+			enabled but the key that was required to decrypt this frame
+			was not valid 
+			
+			<enum 4 decrypt_peer_entry_invalid > Frame has
+			protection enabled but the key that was required to decrypt
+			this frame was not valid
+			
+			<enum 5 decrypt_other > Reserved for other indications
+			
+			
+			
+			<legal 0 - 5>
+
+rx_bitmap_not_updated
+			
+			Frame is received, but RXPCU could not update the
+			receive bitmap due to (temporary) fifo contraints.
+			
+			<legal all>
+
+reserved_1b
+			
+			<legal 0>
+*/
+
+
+/* Description		RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+*/
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
+#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
+
+/* Description		RX_MPDU_END_0_SW_FRAME_GROUP_ID
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+*/
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
+#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
+
+/* Description		RX_MPDU_END_0_RESERVED_0
+			
+			<legal 0>
+*/
+#define RX_MPDU_END_0_RESERVED_0_OFFSET                              0x00000000
+#define RX_MPDU_END_0_RESERVED_0_LSB                                 9
+#define RX_MPDU_END_0_RESERVED_0_MASK                                0x0000fe00
+
+/* Description		RX_MPDU_END_0_PHY_PPDU_ID
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+*/
+#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
+#define RX_MPDU_END_0_PHY_PPDU_ID_LSB                                16
+#define RX_MPDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
+
+/* Description		RX_MPDU_END_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define RX_MPDU_END_1_RESERVED_1A_OFFSET                             0x00000004
+#define RX_MPDU_END_1_RESERVED_1A_LSB                                0
+#define RX_MPDU_END_1_RESERVED_1A_MASK                               0x000007ff
+
+/* Description		RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME
+			
+			This bit will be '1' when WEP or TKIP or WAPI key type
+			is received for 11ah short frame.  Crypto will bypass the
+			received packet without decryption to RxOLE after setting
+			this bit.
+*/
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET                 0x00000004
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB                    11
+#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK                   0x00000800
+
+/* Description		RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP
+			
+			Indicates that RX packet is not decrypted as Crypto is
+			busy with TX packet processing.
+*/
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET                    0x00000004
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB                       12
+#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK                      0x00001000
+
+/* Description		RX_MPDU_END_1_OVERFLOW_ERR
+			
+			RXPCU Receive FIFO ran out of space to receive the full
+			MPDU. Therefor this MPDU is terminated early and is thus
+			corrupted.  
+			
+			
+			
+			This MPDU will not be ACKed.
+			
+			RXPCU might still be able to correctly receive the
+			following MPDUs in the PPDU if enough fifo space became
+			available in time
+*/
+#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET                            0x00000004
+#define RX_MPDU_END_1_OVERFLOW_ERR_LSB                               13
+#define RX_MPDU_END_1_OVERFLOW_ERR_MASK                              0x00002000
+
+/* Description		RX_MPDU_END_1_MPDU_LENGTH_ERR
+			
+			Set by RXPCU if the expected MPDU length does not
+			correspond with the actually received number of bytes in the
+			MPDU.
+*/
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET                         0x00000004
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB                            14
+#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK                           0x00004000
+
+/* Description		RX_MPDU_END_1_TKIP_MIC_ERR
+			
+			Set by RX CRYPTO when CRYPTO detected a TKIP MIC error
+			for this MPDU
+*/
+#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET                            0x00000004
+#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB                               15
+#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK                              0x00008000
+
+/* Description		RX_MPDU_END_1_DECRYPT_ERR
+			
+			Set by RX CRYPTO when CRYPTO detected a decrypt error
+			for this MPDU.
+*/
+#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET                             0x00000004
+#define RX_MPDU_END_1_DECRYPT_ERR_LSB                                16
+#define RX_MPDU_END_1_DECRYPT_ERR_MASK                               0x00010000
+
+/* Description		RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR
+			
+			Set by RX CRYPTO when CRYPTO detected an unencrypted
+			frame while in the peer entry field
+			'All_frames_shall_be_encrypted' is set.
+*/
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET                   0x00000004
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB                      17
+#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK                     0x00020000
+
+/* Description		RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO
+			
+			Set by RX CRYPTO to indicate that there is a valid PN
+			field present in this MPDU
+*/
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET            0x00000004
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB               18
+#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK              0x00040000
+
+/* Description		RX_MPDU_END_1_FCS_ERR
+			
+			Set by RXPCU when there is an FCS error detected for
+			this MPDU
+*/
+#define RX_MPDU_END_1_FCS_ERR_OFFSET                                 0x00000004
+#define RX_MPDU_END_1_FCS_ERR_LSB                                    19
+#define RX_MPDU_END_1_FCS_ERR_MASK                                   0x00080000
+
+/* Description		RX_MPDU_END_1_MSDU_LENGTH_ERR
+			
+			Set by RXOLE when there is an msdu length error detected
+			in at least 1 of the MSDUs embedded within the MPDU
+*/
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET                         0x00000004
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB                            20
+#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK                           0x00100000
+
+/* Description		RX_MPDU_END_1_RXDMA0_DESTINATION_RING
+			
+			The ring to which RXDMA0 shall push the frame, assuming
+			no MPDU level errors are detected. In case of MPDU level
+			errors, RXDMA0 might change the RXDMA0 destination
+			
+			
+			
+			<enum 0  rxdma_release_ring >  RXDMA0 shall push the
+			frame to the Release ring. Effectively this means the frame
+			needs to be dropped.
+			
+			
+			
+			<enum 1  rxdma2fw_ring >  RXDMA0 shall push the frame to
+			the FW ring 
+			
+			
+			
+			<enum 2  rxdma2sw_ring >  RXDMA0 shall push the frame to
+			the SW ring 
+			
+			
+			
+			<enum 3  rxdma2reo_ring >  RXDMA0 shall push the frame
+			to the REO entrance ring 
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET                 0x00000004
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB                    21
+#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK                   0x00600000
+
+/* Description		RX_MPDU_END_1_RXDMA1_DESTINATION_RING
+			
+			The ring to which RXDMA1 shall push the frame, assuming
+			no MPDU level errors are detected. In case of MPDU level
+			errors, RXDMA1 might change the RXDMA destination
+			
+			
+			
+			<enum 0  rxdma_release_ring >  RXDMA1 shall push the
+			frame to the Release ring. Effectively this means the frame
+			needs to be dropped.
+			
+			
+			
+			<enum 1  rxdma2fw_ring >  RXDMA1 shall push the frame to
+			the FW ring 
+			
+			
+			
+			<enum 2  rxdma2sw_ring >  RXDMA1 shall push the frame to
+			the SW ring 
+			
+			
+			
+			<enum 3  rxdma2reo_ring >  RXDMA1 shall push the frame
+			to the REO entrance ring 
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET                 0x00000004
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB                    23
+#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK                   0x01800000
+
+/* Description		RX_MPDU_END_1_DECRYPT_STATUS_CODE
+			
+			Field provides insight into the decryption performed
+			
+			
+			
+			<enum 0 decrypt_ok> Frame had protection enabled and
+			decrypted properly 
+			
+			<enum 1 decrypt_unprotected_frame > Frame is unprotected
+			and hence bypassed 
+			
+			<enum 2 decrypt_data_err > Frame has protection enabled
+			and could not be properly decrypted due to MIC/ICV mismatch
+			etc. 
+			
+			<enum 3 decrypt_key_invalid > Frame has protection
+			enabled but the key that was required to decrypt this frame
+			was not valid 
+			
+			<enum 4 decrypt_peer_entry_invalid > Frame has
+			protection enabled but the key that was required to decrypt
+			this frame was not valid
+			
+			<enum 5 decrypt_other > Reserved for other indications
+			
+			
+			
+			<legal 0 - 5>
+*/
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET                     0x00000004
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB                        25
+#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK                       0x0e000000
+
+/* Description		RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED
+			
+			Frame is received, but RXPCU could not update the
+			receive bitmap due to (temporary) fifo contraints.
+			
+			<legal all>
+*/
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET                   0x00000004
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB                      28
+#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK                     0x10000000
+
+/* Description		RX_MPDU_END_1_RESERVED_1B
+			
+			<legal 0>
+*/
+#define RX_MPDU_END_1_RESERVED_1B_OFFSET                             0x00000004
+#define RX_MPDU_END_1_RESERVED_1B_LSB                                29
+#define RX_MPDU_END_1_RESERVED_1B_MASK                               0xe0000000
+
+
+#endif // _RX_MPDU_END_H_

hw/qca6290/v1/rx_mpdu_info.h

@@ -0,0 +1,2871 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_INFO_H_
+#define _RX_MPDU_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rxpt_classify_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_0a[15:14], phy_ppdu_id[31:16]
+//	1	ast_index[15:0], sw_peer_id[31:16]
+//	2	mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], reserved_2a[15:10], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20]
+//	3	epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], mesh_sta[6], bssid_hit[7], bssid_number[11:8], tid[15:12], reserved_3a[31:16]
+//	4	pn_31_0[31:0]
+//	5	pn_63_32[31:0]
+//	6	pn_95_64[31:0]
+//	7	pn_127_96[31:0]
+//	8	peer_meta_data[31:0]
+//	9	struct rxpt_classify_info rxpt_classify_info_details;
+//	10	rx_reo_queue_desc_addr_31_0[31:0]
+//	11	rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_11[31:26]
+//	12	key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], reserved_12[31:30]
+//	13	mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], reserved_13[31:30]
+//	14	mpdu_frame_control_field[15:0], mpdu_duration_field[31:16]
+//	15	mac_addr_ad1_31_0[31:0]
+//	16	mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16]
+//	17	mac_addr_ad2_47_16[31:0]
+//	18	mac_addr_ad3_31_0[31:0]
+//	19	mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16]
+//	20	mac_addr_ad4_31_0[31:0]
+//	21	mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16]
+//	22	mpdu_ht_control_field[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_INFO 23
+
+struct rx_mpdu_info {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
+                      sw_frame_group_id               :  7, //[8:2]
+                      ndp_frame                       :  1, //[9]
+                      phy_err                         :  1, //[10]
+                      phy_err_during_mpdu_header      :  1, //[11]
+                      protocol_version_err            :  1, //[12]
+                      ast_based_lookup_valid          :  1, //[13]
+                      reserved_0a                     :  2, //[15:14]
+                      phy_ppdu_id                     : 16; //[31:16]
+             uint32_t ast_index                       : 16, //[15:0]
+                      sw_peer_id                      : 16; //[31:16]
+             uint32_t mpdu_frame_control_valid        :  1, //[0]
+                      mpdu_duration_valid             :  1, //[1]
+                      mac_addr_ad1_valid              :  1, //[2]
+                      mac_addr_ad2_valid              :  1, //[3]
+                      mac_addr_ad3_valid              :  1, //[4]
+                      mac_addr_ad4_valid              :  1, //[5]
+                      mpdu_sequence_control_valid     :  1, //[6]
+                      mpdu_qos_control_valid          :  1, //[7]
+                      mpdu_ht_control_valid           :  1, //[8]
+                      frame_encryption_info_valid     :  1, //[9]
+                      reserved_2a                     :  6, //[15:10]
+                      fr_ds                           :  1, //[16]
+                      to_ds                           :  1, //[17]
+                      encrypted                       :  1, //[18]
+                      mpdu_retry                      :  1, //[19]
+                      mpdu_sequence_number            : 12; //[31:20]
+             uint32_t epd_en                          :  1, //[0]
+                      all_frames_shall_be_encrypted   :  1, //[1]
+                      encrypt_type                    :  4, //[5:2]
+                      mesh_sta                        :  1, //[6]
+                      bssid_hit                       :  1, //[7]
+                      bssid_number                    :  4, //[11:8]
+                      tid                             :  4, //[15:12]
+                      reserved_3a                     : 16; //[31:16]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+             uint32_t peer_meta_data                  : 32; //[31:0]
+    struct            rxpt_classify_info                       rxpt_classify_info_details;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      receive_queue_number            : 16, //[23:8]
+                      pre_delim_err_warning           :  1, //[24]
+                      first_delim_err                 :  1, //[25]
+                      reserved_11                     :  6; //[31:26]
+             uint32_t key_id_octet                    :  8, //[7:0]
+                      new_peer_entry                  :  1, //[8]
+                      decrypt_needed                  :  1, //[9]
+                      decap_type                      :  2, //[11:10]
+                      rx_insert_vlan_c_tag_padding    :  1, //[12]
+                      rx_insert_vlan_s_tag_padding    :  1, //[13]
+                      strip_vlan_c_tag_decap          :  1, //[14]
+                      strip_vlan_s_tag_decap          :  1, //[15]
+                      pre_delim_count                 : 12, //[27:16]
+                      ampdu_flag                      :  1, //[28]
+                      bar_frame                       :  1, //[29]
+                      reserved_12                     :  2; //[31:30]
+             uint32_t mpdu_length                     : 14, //[13:0]
+                      first_mpdu                      :  1, //[14]
+                      mcast_bcast                     :  1, //[15]
+                      ast_index_not_found             :  1, //[16]
+                      ast_index_timeout               :  1, //[17]
+                      power_mgmt                      :  1, //[18]
+                      non_qos                         :  1, //[19]
+                      null_data                       :  1, //[20]
+                      mgmt_type                       :  1, //[21]
+                      ctrl_type                       :  1, //[22]
+                      more_data                       :  1, //[23]
+                      eosp                            :  1, //[24]
+                      fragment_flag                   :  1, //[25]
+                      order                           :  1, //[26]
+                      u_apsd_trigger                  :  1, //[27]
+                      encrypt_required                :  1, //[28]
+                      directed                        :  1, //[29]
+                      reserved_13                     :  2; //[31:30]
+             uint32_t mpdu_frame_control_field        : 16, //[15:0]
+                      mpdu_duration_field             : 16; //[31:16]
+             uint32_t mac_addr_ad1_31_0               : 32; //[31:0]
+             uint32_t mac_addr_ad1_47_32              : 16, //[15:0]
+                      mac_addr_ad2_15_0               : 16; //[31:16]
+             uint32_t mac_addr_ad2_47_16              : 32; //[31:0]
+             uint32_t mac_addr_ad3_31_0               : 32; //[31:0]
+             uint32_t mac_addr_ad3_47_32              : 16, //[15:0]
+                      mpdu_sequence_control_field     : 16; //[31:16]
+             uint32_t mac_addr_ad4_31_0               : 32; //[31:0]
+             uint32_t mac_addr_ad4_47_32              : 16, //[15:0]
+                      mpdu_qos_control_field          : 16; //[31:16]
+             uint32_t mpdu_ht_control_field           : 32; //[31:0]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			
+			
+			Note: for ndp frame, if it was expected because the
+			preceding NDPA was filter_pass, the setting 
+			rxpcu_filter_pass will be used. This setting will also be
+			used for every ndp frame in case Promiscuous mode is
+			enabled.
+			
+			
+			
+			In case promiscuous is not enabled, and an NDP is not
+			preceded by a NPDA filter pass frame, the only other setting
+			that could appear here for the NDP is rxpcu_monitor_other. 
+			
+			(rxpcu has a configuration bit specifically for this
+			scenario)
+			
+			
+			
+			Note: for 
+			
+			<legal 0-2>
+
+sw_frame_group_id
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> Note: The
+			corresponding Rxpcu_Mpdu_filter_in_category can be
+			rxpcu_filter_pass or rxpcu_monitor_other
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0 
+			
+			Note: The corresponding Rxpcu_Mpdu_filter_in_category
+			can only be rxpcu_monitor_other
+			
+			
+			
+			
+			Note: The corresponding Rxpcu_Mpdu_filter_in_category
+			can be rxpcu_filter_pass
+			
+			
+			
+			<legal 0-37>
+
+ndp_frame
+			
+			When set, the received frame was an NDP frame, and thus
+			there will be no MPDU data.
+			
+			<legal all>
+
+phy_err
+			
+			When set, a PHY error was received before MAC received
+			any data, and thus there will be no MPDU data.
+			
+			<legal all>
+
+phy_err_during_mpdu_header
+			
+			When set, a PHY error was received before MAC received
+			the complete MPDU header which was needed for proper
+			decoding
+			
+			<legal all>
+
+protocol_version_err
+			
+			Set when RXPCU detected a version error in the Frame
+			control field
+			
+			<legal all>
+
+ast_based_lookup_valid
+			
+			When set, AST based lookup for this frame has found a
+			valid result.
+			
+			
+			
+			Note that for NDP frame this will never be set
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+
+phy_ppdu_id
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+
+ast_index
+			
+			This field indicates the index of the AST entry
+			corresponding to this MPDU. It is provided by the GSE module
+			instantiated in RXPCU.
+			
+			A value of 0xFFFF indicates an invalid AST index,
+			meaning that No AST entry was found or NO AST search was
+			performed
+			
+			
+			
+			In case of ndp or phy_err, this field will be set to
+			0xFFFF
+			
+			<legal all>
+
+sw_peer_id
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			This field indicates a unique peer identifier. It is set
+			equal to field 'sw_peer_id' from the AST entry
+			
+			
+			
+			<legal all>
+
+mpdu_frame_control_valid
+			
+			When set, the field Mpdu_Frame_control_field has valid
+			information
+			
+			
+			
+			
+			<legal all>
+
+mpdu_duration_valid
+			
+			When set, the field Mpdu_duration_field has valid
+			information
+			
+			
+			
+			
+			<legal all>
+
+mac_addr_ad1_valid
+			
+			When set, the fields mac_addr_ad1_..... have valid
+			information
+			
+			
+			
+			
+			<legal all>
+
+mac_addr_ad2_valid
+			
+			When set, the fields mac_addr_ad2_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+
+mac_addr_ad3_valid
+			
+			When set, the fields mac_addr_ad3_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+
+mac_addr_ad4_valid
+			
+			When set, the fields mac_addr_ad4_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+
+mpdu_sequence_control_valid
+			
+			When set, the fields mpdu_sequence_control_field and
+			mpdu_sequence_number have valid information as well as field
+			
+			
+			
+			For MPDUs without a sequence control field, this field
+			will not be set.
+			
+			
+			
+			
+			<legal all>
+
+mpdu_qos_control_valid
+			
+			When set, the field mpdu_qos_control_field has valid
+			information
+			
+			
+			
+			For MPDUs without a QoS control field, this field will
+			not be set.
+			
+			
+			
+			
+			<legal all>
+
+mpdu_ht_control_valid
+			
+			When set, the field mpdu_HT_control_field has valid
+			information
+			
+			
+			
+			For MPDUs without a HT control field, this field will
+			not be set.
+			
+			
+			
+			
+			<legal all>
+
+frame_encryption_info_valid
+			
+			When set, the encryption related info fields, like IV
+			and PN are valid
+			
+			
+			
+			For MPDUs that are not encrypted, this will not be set.
+			
+			
+			
+			
+			<legal all>
+
+reserved_2a
+			
+			<legal 0>
+
+fr_ds
+			
+			Field only valid when Mpdu_frame_control_valid is set
+			
+			
+			
+			Set if the from DS bit is set in the frame control.
+			
+			<legal all>
+
+to_ds
+			
+			Field only valid when Mpdu_frame_control_valid is set 
+			
+			
+			
+			Set if the to DS bit is set in the frame control.
+			
+			<legal all>
+
+encrypted
+			
+			Field only valid when Mpdu_frame_control_valid is set.
+			
+			
+			
+			Protected bit from the frame control.  
+			
+			<legal all>
+
+mpdu_retry
+			
+			Field only valid when Mpdu_frame_control_valid is set.
+			
+			
+			
+			Retry bit from the frame control.  Only valid when
+			first_msdu is set.
+			
+			<legal all>
+
+mpdu_sequence_number
+			
+			Field only valid when Mpdu_sequence_control_valid is
+			set.
+			
+			
+			
+			The sequence number from the 802.11 header.
+			
+			<legal all>
+
+epd_en
+			
+			Field only valid when AST_based_lookup_valid == 1.
+			
+			
+			
+			
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			If set to one use EPD instead of LPD
+			
+			
+			
+			
+			<legal all>
+
+all_frames_shall_be_encrypted
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, all frames (data only ?) shall be encrypted.
+			If not, RX CRYPTO shall set an error flag.
+			
+			<legal all>
+
+encrypt_type
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Indicates type of decrypt cipher used (as defined in the
+			peer entry)
+			
+			
+			
+			<enum 0 wep_40> WEP 40-bit
+			
+			<enum 1 wep_104> WEP 104-bit
+			
+			<enum 2 tkip_no_mic> TKIP without MIC
+			
+			<enum 3 wep_128> WEP 128-bit
+			
+			<enum 4 tkip_with_mic> TKIP with MIC
+			
+			<enum 5 wapi> WAPI
+			
+			<enum 6 aes_ccmp_128> AES CCMP 128
+			
+			<enum 7 no_cipher> No crypto
+			
+			<enum 8 aes_ccmp_256> AES CCMP 256
+			
+			<enum 9 aes_gcmp_128> AES CCMP 128
+			
+			<enum 10 aes_gcmp_256> AES CCMP 256
+			
+			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
+			
+			
+			
+			
+			<legal 0-11>
+
+mesh_sta
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, this is a Mesh (11s) STA
+			
+			<legal all>
+
+bssid_hit
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, the BSSID of the incoming frame matched one of
+			the 8 BSSID register values
+			
+			
+			
+			<legal all>
+
+bssid_number
+			
+			Field only valid when bssid_hit is set.
+			
+			
+			
+			This number indicates which one out of the 8 BSSID
+			register values matched the incoming frame
+			
+			<legal all>
+
+tid
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The TID field in the QoS control field
+			
+			<legal all>
+
+reserved_3a
+			
+			<legal 0>
+
+pn_31_0
+			
+			
+			
+			
+			
+			WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0]
+			is valid.
+			
+			TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
+			WEPSeed[1], pn1}.  Only pn[47:0] is valid.
+			
+			AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
+			pn1, pn0}.  Only pn[47:0] is valid.
+			
+			WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
+			pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
+			pn0}.  pn[127:0] are valid.
+			
+			
+			
+
+pn_63_32
+			
+			
+			
+			
+			Bits [63:32] of the PN number.   See description for
+			pn_31_0.
+			
+			
+			
+
+pn_95_64
+			
+			
+			
+			
+			Bits [95:64] of the PN number.  See description for
+			pn_31_0.
+			
+			
+			
+
+pn_127_96
+			
+			
+			
+			
+			Bits [127:96] of the PN number.  See description for
+			pn_31_0.
+			
+			
+			
+
+peer_meta_data
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Meta data that SW has programmed in the Peer table entry
+			of the transmitting STA.
+			
+			<legal all>
+
+struct rxpt_classify_info rxpt_classify_info_details
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			RXOLE related classification info
+			
+			<legal all
+
+rx_reo_queue_desc_addr_31_0
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			
+			
+			If no Peer entry lookup happened for this frame, the
+			value wil be set to 0, and the frame shall never be pushed
+			to REO entrance ring.
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			
+			
+			If no Peer entry lookup happened for this frame, the
+			value wil be set to 0, and the frame shall never be pushed
+			to REO entrance ring.
+			
+			<legal all>
+
+receive_queue_number
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Indicates the MPDU queue ID to which this MPDU link
+			descriptor belongs
+			
+			Used for tracking and debugging
+			
+			<legal all>
+
+pre_delim_err_warning
+			
+			Indicates that a delimiter FCS error was found in
+			between the Previous MPDU and this MPDU.
+			
+			
+			
+			Note that this is just a warning, and does not mean that
+			this MPDU is corrupted in any way. If it is, there will be
+			other errors indicated such as FCS or decrypt errors
+			
+			
+			
+
+first_delim_err
+			
+			Indicates that the first delimiter had a FCS failure. 
+			Only valid when first_mpdu and first_msdu are set.
+			
+			
+			
+
+reserved_11
+			
+			<legal 0>
+
+key_id_octet
+			
+			
+			
+			
+			The key ID octet from the IV.
+			
+			
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			<legal all>
+
+new_peer_entry
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Set if new RX_PEER_ENTRY TLV follows. If clear,
+			RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
+			uses old peer entry or not decrypt. 
+			
+			<legal all>
+
+decrypt_needed
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Set if decryption is needed. 
+			
+			
+			
+			Note:
+			
+			When RXPCU sets bit 'ast_index_not_found' and/or
+			ast_index_timeout', RXPCU will also ensure that this bit is
+			NOT set
+			
+			CRYPTO for that reason only needs to evaluate this bit
+			and non of the other ones.
+			
+			<legal all>
+
+decap_type
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Used by the OLE during decapsulation.
+			
+			
+			
+			Indicates the decapsulation that HW will perform:
+			
+			
+			
+			<enum 0 PTE_DECAP_RAW> No encapsulation
+			
+			<enum 1 PTE_DECAP_Native_WiFi>
+			
+			<enum 2 PTE_DECAP_Ethernet_802_3>  Ethernet 2 (DIX) or
+			802.3 (uses SNAP/LLC)
+			
+			<legal 0-2>
+
+rx_insert_vlan_c_tag_padding
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Insert 4 byte of all zeros as VLAN tag if the rx payload
+			does not have VLAN. Used during decapsulation. 
+			
+			<legal all>
+
+rx_insert_vlan_s_tag_padding
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Insert 4 byte of all zeros as double VLAN tag if the rx
+			payload does not have VLAN. Used during 
+			
+			<legal all>
+
+strip_vlan_c_tag_decap
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Strip the VLAN during decapsulation.  Used by the OLE.
+			
+			<legal all>
+
+strip_vlan_s_tag_decap
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Strip the double VLAN during decapsulation.  Used by
+			the OLE.
+			
+			<legal all>
+
+pre_delim_count
+			
+			The number of delimiters before this MPDU.  
+			
+			
+			
+			In case of ndp or phy_err, this field will be set to 0
+
+ampdu_flag
+			
+			When set, received frame was part of an A-MPDU.
+			
+			
+			
+			
+			<legal all>
+
+bar_frame
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, received frame is a BAR frame
+			
+			<legal all>
+
+reserved_12
+			
+			<legal 0>.
+
+mpdu_length
+			
+			In case of ndp or phy_err this field will be set to 0
+			
+			
+			
+			MPDU length before decapsulation.
+			
+			<legal all>
+
+first_mpdu
+			
+			See definition in RX attention descriptor
+			
+			
+			
+			In case of ndp or phy_err, this field will be set. Note
+			however that there will not actually be any data contents in
+			the MPDU.
+			
+			<legal all>
+
+mcast_bcast
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+ast_index_not_found
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+ast_index_timeout
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+power_mgmt
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+non_qos
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 1
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+null_data
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+mgmt_type
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+ctrl_type
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+more_data
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+eosp
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+fragment_flag
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+order
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			
+			
+			<legal all>
+
+u_apsd_trigger
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+encrypt_required
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+directed
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+
+reserved_13
+			
+			<legal 0>
+
+mpdu_frame_control_field
+			
+			Field only valid when Mpdu_frame_control_valid is set
+			
+			
+			
+			The frame control field of this received MPDU.
+			
+			
+			
+			Field only valid when Ndp_frame and phy_err are NOT set
+			
+			
+			
+			Bytes 0 + 1 of the received MPDU
+			
+			<legal all>
+
+mpdu_duration_field
+			
+			Field only valid when Mpdu_duration_valid is set
+			
+			
+			
+			The duration field of this received MPDU.
+			
+			<legal all>
+
+mac_addr_ad1_31_0
+			
+			Field only valid when mac_addr_ad1_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD1
+			
+			<legal all>
+
+mac_addr_ad1_47_32
+			
+			Field only valid when mac_addr_ad1_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD1
+			
+			<legal all>
+
+mac_addr_ad2_15_0
+			
+			Field only valid when mac_addr_ad2_valid is set
+			
+			
+			
+			The Least Significant 2 bytes of the Received Frames MAC
+			Address AD2
+			
+			<legal all>
+
+mac_addr_ad2_47_16
+			
+			Field only valid when mac_addr_ad2_valid is set
+			
+			
+			
+			The 4 most significant bytes of the Received Frames MAC
+			Address AD2
+			
+			<legal all>
+
+mac_addr_ad3_31_0
+			
+			Field only valid when mac_addr_ad3_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD3
+			
+			<legal all>
+
+mac_addr_ad3_47_32
+			
+			Field only valid when mac_addr_ad3_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD3
+			
+			<legal all>
+
+mpdu_sequence_control_field
+			
+			
+			
+			
+			The sequence control field of the MPDU
+			
+			<legal all>
+
+mac_addr_ad4_31_0
+			
+			Field only valid when mac_addr_ad4_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD4
+			
+			<legal all>
+
+mac_addr_ad4_47_32
+			
+			Field only valid when mac_addr_ad4_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD4
+			
+			<legal all>
+
+mpdu_qos_control_field
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The sequence control field of the MPDU
+			
+			<legal all>
+
+mpdu_ht_control_field
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The HT control field of the MPDU
+			
+			<legal all>
+*/
+
+
+/* Description		RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			
+			
+			Note: for ndp frame, if it was expected because the
+			preceding NDPA was filter_pass, the setting 
+			rxpcu_filter_pass will be used. This setting will also be
+			used for every ndp frame in case Promiscuous mode is
+			enabled.
+			
+			
+			
+			In case promiscuous is not enabled, and an NDP is not
+			preceded by a NPDA filter pass frame, the only other setting
+			that could appear here for the NDP is rxpcu_monitor_other. 
+			
+			(rxpcu has a configuration bit specifically for this
+			scenario)
+			
+			
+			
+			Note: for 
+			
+			<legal 0-2>
+*/
+#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET          0x00000000
+#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB             0
+#define RX_MPDU_INFO_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK            0x00000003
+
+/* Description		RX_MPDU_INFO_0_SW_FRAME_GROUP_ID
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> Note: The
+			corresponding Rxpcu_Mpdu_filter_in_category can be
+			rxpcu_filter_pass or rxpcu_monitor_other
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0 
+			
+			Note: The corresponding Rxpcu_Mpdu_filter_in_category
+			can only be rxpcu_monitor_other
+			
+			
+			
+			
+			Note: The corresponding Rxpcu_Mpdu_filter_in_category
+			can be rxpcu_filter_pass
+			
+			
+			
+			<legal 0-37>
+*/
+#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET                      0x00000000
+#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB                         2
+#define RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK                        0x000001fc
+
+/* Description		RX_MPDU_INFO_0_NDP_FRAME
+			
+			When set, the received frame was an NDP frame, and thus
+			there will be no MPDU data.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_NDP_FRAME_OFFSET                              0x00000000
+#define RX_MPDU_INFO_0_NDP_FRAME_LSB                                 9
+#define RX_MPDU_INFO_0_NDP_FRAME_MASK                                0x00000200
+
+/* Description		RX_MPDU_INFO_0_PHY_ERR
+			
+			When set, a PHY error was received before MAC received
+			any data, and thus there will be no MPDU data.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_PHY_ERR_OFFSET                                0x00000000
+#define RX_MPDU_INFO_0_PHY_ERR_LSB                                   10
+#define RX_MPDU_INFO_0_PHY_ERR_MASK                                  0x00000400
+
+/* Description		RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER
+			
+			When set, a PHY error was received before MAC received
+			the complete MPDU header which was needed for proper
+			decoding
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_OFFSET             0x00000000
+#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_LSB                11
+#define RX_MPDU_INFO_0_PHY_ERR_DURING_MPDU_HEADER_MASK               0x00000800
+
+/* Description		RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR
+			
+			Set when RXPCU detected a version error in the Frame
+			control field
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_OFFSET                   0x00000000
+#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_LSB                      12
+#define RX_MPDU_INFO_0_PROTOCOL_VERSION_ERR_MASK                     0x00001000
+
+/* Description		RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID
+			
+			When set, AST based lookup for this frame has found a
+			valid result.
+			
+			
+			
+			Note that for NDP frame this will never be set
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_OFFSET                 0x00000000
+#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_LSB                    13
+#define RX_MPDU_INFO_0_AST_BASED_LOOKUP_VALID_MASK                   0x00002000
+
+/* Description		RX_MPDU_INFO_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define RX_MPDU_INFO_0_RESERVED_0A_OFFSET                            0x00000000
+#define RX_MPDU_INFO_0_RESERVED_0A_LSB                               14
+#define RX_MPDU_INFO_0_RESERVED_0A_MASK                              0x0000c000
+
+/* Description		RX_MPDU_INFO_0_PHY_PPDU_ID
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_0_PHY_PPDU_ID_OFFSET                            0x00000000
+#define RX_MPDU_INFO_0_PHY_PPDU_ID_LSB                               16
+#define RX_MPDU_INFO_0_PHY_PPDU_ID_MASK                              0xffff0000
+
+/* Description		RX_MPDU_INFO_1_AST_INDEX
+			
+			This field indicates the index of the AST entry
+			corresponding to this MPDU. It is provided by the GSE module
+			instantiated in RXPCU.
+			
+			A value of 0xFFFF indicates an invalid AST index,
+			meaning that No AST entry was found or NO AST search was
+			performed
+			
+			
+			
+			In case of ndp or phy_err, this field will be set to
+			0xFFFF
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_1_AST_INDEX_OFFSET                              0x00000004
+#define RX_MPDU_INFO_1_AST_INDEX_LSB                                 0
+#define RX_MPDU_INFO_1_AST_INDEX_MASK                                0x0000ffff
+
+/* Description		RX_MPDU_INFO_1_SW_PEER_ID
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			This field indicates a unique peer identifier. It is set
+			equal to field 'sw_peer_id' from the AST entry
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_1_SW_PEER_ID_OFFSET                             0x00000004
+#define RX_MPDU_INFO_1_SW_PEER_ID_LSB                                16
+#define RX_MPDU_INFO_1_SW_PEER_ID_MASK                               0xffff0000
+
+/* Description		RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID
+			
+			When set, the field Mpdu_Frame_control_field has valid
+			information
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_OFFSET               0x00000008
+#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_LSB                  0
+#define RX_MPDU_INFO_2_MPDU_FRAME_CONTROL_VALID_MASK                 0x00000001
+
+/* Description		RX_MPDU_INFO_2_MPDU_DURATION_VALID
+			
+			When set, the field Mpdu_duration_field has valid
+			information
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_OFFSET                    0x00000008
+#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_LSB                       1
+#define RX_MPDU_INFO_2_MPDU_DURATION_VALID_MASK                      0x00000002
+
+/* Description		RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID
+			
+			When set, the fields mac_addr_ad1_..... have valid
+			information
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_OFFSET                     0x00000008
+#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_LSB                        2
+#define RX_MPDU_INFO_2_MAC_ADDR_AD1_VALID_MASK                       0x00000004
+
+/* Description		RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID
+			
+			When set, the fields mac_addr_ad2_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_OFFSET                     0x00000008
+#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_LSB                        3
+#define RX_MPDU_INFO_2_MAC_ADDR_AD2_VALID_MASK                       0x00000008
+
+/* Description		RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID
+			
+			When set, the fields mac_addr_ad3_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_OFFSET                     0x00000008
+#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_LSB                        4
+#define RX_MPDU_INFO_2_MAC_ADDR_AD3_VALID_MASK                       0x00000010
+
+/* Description		RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID
+			
+			When set, the fields mac_addr_ad4_..... have valid
+			information
+			
+			
+			
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_OFFSET                     0x00000008
+#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_LSB                        5
+#define RX_MPDU_INFO_2_MAC_ADDR_AD4_VALID_MASK                       0x00000020
+
+/* Description		RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID
+			
+			When set, the fields mpdu_sequence_control_field and
+			mpdu_sequence_number have valid information as well as field
+			
+			
+			
+			For MPDUs without a sequence control field, this field
+			will not be set.
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_OFFSET            0x00000008
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_LSB               6
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_CONTROL_VALID_MASK              0x00000040
+
+/* Description		RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID
+			
+			When set, the field mpdu_qos_control_field has valid
+			information
+			
+			
+			
+			For MPDUs without a QoS control field, this field will
+			not be set.
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET                 0x00000008
+#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB                    7
+#define RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK                   0x00000080
+
+/* Description		RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID
+			
+			When set, the field mpdu_HT_control_field has valid
+			information
+			
+			
+			
+			For MPDUs without a HT control field, this field will
+			not be set.
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_OFFSET                  0x00000008
+#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_LSB                     8
+#define RX_MPDU_INFO_2_MPDU_HT_CONTROL_VALID_MASK                    0x00000100
+
+/* Description		RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID
+			
+			When set, the encryption related info fields, like IV
+			and PN are valid
+			
+			
+			
+			For MPDUs that are not encrypted, this will not be set.
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_OFFSET            0x00000008
+#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_LSB               9
+#define RX_MPDU_INFO_2_FRAME_ENCRYPTION_INFO_VALID_MASK              0x00000200
+
+/* Description		RX_MPDU_INFO_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET                            0x00000008
+#define RX_MPDU_INFO_2_RESERVED_2A_LSB                               10
+#define RX_MPDU_INFO_2_RESERVED_2A_MASK                              0x0000fc00
+
+/* Description		RX_MPDU_INFO_2_FR_DS
+			
+			Field only valid when Mpdu_frame_control_valid is set
+			
+			
+			
+			Set if the from DS bit is set in the frame control.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_FR_DS_OFFSET                                  0x00000008
+#define RX_MPDU_INFO_2_FR_DS_LSB                                     16
+#define RX_MPDU_INFO_2_FR_DS_MASK                                    0x00010000
+
+/* Description		RX_MPDU_INFO_2_TO_DS
+			
+			Field only valid when Mpdu_frame_control_valid is set 
+			
+			
+			
+			Set if the to DS bit is set in the frame control.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_TO_DS_OFFSET                                  0x00000008
+#define RX_MPDU_INFO_2_TO_DS_LSB                                     17
+#define RX_MPDU_INFO_2_TO_DS_MASK                                    0x00020000
+
+/* Description		RX_MPDU_INFO_2_ENCRYPTED
+			
+			Field only valid when Mpdu_frame_control_valid is set.
+			
+			
+			
+			Protected bit from the frame control.  
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_ENCRYPTED_OFFSET                              0x00000008
+#define RX_MPDU_INFO_2_ENCRYPTED_LSB                                 18
+#define RX_MPDU_INFO_2_ENCRYPTED_MASK                                0x00040000
+
+/* Description		RX_MPDU_INFO_2_MPDU_RETRY
+			
+			Field only valid when Mpdu_frame_control_valid is set.
+			
+			
+			
+			Retry bit from the frame control.  Only valid when
+			first_msdu is set.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_RETRY_OFFSET                             0x00000008
+#define RX_MPDU_INFO_2_MPDU_RETRY_LSB                                19
+#define RX_MPDU_INFO_2_MPDU_RETRY_MASK                               0x00080000
+
+/* Description		RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER
+			
+			Field only valid when Mpdu_sequence_control_valid is
+			set.
+			
+			
+			
+			The sequence number from the 802.11 header.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_OFFSET                   0x00000008
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_LSB                      20
+#define RX_MPDU_INFO_2_MPDU_SEQUENCE_NUMBER_MASK                     0xfff00000
+
+/* Description		RX_MPDU_INFO_3_EPD_EN
+			
+			Field only valid when AST_based_lookup_valid == 1.
+			
+			
+			
+			
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			If set to one use EPD instead of LPD
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_EPD_EN_OFFSET                                 0x0000000c
+#define RX_MPDU_INFO_3_EPD_EN_LSB                                    0
+#define RX_MPDU_INFO_3_EPD_EN_MASK                                   0x00000001
+
+/* Description		RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, all frames (data only ?) shall be encrypted.
+			If not, RX CRYPTO shall set an error flag.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET          0x0000000c
+#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB             1
+#define RX_MPDU_INFO_3_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK            0x00000002
+
+/* Description		RX_MPDU_INFO_3_ENCRYPT_TYPE
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Indicates type of decrypt cipher used (as defined in the
+			peer entry)
+			
+			
+			
+			<enum 0 wep_40> WEP 40-bit
+			
+			<enum 1 wep_104> WEP 104-bit
+			
+			<enum 2 tkip_no_mic> TKIP without MIC
+			
+			<enum 3 wep_128> WEP 128-bit
+			
+			<enum 4 tkip_with_mic> TKIP with MIC
+			
+			<enum 5 wapi> WAPI
+			
+			<enum 6 aes_ccmp_128> AES CCMP 128
+			
+			<enum 7 no_cipher> No crypto
+			
+			<enum 8 aes_ccmp_256> AES CCMP 256
+			
+			<enum 9 aes_gcmp_128> AES CCMP 128
+			
+			<enum 10 aes_gcmp_256> AES CCMP 256
+			
+			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
+			
+			
+			
+			
+			<legal 0-11>
+*/
+#define RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET                           0x0000000c
+#define RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB                              2
+#define RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK                             0x0000003c
+
+/* Description		RX_MPDU_INFO_3_MESH_STA
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, this is a Mesh (11s) STA
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_MESH_STA_OFFSET                               0x0000000c
+#define RX_MPDU_INFO_3_MESH_STA_LSB                                  6
+#define RX_MPDU_INFO_3_MESH_STA_MASK                                 0x00000040
+
+/* Description		RX_MPDU_INFO_3_BSSID_HIT
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, the BSSID of the incoming frame matched one of
+			the 8 BSSID register values
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_BSSID_HIT_OFFSET                              0x0000000c
+#define RX_MPDU_INFO_3_BSSID_HIT_LSB                                 7
+#define RX_MPDU_INFO_3_BSSID_HIT_MASK                                0x00000080
+
+/* Description		RX_MPDU_INFO_3_BSSID_NUMBER
+			
+			Field only valid when bssid_hit is set.
+			
+			
+			
+			This number indicates which one out of the 8 BSSID
+			register values matched the incoming frame
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_BSSID_NUMBER_OFFSET                           0x0000000c
+#define RX_MPDU_INFO_3_BSSID_NUMBER_LSB                              8
+#define RX_MPDU_INFO_3_BSSID_NUMBER_MASK                             0x00000f00
+
+/* Description		RX_MPDU_INFO_3_TID
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The TID field in the QoS control field
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_3_TID_OFFSET                                    0x0000000c
+#define RX_MPDU_INFO_3_TID_LSB                                       12
+#define RX_MPDU_INFO_3_TID_MASK                                      0x0000f000
+
+/* Description		RX_MPDU_INFO_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define RX_MPDU_INFO_3_RESERVED_3A_OFFSET                            0x0000000c
+#define RX_MPDU_INFO_3_RESERVED_3A_LSB                               16
+#define RX_MPDU_INFO_3_RESERVED_3A_MASK                              0xffff0000
+
+/* Description		RX_MPDU_INFO_4_PN_31_0
+			
+			
+			
+			
+			
+			WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0]
+			is valid.
+			
+			TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0,
+			WEPSeed[1], pn1}.  Only pn[47:0] is valid.
+			
+			AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0,
+			pn1, pn0}.  Only pn[47:0] is valid.
+			
+			WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12,
+			pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1,
+			pn0}.  pn[127:0] are valid.
+			
+			
+			
+*/
+#define RX_MPDU_INFO_4_PN_31_0_OFFSET                                0x00000010
+#define RX_MPDU_INFO_4_PN_31_0_LSB                                   0
+#define RX_MPDU_INFO_4_PN_31_0_MASK                                  0xffffffff
+
+/* Description		RX_MPDU_INFO_5_PN_63_32
+			
+			
+			
+			
+			Bits [63:32] of the PN number.   See description for
+			pn_31_0.
+			
+			
+			
+*/
+#define RX_MPDU_INFO_5_PN_63_32_OFFSET                               0x00000014
+#define RX_MPDU_INFO_5_PN_63_32_LSB                                  0
+#define RX_MPDU_INFO_5_PN_63_32_MASK                                 0xffffffff
+
+/* Description		RX_MPDU_INFO_6_PN_95_64
+			
+			
+			
+			
+			Bits [95:64] of the PN number.  See description for
+			pn_31_0.
+			
+			
+			
+*/
+#define RX_MPDU_INFO_6_PN_95_64_OFFSET                               0x00000018
+#define RX_MPDU_INFO_6_PN_95_64_LSB                                  0
+#define RX_MPDU_INFO_6_PN_95_64_MASK                                 0xffffffff
+
+/* Description		RX_MPDU_INFO_7_PN_127_96
+			
+			
+			
+			
+			Bits [127:96] of the PN number.  See description for
+			pn_31_0.
+			
+			
+			
+*/
+#define RX_MPDU_INFO_7_PN_127_96_OFFSET                              0x0000001c
+#define RX_MPDU_INFO_7_PN_127_96_LSB                                 0
+#define RX_MPDU_INFO_7_PN_127_96_MASK                                0xffffffff
+
+/* Description		RX_MPDU_INFO_8_PEER_META_DATA
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Meta data that SW has programmed in the Peer table entry
+			of the transmitting STA.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET                         0x00000020
+#define RX_MPDU_INFO_8_PEER_META_DATA_LSB                            0
+#define RX_MPDU_INFO_8_PEER_META_DATA_MASK                           0xffffffff
+#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_OFFSET 0x00000024
+#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_LSB 0
+#define RX_MPDU_INFO_9_RXPT_CLASSIFY_INFO_RXPT_CLASSIFY_INFO_DETAILS_MASK 0xffffffff
+
+/* Description		RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			
+			
+			If no Peer entry lookup happened for this frame, the
+			value wil be set to 0, and the frame shall never be pushed
+			to REO entrance ring.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET           0x00000028
+#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_LSB              0
+#define RX_MPDU_INFO_10_RX_REO_QUEUE_DESC_ADDR_31_0_MASK             0xffffffff
+
+/* Description		RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			
+			
+			If no Peer entry lookup happened for this frame, the
+			value wil be set to 0, and the frame shall never be pushed
+			to REO entrance ring.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET          0x0000002c
+#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_LSB             0
+#define RX_MPDU_INFO_11_RX_REO_QUEUE_DESC_ADDR_39_32_MASK            0x000000ff
+
+/* Description		RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Indicates the MPDU queue ID to which this MPDU link
+			descriptor belongs
+			
+			Used for tracking and debugging
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_OFFSET                  0x0000002c
+#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_LSB                     8
+#define RX_MPDU_INFO_11_RECEIVE_QUEUE_NUMBER_MASK                    0x00ffff00
+
+/* Description		RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING
+			
+			Indicates that a delimiter FCS error was found in
+			between the Previous MPDU and this MPDU.
+			
+			
+			
+			Note that this is just a warning, and does not mean that
+			this MPDU is corrupted in any way. If it is, there will be
+			other errors indicated such as FCS or decrypt errors
+			
+			
+			
+*/
+#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_OFFSET                 0x0000002c
+#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_LSB                    24
+#define RX_MPDU_INFO_11_PRE_DELIM_ERR_WARNING_MASK                   0x01000000
+
+/* Description		RX_MPDU_INFO_11_FIRST_DELIM_ERR
+			
+			Indicates that the first delimiter had a FCS failure. 
+			Only valid when first_mpdu and first_msdu are set.
+			
+			
+			
+*/
+#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_OFFSET                       0x0000002c
+#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_LSB                          25
+#define RX_MPDU_INFO_11_FIRST_DELIM_ERR_MASK                         0x02000000
+
+/* Description		RX_MPDU_INFO_11_RESERVED_11
+			
+			<legal 0>
+*/
+#define RX_MPDU_INFO_11_RESERVED_11_OFFSET                           0x0000002c
+#define RX_MPDU_INFO_11_RESERVED_11_LSB                              26
+#define RX_MPDU_INFO_11_RESERVED_11_MASK                             0xfc000000
+
+/* Description		RX_MPDU_INFO_12_KEY_ID_OCTET
+			
+			
+			
+			
+			The key ID octet from the IV.
+			
+			
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET                          0x00000030
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB                             0
+#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK                            0x000000ff
+
+/* Description		RX_MPDU_INFO_12_NEW_PEER_ENTRY
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Set if new RX_PEER_ENTRY TLV follows. If clear,
+			RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either
+			uses old peer entry or not decrypt. 
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET                        0x00000030
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB                           8
+#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK                          0x00000100
+
+/* Description		RX_MPDU_INFO_12_DECRYPT_NEEDED
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Set if decryption is needed. 
+			
+			
+			
+			Note:
+			
+			When RXPCU sets bit 'ast_index_not_found' and/or
+			ast_index_timeout', RXPCU will also ensure that this bit is
+			NOT set
+			
+			CRYPTO for that reason only needs to evaluate this bit
+			and non of the other ones.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET                        0x00000030
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB                           9
+#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK                          0x00000200
+
+/* Description		RX_MPDU_INFO_12_DECAP_TYPE
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Used by the OLE during decapsulation.
+			
+			
+			
+			Indicates the decapsulation that HW will perform:
+			
+			
+			
+			<enum 0 PTE_DECAP_RAW> No encapsulation
+			
+			<enum 1 PTE_DECAP_Native_WiFi>
+			
+			<enum 2 PTE_DECAP_Ethernet_802_3>  Ethernet 2 (DIX) or
+			802.3 (uses SNAP/LLC)
+			
+			<legal 0-2>
+*/
+#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET                            0x00000030
+#define RX_MPDU_INFO_12_DECAP_TYPE_LSB                               10
+#define RX_MPDU_INFO_12_DECAP_TYPE_MASK                              0x00000c00
+
+/* Description		RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Insert 4 byte of all zeros as VLAN tag if the rx payload
+			does not have VLAN. Used during decapsulation. 
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET          0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB             12
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK            0x00001000
+
+/* Description		RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Insert 4 byte of all zeros as double VLAN tag if the rx
+			payload does not have VLAN. Used during 
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET          0x00000030
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB             13
+#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK            0x00002000
+
+/* Description		RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Strip the VLAN during decapsulation.  Used by the OLE.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET                0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB                   14
+#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK                  0x00004000
+
+/* Description		RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			Strip the double VLAN during decapsulation.  Used by
+			the OLE.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET                0x00000030
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB                   15
+#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK                  0x00008000
+
+/* Description		RX_MPDU_INFO_12_PRE_DELIM_COUNT
+			
+			The number of delimiters before this MPDU.  
+			
+			
+			
+			In case of ndp or phy_err, this field will be set to 0
+*/
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET                       0x00000030
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB                          16
+#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK                         0x0fff0000
+
+/* Description		RX_MPDU_INFO_12_AMPDU_FLAG
+			
+			When set, received frame was part of an A-MPDU.
+			
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET                            0x00000030
+#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB                               28
+#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK                              0x10000000
+
+/* Description		RX_MPDU_INFO_12_BAR_FRAME
+			
+			In case of ndp or phy_err or AST_based_lookup_valid ==
+			0, this field will be set to 0
+			
+			
+			
+			When set, received frame is a BAR frame
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET                             0x00000030
+#define RX_MPDU_INFO_12_BAR_FRAME_LSB                                29
+#define RX_MPDU_INFO_12_BAR_FRAME_MASK                               0x20000000
+
+/* Description		RX_MPDU_INFO_12_RESERVED_12
+			
+			<legal 0>.
+*/
+#define RX_MPDU_INFO_12_RESERVED_12_OFFSET                           0x00000030
+#define RX_MPDU_INFO_12_RESERVED_12_LSB                              30
+#define RX_MPDU_INFO_12_RESERVED_12_MASK                             0xc0000000
+
+/* Description		RX_MPDU_INFO_13_MPDU_LENGTH
+			
+			In case of ndp or phy_err this field will be set to 0
+			
+			
+			
+			MPDU length before decapsulation.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB                              0
+#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK                             0x00003fff
+
+/* Description		RX_MPDU_INFO_13_FIRST_MPDU
+			
+			See definition in RX attention descriptor
+			
+			
+			
+			In case of ndp or phy_err, this field will be set. Note
+			however that there will not actually be any data contents in
+			the MPDU.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET                            0x00000034
+#define RX_MPDU_INFO_13_FIRST_MPDU_LSB                               14
+#define RX_MPDU_INFO_13_FIRST_MPDU_MASK                              0x00004000
+
+/* Description		RX_MPDU_INFO_13_MCAST_BCAST
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_MCAST_BCAST_LSB                              15
+#define RX_MPDU_INFO_13_MCAST_BCAST_MASK                             0x00008000
+
+/* Description		RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET                   0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB                      16
+#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK                     0x00010000
+
+/* Description		RX_MPDU_INFO_13_AST_INDEX_TIMEOUT
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET                     0x00000034
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB                        17
+#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK                       0x00020000
+
+/* Description		RX_MPDU_INFO_13_POWER_MGMT
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET                            0x00000034
+#define RX_MPDU_INFO_13_POWER_MGMT_LSB                               18
+#define RX_MPDU_INFO_13_POWER_MGMT_MASK                              0x00040000
+
+/* Description		RX_MPDU_INFO_13_NON_QOS
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 1
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_NON_QOS_OFFSET                               0x00000034
+#define RX_MPDU_INFO_13_NON_QOS_LSB                                  19
+#define RX_MPDU_INFO_13_NON_QOS_MASK                                 0x00080000
+
+/* Description		RX_MPDU_INFO_13_NULL_DATA
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_NULL_DATA_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_NULL_DATA_LSB                                20
+#define RX_MPDU_INFO_13_NULL_DATA_MASK                               0x00100000
+
+/* Description		RX_MPDU_INFO_13_MGMT_TYPE
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_MGMT_TYPE_LSB                                21
+#define RX_MPDU_INFO_13_MGMT_TYPE_MASK                               0x00200000
+
+/* Description		RX_MPDU_INFO_13_CTRL_TYPE
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_CTRL_TYPE_LSB                                22
+#define RX_MPDU_INFO_13_CTRL_TYPE_MASK                               0x00400000
+
+/* Description		RX_MPDU_INFO_13_MORE_DATA
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_MORE_DATA_OFFSET                             0x00000034
+#define RX_MPDU_INFO_13_MORE_DATA_LSB                                23
+#define RX_MPDU_INFO_13_MORE_DATA_MASK                               0x00800000
+
+/* Description		RX_MPDU_INFO_13_EOSP
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_EOSP_OFFSET                                  0x00000034
+#define RX_MPDU_INFO_13_EOSP_LSB                                     24
+#define RX_MPDU_INFO_13_EOSP_MASK                                    0x01000000
+
+/* Description		RX_MPDU_INFO_13_FRAGMENT_FLAG
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET                         0x00000034
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB                            25
+#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK                           0x02000000
+
+/* Description		RX_MPDU_INFO_13_ORDER
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_ORDER_OFFSET                                 0x00000034
+#define RX_MPDU_INFO_13_ORDER_LSB                                    26
+#define RX_MPDU_INFO_13_ORDER_MASK                                   0x04000000
+
+/* Description		RX_MPDU_INFO_13_U_APSD_TRIGGER
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET                        0x00000034
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB                           27
+#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK                          0x08000000
+
+/* Description		RX_MPDU_INFO_13_ENCRYPT_REQUIRED
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET                      0x00000034
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB                         28
+#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK                        0x10000000
+
+/* Description		RX_MPDU_INFO_13_DIRECTED
+			
+			In case of ndp or phy_err or Phy_err_during_mpdu_header
+			this field will be set to 0
+			
+			
+			
+			See definition in RX attention descriptor
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_13_DIRECTED_OFFSET                              0x00000034
+#define RX_MPDU_INFO_13_DIRECTED_LSB                                 29
+#define RX_MPDU_INFO_13_DIRECTED_MASK                                0x20000000
+
+/* Description		RX_MPDU_INFO_13_RESERVED_13
+			
+			<legal 0>
+*/
+#define RX_MPDU_INFO_13_RESERVED_13_OFFSET                           0x00000034
+#define RX_MPDU_INFO_13_RESERVED_13_LSB                              30
+#define RX_MPDU_INFO_13_RESERVED_13_MASK                             0xc0000000
+
+/* Description		RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD
+			
+			Field only valid when Mpdu_frame_control_valid is set
+			
+			
+			
+			The frame control field of this received MPDU.
+			
+			
+			
+			Field only valid when Ndp_frame and phy_err are NOT set
+			
+			
+			
+			Bytes 0 + 1 of the received MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET              0x00000038
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB                 0
+#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK                0x0000ffff
+
+/* Description		RX_MPDU_INFO_14_MPDU_DURATION_FIELD
+			
+			Field only valid when Mpdu_duration_valid is set
+			
+			
+			
+			The duration field of this received MPDU.
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET                   0x00000038
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB                      16
+#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK                     0xffff0000
+
+/* Description		RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0
+			
+			Field only valid when mac_addr_ad1_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD1
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET                     0x0000003c
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB                        0
+#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK                       0xffffffff
+
+/* Description		RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32
+			
+			Field only valid when mac_addr_ad1_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD1
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET                    0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB                       0
+#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK                      0x0000ffff
+
+/* Description		RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0
+			
+			Field only valid when mac_addr_ad2_valid is set
+			
+			
+			
+			The Least Significant 2 bytes of the Received Frames MAC
+			Address AD2
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET                     0x00000040
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB                        16
+#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK                       0xffff0000
+
+/* Description		RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16
+			
+			Field only valid when mac_addr_ad2_valid is set
+			
+			
+			
+			The 4 most significant bytes of the Received Frames MAC
+			Address AD2
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET                    0x00000044
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB                       0
+#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK                      0xffffffff
+
+/* Description		RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0
+			
+			Field only valid when mac_addr_ad3_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD3
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET                     0x00000048
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB                        0
+#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK                       0xffffffff
+
+/* Description		RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32
+			
+			Field only valid when mac_addr_ad3_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD3
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET                    0x0000004c
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB                       0
+#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK                      0x0000ffff
+
+/* Description		RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD
+			
+			
+			
+			
+			The sequence control field of the MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET           0x0000004c
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB              16
+#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK             0xffff0000
+
+/* Description		RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0
+			
+			Field only valid when mac_addr_ad4_valid is set
+			
+			
+			
+			The Least Significant 4 bytes of the Received Frames MAC
+			Address AD4
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET                     0x00000050
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB                        0
+#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK                       0xffffffff
+
+/* Description		RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32
+			
+			Field only valid when mac_addr_ad4_valid is set
+			
+			
+			
+			The 2 most significant bytes of the Received Frames MAC
+			Address AD4
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET                    0x00000054
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB                       0
+#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK                      0x0000ffff
+
+/* Description		RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The sequence control field of the MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET                0x00000054
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB                   16
+#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK                  0xffff0000
+
+/* Description		RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD
+			
+			Field only valid when mpdu_qos_control_valid is set
+			
+			
+			
+			The HT control field of the MPDU
+			
+			<legal all>
+*/
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET                 0x00000058
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB                    0
+#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK                   0xffffffff
+
+
+#endif // _RX_MPDU_INFO_H_

hw/qca6290/v1/rx_mpdu_link_ptr.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_LINK_PTR_H_
+#define _RX_MPDU_LINK_PTR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info mpdu_link_desc_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2
+
+struct rx_mpdu_link_ptr {
+    struct            buffer_addr_info                       mpdu_link_desc_addr_info;
+};
+
+/*
+
+struct buffer_addr_info mpdu_link_desc_addr_info
+			
+			Details of the physical address of an MPDU link
+			descriptor
+*/
+
+#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
+#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MPDU_LINK_PTR_0_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
+#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MPDU_LINK_PTR_1_BUFFER_ADDR_INFO_MPDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+
+
+#endif // _RX_MPDU_LINK_PTR_H_

hw/qca6290/v1/rx_mpdu_start.h

@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MPDU_START_H_
+#define _RX_MPDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-22	struct rx_mpdu_info rx_mpdu_info_details;
+//	23	raw_mpdu[0], reserved_23[31:1]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MPDU_START 24
+
+struct rx_mpdu_start {
+    struct            rx_mpdu_info                       rx_mpdu_info_details;
+             uint32_t raw_mpdu                        :  1, //[0]
+                      reserved_23                     : 31; //[31:1]
+};
+
+/*
+
+struct rx_mpdu_info rx_mpdu_info_details
+			
+			Structure containing all the MPDU header details that
+			might be needed for other modules further down the received
+			path
+
+raw_mpdu
+			
+			Set by OLE when it has not performed any .11 to .3
+			header conversion on this MPDU.
+			
+			<legal all>
+
+reserved_23
+			
+			<legal 0>
+*/
+
+#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000000
+#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000004
+#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_1_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000008
+#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_2_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x0000000c
+#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_3_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000010
+#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_4_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000014
+#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_5_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000018
+#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_6_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x0000001c
+#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_7_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000020
+#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_8_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET     0x00000024
+#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB        1
+#define RX_MPDU_START_9_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK       0xffffffff
+#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000028
+#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_10_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x0000002c
+#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_11_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000030
+#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_12_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000034
+#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_13_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000038
+#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_14_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x0000003c
+#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_15_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000040
+#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_16_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000044
+#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_17_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000048
+#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_18_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x0000004c
+#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_19_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000050
+#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_20_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000054
+#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_21_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET    0x00000058
+#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_LSB       1
+#define RX_MPDU_START_22_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_MASK      0xffffffff
+
+/* Description		RX_MPDU_START_23_RAW_MPDU
+			
+			Set by OLE when it has not performed any .11 to .3
+			header conversion on this MPDU.
+			
+			<legal all>
+*/
+#define RX_MPDU_START_23_RAW_MPDU_OFFSET                             0x0000005c
+#define RX_MPDU_START_23_RAW_MPDU_LSB                                0
+#define RX_MPDU_START_23_RAW_MPDU_MASK                               0x00000001
+
+/* Description		RX_MPDU_START_23_RESERVED_23
+			
+			<legal 0>
+*/
+#define RX_MPDU_START_23_RESERVED_23_OFFSET                          0x0000005c
+#define RX_MPDU_START_23_RESERVED_23_LSB                             1
+#define RX_MPDU_START_23_RESERVED_23_MASK                            0xfffffffe
+
+
+#endif // _RX_MPDU_START_H_

hw/qca6290/v1/rx_msdu_desc_info.h

@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MSDU_DESC_INFO_H_
+#define _RX_MSDU_DESC_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], reserved_0a[31:28]
+//	1	reserved_1a[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2
+
+struct rx_msdu_desc_info {
+             uint32_t first_msdu_in_mpdu_flag         :  1, //[0]
+                      last_msdu_in_mpdu_flag          :  1, //[1]
+                      msdu_continuation               :  1, //[2]
+                      msdu_length                     : 14, //[16:3]
+                      reo_destination_indication      :  5, //[21:17]
+                      msdu_drop                       :  1, //[22]
+                      sa_is_valid                     :  1, //[23]
+                      sa_idx_timeout                  :  1, //[24]
+                      da_is_valid                     :  1, //[25]
+                      da_is_mcbc                      :  1, //[26]
+                      da_idx_timeout                  :  1, //[27]
+                      reserved_0a                     :  4; //[31:28]
+             uint32_t reserved_1a                     : 32; //[31:0]
+};
+
+/*
+
+first_msdu_in_mpdu_flag
+			
+			<enum 0 Not_first_msdu> This is not the first MSDU in
+			the MPDU. 
+			
+			<enum 1 first_msdu> This MSDU is the first one in the
+			MPDU. <legal all>
+
+last_msdu_in_mpdu_flag
+			
+			Consumer: WBM/REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			
+			
+			<enum 0 Not_last_msdu> There are more MSDUs linked to
+			this MSDU that belongs to this MPDU 
+			
+			<enum 1 Last_msdu> this MSDU is the last one in the
+			MPDU. This setting is only allowed in combination with
+			'Msdu_continuation' set to 0. This implies that when an msdu
+			is spread out over multiple buffers and thus
+			msdu_continuation is set, only for the very last buffer of
+			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+			
+			
+			
+			When both first_msdu_in_mpdu_flag and
+			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+			belongs to only contains a single MSDU.
+			
+			<legal all>
+
+msdu_continuation
+			
+			When set, this MSDU buffer was not able to hold the
+			entire MSDU. The next buffer will therefor contain
+			additional information related to this MSDU.
+			
+			
+			
+			<legal all>
+
+msdu_length
+			
+			Field is only valid in combination with the
+			'first_msdu_in_mpdu_flag ' being set. When the
+			'first_msdu_in_mpdu_flag ' is not set, this field shall be
+			0.
+			
+			
+			
+			Full MSDU length in bytes after decapsulation. 
+			
+			
+			
+			This field is still valid for MPDU frames without
+			A-MSDU.  It still represents MSDU length after decapsulation
+			
+			
+			
+			Or in case of RAW MPDUs, it indicates the length of the
+			entire MPDU (without FCS field)
+			
+			<legal all>
+
+reo_destination_indication
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+msdu_drop
+			
+			When set, REO shall drop this MSDU and not forward it to
+			any other ring...
+			
+			<legal all>
+
+sa_is_valid
+			
+			Indicates that OLE found a valid SA entry for this MSDU
+			
+			<legal all>
+
+sa_idx_timeout
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer for this MSDU
+			
+			<legal all>
+
+da_is_valid
+			
+			Indicates that OLE found a valid DA entry for this MSDU
+			
+			<legal all>
+
+da_is_mcbc
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address for this MSDU
+			
+			<legal all>
+
+da_idx_timeout
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer for this MSDU
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+
+reserved_1a
+			
+			<legal 0>
+*/
+
+
+/* Description		RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG
+			
+			<enum 0 Not_first_msdu> This is not the first MSDU in
+			the MPDU. 
+			
+			<enum 1 first_msdu> This MSDU is the first one in the
+			MPDU. <legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET           0x00000000
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB              0
+#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK             0x00000001
+
+/* Description		RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG
+			
+			Consumer: WBM/REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			
+			
+			<enum 0 Not_last_msdu> There are more MSDUs linked to
+			this MSDU that belongs to this MPDU 
+			
+			<enum 1 Last_msdu> this MSDU is the last one in the
+			MPDU. This setting is only allowed in combination with
+			'Msdu_continuation' set to 0. This implies that when an msdu
+			is spread out over multiple buffers and thus
+			msdu_continuation is set, only for the very last buffer of
+			the msdu, can the 'last_msdu_in_mpdu_flag' be set.
+			
+			
+			
+			When both first_msdu_in_mpdu_flag and
+			last_msdu_in_mpdu_flag are set, the MPDU that this MSDU
+			belongs to only contains a single MSDU.
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET            0x00000000
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB               1
+#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK              0x00000002
+
+/* Description		RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION
+			
+			When set, this MSDU buffer was not able to hold the
+			entire MSDU. The next buffer will therefor contain
+			additional information related to this MSDU.
+			
+			
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET                 0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB                    2
+#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK                   0x00000004
+
+/* Description		RX_MSDU_DESC_INFO_0_MSDU_LENGTH
+			
+			Field is only valid in combination with the
+			'first_msdu_in_mpdu_flag ' being set. When the
+			'first_msdu_in_mpdu_flag ' is not set, this field shall be
+			0.
+			
+			
+			
+			Full MSDU length in bytes after decapsulation. 
+			
+			
+			
+			This field is still valid for MPDU frames without
+			A-MSDU.  It still represents MSDU length after decapsulation
+			
+			
+			
+			Or in case of RAW MPDUs, it indicates the length of the
+			entire MPDU (without FCS field)
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB                          3
+#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK                         0x0001fff8
+
+/* Description		RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET        0x00000000
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB           17
+#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK          0x003e0000
+
+/* Description		RX_MSDU_DESC_INFO_0_MSDU_DROP
+			
+			When set, REO shall drop this MSDU and not forward it to
+			any other ring...
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET                         0x00000000
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB                            22
+#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK                           0x00400000
+
+/* Description		RX_MSDU_DESC_INFO_0_SA_IS_VALID
+			
+			Indicates that OLE found a valid SA entry for this MSDU
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB                          23
+#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK                         0x00800000
+
+/* Description		RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer for this MSDU
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB                       24
+#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK                      0x01000000
+
+/* Description		RX_MSDU_DESC_INFO_0_DA_IS_VALID
+			
+			Indicates that OLE found a valid DA entry for this MSDU
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB                          25
+#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK                         0x02000000
+
+/* Description		RX_MSDU_DESC_INFO_0_DA_IS_MCBC
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address for this MSDU
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET                        0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB                           26
+#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK                          0x04000000
+
+/* Description		RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer for this MSDU
+			
+			<legal all>
+*/
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET                    0x00000000
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB                       27
+#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK                      0x08000000
+
+/* Description		RX_MSDU_DESC_INFO_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define RX_MSDU_DESC_INFO_0_RESERVED_0A_OFFSET                       0x00000000
+#define RX_MSDU_DESC_INFO_0_RESERVED_0A_LSB                          28
+#define RX_MSDU_DESC_INFO_0_RESERVED_0A_MASK                         0xf0000000
+
+/* Description		RX_MSDU_DESC_INFO_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define RX_MSDU_DESC_INFO_1_RESERVED_1A_OFFSET                       0x00000004
+#define RX_MSDU_DESC_INFO_1_RESERVED_1A_LSB                          0
+#define RX_MSDU_DESC_INFO_1_RESERVED_1A_MASK                         0xffffffff
+
+
+#endif // _RX_MSDU_DESC_INFO_H_

hw/qca6290/v1/rx_msdu_details.h

@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MSDU_DETAILS_H_
+#define _RX_MSDU_DETAILS_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_msdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info buffer_addr_info_details;
+//	2-3	struct rx_msdu_desc_info rx_msdu_desc_info_details;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4
+
+struct rx_msdu_details {
+    struct            buffer_addr_info                       buffer_addr_info_details;
+    struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
+};
+
+/*
+
+struct buffer_addr_info buffer_addr_info_details
+			
+			Consumer: REO/SW
+			
+			Producer: RXDMA
+			
+			
+			
+			Details of the physical address of the buffer containing
+			an MSDU (or entire MPDU)
+
+struct rx_msdu_desc_info rx_msdu_desc_info_details
+			
+			Consumer: REO/SW
+			
+			Producer: RXDMA
+			
+			
+			
+			General information related to the MSDU that should be
+			passed on from RXDMA all the way to to the REO destination
+			ring.
+*/
+
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000000
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0
+#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_OFFSET 0x00000004
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_LSB 0
+#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_BUFFER_ADDR_INFO_DETAILS_MASK 0xffffffff
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000008
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0
+#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 0
+#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+
+
+#endif // _RX_MSDU_DETAILS_H_

hw/qca6290/v1/rx_msdu_end.h

@@ -0,0 +1,1238 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MSDU_END_H_
+#define _RX_MSDU_END_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+//	1	ip_hdr_chksum[15:0], tcp_udp_chksum[31:16]
+//	2	key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], ext_wapi_pn_63_48[31:16]
+//	3	ext_wapi_pn_95_64[31:0]
+//	4	ext_wapi_pn_127_96[31:0]
+//	5	reported_mpdu_length[13:0], first_msdu[14], last_msdu[15], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], reserved_5a[31:26]
+//	6	ipv6_options_crc[31:0]
+//	7	tcp_seq_number[31:0]
+//	8	tcp_ack_number[31:0]
+//	9	tcp_flag[8:0], lro_eligible[9], l3_header_padding[12:10], reserved_9a[15:13], window_size[31:16]
+//	10	da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], type_offset[20:14], reserved_10a[31:21]
+//	11	rule_indication_31_0[31:0]
+//	12	rule_indication_63_32[31:0]
+//	13	sa_idx[15:0], da_idx[31:16]
+//	14	msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_14[31:26]
+//	15	fse_metadata[31:0]
+//	16	cce_metadata[15:0], sa_sw_peer_id[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_END 17
+
+struct rx_msdu_end {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
+                      sw_frame_group_id               :  7, //[8:2]
+                      reserved_0                      :  7, //[15:9]
+                      phy_ppdu_id                     : 16; //[31:16]
+             uint32_t ip_hdr_chksum                   : 16, //[15:0]
+                      tcp_udp_chksum                  : 16; //[31:16]
+             uint32_t key_id_octet                    :  8, //[7:0]
+                      cce_super_rule                  :  6, //[13:8]
+                      cce_classify_not_done_truncate  :  1, //[14]
+                      cce_classify_not_done_cce_dis   :  1, //[15]
+                      ext_wapi_pn_63_48               : 16; //[31:16]
+             uint32_t ext_wapi_pn_95_64               : 32; //[31:0]
+             uint32_t ext_wapi_pn_127_96              : 32; //[31:0]
+             uint32_t reported_mpdu_length            : 14, //[13:0]
+                      first_msdu                      :  1, //[14]
+                      last_msdu                       :  1, //[15]
+                      sa_idx_timeout                  :  1, //[16]
+                      da_idx_timeout                  :  1, //[17]
+                      msdu_limit_error                :  1, //[18]
+                      flow_idx_timeout                :  1, //[19]
+                      flow_idx_invalid                :  1, //[20]
+                      wifi_parser_error               :  1, //[21]
+                      amsdu_parser_error              :  1, //[22]
+                      sa_is_valid                     :  1, //[23]
+                      da_is_valid                     :  1, //[24]
+                      da_is_mcbc                      :  1, //[25]
+                      reserved_5a                     :  6; //[31:26]
+             uint32_t ipv6_options_crc                : 32; //[31:0]
+             uint32_t tcp_seq_number                  : 32; //[31:0]
+             uint32_t tcp_ack_number                  : 32; //[31:0]
+             uint32_t tcp_flag                        :  9, //[8:0]
+                      lro_eligible                    :  1, //[9]
+                      l3_header_padding               :  3, //[12:10]
+                      reserved_9a                     :  3, //[15:13]
+                      window_size                     : 16; //[31:16]
+             uint32_t da_offset                       :  6, //[5:0]
+                      sa_offset                       :  6, //[11:6]
+                      da_offset_valid                 :  1, //[12]
+                      sa_offset_valid                 :  1, //[13]
+                      type_offset                     :  7, //[20:14]
+                      reserved_10a                    : 11; //[31:21]
+             uint32_t rule_indication_31_0            : 32; //[31:0]
+             uint32_t rule_indication_63_32           : 32; //[31:0]
+             uint32_t sa_idx                          : 16, //[15:0]
+                      da_idx                          : 16; //[31:16]
+             uint32_t msdu_drop                       :  1, //[0]
+                      reo_destination_indication      :  5, //[5:1]
+                      flow_idx                        : 20, //[25:6]
+                      reserved_14                     :  6; //[31:26]
+             uint32_t fse_metadata                    : 32; //[31:0]
+             uint32_t cce_metadata                    : 16, //[15:0]
+                      sa_sw_peer_id                   : 16; //[31:16]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+
+sw_frame_group_id
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 >
+			
+			 
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+
+reserved_0
+			
+			<legal 0>
+
+phy_ppdu_id
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+
+ip_hdr_chksum
+			
+			This can include the IP header checksum or the pseudo
+			header checksum used by TCP/UDP checksum.
+
+tcp_udp_chksum
+			
+			The value of the computed TCP/UDP checksum.  A mode bit
+			selects whether this checksum is the full checksum or the
+			partial checksum which does not include the pseudo header. 
+
+key_id_octet
+			
+			The key ID octet from the IV.  Only valid when
+			first_msdu is set.
+
+cce_super_rule
+			
+			Indicates the super filter rule 
+
+cce_classify_not_done_truncate
+			
+			Classification failed due to truncated frame
+
+cce_classify_not_done_cce_dis
+			
+			Classification failed due to CCE global disable
+
+ext_wapi_pn_63_48
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 
+			The WAPI PN bits [63:0] are in the pn field of the
+			rx_mpdu_start descriptor.
+
+ext_wapi_pn_95_64
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
+			and pn11).
+
+ext_wapi_pn_127_96
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
+			pn14, pn15).
+
+reported_mpdu_length
+			
+			MPDU length before decapsulation.  Only valid when
+			first_msdu is set.  This field is taken directly from the
+			length field of the A-MPDU delimiter or the preamble length
+			field for non-A-MPDU frames.
+
+first_msdu
+			
+			Indicates the first MSDU of A-MSDU.  If both first_msdu
+			and last_msdu are set in the MSDU then this is a
+			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
+			A-MSDU shall have both first_mpdu and last_mpdu bits set to
+			0.
+
+last_msdu
+			
+			Indicates the last MSDU of the A-MSDU.  MPDU end status
+			is only valid when last_msdu is set.
+
+sa_idx_timeout
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer.
+
+da_idx_timeout
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer.
+
+msdu_limit_error
+			
+			Indicates that the MSDU threshold was exceeded and thus
+			all the rest of the MSDUs will not be scattered and will not
+			be decapsulated but will be DMA'ed in RAW format as a single
+			MSDU buffer
+
+flow_idx_timeout
+			
+			Indicates an unsuccessful flow search due to the
+			expiring of the search timer.
+			
+			<legal all>
+
+flow_idx_invalid
+			
+			flow id is not valid
+			
+			<legal all>
+
+wifi_parser_error
+			
+			TODO: add details to the description
+			
+			<legal all>
+
+amsdu_parser_error
+			
+			A-MSDU could not be properly de-agregated.
+			
+			<legal all>
+
+sa_is_valid
+			
+			Indicates that OLE found a valid SA entry
+
+da_is_valid
+			
+			Indicates that OLE found a valid DA entry
+
+da_is_mcbc
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address.
+
+reserved_5a
+			
+			<legal 0>
+
+ipv6_options_crc
+			
+			32 bit CRC computed out of  IP v6 extension headers
+
+tcp_seq_number
+			
+			TCP sequence number
+
+tcp_ack_number
+			
+			TCP acknowledge number
+
+tcp_flag
+			
+			TCP flags
+			
+			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
+
+lro_eligible
+			
+			Computed out of TCP and IP fields to indicate that this
+			MSDU is eligible for  LRO
+
+l3_header_padding
+			
+			Number of bytes padded  to make sure that the L3 header
+			will always start of a Dword   boundary
+
+reserved_9a
+			
+			<legal 0>
+
+window_size
+			
+			TCP receive window size
+
+da_offset
+			
+			Offset into MSDU buffer for DA
+
+sa_offset
+			
+			Offset into MSDU buffer for SA
+
+da_offset_valid
+			
+			da_offset field is valid. This will be set to 0 in case
+			of a dynamic A-MSDU when DA is compressed
+
+sa_offset_valid
+			
+			sa_offset field is valid. This will be set to 0 in case
+			of a dynamic A-MSDU when SA is compressed
+
+type_offset
+			
+			Offset into MSDU buffer for Type
+
+reserved_10a
+			
+			<legal 0>
+
+rule_indication_31_0
+			
+			Bitmap indicating which of rules 31-0 have matched
+
+rule_indication_63_32
+			
+			Bitmap indicating which of rules 63-32 have matched
+
+sa_idx
+			
+			The offset in the address table which matches the MAC
+			source address.
+
+da_idx
+			
+			The offset in the address table which matches the MAC
+			source address
+
+msdu_drop
+			
+			When set, REO shall drop this MSDU and not forward it to
+			any other ring...
+			
+			<legal all>
+
+reo_destination_indication
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+flow_idx
+			
+			Flow table index
+			
+			<legal all>
+
+reserved_14
+			
+			<legal 0>
+
+fse_metadata
+			
+			FSE related meta data:
+			
+			<legal all>
+
+cce_metadata
+			
+			CCE related meta data:
+			
+			<legal all>
+
+sa_sw_peer_id
+			
+			sw_peer_id from the address search entry corresponding
+			to the source address of the MSDU
+			
+			<legal 0>
+*/
+
+
+/* Description		RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+*/
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET           0x00000000
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB              0
+#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK             0x00000003
+
+/* Description		RX_MSDU_END_0_SW_FRAME_GROUP_ID
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 >
+			
+			 
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+*/
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET                       0x00000000
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB                          2
+#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK                         0x000001fc
+
+/* Description		RX_MSDU_END_0_RESERVED_0
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_0_RESERVED_0_OFFSET                              0x00000000
+#define RX_MSDU_END_0_RESERVED_0_LSB                                 9
+#define RX_MSDU_END_0_RESERVED_0_MASK                                0x0000fe00
+
+/* Description		RX_MSDU_END_0_PHY_PPDU_ID
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+*/
+#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET                             0x00000000
+#define RX_MSDU_END_0_PHY_PPDU_ID_LSB                                16
+#define RX_MSDU_END_0_PHY_PPDU_ID_MASK                               0xffff0000
+
+/* Description		RX_MSDU_END_1_IP_HDR_CHKSUM
+			
+			This can include the IP header checksum or the pseudo
+			header checksum used by TCP/UDP checksum.
+*/
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET                           0x00000004
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB                              0
+#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK                             0x0000ffff
+
+/* Description		RX_MSDU_END_1_TCP_UDP_CHKSUM
+			
+			The value of the computed TCP/UDP checksum.  A mode bit
+			selects whether this checksum is the full checksum or the
+			partial checksum which does not include the pseudo header. 
+*/
+#define RX_MSDU_END_1_TCP_UDP_CHKSUM_OFFSET                          0x00000004
+#define RX_MSDU_END_1_TCP_UDP_CHKSUM_LSB                             16
+#define RX_MSDU_END_1_TCP_UDP_CHKSUM_MASK                            0xffff0000
+
+/* Description		RX_MSDU_END_2_KEY_ID_OCTET
+			
+			The key ID octet from the IV.  Only valid when
+			first_msdu is set.
+*/
+#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET                            0x00000008
+#define RX_MSDU_END_2_KEY_ID_OCTET_LSB                               0
+#define RX_MSDU_END_2_KEY_ID_OCTET_MASK                              0x000000ff
+
+/* Description		RX_MSDU_END_2_CCE_SUPER_RULE
+			
+			Indicates the super filter rule 
+*/
+#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET                          0x00000008
+#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB                             8
+#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK                            0x00003f00
+
+/* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE
+			
+			Classification failed due to truncated frame
+*/
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET          0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB             14
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK            0x00004000
+
+/* Description		RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS
+			
+			Classification failed due to CCE global disable
+*/
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET           0x00000008
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB              15
+#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK             0x00008000
+
+/* Description		RX_MSDU_END_2_EXT_WAPI_PN_63_48
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [63:48] (pn6 and pn7). 
+			The WAPI PN bits [63:0] are in the pn field of the
+			rx_mpdu_start descriptor.
+*/
+#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_OFFSET                       0x00000008
+#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_LSB                          16
+#define RX_MSDU_END_2_EXT_WAPI_PN_63_48_MASK                         0xffff0000
+
+/* Description		RX_MSDU_END_3_EXT_WAPI_PN_95_64
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [95:64] (pn8, pn9, pn10
+			and pn11).
+*/
+#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_OFFSET                       0x0000000c
+#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_LSB                          0
+#define RX_MSDU_END_3_EXT_WAPI_PN_95_64_MASK                         0xffffffff
+
+/* Description		RX_MSDU_END_4_EXT_WAPI_PN_127_96
+			
+			Extension PN (packet number) which is only used by WAPI.
+			This corresponds to WAPI PN bits [127:96] (pn12, pn13,
+			pn14, pn15).
+*/
+#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_OFFSET                      0x00000010
+#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_LSB                         0
+#define RX_MSDU_END_4_EXT_WAPI_PN_127_96_MASK                        0xffffffff
+
+/* Description		RX_MSDU_END_5_REPORTED_MPDU_LENGTH
+			
+			MPDU length before decapsulation.  Only valid when
+			first_msdu is set.  This field is taken directly from the
+			length field of the A-MPDU delimiter or the preamble length
+			field for non-A-MPDU frames.
+*/
+#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_OFFSET                    0x00000014
+#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_LSB                       0
+#define RX_MSDU_END_5_REPORTED_MPDU_LENGTH_MASK                      0x00003fff
+
+/* Description		RX_MSDU_END_5_FIRST_MSDU
+			
+			Indicates the first MSDU of A-MSDU.  If both first_msdu
+			and last_msdu are set in the MSDU then this is a
+			non-aggregated MSDU frame: normal MPDU.  Interior MSDU in an
+			A-MSDU shall have both first_mpdu and last_mpdu bits set to
+			0.
+*/
+#define RX_MSDU_END_5_FIRST_MSDU_OFFSET                              0x00000014
+#define RX_MSDU_END_5_FIRST_MSDU_LSB                                 14
+#define RX_MSDU_END_5_FIRST_MSDU_MASK                                0x00004000
+
+/* Description		RX_MSDU_END_5_LAST_MSDU
+			
+			Indicates the last MSDU of the A-MSDU.  MPDU end status
+			is only valid when last_msdu is set.
+*/
+#define RX_MSDU_END_5_LAST_MSDU_OFFSET                               0x00000014
+#define RX_MSDU_END_5_LAST_MSDU_LSB                                  15
+#define RX_MSDU_END_5_LAST_MSDU_MASK                                 0x00008000
+
+/* Description		RX_MSDU_END_5_SA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC source address search due
+			to the expiring of the search timer.
+*/
+#define RX_MSDU_END_5_SA_IDX_TIMEOUT_OFFSET                          0x00000014
+#define RX_MSDU_END_5_SA_IDX_TIMEOUT_LSB                             16
+#define RX_MSDU_END_5_SA_IDX_TIMEOUT_MASK                            0x00010000
+
+/* Description		RX_MSDU_END_5_DA_IDX_TIMEOUT
+			
+			Indicates an unsuccessful MAC destination address search
+			due to the expiring of the search timer.
+*/
+#define RX_MSDU_END_5_DA_IDX_TIMEOUT_OFFSET                          0x00000014
+#define RX_MSDU_END_5_DA_IDX_TIMEOUT_LSB                             17
+#define RX_MSDU_END_5_DA_IDX_TIMEOUT_MASK                            0x00020000
+
+/* Description		RX_MSDU_END_5_MSDU_LIMIT_ERROR
+			
+			Indicates that the MSDU threshold was exceeded and thus
+			all the rest of the MSDUs will not be scattered and will not
+			be decapsulated but will be DMA'ed in RAW format as a single
+			MSDU buffer
+*/
+#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_OFFSET                        0x00000014
+#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_LSB                           18
+#define RX_MSDU_END_5_MSDU_LIMIT_ERROR_MASK                          0x00040000
+
+/* Description		RX_MSDU_END_5_FLOW_IDX_TIMEOUT
+			
+			Indicates an unsuccessful flow search due to the
+			expiring of the search timer.
+			
+			<legal all>
+*/
+#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_OFFSET                        0x00000014
+#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_LSB                           19
+#define RX_MSDU_END_5_FLOW_IDX_TIMEOUT_MASK                          0x00080000
+
+/* Description		RX_MSDU_END_5_FLOW_IDX_INVALID
+			
+			flow id is not valid
+			
+			<legal all>
+*/
+#define RX_MSDU_END_5_FLOW_IDX_INVALID_OFFSET                        0x00000014
+#define RX_MSDU_END_5_FLOW_IDX_INVALID_LSB                           20
+#define RX_MSDU_END_5_FLOW_IDX_INVALID_MASK                          0x00100000
+
+/* Description		RX_MSDU_END_5_WIFI_PARSER_ERROR
+			
+			TODO: add details to the description
+			
+			<legal all>
+*/
+#define RX_MSDU_END_5_WIFI_PARSER_ERROR_OFFSET                       0x00000014
+#define RX_MSDU_END_5_WIFI_PARSER_ERROR_LSB                          21
+#define RX_MSDU_END_5_WIFI_PARSER_ERROR_MASK                         0x00200000
+
+/* Description		RX_MSDU_END_5_AMSDU_PARSER_ERROR
+			
+			A-MSDU could not be properly de-agregated.
+			
+			<legal all>
+*/
+#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_OFFSET                      0x00000014
+#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_LSB                         22
+#define RX_MSDU_END_5_AMSDU_PARSER_ERROR_MASK                        0x00400000
+
+/* Description		RX_MSDU_END_5_SA_IS_VALID
+			
+			Indicates that OLE found a valid SA entry
+*/
+#define RX_MSDU_END_5_SA_IS_VALID_OFFSET                             0x00000014
+#define RX_MSDU_END_5_SA_IS_VALID_LSB                                23
+#define RX_MSDU_END_5_SA_IS_VALID_MASK                               0x00800000
+
+/* Description		RX_MSDU_END_5_DA_IS_VALID
+			
+			Indicates that OLE found a valid DA entry
+*/
+#define RX_MSDU_END_5_DA_IS_VALID_OFFSET                             0x00000014
+#define RX_MSDU_END_5_DA_IS_VALID_LSB                                24
+#define RX_MSDU_END_5_DA_IS_VALID_MASK                               0x01000000
+
+/* Description		RX_MSDU_END_5_DA_IS_MCBC
+			
+			Field Only valid if da_is_valid is set
+			
+			
+			
+			Indicates the DA address was a Multicast of Broadcast
+			address.
+*/
+#define RX_MSDU_END_5_DA_IS_MCBC_OFFSET                              0x00000014
+#define RX_MSDU_END_5_DA_IS_MCBC_LSB                                 25
+#define RX_MSDU_END_5_DA_IS_MCBC_MASK                                0x02000000
+
+/* Description		RX_MSDU_END_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_5_RESERVED_5A_OFFSET                             0x00000014
+#define RX_MSDU_END_5_RESERVED_5A_LSB                                26
+#define RX_MSDU_END_5_RESERVED_5A_MASK                               0xfc000000
+
+/* Description		RX_MSDU_END_6_IPV6_OPTIONS_CRC
+			
+			32 bit CRC computed out of  IP v6 extension headers
+*/
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET                        0x00000018
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB                           0
+#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK                          0xffffffff
+
+/* Description		RX_MSDU_END_7_TCP_SEQ_NUMBER
+			
+			TCP sequence number
+*/
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET                          0x0000001c
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB                             0
+#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK                            0xffffffff
+
+/* Description		RX_MSDU_END_8_TCP_ACK_NUMBER
+			
+			TCP acknowledge number
+*/
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET                          0x00000020
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB                             0
+#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK                            0xffffffff
+
+/* Description		RX_MSDU_END_9_TCP_FLAG
+			
+			TCP flags
+			
+			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}
+*/
+#define RX_MSDU_END_9_TCP_FLAG_OFFSET                                0x00000024
+#define RX_MSDU_END_9_TCP_FLAG_LSB                                   0
+#define RX_MSDU_END_9_TCP_FLAG_MASK                                  0x000001ff
+
+/* Description		RX_MSDU_END_9_LRO_ELIGIBLE
+			
+			Computed out of TCP and IP fields to indicate that this
+			MSDU is eligible for  LRO
+*/
+#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET                            0x00000024
+#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB                               9
+#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK                              0x00000200
+
+/* Description		RX_MSDU_END_9_L3_HEADER_PADDING
+			
+			Number of bytes padded  to make sure that the L3 header
+			will always start of a Dword   boundary
+*/
+#define RX_MSDU_END_9_L3_HEADER_PADDING_OFFSET                       0x00000024
+#define RX_MSDU_END_9_L3_HEADER_PADDING_LSB                          10
+#define RX_MSDU_END_9_L3_HEADER_PADDING_MASK                         0x00001c00
+
+/* Description		RX_MSDU_END_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_9_RESERVED_9A_OFFSET                             0x00000024
+#define RX_MSDU_END_9_RESERVED_9A_LSB                                13
+#define RX_MSDU_END_9_RESERVED_9A_MASK                               0x0000e000
+
+/* Description		RX_MSDU_END_9_WINDOW_SIZE
+			
+			TCP receive window size
+*/
+#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET                             0x00000024
+#define RX_MSDU_END_9_WINDOW_SIZE_LSB                                16
+#define RX_MSDU_END_9_WINDOW_SIZE_MASK                               0xffff0000
+
+/* Description		RX_MSDU_END_10_DA_OFFSET
+			
+			Offset into MSDU buffer for DA
+*/
+#define RX_MSDU_END_10_DA_OFFSET_OFFSET                              0x00000028
+#define RX_MSDU_END_10_DA_OFFSET_LSB                                 0
+#define RX_MSDU_END_10_DA_OFFSET_MASK                                0x0000003f
+
+/* Description		RX_MSDU_END_10_SA_OFFSET
+			
+			Offset into MSDU buffer for SA
+*/
+#define RX_MSDU_END_10_SA_OFFSET_OFFSET                              0x00000028
+#define RX_MSDU_END_10_SA_OFFSET_LSB                                 6
+#define RX_MSDU_END_10_SA_OFFSET_MASK                                0x00000fc0
+
+/* Description		RX_MSDU_END_10_DA_OFFSET_VALID
+			
+			da_offset field is valid. This will be set to 0 in case
+			of a dynamic A-MSDU when DA is compressed
+*/
+#define RX_MSDU_END_10_DA_OFFSET_VALID_OFFSET                        0x00000028
+#define RX_MSDU_END_10_DA_OFFSET_VALID_LSB                           12
+#define RX_MSDU_END_10_DA_OFFSET_VALID_MASK                          0x00001000
+
+/* Description		RX_MSDU_END_10_SA_OFFSET_VALID
+			
+			sa_offset field is valid. This will be set to 0 in case
+			of a dynamic A-MSDU when SA is compressed
+*/
+#define RX_MSDU_END_10_SA_OFFSET_VALID_OFFSET                        0x00000028
+#define RX_MSDU_END_10_SA_OFFSET_VALID_LSB                           13
+#define RX_MSDU_END_10_SA_OFFSET_VALID_MASK                          0x00002000
+
+/* Description		RX_MSDU_END_10_TYPE_OFFSET
+			
+			Offset into MSDU buffer for Type
+*/
+#define RX_MSDU_END_10_TYPE_OFFSET_OFFSET                            0x00000028
+#define RX_MSDU_END_10_TYPE_OFFSET_LSB                               14
+#define RX_MSDU_END_10_TYPE_OFFSET_MASK                              0x001fc000
+
+/* Description		RX_MSDU_END_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_10_RESERVED_10A_OFFSET                           0x00000028
+#define RX_MSDU_END_10_RESERVED_10A_LSB                              21
+#define RX_MSDU_END_10_RESERVED_10A_MASK                             0xffe00000
+
+/* Description		RX_MSDU_END_11_RULE_INDICATION_31_0
+			
+			Bitmap indicating which of rules 31-0 have matched
+*/
+#define RX_MSDU_END_11_RULE_INDICATION_31_0_OFFSET                   0x0000002c
+#define RX_MSDU_END_11_RULE_INDICATION_31_0_LSB                      0
+#define RX_MSDU_END_11_RULE_INDICATION_31_0_MASK                     0xffffffff
+
+/* Description		RX_MSDU_END_12_RULE_INDICATION_63_32
+			
+			Bitmap indicating which of rules 63-32 have matched
+*/
+#define RX_MSDU_END_12_RULE_INDICATION_63_32_OFFSET                  0x00000030
+#define RX_MSDU_END_12_RULE_INDICATION_63_32_LSB                     0
+#define RX_MSDU_END_12_RULE_INDICATION_63_32_MASK                    0xffffffff
+
+/* Description		RX_MSDU_END_13_SA_IDX
+			
+			The offset in the address table which matches the MAC
+			source address.
+*/
+#define RX_MSDU_END_13_SA_IDX_OFFSET                                 0x00000034
+#define RX_MSDU_END_13_SA_IDX_LSB                                    0
+#define RX_MSDU_END_13_SA_IDX_MASK                                   0x0000ffff
+
+/* Description		RX_MSDU_END_13_DA_IDX
+			
+			The offset in the address table which matches the MAC
+			source address
+*/
+#define RX_MSDU_END_13_DA_IDX_OFFSET                                 0x00000034
+#define RX_MSDU_END_13_DA_IDX_LSB                                    16
+#define RX_MSDU_END_13_DA_IDX_MASK                                   0xffff0000
+
+/* Description		RX_MSDU_END_14_MSDU_DROP
+			
+			When set, REO shall drop this MSDU and not forward it to
+			any other ring...
+			
+			<legal all>
+*/
+#define RX_MSDU_END_14_MSDU_DROP_OFFSET                              0x00000038
+#define RX_MSDU_END_14_MSDU_DROP_LSB                                 0
+#define RX_MSDU_END_14_MSDU_DROP_MASK                                0x00000001
+
+/* Description		RX_MSDU_END_14_REO_DESTINATION_INDICATION
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_OFFSET             0x00000038
+#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_LSB                1
+#define RX_MSDU_END_14_REO_DESTINATION_INDICATION_MASK               0x0000003e
+
+/* Description		RX_MSDU_END_14_FLOW_IDX
+			
+			Flow table index
+			
+			<legal all>
+*/
+#define RX_MSDU_END_14_FLOW_IDX_OFFSET                               0x00000038
+#define RX_MSDU_END_14_FLOW_IDX_LSB                                  6
+#define RX_MSDU_END_14_FLOW_IDX_MASK                                 0x03ffffc0
+
+/* Description		RX_MSDU_END_14_RESERVED_14
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_14_RESERVED_14_OFFSET                            0x00000038
+#define RX_MSDU_END_14_RESERVED_14_LSB                               26
+#define RX_MSDU_END_14_RESERVED_14_MASK                              0xfc000000
+
+/* Description		RX_MSDU_END_15_FSE_METADATA
+			
+			FSE related meta data:
+			
+			<legal all>
+*/
+#define RX_MSDU_END_15_FSE_METADATA_OFFSET                           0x0000003c
+#define RX_MSDU_END_15_FSE_METADATA_LSB                              0
+#define RX_MSDU_END_15_FSE_METADATA_MASK                             0xffffffff
+
+/* Description		RX_MSDU_END_16_CCE_METADATA
+			
+			CCE related meta data:
+			
+			<legal all>
+*/
+#define RX_MSDU_END_16_CCE_METADATA_OFFSET                           0x00000040
+#define RX_MSDU_END_16_CCE_METADATA_LSB                              0
+#define RX_MSDU_END_16_CCE_METADATA_MASK                             0x0000ffff
+
+/* Description		RX_MSDU_END_16_SA_SW_PEER_ID
+			
+			sw_peer_id from the address search entry corresponding
+			to the source address of the MSDU
+			
+			<legal 0>
+*/
+#define RX_MSDU_END_16_SA_SW_PEER_ID_OFFSET                          0x00000040
+#define RX_MSDU_END_16_SA_SW_PEER_ID_LSB                             16
+#define RX_MSDU_END_16_SA_SW_PEER_ID_MASK                            0xffff0000
+
+
+#endif // _RX_MSDU_END_H_

hw/qca6290/v1/rx_msdu_link.h

@@ -0,0 +1,345 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MSDU_LINK_H_
+#define _RX_MSDU_LINK_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "buffer_addr_info.h"
+#include "rx_msdu_details.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_descriptor_header descriptor_header;
+//	1-2	struct buffer_addr_info next_msdu_link_desc_addr_info;
+//	3	receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17]
+//	4	pn_31_0[31:0]
+//	5	pn_63_32[31:0]
+//	6	pn_95_64[31:0]
+//	7	pn_127_96[31:0]
+//	8-11	struct rx_msdu_details msdu_0;
+//	12-15	struct rx_msdu_details msdu_1;
+//	16-19	struct rx_msdu_details msdu_2;
+//	20-23	struct rx_msdu_details msdu_3;
+//	24-27	struct rx_msdu_details msdu_4;
+//	28-31	struct rx_msdu_details msdu_5;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_LINK 32
+
+struct rx_msdu_link {
+    struct            uniform_descriptor_header                       descriptor_header;
+    struct            buffer_addr_info                       next_msdu_link_desc_addr_info;
+             uint32_t receive_queue_number            : 16, //[15:0]
+                      first_rx_msdu_link_struct       :  1, //[16]
+                      reserved_3a                     : 15; //[31:17]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+    struct            rx_msdu_details                       msdu_0;
+    struct            rx_msdu_details                       msdu_1;
+    struct            rx_msdu_details                       msdu_2;
+    struct            rx_msdu_details                       msdu_3;
+    struct            rx_msdu_details                       msdu_4;
+    struct            rx_msdu_details                       msdu_5;
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+			
+			Details about which module owns this struct.
+			
+			Note that sub field Buffer_type shall be set to
+			Receive_MSDU_Link_descriptor
+
+struct buffer_addr_info next_msdu_link_desc_addr_info
+			
+			Details of the physical address of the next MSDU link
+			descriptor that contains info about additional MSDUs that
+			are part of this MPDU.
+
+receive_queue_number
+			
+			Indicates the Receive queue to which this MPDU
+			descriptor belongs
+			
+			Used for tracking, finding bugs and debugging.
+			
+			<legal all>
+
+first_rx_msdu_link_struct
+			
+			When set, this RX_MSDU_link descriptor is the first one
+			in the MSDU link list. Field MSDU_0 points to the very first
+			MSDU buffer descriptor in the MPDU
+			
+			<legal all>
+
+reserved_3a
+			
+			<legal 0>
+
+pn_31_0
+			
+			
+			
+			
+			31-0 bits of the 256-bit packet number bitmap.  
+			
+			<legal all>
+
+pn_63_32
+			
+			
+			
+			
+			63-32 bits of the 256-bit packet number bitmap.  
+			
+			<legal all>
+
+pn_95_64
+			
+			
+			
+			
+			95-64 bits of the 256-bit packet number bitmap. 
+			
+			<legal all>
+
+pn_127_96
+			
+			
+			
+			
+			127-96 bits of the 256-bit packet number bitmap. 
+			
+			<legal all>
+
+struct rx_msdu_details msdu_0
+			
+			When First_RX_MSDU_link_struct  is set, this MSDU is the
+			first in the MPDU
+			
+			
+			
+			When First_RX_MSDU_link_struct  is NOT set, this MSDU
+			follows the last MSDU in the previous RX_MSDU_link data
+			structure
+
+struct rx_msdu_details msdu_1
+			
+			Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_2
+			
+			Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_3
+			
+			Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_4
+			
+			Details of next MSDU in this (MSDU flow) linked list
+
+struct rx_msdu_details msdu_5
+			
+			Details of next MSDU in this (MSDU flow) linked list
+*/
+
+#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
+#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
+#define RX_MSDU_LINK_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
+#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
+#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MSDU_LINK_1_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_OFFSET 0x00000008
+#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_LSB 0
+#define RX_MSDU_LINK_2_BUFFER_ADDR_INFO_NEXT_MSDU_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+
+/* Description		RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER
+			
+			Indicates the Receive queue to which this MPDU
+			descriptor belongs
+			
+			Used for tracking, finding bugs and debugging.
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET                   0x0000000c
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB                      0
+#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
+
+/* Description		RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT
+			
+			When set, this RX_MSDU_link descriptor is the first one
+			in the MSDU link list. Field MSDU_0 points to the very first
+			MSDU buffer descriptor in the MPDU
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET              0x0000000c
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB                 16
+#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK                0x00010000
+
+/* Description		RX_MSDU_LINK_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET                            0x0000000c
+#define RX_MSDU_LINK_3_RESERVED_3A_LSB                               17
+#define RX_MSDU_LINK_3_RESERVED_3A_MASK                              0xfffe0000
+
+/* Description		RX_MSDU_LINK_4_PN_31_0
+			
+			
+			
+			
+			31-0 bits of the 256-bit packet number bitmap.  
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_4_PN_31_0_OFFSET                                0x00000010
+#define RX_MSDU_LINK_4_PN_31_0_LSB                                   0
+#define RX_MSDU_LINK_4_PN_31_0_MASK                                  0xffffffff
+
+/* Description		RX_MSDU_LINK_5_PN_63_32
+			
+			
+			
+			
+			63-32 bits of the 256-bit packet number bitmap.  
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_5_PN_63_32_OFFSET                               0x00000014
+#define RX_MSDU_LINK_5_PN_63_32_LSB                                  0
+#define RX_MSDU_LINK_5_PN_63_32_MASK                                 0xffffffff
+
+/* Description		RX_MSDU_LINK_6_PN_95_64
+			
+			
+			
+			
+			95-64 bits of the 256-bit packet number bitmap. 
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_6_PN_95_64_OFFSET                               0x00000018
+#define RX_MSDU_LINK_6_PN_95_64_LSB                                  0
+#define RX_MSDU_LINK_6_PN_95_64_MASK                                 0xffffffff
+
+/* Description		RX_MSDU_LINK_7_PN_127_96
+			
+			
+			
+			
+			127-96 bits of the 256-bit packet number bitmap. 
+			
+			<legal all>
+*/
+#define RX_MSDU_LINK_7_PN_127_96_OFFSET                              0x0000001c
+#define RX_MSDU_LINK_7_PN_127_96_LSB                                 0
+#define RX_MSDU_LINK_7_PN_127_96_MASK                                0xffffffff
+#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET                 0x00000020
+#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_LSB                    0
+#define RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_MASK                   0xffffffff
+#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_OFFSET                 0x00000024
+#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_LSB                    0
+#define RX_MSDU_LINK_9_RX_MSDU_DETAILS_MSDU_0_MASK                   0xffffffff
+#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_OFFSET                0x00000028
+#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_LSB                   0
+#define RX_MSDU_LINK_10_RX_MSDU_DETAILS_MSDU_0_MASK                  0xffffffff
+#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_OFFSET                0x0000002c
+#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_LSB                   0
+#define RX_MSDU_LINK_11_RX_MSDU_DETAILS_MSDU_0_MASK                  0xffffffff
+#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_OFFSET                0x00000030
+#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_LSB                   0
+#define RX_MSDU_LINK_12_RX_MSDU_DETAILS_MSDU_1_MASK                  0xffffffff
+#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_OFFSET                0x00000034
+#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_LSB                   0
+#define RX_MSDU_LINK_13_RX_MSDU_DETAILS_MSDU_1_MASK                  0xffffffff
+#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_OFFSET                0x00000038
+#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_LSB                   0
+#define RX_MSDU_LINK_14_RX_MSDU_DETAILS_MSDU_1_MASK                  0xffffffff
+#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_OFFSET                0x0000003c
+#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_LSB                   0
+#define RX_MSDU_LINK_15_RX_MSDU_DETAILS_MSDU_1_MASK                  0xffffffff
+#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_OFFSET                0x00000040
+#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_LSB                   0
+#define RX_MSDU_LINK_16_RX_MSDU_DETAILS_MSDU_2_MASK                  0xffffffff
+#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_OFFSET                0x00000044
+#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_LSB                   0
+#define RX_MSDU_LINK_17_RX_MSDU_DETAILS_MSDU_2_MASK                  0xffffffff
+#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_OFFSET                0x00000048
+#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_LSB                   0
+#define RX_MSDU_LINK_18_RX_MSDU_DETAILS_MSDU_2_MASK                  0xffffffff
+#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_OFFSET                0x0000004c
+#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_LSB                   0
+#define RX_MSDU_LINK_19_RX_MSDU_DETAILS_MSDU_2_MASK                  0xffffffff
+#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_OFFSET                0x00000050
+#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_LSB                   0
+#define RX_MSDU_LINK_20_RX_MSDU_DETAILS_MSDU_3_MASK                  0xffffffff
+#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_OFFSET                0x00000054
+#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_LSB                   0
+#define RX_MSDU_LINK_21_RX_MSDU_DETAILS_MSDU_3_MASK                  0xffffffff
+#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_OFFSET                0x00000058
+#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_LSB                   0
+#define RX_MSDU_LINK_22_RX_MSDU_DETAILS_MSDU_3_MASK                  0xffffffff
+#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_OFFSET                0x0000005c
+#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_LSB                   0
+#define RX_MSDU_LINK_23_RX_MSDU_DETAILS_MSDU_3_MASK                  0xffffffff
+#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_OFFSET                0x00000060
+#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_LSB                   0
+#define RX_MSDU_LINK_24_RX_MSDU_DETAILS_MSDU_4_MASK                  0xffffffff
+#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_OFFSET                0x00000064
+#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_LSB                   0
+#define RX_MSDU_LINK_25_RX_MSDU_DETAILS_MSDU_4_MASK                  0xffffffff
+#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_OFFSET                0x00000068
+#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_LSB                   0
+#define RX_MSDU_LINK_26_RX_MSDU_DETAILS_MSDU_4_MASK                  0xffffffff
+#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_OFFSET                0x0000006c
+#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_LSB                   0
+#define RX_MSDU_LINK_27_RX_MSDU_DETAILS_MSDU_4_MASK                  0xffffffff
+#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_OFFSET                0x00000070
+#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_LSB                   0
+#define RX_MSDU_LINK_28_RX_MSDU_DETAILS_MSDU_5_MASK                  0xffffffff
+#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_OFFSET                0x00000074
+#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_LSB                   0
+#define RX_MSDU_LINK_29_RX_MSDU_DETAILS_MSDU_5_MASK                  0xffffffff
+#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_OFFSET                0x00000078
+#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_LSB                   0
+#define RX_MSDU_LINK_30_RX_MSDU_DETAILS_MSDU_5_MASK                  0xffffffff
+#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_OFFSET                0x0000007c
+#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_LSB                   0
+#define RX_MSDU_LINK_31_RX_MSDU_DETAILS_MSDU_5_MASK                  0xffffffff
+
+
+#endif // _RX_MSDU_LINK_H_

hw/qca6290/v1/rx_msdu_start.h

@@ -0,0 +1,1081 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_MSDU_START_H_
+#define _RX_MSDU_START_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16]
+//	1	msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24]
+//	2	msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], reserved_2a[31:16]
+//	3	reserved_3a[10:0], da_is_bcast_mcast[11], reserved_3b[15:12], ip4_protocol_ip6_next_header[23:16], reserved_3c[30:24], toeplitz_hash[31]
+//	4	toeplitz_hash_2_or_4[31:0]
+//	5	flow_id_toeplitz[31:0]
+//	6	user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[22:21], nss[25:23], reserved_6[31:26]
+//	7	ppdu_start_timestamp[31:0]
+//	8	sw_phy_meta_data[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_MSDU_START 9
+
+struct rx_msdu_start {
+             uint32_t rxpcu_mpdu_filter_in_category   :  2, //[1:0]
+                      sw_frame_group_id               :  7, //[8:2]
+                      reserved_0                      :  7, //[15:9]
+                      phy_ppdu_id                     : 16; //[31:16]
+             uint32_t msdu_length                     : 14, //[13:0]
+                      reserved_1a                     :  1, //[14]
+                      ipsec_esp                       :  1, //[15]
+                      l3_offset                       :  7, //[22:16]
+                      ipsec_ah                        :  1, //[23]
+                      l4_offset                       :  8; //[31:24]
+             uint32_t msdu_number                     :  8, //[7:0]
+                      decap_format                    :  2, //[9:8]
+                      ipv4_proto                      :  1, //[10]
+                      ipv6_proto                      :  1, //[11]
+                      tcp_proto                       :  1, //[12]
+                      udp_proto                       :  1, //[13]
+                      ip_frag                         :  1, //[14]
+                      tcp_only_ack                    :  1, //[15]
+                      reserved_2a                     : 16; //[31:16]
+             uint32_t reserved_3a                     : 11, //[10:0]
+                      da_is_bcast_mcast               :  1, //[11]
+                      reserved_3b                     :  4, //[15:12]
+                      ip4_protocol_ip6_next_header    :  8, //[23:16]
+                      reserved_3c                     :  7, //[30:24]
+                      toeplitz_hash                   :  1; //[31]
+             uint32_t toeplitz_hash_2_or_4            : 32; //[31:0]
+             uint32_t flow_id_toeplitz                : 32; //[31:0]
+             uint32_t user_rssi                       :  8, //[7:0]
+                      pkt_type                        :  4, //[11:8]
+                      stbc                            :  1, //[12]
+                      sgi                             :  2, //[14:13]
+                      rate_mcs                        :  4, //[18:15]
+                      receive_bandwidth               :  2, //[20:19]
+                      reception_type                  :  2, //[22:21]
+                      nss                             :  3, //[25:23]
+                      reserved_6                      :  6; //[31:26]
+             uint32_t ppdu_start_timestamp            : 32; //[31:0]
+             uint32_t sw_phy_meta_data                : 32; //[31:0]
+};
+
+/*
+
+rxpcu_mpdu_filter_in_category
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+
+sw_frame_group_id
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+
+reserved_0
+			
+			<legal 0>
+
+phy_ppdu_id
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+
+msdu_length
+			
+			MSDU length in bytes after decapsulation. 
+			
+			
+			
+			This field is still valid for MPDU frames without
+
+reserved_1a
+			
+			<legal 0>
+
+ipsec_esp
+			
+			Set if IPv4/v6 packet is using IPsec ESP
+
+l3_offset
+			
+			Depending upon mode bit, this field either indicates the
+			L3 offset in bytes from the start of the RX_HEADER or the IP
+			offset in bytes from the start of the packet after
+			decapsulation.  The latter is only valid if ipv4_proto or
+			ipv6_proto is set.
+
+ipsec_ah
+			
+			Set if IPv4/v6 packet is using IPsec AH
+
+l4_offset
+			
+			Depending upon mode bit, this field either indicates the
+			L4 offset nin bytes from the start of RX_HEADER(only valid
+			if either ipv4_proto or ipv6_proto is set to 1) or indicates
+			the offset in bytes to the start of TCP or UDP header from
+			the start of the IP header after decapsulation(Only valid if
+			tcp_proto or udp_proto is set).  The value 0 indicates that
+			the offset is longer than 127 bytes.
+
+msdu_number
+			
+			Indicates the MSDU number within a MPDU.  This value is
+			reset to zero at the start of each MPDU.  If the number of
+			MSDU exceeds 255 this number will wrap using modulo 256.
+
+decap_format
+			
+			Indicates the format after decapsulation:
+			
+			
+			
+			<enum 0 RAW> No encapsulation
+			
+			<enum 1 Native_WiFi>
+			
+			<enum 2 Ethernet> Ethernet 2 (DIX)  
+			
+			<enum 3 802_3> 802.3 (uses SNAP/LLC)
+			
+			<legal all>
+
+ipv4_proto
+			
+			Set if L2 layer indicates IPv4 protocol.
+
+ipv6_proto
+			
+			Set if L2 layer indicates IPv6 protocol.
+
+tcp_proto
+			
+			Set if the ipv4_proto or ipv6_proto are set and the IP
+			protocol indicates TCP.
+
+udp_proto
+			
+			Set if the ipv4_proto or ipv6_proto are set and the IP
+			protocol indicates UDP.
+
+ip_frag
+			
+			Indicates that either the IP More frag bit is set or IP
+			frag number is non-zero.  If set indicates that this is a
+			fragmented IP packet.
+
+tcp_only_ack
+			
+			Set if only the TCP Ack bit is set in the TCP flags and
+			if the TCP payload is 0.
+
+reserved_2a
+			
+			<legal 0>
+
+reserved_3a
+			
+			<legal 0>
+
+da_is_bcast_mcast
+			
+			The destination address is broadcast or multicast.
+
+reserved_3b
+			
+			<legal 0>
+
+ip4_protocol_ip6_next_header
+			
+			For IPv4 this is the 8 bit protocol field (when
+			ipv4_proto is set).  For IPv6 this is the 8 bit next_header
+			field (when ipv6_proto is set).
+
+reserved_3c
+			
+			<legal 0>
+
+toeplitz_hash
+			
+			Actual choosen Hash.
+			
+			
+			
+			0 -> Toeplitz hash of 2-tuple (IP source address, IP
+			destination address)1 -> Toeplitz hash of 4-tuple (IP source
+			address, IP destination address, L4 (TCP/UDP) source port,
+			L4 (TCP/UDP) destination port)
+
+toeplitz_hash_2_or_4
+			
+			Controlled by RxOLE register - If register bit set to 0,
+			Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
+			addresses; otherwise, toeplitz hash is computed over 4-tuple
+			IPv4 or IPv6 src/dest addresses and src/dest ports
+
+flow_id_toeplitz
+			
+			Toeplitz hash of 5-tuple 
+			
+			{IP source address, IP destination address, IP source
+			port, IP destination port, L4 protocol}  in case of
+			non-IPSec.
+			
+			In case of IPSec - Toeplitz hash of 4-tuple 
+			
+			{IP source address, IP destination address, SPI, L4
+			protocol} 
+			
+			
+			
+			The relevant Toeplitz key registers are provided in
+			RxOLE's instance of common parser module. These registers
+			are separate from the Toeplitz keys used by ASE/FSE modules
+			inside RxOLE.The actual value will be passed on from common
+			parser module to RxOLE in one of the WHO_* TLVs.
+			
+			<legal all>
+
+user_rssi
+			
+			RSSI for this user
+			
+			<legal all>
+
+pkt_type
+			
+			Packet type:
+			
+			<enum 0 dot11a>802.11a PPDU type
+			
+			<enum 1 dot11b>802.11b PPDU type
+			
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+			
+			<enum 3 dot11ac>802.11ac PPDU type
+			
+			<enum 4 dot11ax>802.11ax PPDU type
+
+stbc
+			
+			When set, use STBC transmission rates
+
+sgi
+			
+			Field only valid when pkt type is HT, VHT or HE.
+			
+			
+			
+			<enum 0     0_8_us_sgi > Legacy normal GI
+			
+			<enum 1     0_4_us_sgi > Legacy short GI
+			
+			<enum 2     1_6_us_sgi > HE related GI
+			
+			<enum 3     3_2_us_sgi > HE related GI
+			
+			<legal 0 - 3>
+
+rate_mcs
+			
+			For details, refer to  MCS_TYPE description
+			
+			<legal all>
+
+receive_bandwidth
+			
+			Full receive Bandwidth
+			
+			
+			
+			<enum 0     full_rx_bw_20_mhz>
+			
+			<enum 1      full_rx_bw_40_mhz>
+			
+			<enum 2      full_rx_bw_80_mhz>
+			
+			<enum 3      full_rx_bw_160_mhz> 
+			
+			
+			
+			<legal 0-3>
+
+reception_type
+			
+			Indicates what type of reception this is.
+			
+			<enum 0     reception_type_SU > 
+			
+			<enum 1     reception_type_MU_MIMO > 
+			
+			<enum 2     reception_type_MU_OFDMA > 
+			
+			<enum 3     reception_type_MU_OFDMA_MIMO > 
+			
+			<legal all>
+
+nss
+			
+			Field only valid when Reception_type =
+			reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO
+			
+			
+			
+			Number of Spatial Streams occupied by the User
+			
+			
+			
+			<enum 0 1_spatial_stream>Single spatial stream
+			
+			<enum 1 2_spatial_streams>2 spatial streams
+			
+			<enum 2 3_spatial_streams>3 spatial streams
+			
+			<enum 3 4_spatial_streams>4 spatial streams
+			
+			<enum 4 5_spatial_streams>5 spatial streams
+			
+			<enum 5 6_spatial_streams>6 spatial streams
+			
+			<enum 6 7_spatial_streams>7 spatial streams
+			
+			<enum 7 8_spatial_streams>8 spatial streams
+
+reserved_6
+			
+			<legal 0>
+
+ppdu_start_timestamp
+			
+			Timestamp that indicates when the PPDU that contained
+			this MPDU started on the medium.
+			
+			<legal all>
+
+sw_phy_meta_data
+			
+			SW programmed Meta data provided by the PHY.
+			
+			
+			
+			Can be used for SW to indicate the channel the device is
+			on.
+			
+			<legal all>
+*/
+
+
+/* Description		RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY
+			
+			Field indicates what the reason was that this MPDU frame
+			was allowed to come into the receive path by RXPCU
+			
+			<enum 0 rxpcu_filter_pass> This MPDU passed the normal
+			frame filter programming of rxpcu
+			
+			<enum 1 rxpcu_monitor_client> This MPDU did NOT pass the
+			regular frame filter and would have been dropped, were it
+			not for the frame fitting into the 'monitor_client'
+			category.
+			
+			<enum 2 rxpcu_monitor_other> This MPDU did NOT pass the
+			regular frame filter and also did not pass the
+			rxpcu_monitor_client filter. It would have been dropped
+			accept that it did pass the 'monitor_other' category.
+			
+			<legal 0-2>
+*/
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET         0x00000000
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB            0
+#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK           0x00000003
+
+/* Description		RX_MSDU_START_0_SW_FRAME_GROUP_ID
+			
+			SW processes frames based on certain classifications.
+			This field indicates to what sw classification this MPDU is
+			mapped.
+			
+			The classification is given in priority order
+			
+			
+			
+			<enum 0 sw_frame_group_NDP_frame> 
+			
+			
+			
+			<enum 1 sw_frame_group_Multicast_data> 
+			
+			<enum 2 sw_frame_group_Unicast_data> 
+			
+			<enum 3 sw_frame_group_Null_data > This includes mpdus
+			of type Data Null as well as QoS Data Null
+			
+			
+			
+			<enum 4 sw_frame_group_mgmt_0000 > 
+			
+			<enum 5 sw_frame_group_mgmt_0001 > 
+			
+			<enum 6 sw_frame_group_mgmt_0010 > 
+			
+			<enum 7 sw_frame_group_mgmt_0011 > 
+			
+			<enum 8 sw_frame_group_mgmt_0100 > 
+			
+			<enum 9 sw_frame_group_mgmt_0101 > 
+			
+			<enum 10 sw_frame_group_mgmt_0110 > 
+			
+			<enum 11 sw_frame_group_mgmt_0111 > 
+			
+			<enum 12 sw_frame_group_mgmt_1000 > 
+			
+			<enum 13 sw_frame_group_mgmt_1001 > 
+			
+			<enum 14 sw_frame_group_mgmt_1010 > 
+			
+			<enum 15 sw_frame_group_mgmt_1011 > 
+			
+			<enum 16 sw_frame_group_mgmt_1100 > 
+			
+			<enum 17 sw_frame_group_mgmt_1101 > 
+			
+			<enum 18 sw_frame_group_mgmt_1110 > 
+			
+			<enum 19 sw_frame_group_mgmt_1111 > 
+			
+			
+			
+			<enum 20 sw_frame_group_ctrl_0000 > 
+			
+			<enum 21 sw_frame_group_ctrl_0001 > 
+			
+			<enum 22 sw_frame_group_ctrl_0010 > 
+			
+			<enum 23 sw_frame_group_ctrl_0011 > 
+			
+			<enum 24 sw_frame_group_ctrl_0100 > 
+			
+			<enum 25 sw_frame_group_ctrl_0101 > 
+			
+			<enum 26 sw_frame_group_ctrl_0110 > 
+			
+			<enum 27 sw_frame_group_ctrl_0111 > 
+			
+			<enum 28 sw_frame_group_ctrl_1000 > 
+			
+			<enum 29 sw_frame_group_ctrl_1001 > 
+			
+			<enum 30 sw_frame_group_ctrl_1010 > 
+			
+			<enum 31 sw_frame_group_ctrl_1011 > 
+			
+			<enum 32 sw_frame_group_ctrl_1100 > 
+			
+			<enum 33 sw_frame_group_ctrl_1101 > 
+			
+			<enum 34 sw_frame_group_ctrl_1110 > 
+			
+			<enum 35 sw_frame_group_ctrl_1111 > 
+			
+			
+			
+			<enum 36 sw_frame_group_unsupported> This covers type 3
+			and protocol version != 0
+			
+			
+			
+			
+			
+			
+			<legal 0-37>
+*/
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET                     0x00000000
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB                        2
+#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK                       0x000001fc
+
+/* Description		RX_MSDU_START_0_RESERVED_0
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_0_RESERVED_0_OFFSET                            0x00000000
+#define RX_MSDU_START_0_RESERVED_0_LSB                               9
+#define RX_MSDU_START_0_RESERVED_0_MASK                              0x0000fe00
+
+/* Description		RX_MSDU_START_0_PHY_PPDU_ID
+			
+			A ppdu counter value that PHY increments for every PPDU
+			received. The counter value wraps around  
+			
+			<legal all>
+*/
+#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET                           0x00000000
+#define RX_MSDU_START_0_PHY_PPDU_ID_LSB                              16
+#define RX_MSDU_START_0_PHY_PPDU_ID_MASK                             0xffff0000
+
+/* Description		RX_MSDU_START_1_MSDU_LENGTH
+			
+			MSDU length in bytes after decapsulation. 
+			
+			
+			
+			This field is still valid for MPDU frames without
+*/
+#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET                           0x00000004
+#define RX_MSDU_START_1_MSDU_LENGTH_LSB                              0
+#define RX_MSDU_START_1_MSDU_LENGTH_MASK                             0x00003fff
+
+/* Description		RX_MSDU_START_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_1_RESERVED_1A_OFFSET                           0x00000004
+#define RX_MSDU_START_1_RESERVED_1A_LSB                              14
+#define RX_MSDU_START_1_RESERVED_1A_MASK                             0x00004000
+
+/* Description		RX_MSDU_START_1_IPSEC_ESP
+			
+			Set if IPv4/v6 packet is using IPsec ESP
+*/
+#define RX_MSDU_START_1_IPSEC_ESP_OFFSET                             0x00000004
+#define RX_MSDU_START_1_IPSEC_ESP_LSB                                15
+#define RX_MSDU_START_1_IPSEC_ESP_MASK                               0x00008000
+
+/* Description		RX_MSDU_START_1_L3_OFFSET
+			
+			Depending upon mode bit, this field either indicates the
+			L3 offset in bytes from the start of the RX_HEADER or the IP
+			offset in bytes from the start of the packet after
+			decapsulation.  The latter is only valid if ipv4_proto or
+			ipv6_proto is set.
+*/
+#define RX_MSDU_START_1_L3_OFFSET_OFFSET                             0x00000004
+#define RX_MSDU_START_1_L3_OFFSET_LSB                                16
+#define RX_MSDU_START_1_L3_OFFSET_MASK                               0x007f0000
+
+/* Description		RX_MSDU_START_1_IPSEC_AH
+			
+			Set if IPv4/v6 packet is using IPsec AH
+*/
+#define RX_MSDU_START_1_IPSEC_AH_OFFSET                              0x00000004
+#define RX_MSDU_START_1_IPSEC_AH_LSB                                 23
+#define RX_MSDU_START_1_IPSEC_AH_MASK                                0x00800000
+
+/* Description		RX_MSDU_START_1_L4_OFFSET
+			
+			Depending upon mode bit, this field either indicates the
+			L4 offset nin bytes from the start of RX_HEADER(only valid
+			if either ipv4_proto or ipv6_proto is set to 1) or indicates
+			the offset in bytes to the start of TCP or UDP header from
+			the start of the IP header after decapsulation(Only valid if
+			tcp_proto or udp_proto is set).  The value 0 indicates that
+			the offset is longer than 127 bytes.
+*/
+#define RX_MSDU_START_1_L4_OFFSET_OFFSET                             0x00000004
+#define RX_MSDU_START_1_L4_OFFSET_LSB                                24
+#define RX_MSDU_START_1_L4_OFFSET_MASK                               0xff000000
+
+/* Description		RX_MSDU_START_2_MSDU_NUMBER
+			
+			Indicates the MSDU number within a MPDU.  This value is
+			reset to zero at the start of each MPDU.  If the number of
+			MSDU exceeds 255 this number will wrap using modulo 256.
+*/
+#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET                           0x00000008
+#define RX_MSDU_START_2_MSDU_NUMBER_LSB                              0
+#define RX_MSDU_START_2_MSDU_NUMBER_MASK                             0x000000ff
+
+/* Description		RX_MSDU_START_2_DECAP_FORMAT
+			
+			Indicates the format after decapsulation:
+			
+			
+			
+			<enum 0 RAW> No encapsulation
+			
+			<enum 1 Native_WiFi>
+			
+			<enum 2 Ethernet> Ethernet 2 (DIX)  
+			
+			<enum 3 802_3> 802.3 (uses SNAP/LLC)
+			
+			<legal all>
+*/
+#ifndef RX_MSDU_START_2_DECAP_FORMAT_OFFSET
+#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET                          0x00000008
+#endif
+#ifndef RX_MSDU_START_2_DECAP_FORMAT_LSB
+#define RX_MSDU_START_2_DECAP_FORMAT_LSB                             8
+#endif
+#ifndef RX_MSDU_START_2_DECAP_FORMAT_MASK
+#define RX_MSDU_START_2_DECAP_FORMAT_MASK                            0x00000300
+#endif
+/* Description		RX_MSDU_START_2_IPV4_PROTO
+			
+			Set if L2 layer indicates IPv4 protocol.
+*/
+#define RX_MSDU_START_2_IPV4_PROTO_OFFSET                            0x00000008
+#define RX_MSDU_START_2_IPV4_PROTO_LSB                               10
+#define RX_MSDU_START_2_IPV4_PROTO_MASK                              0x00000400
+
+/* Description		RX_MSDU_START_2_IPV6_PROTO
+			
+			Set if L2 layer indicates IPv6 protocol.
+*/
+#define RX_MSDU_START_2_IPV6_PROTO_OFFSET                            0x00000008
+#define RX_MSDU_START_2_IPV6_PROTO_LSB                               11
+#define RX_MSDU_START_2_IPV6_PROTO_MASK                              0x00000800
+
+/* Description		RX_MSDU_START_2_TCP_PROTO
+			
+			Set if the ipv4_proto or ipv6_proto are set and the IP
+			protocol indicates TCP.
+*/
+#define RX_MSDU_START_2_TCP_PROTO_OFFSET                             0x00000008
+#define RX_MSDU_START_2_TCP_PROTO_LSB                                12
+#define RX_MSDU_START_2_TCP_PROTO_MASK                               0x00001000
+
+/* Description		RX_MSDU_START_2_UDP_PROTO
+			
+			Set if the ipv4_proto or ipv6_proto are set and the IP
+			protocol indicates UDP.
+*/
+#define RX_MSDU_START_2_UDP_PROTO_OFFSET                             0x00000008
+#define RX_MSDU_START_2_UDP_PROTO_LSB                                13
+#define RX_MSDU_START_2_UDP_PROTO_MASK                               0x00002000
+
+/* Description		RX_MSDU_START_2_IP_FRAG
+			
+			Indicates that either the IP More frag bit is set or IP
+			frag number is non-zero.  If set indicates that this is a
+			fragmented IP packet.
+*/
+#define RX_MSDU_START_2_IP_FRAG_OFFSET                               0x00000008
+#define RX_MSDU_START_2_IP_FRAG_LSB                                  14
+#define RX_MSDU_START_2_IP_FRAG_MASK                                 0x00004000
+
+/* Description		RX_MSDU_START_2_TCP_ONLY_ACK
+			
+			Set if only the TCP Ack bit is set in the TCP flags and
+			if the TCP payload is 0.
+*/
+#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET                          0x00000008
+#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB                             15
+#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK                            0x00008000
+
+/* Description		RX_MSDU_START_2_RESERVED_2A
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_2_RESERVED_2A_OFFSET                           0x00000008
+#define RX_MSDU_START_2_RESERVED_2A_LSB                              16
+#define RX_MSDU_START_2_RESERVED_2A_MASK                             0xffff0000
+
+/* Description		RX_MSDU_START_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_3_RESERVED_3A_OFFSET                           0x0000000c
+#define RX_MSDU_START_3_RESERVED_3A_LSB                              0
+#define RX_MSDU_START_3_RESERVED_3A_MASK                             0x000007ff
+
+/* Description		RX_MSDU_START_3_DA_IS_BCAST_MCAST
+			
+			The destination address is broadcast or multicast.
+*/
+#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_OFFSET                     0x0000000c
+#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_LSB                        11
+#define RX_MSDU_START_3_DA_IS_BCAST_MCAST_MASK                       0x00000800
+
+/* Description		RX_MSDU_START_3_RESERVED_3B
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_3_RESERVED_3B_OFFSET                           0x0000000c
+#define RX_MSDU_START_3_RESERVED_3B_LSB                              12
+#define RX_MSDU_START_3_RESERVED_3B_MASK                             0x0000f000
+
+/* Description		RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER
+			
+			For IPv4 this is the 8 bit protocol field (when
+			ipv4_proto is set).  For IPv6 this is the 8 bit next_header
+			field (when ipv6_proto is set).
+*/
+#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET          0x0000000c
+#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB             16
+#define RX_MSDU_START_3_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK            0x00ff0000
+
+/* Description		RX_MSDU_START_3_RESERVED_3C
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_3_RESERVED_3C_OFFSET                           0x0000000c
+#define RX_MSDU_START_3_RESERVED_3C_LSB                              24
+#define RX_MSDU_START_3_RESERVED_3C_MASK                             0x7f000000
+
+/* Description		RX_MSDU_START_3_TOEPLITZ_HASH
+			
+			Actual choosen Hash.
+			
+			
+			
+			0 -> Toeplitz hash of 2-tuple (IP source address, IP
+			destination address)1 -> Toeplitz hash of 4-tuple (IP source
+			address, IP destination address, L4 (TCP/UDP) source port,
+			L4 (TCP/UDP) destination port)
+*/
+#define RX_MSDU_START_3_TOEPLITZ_HASH_OFFSET                         0x0000000c
+#define RX_MSDU_START_3_TOEPLITZ_HASH_LSB                            31
+#define RX_MSDU_START_3_TOEPLITZ_HASH_MASK                           0x80000000
+
+/* Description		RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4
+			
+			Controlled by RxOLE register - If register bit set to 0,
+			Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
+			addresses; otherwise, toeplitz hash is computed over 4-tuple
+			IPv4 or IPv6 src/dest addresses and src/dest ports
+*/
+#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_OFFSET                  0x00000010
+#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_LSB                     0
+#define RX_MSDU_START_4_TOEPLITZ_HASH_2_OR_4_MASK                    0xffffffff
+
+/* Description		RX_MSDU_START_5_FLOW_ID_TOEPLITZ
+			
+			Toeplitz hash of 5-tuple 
+			
+			{IP source address, IP destination address, IP source
+			port, IP destination port, L4 protocol}  in case of
+			non-IPSec.
+			
+			In case of IPSec - Toeplitz hash of 4-tuple 
+			
+			{IP source address, IP destination address, SPI, L4
+			protocol} 
+			
+			
+			
+			The relevant Toeplitz key registers are provided in
+			RxOLE's instance of common parser module. These registers
+			are separate from the Toeplitz keys used by ASE/FSE modules
+			inside RxOLE.The actual value will be passed on from common
+			parser module to RxOLE in one of the WHO_* TLVs.
+			
+			<legal all>
+*/
+#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_OFFSET                      0x00000014
+#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_LSB                         0
+#define RX_MSDU_START_5_FLOW_ID_TOEPLITZ_MASK                        0xffffffff
+
+/* Description		RX_MSDU_START_6_USER_RSSI
+			
+			RSSI for this user
+			
+			<legal all>
+*/
+#define RX_MSDU_START_6_USER_RSSI_OFFSET                             0x00000018
+#define RX_MSDU_START_6_USER_RSSI_LSB                                0
+#define RX_MSDU_START_6_USER_RSSI_MASK                               0x000000ff
+
+/* Description		RX_MSDU_START_6_PKT_TYPE
+			
+			Packet type:
+			
+			<enum 0 dot11a>802.11a PPDU type
+			
+			<enum 1 dot11b>802.11b PPDU type
+			
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+			
+			<enum 3 dot11ac>802.11ac PPDU type
+			
+			<enum 4 dot11ax>802.11ax PPDU type
+*/
+#define RX_MSDU_START_6_PKT_TYPE_OFFSET                              0x00000018
+#define RX_MSDU_START_6_PKT_TYPE_LSB                                 8
+#define RX_MSDU_START_6_PKT_TYPE_MASK                                0x00000f00
+
+/* Description		RX_MSDU_START_6_STBC
+			
+			When set, use STBC transmission rates
+*/
+#define RX_MSDU_START_6_STBC_OFFSET                                  0x00000018
+#define RX_MSDU_START_6_STBC_LSB                                     12
+#define RX_MSDU_START_6_STBC_MASK                                    0x00001000
+
+/* Description		RX_MSDU_START_6_SGI
+			
+			Field only valid when pkt type is HT, VHT or HE.
+			
+			
+			
+			<enum 0     0_8_us_sgi > Legacy normal GI
+			
+			<enum 1     0_4_us_sgi > Legacy short GI
+			
+			<enum 2     1_6_us_sgi > HE related GI
+			
+			<enum 3     3_2_us_sgi > HE related GI
+			
+			<legal 0 - 3>
+*/
+#define RX_MSDU_START_6_SGI_OFFSET                                   0x00000018
+#define RX_MSDU_START_6_SGI_LSB                                      13
+#define RX_MSDU_START_6_SGI_MASK                                     0x00006000
+
+/* Description		RX_MSDU_START_6_RATE_MCS
+			
+			For details, refer to  MCS_TYPE description
+			
+			<legal all>
+*/
+#define RX_MSDU_START_6_RATE_MCS_OFFSET                              0x00000018
+#define RX_MSDU_START_6_RATE_MCS_LSB                                 15
+#define RX_MSDU_START_6_RATE_MCS_MASK                                0x00078000
+
+/* Description		RX_MSDU_START_6_RECEIVE_BANDWIDTH
+			
+			Full receive Bandwidth
+			
+			
+			
+			<enum 0     full_rx_bw_20_mhz>
+			
+			<enum 1      full_rx_bw_40_mhz>
+			
+			<enum 2      full_rx_bw_80_mhz>
+			
+			<enum 3      full_rx_bw_160_mhz> 
+			
+			
+			
+			<legal 0-3>
+*/
+#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_OFFSET                     0x00000018
+#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_LSB                        19
+#define RX_MSDU_START_6_RECEIVE_BANDWIDTH_MASK                       0x00180000
+
+/* Description		RX_MSDU_START_6_RECEPTION_TYPE
+			
+			Indicates what type of reception this is.
+			
+			<enum 0     reception_type_SU > 
+			
+			<enum 1     reception_type_MU_MIMO > 
+			
+			<enum 2     reception_type_MU_OFDMA > 
+			
+			<enum 3     reception_type_MU_OFDMA_MIMO > 
+			
+			<legal all>
+*/
+#define RX_MSDU_START_6_RECEPTION_TYPE_OFFSET                        0x00000018
+#define RX_MSDU_START_6_RECEPTION_TYPE_LSB                           21
+#define RX_MSDU_START_6_RECEPTION_TYPE_MASK                          0x00600000
+
+/* Description		RX_MSDU_START_6_NSS
+			
+			Field only valid when Reception_type =
+			reception_type_MU_MIMO or reception_type_MU_OFDMA_MIMO
+			
+			
+			
+			Number of Spatial Streams occupied by the User
+			
+			
+			
+			<enum 0 1_spatial_stream>Single spatial stream
+			
+			<enum 1 2_spatial_streams>2 spatial streams
+			
+			<enum 2 3_spatial_streams>3 spatial streams
+			
+			<enum 3 4_spatial_streams>4 spatial streams
+			
+			<enum 4 5_spatial_streams>5 spatial streams
+			
+			<enum 5 6_spatial_streams>6 spatial streams
+			
+			<enum 6 7_spatial_streams>7 spatial streams
+			
+			<enum 7 8_spatial_streams>8 spatial streams
+*/
+#define RX_MSDU_START_6_NSS_OFFSET                                   0x00000018
+#define RX_MSDU_START_6_NSS_LSB                                      23
+#define RX_MSDU_START_6_NSS_MASK                                     0x03800000
+
+/* Description		RX_MSDU_START_6_RESERVED_6
+			
+			<legal 0>
+*/
+#define RX_MSDU_START_6_RESERVED_6_OFFSET                            0x00000018
+#define RX_MSDU_START_6_RESERVED_6_LSB                               26
+#define RX_MSDU_START_6_RESERVED_6_MASK                              0xfc000000
+
+/* Description		RX_MSDU_START_7_PPDU_START_TIMESTAMP
+			
+			Timestamp that indicates when the PPDU that contained
+			this MPDU started on the medium.
+			
+			<legal all>
+*/
+#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_OFFSET                  0x0000001c
+#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_LSB                     0
+#define RX_MSDU_START_7_PPDU_START_TIMESTAMP_MASK                    0xffffffff
+
+/* Description		RX_MSDU_START_8_SW_PHY_META_DATA
+			
+			SW programmed Meta data provided by the PHY.
+			
+			
+			
+			Can be used for SW to indicate the channel the device is
+			on.
+			
+			<legal all>
+*/
+#define RX_MSDU_START_8_SW_PHY_META_DATA_OFFSET                      0x00000020
+#define RX_MSDU_START_8_SW_PHY_META_DATA_LSB                         0
+#define RX_MSDU_START_8_SW_PHY_META_DATA_MASK                        0xffffffff
+
+
+#endif // _RX_MSDU_START_H_

hw/qca6290/v1/rx_reo_queue.h

@@ -0,0 +1,1662 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_REO_QUEUE_H_
+#define _RX_REO_QUEUE_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_descriptor_header descriptor_header;
+//	1	receive_queue_number[15:0], reserved_1b[31:16]
+//	2	vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26]
+//	3	svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31]
+//	4	pn_31_0[31:0]
+//	5	pn_63_32[31:0]
+//	6	pn_95_64[31:0]
+//	7	pn_127_96[31:0]
+//	8	last_rx_enqueue_timestamp[31:0]
+//	9	last_rx_dequeue_timestamp[31:0]
+//	10	ptr_to_next_aging_queue_31_0[31:0]
+//	11	ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8]
+//	12	ptr_to_previous_aging_queue_31_0[31:0]
+//	13	ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8]
+//	14	rx_bitmap_31_0[31:0]
+//	15	rx_bitmap_63_32[31:0]
+//	16	rx_bitmap_95_64[31:0]
+//	17	rx_bitmap_127_96[31:0]
+//	18	rx_bitmap_159_128[31:0]
+//	19	rx_bitmap_191_160[31:0]
+//	20	rx_bitmap_223_192[31:0]
+//	21	rx_bitmap_255_224[31:0]
+//	22	current_mpdu_count[6:0], current_msdu_count[31:7]
+//	23	reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16]
+//	24	frames_in_order_count[23:0], bar_received_count[31:24]
+//	25	mpdu_frames_processed_count[31:0]
+//	26	msdu_frames_processed_count[31:0]
+//	27	total_processed_byte_count[31:0]
+//	28	late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16]
+//	29	reserved_29[31:0]
+//	30	reserved_30[31:0]
+//	31	reserved_31[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE 32
+
+struct rx_reo_queue {
+    struct            uniform_descriptor_header                       descriptor_header;
+             uint32_t receive_queue_number            : 16, //[15:0]
+                      reserved_1b                     : 16; //[31:16]
+             uint32_t vld                             :  1, //[0]
+                      associated_link_descriptor_counter:  2, //[2:1]
+                      disable_duplicate_detection     :  1, //[3]
+                      soft_reorder_enable             :  1, //[4]
+                      ac                              :  2, //[6:5]
+                      bar                             :  1, //[7]
+                      rty                             :  1, //[8]
+                      chk_2k_mode                     :  1, //[9]
+                      oor_mode                        :  1, //[10]
+                      ba_window_size                  :  8, //[18:11]
+                      pn_check_needed                 :  1, //[19]
+                      pn_shall_be_even                :  1, //[20]
+                      pn_shall_be_uneven              :  1, //[21]
+                      pn_handling_enable              :  1, //[22]
+                      pn_size                         :  2, //[24:23]
+                      ignore_ampdu_flag               :  1, //[25]
+                      reserved_2b                     :  6; //[31:26]
+             uint32_t svld                            :  1, //[0]
+                      ssn                             : 12, //[12:1]
+                      current_index                   :  8, //[20:13]
+                      seq_2k_error_detected_flag      :  1, //[21]
+                      pn_error_detected_flag          :  1, //[22]
+                      reserved_3a                     :  8, //[30:23]
+                      pn_valid                        :  1; //[31]
+             uint32_t pn_31_0                         : 32; //[31:0]
+             uint32_t pn_63_32                        : 32; //[31:0]
+             uint32_t pn_95_64                        : 32; //[31:0]
+             uint32_t pn_127_96                       : 32; //[31:0]
+             uint32_t last_rx_enqueue_timestamp       : 32; //[31:0]
+             uint32_t last_rx_dequeue_timestamp       : 32; //[31:0]
+             uint32_t ptr_to_next_aging_queue_31_0    : 32; //[31:0]
+             uint32_t ptr_to_next_aging_queue_39_32   :  8, //[7:0]
+                      reserved_11a                    : 24; //[31:8]
+             uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0]
+             uint32_t ptr_to_previous_aging_queue_39_32:  8, //[7:0]
+                      reserved_13a                    : 24; //[31:8]
+             uint32_t rx_bitmap_31_0                  : 32; //[31:0]
+             uint32_t rx_bitmap_63_32                 : 32; //[31:0]
+             uint32_t rx_bitmap_95_64                 : 32; //[31:0]
+             uint32_t rx_bitmap_127_96                : 32; //[31:0]
+             uint32_t rx_bitmap_159_128               : 32; //[31:0]
+             uint32_t rx_bitmap_191_160               : 32; //[31:0]
+             uint32_t rx_bitmap_223_192               : 32; //[31:0]
+             uint32_t rx_bitmap_255_224               : 32; //[31:0]
+             uint32_t current_mpdu_count              :  7, //[6:0]
+                      current_msdu_count              : 25; //[31:7]
+             uint32_t reserved_23                     :  4, //[3:0]
+                      timeout_count                   :  6, //[9:4]
+                      forward_due_to_bar_count        :  6, //[15:10]
+                      duplicate_count                 : 16; //[31:16]
+             uint32_t frames_in_order_count           : 24, //[23:0]
+                      bar_received_count              :  8; //[31:24]
+             uint32_t mpdu_frames_processed_count     : 32; //[31:0]
+             uint32_t msdu_frames_processed_count     : 32; //[31:0]
+             uint32_t total_processed_byte_count      : 32; //[31:0]
+             uint32_t late_receive_mpdu_count         : 12, //[11:0]
+                      window_jump_2k                  :  4, //[15:12]
+                      hole_count                      : 16; //[31:16]
+             uint32_t reserved_29                     : 32; //[31:0]
+             uint32_t reserved_30                     : 32; //[31:0]
+             uint32_t reserved_31                     : 32; //[31:0]
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+			
+			Details about which module owns this struct.
+			
+			Note that sub field Buffer_type shall be set to
+			Receive_REO_queue_descriptor
+
+receive_queue_number
+			
+			Indicates the MPDU queue ID to which this MPDU link
+			descriptor belongs
+			
+			Used for tracking and debugging
+			
+			<legal all>
+
+reserved_1b
+			
+			<legal 0>
+
+vld
+			
+			Valid bit indicating a session is established and the
+			queue descriptor is valid(Filled by SW)
+			
+			<legal all>
+
+associated_link_descriptor_counter
+			
+			Indicates which of the 3 link descriptor counters shall
+			be incremented or decremented when link descriptors are
+			added or removed from this flow queue.
+			
+			MSDU link descriptors related with MPDUs stored in the
+			re-order buffer shall also be included in this count.
+			
+			
+			
+			<legal 0-2>
+
+disable_duplicate_detection
+			
+			When set, do not perform any duplicate detection.
+			
+			
+			
+			<legal all>
+
+soft_reorder_enable
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes.
+			
+			
+			
+			Note that this implies that REO is also not going to
+			perform any MSDU level operations, and the entire MPDU (and
+			thus pointer to the MSDU link descriptor) will be pushed to
+			a destination ring that SW has programmed in a SW
+			programmable configuration register in REO
+			
+			
+			
+			<legal all>
+
+ac
+			
+			Indicates which access category the queue descriptor
+			belongs to(filled by SW)
+			
+			<legal all>
+
+bar
+			
+			Indicates if  BAR has been received (mostly used for
+			debug purpose and this is filled by REO)
+			
+			<legal all>
+
+rty
+			
+			Retry bit is checked if this bit is set.  
+			
+			<legal all>
+
+chk_2k_mode
+			
+			Indicates what type of operation is expected from Reo
+			when the received frame SN falls within the 2K window
+			
+			
+			
+			See REO MLD document for programming details.
+			
+			<legal all>
+
+oor_mode
+			
+			Out of Order mode:
+			
+			Indicates what type of operation is expected when the
+			received frame falls within the OOR window.
+			
+			
+			
+			See REO MLD document for programming details.
+			
+			<legal all>
+
+ba_window_size
+			
+			Indicates the negotiated (window size + 1). 
+			
+			it can go up to Max of 256bits.
+			
+			
+			
+			A value 255 means 256 bitmap, 63 means 64 bitmap, 0
+			(means non-BA session, with window size of 0). The 3 values
+			here are the main values validated, but other values should
+			work as well.
+			
+			
+			
+			A BA window size of 0 (=> one frame entry bitmat), means
+			that there is NO RX_REO_QUEUE_EXT descriptor following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			A BA window size of 1 - 105, means that there is 1
+			RX_REO_QUEUE_EXT descriptor directly following this
+			RX_REO_QUEUE STRUCT in memory.
+			
+			
+			
+			A BA window size of 106 - 210, means that there are 2
+			RX_REO_QUEUE_EXT descriptors directly following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			A BA window size of 211 - 256, means that there are 3
+			RX_REO_QUEUE_EXT descriptors directly following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			<legal 0 - 255>
+
+pn_check_needed
+			
+			When set, REO shall perform the PN increment check
+			
+			<legal all>
+
+pn_shall_be_even
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, REO shall confirm that the received PN number
+			is not only incremented, but also always an even number
+			
+			<legal all>
+
+pn_shall_be_uneven
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, REO shall confirm that the received PN number
+			is not only incremented, but also always an uneven number
+			
+			<legal all>
+
+pn_handling_enable
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, and REO detected a PN error, HW shall set the
+			'pn_error_detected_flag'.
+			
+			<legal all>
+
+pn_size
+			
+			Size of the PN field check.
+			
+			Needed for wrap around handling...
+			
+			
+			
+			<enum 0     pn_size_24>
+			
+			<enum 1     pn_size_48>
+			
+			<enum 2     pn_size_128>
+			
+			
+			
+			<legal 0-2>
+
+ignore_ampdu_flag
+			
+			When set, REO shall ignore the ampdu_flag on the
+			entrance descriptor for this queue.
+			
+			<legal all>
+
+reserved_2b
+			
+			<legal 0>
+
+svld
+			
+			Sequence number in next field is valid one. It can be
+			filled by SW if the want to fill in the any negotiated SSN,
+			otherwise REO will fill the sequence number of first
+			received packet and set this bit to 1.
+			
+			<legal all>
+
+ssn
+			
+			Starting Sequence number of the session, this changes
+			whenever window moves. (can be filled by SW then maintained
+			by REO)
+			
+			<legal all>
+
+current_index
+			
+			Points to last forwarded packet
+			
+			<legal all>
+
+seq_2k_error_detected_flag
+			
+			Set by REO, can only be cleared by SW
+			
+			
+			
+			When set, REO has detected a 2k error jump in the
+			sequence number and from that moment forward, all new frames
+			are forwarded directly to FW, without duplicate detect,
+			reordering, etc.
+			
+			<legal all>
+
+pn_error_detected_flag
+			
+			Set by REO, can only be cleared by SW
+			
+			
+			
+			When set, REO has detected a PN error and from that
+			moment forward, all new frames are forwarded directly to FW,
+			without duplicate detect, reordering, etc.
+			
+			<legal all>
+
+reserved_3a
+			
+			<legal 0>
+
+pn_valid
+			
+			PN number in next fields are valid. It can be filled by
+			SW if it wants to fill in the any negotiated SSN, otherwise
+			REO will fill the pn based on the first received packet and
+			set this bit to 1.
+			
+			<legal all>
+
+pn_31_0
+			
+			
+			<legal all>
+
+pn_63_32
+			
+			Bits [63:32] of the PN number.  
+			
+			<legal all> 
+
+pn_95_64
+			
+			Bits [95:64] of the PN number.  
+			
+			<legal all>
+
+pn_127_96
+			
+			Bits [127:96] of the PN number.  
+			
+			<legal all>
+
+last_rx_enqueue_timestamp
+			
+			This timestamp is updated when an MPDU is received and
+			accesses this Queue Descriptor. It does not include the
+			access due to Command TLVs or Aging (which will be updated
+			in Last_rx_dequeue_timestamp).
+			
+			<legal all>
+
+last_rx_dequeue_timestamp
+			
+			This timestamp is used for Aging. When an MPDU or
+			multiple MPDUs are forwarded, either due to window movement,
+			bar, aging or command flush, this timestamp is updated. Also
+			when the bitmap is all zero and the first time an MPDU is
+			queued (opcode=QCUR), this timestamp is updated for aging.
+			
+			<legal all>
+
+ptr_to_next_aging_queue_31_0
+			
+			Address  (address bits 31-0)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the last entry in the list.
+			
+			<legal all>
+
+ptr_to_next_aging_queue_39_32
+			
+			Address  (address bits 39-32)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the last entry in the list.
+			
+			<legal all>
+
+reserved_11a
+			
+			<legal 0>
+
+ptr_to_previous_aging_queue_31_0
+			
+			Address  (address bits 31-0)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the first entry in the list.
+			
+			<legal all>
+
+ptr_to_previous_aging_queue_39_32
+			
+			Address  (address bits 39-32)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the first entry in the list.
+			
+			<legal all>
+
+reserved_13a
+			
+			<legal 0>
+
+rx_bitmap_31_0
+			
+			When a bit is set, the corresponding frame is currently
+			held in the re-order queue.
+			
+			The bitmap  is Fully managed by HW. 
+			
+			SW shall init this to 0, and then never ever change it
+			
+			<legal all>
+
+rx_bitmap_63_32
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_95_64
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_127_96
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_159_128
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_191_160
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_223_192
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+rx_bitmap_255_224
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+
+current_mpdu_count
+			
+			The number of MPDUs in the queue.
+			
+			
+			
+			<legal all>
+
+current_msdu_count
+			
+			The number of MSDUs in the queue.
+			
+			<legal all>
+
+reserved_23
+			
+			<legal 0>
+
+timeout_count
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is Timeout
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+
+forward_due_to_bar_count
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is reception of BAR frame.
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+
+duplicate_count
+			
+			The number of duplicate frames that have been detected
+			
+			<legal all>
+
+frames_in_order_count
+			
+			The number of frames that have been received in order
+			(without a hole that prevented them from being forwarded
+			immediately)
+			
+			
+			
+			This corresponds to the Reorder opcodes:
+			
+			'FWDCUR' and 'FWD BUF'
+			
+			
+			
+			<legal all>
+
+bar_received_count
+			
+			The number of times a BAR frame is received.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'DROP'
+			
+			
+			
+			The counter saturates and freezes at 0xFF
+			
+			<legal all>
+
+mpdu_frames_processed_count
+			
+			The total number of MPDU frames that have been processed
+			by REO. 'Processing' here means that REO has received them
+			out of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			Note that field 'Duplicate_count' indicates how many of
+			these MPDUs were duplicates.
+			
+			
+			
+			<legal all>
+
+msdu_frames_processed_count
+			
+			The total number of MSDU frames that have been processed
+			by REO. 'Processing' here means that REO has received them
+			out of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			<legal all>
+
+total_processed_byte_count
+			
+			An approximation of the number of bytes processed for
+			this queue. 
+			
+			'Processing' here means that REO has received them out
+			of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			In 64 byte units
+			
+			<legal all>
+
+late_receive_mpdu_count
+			
+			The number of MPDUs received after the window had
+			already moved on. The 'late' sequence window is defined as
+			(Window SSN - 256) - (Window SSN - 1)
+			
+			
+			
+			This corresponds with Out of order detection in
+			duplicate detect FSM
+			
+			
+			
+			The counter saturates and freezes at 0xFFF
+			
+			
+			
+			<legal all>
+
+window_jump_2k
+			
+			The number of times the window moved more then 2K
+			
+			
+			
+			The counter saturates and freezes at 0xF
+			
+			
+			
+			(Note: field name can not start with number: previous
+			2k_window_jump)
+			
+			
+			
+			<legal all>
+
+hole_count
+			
+			The number of times a hole was created in the receive
+			bitmap.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'QCUR'
+			
+			
+			
+			<legal all>
+
+reserved_29
+			
+			<legal 0>
+
+reserved_30
+			
+			<legal 0>
+
+reserved_31
+			
+			<legal 0>
+*/
+
+#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
+#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
+#define RX_REO_QUEUE_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
+
+/* Description		RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER
+			
+			Indicates the MPDU queue ID to which this MPDU link
+			descriptor belongs
+			
+			Used for tracking and debugging
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET                   0x00000004
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB                      0
+#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK                     0x0000ffff
+
+/* Description		RX_REO_QUEUE_1_RESERVED_1B
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET                            0x00000004
+#define RX_REO_QUEUE_1_RESERVED_1B_LSB                               16
+#define RX_REO_QUEUE_1_RESERVED_1B_MASK                              0xffff0000
+
+/* Description		RX_REO_QUEUE_2_VLD
+			
+			Valid bit indicating a session is established and the
+			queue descriptor is valid(Filled by SW)
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_VLD_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_VLD_LSB                                       0
+#define RX_REO_QUEUE_2_VLD_MASK                                      0x00000001
+
+/* Description		RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER
+			
+			Indicates which of the 3 link descriptor counters shall
+			be incremented or decremented when link descriptors are
+			added or removed from this flow queue.
+			
+			MSDU link descriptors related with MPDUs stored in the
+			re-order buffer shall also be included in this count.
+			
+			
+			
+			<legal 0-2>
+*/
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET     0x00000008
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB        1
+#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK       0x00000006
+
+/* Description		RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION
+			
+			When set, do not perform any duplicate detection.
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET            0x00000008
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB               3
+#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK              0x00000008
+
+/* Description		RX_REO_QUEUE_2_SOFT_REORDER_ENABLE
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes.
+			
+			
+			
+			Note that this implies that REO is also not going to
+			perform any MSDU level operations, and the entire MPDU (and
+			thus pointer to the MSDU link descriptor) will be pushed to
+			a destination ring that SW has programmed in a SW
+			programmable configuration register in REO
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET                    0x00000008
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB                       4
+#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK                      0x00000010
+
+/* Description		RX_REO_QUEUE_2_AC
+			
+			Indicates which access category the queue descriptor
+			belongs to(filled by SW)
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_AC_OFFSET                                     0x00000008
+#define RX_REO_QUEUE_2_AC_LSB                                        5
+#define RX_REO_QUEUE_2_AC_MASK                                       0x00000060
+
+/* Description		RX_REO_QUEUE_2_BAR
+			
+			Indicates if  BAR has been received (mostly used for
+			debug purpose and this is filled by REO)
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_BAR_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_BAR_LSB                                       7
+#define RX_REO_QUEUE_2_BAR_MASK                                      0x00000080
+
+/* Description		RX_REO_QUEUE_2_RTY
+			
+			Retry bit is checked if this bit is set.  
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_RTY_OFFSET                                    0x00000008
+#define RX_REO_QUEUE_2_RTY_LSB                                       8
+#define RX_REO_QUEUE_2_RTY_MASK                                      0x00000100
+
+/* Description		RX_REO_QUEUE_2_CHK_2K_MODE
+			
+			Indicates what type of operation is expected from Reo
+			when the received frame SN falls within the 2K window
+			
+			
+			
+			See REO MLD document for programming details.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET                            0x00000008
+#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB                               9
+#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK                              0x00000200
+
+/* Description		RX_REO_QUEUE_2_OOR_MODE
+			
+			Out of Order mode:
+			
+			Indicates what type of operation is expected when the
+			received frame falls within the OOR window.
+			
+			
+			
+			See REO MLD document for programming details.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_OOR_MODE_OFFSET                               0x00000008
+#define RX_REO_QUEUE_2_OOR_MODE_LSB                                  10
+#define RX_REO_QUEUE_2_OOR_MODE_MASK                                 0x00000400
+
+/* Description		RX_REO_QUEUE_2_BA_WINDOW_SIZE
+			
+			Indicates the negotiated (window size + 1). 
+			
+			it can go up to Max of 256bits.
+			
+			
+			
+			A value 255 means 256 bitmap, 63 means 64 bitmap, 0
+			(means non-BA session, with window size of 0). The 3 values
+			here are the main values validated, but other values should
+			work as well.
+			
+			
+			
+			A BA window size of 0 (=> one frame entry bitmat), means
+			that there is NO RX_REO_QUEUE_EXT descriptor following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			A BA window size of 1 - 105, means that there is 1
+			RX_REO_QUEUE_EXT descriptor directly following this
+			RX_REO_QUEUE STRUCT in memory.
+			
+			
+			
+			A BA window size of 106 - 210, means that there are 2
+			RX_REO_QUEUE_EXT descriptors directly following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			A BA window size of 211 - 256, means that there are 3
+			RX_REO_QUEUE_EXT descriptors directly following this
+			RX_REO_QUEUE STRUCT in memory
+			
+			
+			
+			<legal 0 - 255>
+*/
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET                         0x00000008
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB                            11
+#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK                           0x0007f800
+
+/* Description		RX_REO_QUEUE_2_PN_CHECK_NEEDED
+			
+			When set, REO shall perform the PN increment check
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET                        0x00000008
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB                           19
+#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK                          0x00080000
+
+/* Description		RX_REO_QUEUE_2_PN_SHALL_BE_EVEN
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, REO shall confirm that the received PN number
+			is not only incremented, but also always an even number
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET                       0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB                          20
+#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK                         0x00100000
+
+/* Description		RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, REO shall confirm that the received PN number
+			is not only incremented, but also always an uneven number
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET                     0x00000008
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB                        21
+#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK                       0x00200000
+
+/* Description		RX_REO_QUEUE_2_PN_HANDLING_ENABLE
+			
+			Field only valid when 'pn_check_needed' is set.
+			
+			
+			
+			When set, and REO detected a PN error, HW shall set the
+			'pn_error_detected_flag'.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET                     0x00000008
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB                        22
+#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK                       0x00400000
+
+/* Description		RX_REO_QUEUE_2_PN_SIZE
+			
+			Size of the PN field check.
+			
+			Needed for wrap around handling...
+			
+			
+			
+			<enum 0     pn_size_24>
+			
+			<enum 1     pn_size_48>
+			
+			<enum 2     pn_size_128>
+			
+			
+			
+			<legal 0-2>
+*/
+#define RX_REO_QUEUE_2_PN_SIZE_OFFSET                                0x00000008
+#define RX_REO_QUEUE_2_PN_SIZE_LSB                                   23
+#define RX_REO_QUEUE_2_PN_SIZE_MASK                                  0x01800000
+
+/* Description		RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG
+			
+			When set, REO shall ignore the ampdu_flag on the
+			entrance descriptor for this queue.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET                      0x00000008
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB                         25
+#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK                        0x02000000
+
+/* Description		RX_REO_QUEUE_2_RESERVED_2B
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET                            0x00000008
+#define RX_REO_QUEUE_2_RESERVED_2B_LSB                               26
+#define RX_REO_QUEUE_2_RESERVED_2B_MASK                              0xfc000000
+
+/* Description		RX_REO_QUEUE_3_SVLD
+			
+			Sequence number in next field is valid one. It can be
+			filled by SW if the want to fill in the any negotiated SSN,
+			otherwise REO will fill the sequence number of first
+			received packet and set this bit to 1.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_SVLD_OFFSET                                   0x0000000c
+#define RX_REO_QUEUE_3_SVLD_LSB                                      0
+#define RX_REO_QUEUE_3_SVLD_MASK                                     0x00000001
+
+/* Description		RX_REO_QUEUE_3_SSN
+			
+			Starting Sequence number of the session, this changes
+			whenever window moves. (can be filled by SW then maintained
+			by REO)
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_SSN_OFFSET                                    0x0000000c
+#define RX_REO_QUEUE_3_SSN_LSB                                       1
+#define RX_REO_QUEUE_3_SSN_MASK                                      0x00001ffe
+
+/* Description		RX_REO_QUEUE_3_CURRENT_INDEX
+			
+			Points to last forwarded packet
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET                          0x0000000c
+#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB                             13
+#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK                            0x001fe000
+
+/* Description		RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG
+			
+			Set by REO, can only be cleared by SW
+			
+			
+			
+			When set, REO has detected a 2k error jump in the
+			sequence number and from that moment forward, all new frames
+			are forwarded directly to FW, without duplicate detect,
+			reordering, etc.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET             0x0000000c
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB                21
+#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK               0x00200000
+
+/* Description		RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG
+			
+			Set by REO, can only be cleared by SW
+			
+			
+			
+			When set, REO has detected a PN error and from that
+			moment forward, all new frames are forwarded directly to FW,
+			without duplicate detect, reordering, etc.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET                 0x0000000c
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB                    22
+#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK                   0x00400000
+
+/* Description		RX_REO_QUEUE_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET                            0x0000000c
+#define RX_REO_QUEUE_3_RESERVED_3A_LSB                               23
+#define RX_REO_QUEUE_3_RESERVED_3A_MASK                              0x7f800000
+
+/* Description		RX_REO_QUEUE_3_PN_VALID
+			
+			PN number in next fields are valid. It can be filled by
+			SW if it wants to fill in the any negotiated SSN, otherwise
+			REO will fill the pn based on the first received packet and
+			set this bit to 1.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_3_PN_VALID_OFFSET                               0x0000000c
+#define RX_REO_QUEUE_3_PN_VALID_LSB                                  31
+#define RX_REO_QUEUE_3_PN_VALID_MASK                                 0x80000000
+
+/* Description		RX_REO_QUEUE_4_PN_31_0
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_4_PN_31_0_OFFSET                                0x00000010
+#define RX_REO_QUEUE_4_PN_31_0_LSB                                   0
+#define RX_REO_QUEUE_4_PN_31_0_MASK                                  0xffffffff
+
+/* Description		RX_REO_QUEUE_5_PN_63_32
+			
+			Bits [63:32] of the PN number.  
+			
+			<legal all> 
+*/
+#define RX_REO_QUEUE_5_PN_63_32_OFFSET                               0x00000014
+#define RX_REO_QUEUE_5_PN_63_32_LSB                                  0
+#define RX_REO_QUEUE_5_PN_63_32_MASK                                 0xffffffff
+
+/* Description		RX_REO_QUEUE_6_PN_95_64
+			
+			Bits [95:64] of the PN number.  
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_6_PN_95_64_OFFSET                               0x00000018
+#define RX_REO_QUEUE_6_PN_95_64_LSB                                  0
+#define RX_REO_QUEUE_6_PN_95_64_MASK                                 0xffffffff
+
+/* Description		RX_REO_QUEUE_7_PN_127_96
+			
+			Bits [127:96] of the PN number.  
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_7_PN_127_96_OFFSET                              0x0000001c
+#define RX_REO_QUEUE_7_PN_127_96_LSB                                 0
+#define RX_REO_QUEUE_7_PN_127_96_MASK                                0xffffffff
+
+/* Description		RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP
+			
+			This timestamp is updated when an MPDU is received and
+			accesses this Queue Descriptor. It does not include the
+			access due to Command TLVs or Aging (which will be updated
+			in Last_rx_dequeue_timestamp).
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET              0x00000020
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB                 0
+#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK                0xffffffff
+
+/* Description		RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP
+			
+			This timestamp is used for Aging. When an MPDU or
+			multiple MPDUs are forwarded, either due to window movement,
+			bar, aging or command flush, this timestamp is updated. Also
+			when the bitmap is all zero and the first time an MPDU is
+			queued (opcode=QCUR), this timestamp is updated for aging.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET              0x00000024
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB                 0
+#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK                0xffffffff
+
+/* Description		RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0
+			
+			Address  (address bits 31-0)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the last entry in the list.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET          0x00000028
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB             0
+#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK            0xffffffff
+
+/* Description		RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32
+			
+			Address  (address bits 39-32)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the last entry in the list.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET         0x0000002c
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB            0
+#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK           0x000000ff
+
+/* Description		RX_REO_QUEUE_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET                          0x0000002c
+#define RX_REO_QUEUE_11_RESERVED_11A_LSB                             8
+#define RX_REO_QUEUE_11_RESERVED_11A_MASK                            0xffffff00
+
+/* Description		RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0
+			
+			Address  (address bits 31-0)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the first entry in the list.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET      0x00000030
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB         0
+#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK        0xffffffff
+
+/* Description		RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32
+			
+			Address  (address bits 39-32)of next RX_REO_QUEUE
+			descriptor in the 'receive timestamp' ordered list.
+			
+			From it the Position of this queue descriptor in the per
+			AC aging waitlist  can be derived.
+			
+			Value 0x0 indicates the 'NULL' pointer which implies
+			that this is the first entry in the list.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET     0x00000034
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB        0
+#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK       0x000000ff
+
+/* Description		RX_REO_QUEUE_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET                          0x00000034
+#define RX_REO_QUEUE_13_RESERVED_13A_LSB                             8
+#define RX_REO_QUEUE_13_RESERVED_13A_MASK                            0xffffff00
+
+/* Description		RX_REO_QUEUE_14_RX_BITMAP_31_0
+			
+			When a bit is set, the corresponding frame is currently
+			held in the re-order queue.
+			
+			The bitmap  is Fully managed by HW. 
+			
+			SW shall init this to 0, and then never ever change it
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET                        0x00000038
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB                           0
+#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK                          0xffffffff
+
+/* Description		RX_REO_QUEUE_15_RX_BITMAP_63_32
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET                       0x0000003c
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB                          0
+#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK                         0xffffffff
+
+/* Description		RX_REO_QUEUE_16_RX_BITMAP_95_64
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET                       0x00000040
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB                          0
+#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK                         0xffffffff
+
+/* Description		RX_REO_QUEUE_17_RX_BITMAP_127_96
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET                      0x00000044
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB                         0
+#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK                        0xffffffff
+
+/* Description		RX_REO_QUEUE_18_RX_BITMAP_159_128
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET                     0x00000048
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB                        0
+#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK                       0xffffffff
+
+/* Description		RX_REO_QUEUE_19_RX_BITMAP_191_160
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET                     0x0000004c
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB                        0
+#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK                       0xffffffff
+
+/* Description		RX_REO_QUEUE_20_RX_BITMAP_223_192
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET                     0x00000050
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB                        0
+#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK                       0xffffffff
+
+/* Description		RX_REO_QUEUE_21_RX_BITMAP_255_224
+			
+			See Rx_bitmap_31_0 description
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET                     0x00000054
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB                        0
+#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK                       0xffffffff
+
+/* Description		RX_REO_QUEUE_22_CURRENT_MPDU_COUNT
+			
+			The number of MPDUs in the queue.
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET                    0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB                       0
+#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK                      0x0000007f
+
+/* Description		RX_REO_QUEUE_22_CURRENT_MSDU_COUNT
+			
+			The number of MSDUs in the queue.
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET                    0x00000058
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB                       7
+#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK                      0xffffff80
+
+/* Description		RX_REO_QUEUE_23_RESERVED_23
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_23_RESERVED_23_OFFSET                           0x0000005c
+#define RX_REO_QUEUE_23_RESERVED_23_LSB                              0
+#define RX_REO_QUEUE_23_RESERVED_23_MASK                             0x0000000f
+
+/* Description		RX_REO_QUEUE_23_TIMEOUT_COUNT
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is Timeout
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET                         0x0000005c
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB                            4
+#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK                           0x000003f0
+
+/* Description		RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT
+			
+			The number of times that REO started forwarding frames
+			even though there is a hole in the bitmap. Forwarding reason
+			is reception of BAR frame.
+			
+			
+			
+			The counter saturates and freezes at 0x3F
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET              0x0000005c
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB                 10
+#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK                0x0000fc00
+
+/* Description		RX_REO_QUEUE_23_DUPLICATE_COUNT
+			
+			The number of duplicate frames that have been detected
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET                       0x0000005c
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB                          16
+#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK                         0xffff0000
+
+/* Description		RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT
+			
+			The number of frames that have been received in order
+			(without a hole that prevented them from being forwarded
+			immediately)
+			
+			
+			
+			This corresponds to the Reorder opcodes:
+			
+			'FWDCUR' and 'FWD BUF'
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET                 0x00000060
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB                    0
+#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK                   0x00ffffff
+
+/* Description		RX_REO_QUEUE_24_BAR_RECEIVED_COUNT
+			
+			The number of times a BAR frame is received.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'DROP'
+			
+			
+			
+			The counter saturates and freezes at 0xFF
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET                    0x00000060
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB                       24
+#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK                      0xff000000
+
+/* Description		RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT
+			
+			The total number of MPDU frames that have been processed
+			by REO. 'Processing' here means that REO has received them
+			out of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			Note that field 'Duplicate_count' indicates how many of
+			these MPDUs were duplicates.
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000064
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB              0
+#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
+
+/* Description		RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT
+			
+			The total number of MSDU frames that have been processed
+			by REO. 'Processing' here means that REO has received them
+			out of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET           0x00000068
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB              0
+#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK             0xffffffff
+
+/* Description		RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT
+			
+			An approximation of the number of bytes processed for
+			this queue. 
+			
+			'Processing' here means that REO has received them out
+			of the entrance ring, and retrieved the corresponding
+			RX_REO_QUEUE Descriptor. 
+			
+			
+			
+			Note that this count includes duplicates, frames that
+			later had errors, etc.
+			
+			
+			
+			In 64 byte units
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET            0x0000006c
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB               0
+#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK              0xffffffff
+
+/* Description		RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT
+			
+			The number of MPDUs received after the window had
+			already moved on. The 'late' sequence window is defined as
+			(Window SSN - 256) - (Window SSN - 1)
+			
+			
+			
+			This corresponds with Out of order detection in
+			duplicate detect FSM
+			
+			
+			
+			The counter saturates and freezes at 0xFFF
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET               0x00000070
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB                  0
+#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK                 0x00000fff
+
+/* Description		RX_REO_QUEUE_28_WINDOW_JUMP_2K
+			
+			The number of times the window moved more then 2K
+			
+			
+			
+			The counter saturates and freezes at 0xF
+			
+			
+			
+			(Note: field name can not start with number: previous
+			2k_window_jump)
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET                        0x00000070
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB                           12
+#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK                          0x0000f000
+
+/* Description		RX_REO_QUEUE_28_HOLE_COUNT
+			
+			The number of times a hole was created in the receive
+			bitmap.
+			
+			
+			
+			This corresponds to the Reorder opcodes with 'QCUR'
+			
+			
+			
+			<legal all>
+*/
+#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET                            0x00000070
+#define RX_REO_QUEUE_28_HOLE_COUNT_LSB                               16
+#define RX_REO_QUEUE_28_HOLE_COUNT_MASK                              0xffff0000
+
+/* Description		RX_REO_QUEUE_29_RESERVED_29
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_29_RESERVED_29_OFFSET                           0x00000074
+#define RX_REO_QUEUE_29_RESERVED_29_LSB                              0
+#define RX_REO_QUEUE_29_RESERVED_29_MASK                             0xffffffff
+
+/* Description		RX_REO_QUEUE_30_RESERVED_30
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_30_RESERVED_30_OFFSET                           0x00000078
+#define RX_REO_QUEUE_30_RESERVED_30_LSB                              0
+#define RX_REO_QUEUE_30_RESERVED_30_MASK                             0xffffffff
+
+/* Description		RX_REO_QUEUE_31_RESERVED_31
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_31_RESERVED_31_OFFSET                           0x0000007c
+#define RX_REO_QUEUE_31_RESERVED_31_LSB                              0
+#define RX_REO_QUEUE_31_RESERVED_31_MASK                             0xffffffff
+
+
+#endif // _RX_REO_QUEUE_H_

hw/qca6290/v1/rx_reo_queue_ext.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RX_REO_QUEUE_EXT_H_
+#define _RX_REO_QUEUE_EXT_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "uniform_descriptor_header.h"
+#include "rx_mpdu_link_ptr.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	struct uniform_descriptor_header descriptor_header;
+//	1	reserved_1a[31:0]
+//	2-3	struct rx_mpdu_link_ptr mpdu_link_pointer_0;
+//	4-5	struct rx_mpdu_link_ptr mpdu_link_pointer_1;
+//	6-7	struct rx_mpdu_link_ptr mpdu_link_pointer_2;
+//	8-9	struct rx_mpdu_link_ptr mpdu_link_pointer_3;
+//	10-11	struct rx_mpdu_link_ptr mpdu_link_pointer_4;
+//	12-13	struct rx_mpdu_link_ptr mpdu_link_pointer_5;
+//	14-15	struct rx_mpdu_link_ptr mpdu_link_pointer_6;
+//	16-17	struct rx_mpdu_link_ptr mpdu_link_pointer_7;
+//	18-19	struct rx_mpdu_link_ptr mpdu_link_pointer_8;
+//	20-21	struct rx_mpdu_link_ptr mpdu_link_pointer_9;
+//	22-23	struct rx_mpdu_link_ptr mpdu_link_pointer_10;
+//	24-25	struct rx_mpdu_link_ptr mpdu_link_pointer_11;
+//	26-27	struct rx_mpdu_link_ptr mpdu_link_pointer_12;
+//	28-29	struct rx_mpdu_link_ptr mpdu_link_pointer_13;
+//	30-31	struct rx_mpdu_link_ptr mpdu_link_pointer_14;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32
+
+struct rx_reo_queue_ext {
+    struct            uniform_descriptor_header                       descriptor_header;
+             uint32_t reserved_1a                     : 32; //[31:0]
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_0;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_1;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_2;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_3;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_4;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_5;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_6;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_7;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_8;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_9;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_10;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_11;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_12;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_13;
+    struct            rx_mpdu_link_ptr                       mpdu_link_pointer_14;
+};
+
+/*
+
+struct uniform_descriptor_header descriptor_header
+			
+			Details about which module owns this struct.
+			
+			Note that sub field Buffer_type shall be set to
+			Receive_REO_queue_ext_descriptor
+
+reserved_1a
+			
+			<legal 0>
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_0
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_1
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_2
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_3
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_4
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_5
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_6
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_7
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_8
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_9
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_10
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_11
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_12
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_13
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+
+struct rx_mpdu_link_ptr mpdu_link_pointer_14
+			
+			Consumer: REO
+			
+			Producer: REO
+			
+			
+			
+			Pointer to the next MPDU_link descriptor in the MPDU
+			queue
+*/
+
+#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_OFFSET 0x00000000
+#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_LSB 0
+#define RX_REO_QUEUE_EXT_0_UNIFORM_DESCRIPTOR_HEADER_DESCRIPTOR_HEADER_MASK 0xffffffff
+
+/* Description		RX_REO_QUEUE_EXT_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET                        0x00000004
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB                           0
+#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK                          0xffffffff
+#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x00000008
+#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB  0
+#define RX_REO_QUEUE_EXT_2_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_OFFSET 0x0000000c
+#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_LSB  0
+#define RX_REO_QUEUE_EXT_3_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_0_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000010
+#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB  0
+#define RX_REO_QUEUE_EXT_4_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_OFFSET 0x00000014
+#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_LSB  0
+#define RX_REO_QUEUE_EXT_5_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_1_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x00000018
+#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB  0
+#define RX_REO_QUEUE_EXT_6_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_OFFSET 0x0000001c
+#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_LSB  0
+#define RX_REO_QUEUE_EXT_7_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_2_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000020
+#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB  0
+#define RX_REO_QUEUE_EXT_8_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_OFFSET 0x00000024
+#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_LSB  0
+#define RX_REO_QUEUE_EXT_9_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_3_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x00000028
+#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0
+#define RX_REO_QUEUE_EXT_10_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_OFFSET 0x0000002c
+#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_LSB 0
+#define RX_REO_QUEUE_EXT_11_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_4_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000030
+#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0
+#define RX_REO_QUEUE_EXT_12_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_OFFSET 0x00000034
+#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_LSB 0
+#define RX_REO_QUEUE_EXT_13_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_5_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x00000038
+#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0
+#define RX_REO_QUEUE_EXT_14_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_OFFSET 0x0000003c
+#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_LSB 0
+#define RX_REO_QUEUE_EXT_15_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_6_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000040
+#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0
+#define RX_REO_QUEUE_EXT_16_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_OFFSET 0x00000044
+#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_LSB 0
+#define RX_REO_QUEUE_EXT_17_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_7_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x00000048
+#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0
+#define RX_REO_QUEUE_EXT_18_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_OFFSET 0x0000004c
+#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_LSB 0
+#define RX_REO_QUEUE_EXT_19_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_8_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000050
+#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0
+#define RX_REO_QUEUE_EXT_20_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_OFFSET 0x00000054
+#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_LSB 0
+#define RX_REO_QUEUE_EXT_21_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_9_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x00000058
+#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0
+#define RX_REO_QUEUE_EXT_22_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_OFFSET 0x0000005c
+#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_LSB 0
+#define RX_REO_QUEUE_EXT_23_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_10_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000060
+#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0
+#define RX_REO_QUEUE_EXT_24_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_OFFSET 0x00000064
+#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_LSB 0
+#define RX_REO_QUEUE_EXT_25_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_11_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x00000068
+#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0
+#define RX_REO_QUEUE_EXT_26_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_OFFSET 0x0000006c
+#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_LSB 0
+#define RX_REO_QUEUE_EXT_27_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_12_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000070
+#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0
+#define RX_REO_QUEUE_EXT_28_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_OFFSET 0x00000074
+#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_LSB 0
+#define RX_REO_QUEUE_EXT_29_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_13_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x00000078
+#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0
+#define RX_REO_QUEUE_EXT_30_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff
+#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_OFFSET 0x0000007c
+#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_LSB 0
+#define RX_REO_QUEUE_EXT_31_RX_MPDU_LINK_PTR_MPDU_LINK_POINTER_14_MASK 0xffffffff
+
+
+#endif // _RX_REO_QUEUE_EXT_H_

hw/qca6290/v1/rxpt_classify_info.h

@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _RXPT_CLASSIFY_INFO_H_
+#define _RXPT_CLASSIFY_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	reo_destination_indication[4:0], use_flow_id_toeplitz_clfy[5], reserved_0a[31:6]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1
+
+struct rxpt_classify_info {
+             uint32_t reo_destination_indication      :  5, //[4:0]
+                      use_flow_id_toeplitz_clfy       :  1, //[5]
+                      reserved_0a                     : 26; //[31:6]
+};
+
+/*
+
+reo_destination_indication
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+use_flow_id_toeplitz_clfy
+			
+			indication to Rx OLE to enable classification based on
+			'flow_id_toeplitz' from Common Parser, in case flow search
+			fails
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+*/
+
+
+/* Description		RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET       0x00000000
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB          0
+#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK         0x0000001f
+
+/* Description		RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY
+			
+			indication to Rx OLE to enable classification based on
+			'flow_id_toeplitz' from Common Parser, in case flow search
+			fails
+			
+			<legal all>
+*/
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET        0x00000000
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB           5
+#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK          0x00000020
+
+/* Description		RXPT_CLASSIFY_INFO_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_OFFSET                      0x00000000
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_LSB                         6
+#define RXPT_CLASSIFY_INFO_0_RESERVED_0A_MASK                        0xffffffc0
+
+
+#endif // _RXPT_CLASSIFY_INFO_H_

hw/qca6290/v1/seq_hwio.h

@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/*********************************************************************************
+ *
+ * DESCRIPTION
+ * - This is an extension of standard msmhwio.h to support relative addressing
+ *   scheme used in SCALe auto-generated sequences.
+ * - The objective of this new addressing scheme is enable the same C function
+ *   definition to be applicable to multiple baseances of the same block. 
+ * - Such code reuse is not feasible with the standard HWIO macros that use a
+ *   absolute addressing scheme.
+ * - Compared to the standard HWIO macros, the new macros defined here take an
+ *   additional parameter 'baseance offset'.  So are the C functions generated
+ *   by SCALe Autoseq from .seq inputs.
+ * - As such, macros defined in this file must be used with 'seq_msmhwiobase.h',
+ *   'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq.
+ * - Macros defined in this file leverage the lower-level macros from the
+ *   standard 'msmhwio.h', and the two sets of macros are compatible.
+ *
+ ********************************************************************************/
+
+#ifndef __SEQ_H__
+#define __SEQ_H__
+
+#include "HALhwio.h"
+
+
+
+/**** Register Ref Read ****/
+#define SEQ_INH(base, regtype, reg) \
+        SEQ_##regtype##_INH(base, reg)
+
+/**** Masked Register Read ****/
+#define SEQ_INMH(base, regtype, reg, mask) \
+        SEQ_##regtype##_INMH(base, reg, mask)
+
+
+/**** Ref Reg Field Read ****/
+#define SEQ_INFH(base, regtype, reg, fld) \
+        (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld))
+
+
+/**** Ref Register  Write ****/
+#define SEQ_OUTH(base, regtype, reg, val) \
+        SEQ_##regtype##_OUTH(base, reg, val)
+
+/**** Ref Register Masked Write ****/
+#define SEQ_OUTMH(base, regtype, reg, mask, val) \
+        SEQ_##regtype##_OUTMH(base, reg, mask, val)
+
+
+/**** Ref Register Field Write ****/
+#define SEQ_OUTFH(base, regtype, reg, fld, val) \
+        SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld))
+
+
+/**** seq_msg() ****
+
+typedef enum {
+	DEBUG,
+	INFO,
+	WARNING,
+	ERROR,
+	FATAL
+} SeverityLevel ;
+
+void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... );
+
+*/
+
+/************ seq_wait() ************/
+
+typedef enum {
+    SEC,
+    MS,
+    US,
+    NS
+} SEQ_TimeUnit;
+
+extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit);
+
+
+/************ seq_poll() ************/
+extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt);
+
+#endif /* __SEQ_H__ */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

hw/qca6290/v1/sw_xml_headers.h

@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+#ifndef _SW_XML_HEADERS_H_
+#define _SW_XML_HEADERS_H_
+
+
+#include "ack_report.h"
+#include "addr_search_entry.h"
+#include "buffer_addr_info.h"
+#include "cce_rule.h"
+#include "ce_src_desc.h"
+#include "he_sig_a_mu_dl_info.h"
+#include "he_sig_a_mu_ul_info.h"
+#include "he_sig_a_su_info.h"
+#include "he_sig_b1_mu_info.h"
+#include "he_sig_b2_mu_info.h"
+#include "he_sig_b2_ofdma_info.h"
+#include "ht_sig_info.h"
+#include "l_sig_a_info.h"
+#include "l_sig_b_info.h"
+#include "mactx_abort_request_info.h"
+#include "mimo_control_info.h"
+#include "no_ack_report.h"
+#include "pcu_ppdu_setup_end_info.h"
+#include "pdg_response_rate_setting.h"
+#include "peer_table_entry.h"
+#include "phyrx_abort_request_info.h"
+#include "ppdu_rate_setting.h"
+#include "prot_rate_setting.h"
+#include "receive_rssi_info.h"
+#include "receive_user_info.h"
+#include "received_trigger_info_details.h"
+#include "reo_destination_ring.h"
+#include "reo_entrance_ring.h"
+#include "reo_to_ppe_ring.h"
+#include "response_rate_setting.h"
+#include "rx_flow_search_entry.h"
+#include "rx_location_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_mpdu_details.h"
+#include "rx_mpdu_info.h"
+#include "rx_mpdu_link.h"
+#include "rx_mpdu_link_ptr.h"
+#include "rx_msdu_desc_info.h"
+#include "rx_msdu_details.h"
+#include "rx_msdu_link.h"
+#include "rx_peer_entry_details.h"
+#include "rx_reo_queue.h"
+#include "rx_reo_queue_ext.h"
+#include "rx_reo_queue_reference.h"
+#include "rx_rxpcu_classification_overview.h"
+#include "rx_timing_offset_info.h"
+#include "rxole_cce_classify_info.h"
+#include "rxole_cce_info.h"
+#include "rxole_cce_superrule.h"
+#include "rxpt_classify_info.h"
+#include "scheduler_cmd.h"
+#include "service_info.h"
+#include "sw_peer_info.h"
+#include "tcl_cce_classify_info.h"
+#include "tcl_cce_info.h"
+#include "tcl_cce_superrule.h"
+#include "tcl_compact_exit_ring.h"
+#include "tcl_entrance_from_ppe_ring.h"
+#include "tcl_exit_base.h"
+#include "tcl_extended_exit_ring.h"
+#include "tcl_regular_exit_ring.h"
+#include "tcl_status_ring.h"
+#include "tqm_entrance_ring.h"
+#include "tx_flow_search_entry.h"
+#include "tx_mpdu_details.h"
+#include "tx_mpdu_link.h"
+#include "tx_mpdu_link_ptr.h"
+#include "tx_mpdu_queue_ext.h"
+#include "tx_mpdu_queue_ext_ptr.h"
+#include "tx_mpdu_queue_head.h"
+#include "tx_msdu_details.h"
+#include "tx_msdu_extension.h"
+#include "tx_msdu_flow.h"
+#include "tx_msdu_link.h"
+#include "tx_msdu_link_entry_ptr.h"
+#include "tx_rate_stats_info.h"
+#include "txpcu_buffer_basics.h"
+#include "txpt_classify_info.h"
+#include "uniform_descriptor_header.h"
+#include "uniform_reo_cmd_header.h"
+#include "uniform_reo_status_header.h"
+#include "uniform_tqm_cmd_header.h"
+#include "uniform_tqm_status_header.h"
+#include "uplink_common_info.h"
+#include "uplink_user_setup_info.h"
+#include "user_rate_setting.h"
+#include "vht_sig_a_info.h"
+#include "vht_sig_b_mu160_info.h"
+#include "vht_sig_b_mu20_info.h"
+#include "vht_sig_b_mu40_info.h"
+#include "vht_sig_b_mu80_info.h"
+#include "vht_sig_b_su160_info.h"
+#include "vht_sig_b_su20_info.h"
+#include "vht_sig_b_su40_info.h"
+#include "vht_sig_b_su80_info.h"
+#include "wbm_buffer_ring.h"
+#include "wbm_link_descriptor_ring.h"
+#include "wbm_release_ring.h"
+#include "who_classify_info.h"
+#include "macrx_abort_request_info.h"
+#include "phytx_abort_request_info.h"
+#include "ce_stat_desc.h"
+#include "coex_mac_nap.h"
+#include "coex_rx_status.h"
+#include "coex_status_broadcast.h"
+#include "coex_tx_req.h"
+#include "coex_tx_resp.h"
+#include "coex_tx_status.h"
+#include "coex_tx_stop_ctrl.h"
+#include "crypto_status.h"
+#include "expected_response.h"
+#include "mactx_abort_request.h"
+#include "mactx_bf_params_common.h"
+#include "mactx_coex_phy_ctrl.h"
+#include "mactx_delete_cv.h"
+#include "mactx_he_sig_a_mu_dl.h"
+#include "mactx_he_sig_a_mu_ul.h"
+#include "mactx_he_sig_a_su.h"
+#include "mactx_he_sig_b1_mu.h"
+#include "mactx_he_sig_b2_mu.h"
+#include "mactx_he_sig_b2_ofdma.h"
+#include "mactx_ht_sig.h"
+#include "mactx_l_sig_a.h"
+#include "mactx_l_sig_b.h"
+#include "mactx_mu_uplink_common.h"
+#include "mactx_phy_desc.h"
+#include "mactx_phy_nap.h"
+#include "mactx_pre_phy_desc.h"
+#include "mactx_prefetch_cv.h"
+#include "mactx_user_desc_common.h"
+#include "mactx_vht_sig_a.h"
+#include "mactx_vht_sig_b_su160.h"
+#include "mactx_vht_sig_b_su20.h"
+#include "mactx_vht_sig_b_su40.h"
+#include "mactx_vht_sig_b_su80.h"
+#include "ofdma_trigger_details.h"
+#include "ole_buf_status.h"
+#include "pcu_ppdu_setup_end.h"
+#include "pcu_ppdu_setup_init.h"
+#include "pcu_ppdu_setup_start.h"
+#include "pdg_fes_setup.h"
+#include "pdg_response.h"
+#include "pdg_sw_mode_bw_start.h"
+#include "pdg_tx_req.h"
+#include "pdg_wait_for_mac_request.h"
+#include "pdg_wait_for_phy_request.h"
+#include "phyrx_cbf_read_request_ack.h"
+#include "phyrx_generated_cbf_details.h"
+#include "phyrx_he_sig_a_mu_dl.h"
+#include "phyrx_he_sig_a_mu_ul.h"
+#include "phyrx_he_sig_a_su.h"
+#include "phyrx_he_sig_b1_mu.h"
+#include "phyrx_he_sig_b2_mu.h"
+#include "phyrx_he_sig_b2_ofdma.h"
+#include "phyrx_ht_sig.h"
+#include "phyrx_l_sig_a.h"
+#include "phyrx_l_sig_b.h"
+#include "phyrx_pkt_end.h"
+#include "phyrx_rssi_ht.h"
+#include "phyrx_rssi_legacy.h"
+#include "phyrx_vht_sig_a.h"
+#include "phyrx_vht_sig_b_su160.h"
+#include "phyrx_vht_sig_b_su20.h"
+#include "phyrx_vht_sig_b_su40.h"
+#include "phyrx_vht_sig_b_su80.h"
+#include "received_response_info.h"
+#include "received_trigger_info.h"
+#include "reo_descriptor_threshold_reached_status.h"
+#include "reo_flush_cache.h"
+#include "reo_flush_cache_status.h"
+#include "reo_flush_queue.h"
+#include "reo_flush_queue_status.h"
+#include "reo_flush_timeout_list.h"
+#include "reo_flush_timeout_list_status.h"
+#include "reo_get_queue_stats.h"
+#include "reo_get_queue_stats_status.h"
+#include "reo_unblock_cache.h"
+#include "reo_unblock_cache_status.h"
+#include "reo_update_rx_reo_queue.h"
+#include "reo_update_rx_reo_queue_status.h"
+#include "response_end_status.h"
+#include "response_start_status.h"
+#include "rx_frame_bitmap_req.h"
+#include "rx_frameless_bar_details.h"
+#include "rx_pm_info.h"
+#include "rx_ppdu_ack_report.h"
+#include "rx_ppdu_end_status_done.h"
+#include "rx_ppdu_no_ack_report.h"
+#include "rx_ppdu_start.h"
+#include "rx_preamble.h"
+#include "rx_response_required_info.h"
+#include "rx_ring_mask.h"
+#include "rx_start_param.h"
+#include "rx_trig_info.h"
+#include "rxpcu_ppdu_end_info.h"
+#include "rxpcu_setup.h"
+#include "sch_coex_status.h"
+#include "sch_wait_instr.h"
+#include "scheduler_command_status.h"
+#include "scheduler_rx_ppdu_no_response_status.h"
+#include "scheduler_rx_sifs_response_trigger_status.h"
+#include "scheduler_selfgen_response_status.h"
+#include "tcl_data_cmd.h"
+#include "tcl_gse_cmd.h"
+#include "tqm_acked_mpdu_status.h"
+#include "tqm_add_msdu_status.h"
+#include "tqm_descriptor_threshold_reached_status.h"
+#include "tqm_flow_empty_status.h"
+#include "tqm_flow_not_empty_status.h"
+#include "tqm_flush_cache.h"
+#include "tqm_flush_cache_status.h"
+#include "tqm_gen_mpdu_length_list.h"
+#include "tqm_gen_mpdu_length_list_status.h"
+#include "tqm_gen_mpdus.h"
+#include "tqm_gen_mpdus_status.h"
+#include "tqm_get_mpdu_head_info.h"
+#include "tqm_get_mpdu_head_info_status.h"
+#include "tqm_get_mpdu_queue_stats.h"
+#include "tqm_get_mpdu_queue_stats_status.h"
+#include "tqm_get_msdu_flow_stats.h"
+#include "tqm_get_msdu_flow_stats_status.h"
+#include "tqm_remove_mpdu.h"
+#include "tqm_remove_mpdu_status.h"
+#include "tqm_remove_msdu.h"
+#include "tqm_remove_msdu_status.h"
+#include "tqm_sync_cmd.h"
+#include "tqm_sync_cmd_status.h"
+#include "tqm_threshold_drop_notification_status.h"
+#include "tqm_unblock_cache.h"
+#include "tqm_unblock_cache_status.h"
+#include "tqm_update_tx_mpdu_count_status.h"
+#include "tqm_update_tx_mpdu_queue_head.h"
+#include "tqm_update_tx_mpdu_queue_head_status.h"
+#include "tqm_update_tx_msdu_flow.h"
+#include "tqm_update_tx_msdu_flow_status.h"
+#include "tqm_write_cmd.h"
+#include "tqm_write_cmd_status.h"
+#include "tx_cbf_info.h"
+#include "tx_data_sync.h"
+#include "tx_fes_setup.h"
+#include "tx_fes_status_end.h"
+#include "tx_fes_status_prot.h"
+#include "tx_fes_status_start.h"
+#include "tx_fes_status_start_ppdu.h"
+#include "tx_fes_status_start_prot.h"
+#include "tx_flush_req.h"
+#include "tx_sw_mode_setup.h"
+#include "txpcu_buffer_status.h"
+#include "who_terminate.h"
+#include "data_to_time_config.h"
+#include "mactx_bf_params_per_user.h"
+#include "mactx_expect_cbf_common.h"
+#include "mactx_expect_cbf_per_user.h"
+#include "mactx_mu_uplink_user_setup.h"
+#include "mactx_service.h"
+#include "mactx_user_desc_per_user.h"
+#include "mactx_vht_sig_b_mu160.h"
+#include "mactx_vht_sig_b_mu20.h"
+#include "mactx_vht_sig_b_mu40.h"
+#include "mactx_vht_sig_b_mu80.h"
+#include "mpdu_info.h"
+#include "mpdu_info_bitmap.h"
+#include "mpdu_limit.h"
+#include "pcu_ppdu_setup_user.h"
+#include "pdg_user_setup.h"
+#include "phyrx_common_user_info.h"
+#include "phyrx_user_info.h"
+#include "phyrx_vht_sig_b_mu160.h"
+#include "phyrx_vht_sig_b_mu20.h"
+#include "phyrx_vht_sig_b_mu40.h"
+#include "phyrx_vht_sig_b_mu80.h"
+#include "rx_attention.h"
+#include "rx_frame_bitmap_ack.h"
+#include "rx_header.h"
+#include "rx_mpdu_end.h"
+#include "rx_mpdu_pcu_start.h"
+#include "rx_mpdu_start.h"
+#include "rx_msdu_end.h"
+#include "rx_msdu_start.h"
+#include "rx_peer_entry.h"
+#include "rx_ppdu_end_user_stats.h"
+#include "rx_ppdu_end_user_stats_ext.h"
+#include "rx_ppdu_start_user_info.h"
+#include "rxpcu_user_setup.h"
+#include "rxpcu_user_setup_ext.h"
+#include "tqm_acked_mpdu.h"
+#include "tqm_update_tx_mpdu_count.h"
+#include "tx_11ah_setup.h"
+#include "tx_cv_start.h"
+#include "tx_fes_status_ack_or_ba.h"
+#include "tx_fes_status_user_ppdu.h"
+#include "tx_fes_status_user_response.h"
+#include "tx_mpdu_start.h"
+#include "tx_msdu_start.h"
+#include "tx_peer_entry.h"
+#include "tx_queue_extension.h"
+#include "tx_raw_or_native_frame_setup.h"
+#include "txpcu_user_buffer_status.h"
+#include "txpcu_user_setup.h"
+#include "who_anchor_value.h"
+#include "who_cce_info.h"
+#include "who_commit_done.h"
+#include "who_l2_llc.h"
+#include "who_l3_checksum.h"
+#include "who_l3_info.h"
+#include "who_l4_checksum.h"
+#include "who_l4_info.h"
+#include "who_mesh_control.h"
+#include "who_msdu_misc.h"
+#include "who_packet_hdr.h"
+#include "who_tso.h"
+#include "who_wmac_header_pv0.h"
+#include "who_wmac_header_pv1.h"
+#include "who_wmac_iv.h"
+#include "tlv_tag_def.h"
+#include "mactx_cbf_data.h"
+#include "mactx_cbf_done.h"
+#include "mactx_cbf_start.h"
+#include "mactx_data_resp.h"
+#include "phyrx_abort_request.h"
+#include "phyrx_cbf_data_resp.h"
+#include "phyrx_data.h"
+#include "phyrx_user_abort_notification.h"
+#include "macrx_abort_request.h"
+#include "macrx_cbf_data_request.h"
+#include "macrx_cbf_read_request.h"
+#include "macrx_chain_mask.h"
+#include "macrx_expect_ndp_reception.h"
+#include "macrx_freeze_capture_channel.h"
+#include "macrx_req_implicit_fb.h"
+#include "phytx_abort_request.h"
+#include "phytx_bf_cv_loading_done.h"
+#include "phytx_nap_ack.h"
+#include "phytx_pkt_end.h"
+#include "phytx_ppdu_header_info_request.h"
+#include "phytx_request_ctrl_info.h"
+
+
+#endif

hw/qca6290/v1/tcl_data_cmd.h

@@ -0,0 +1,890 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _TCL_DATA_CMD_H_
+#define _TCL_DATA_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info buf_addr_info;
+//	2	buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], reserved[13:10], addrx_en[14], addry_en[15], tcl_cmd_number[31:16]
+//	3	data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], dscp_to_tid_priority_table_id[22], packet_offset[31:23]
+//	4	buffer_timestamp[18:0], buffer_timestamp_valid[19], mesh_enable[20], hlos_tid_overwrite[21], hlos_tid[25:22], reserved_4[31:26]
+//	5	reserved_5[31:0]
+//	6	reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_DATA_CMD 7
+
+struct tcl_data_cmd {
+    struct            buffer_addr_info                       buf_addr_info;
+             uint32_t buf_or_ext_desc_type            :  1, //[0]
+                      epd                             :  1, //[1]
+                      encap_type                      :  2, //[3:2]
+                      encrypt_type                    :  4, //[7:4]
+                      src_buffer_swap                 :  1, //[8]
+                      link_meta_swap                  :  1, //[9]
+                      reserved                        :  4, //[13:10]
+                      addrx_en                        :  1, //[14]
+                      addry_en                        :  1, //[15]
+                      tcl_cmd_number                  : 16; //[31:16]
+             uint32_t data_length                     : 16, //[15:0]
+                      ipv4_checksum_en                :  1, //[16]
+                      udp_over_ipv4_checksum_en       :  1, //[17]
+                      udp_over_ipv6_checksum_en       :  1, //[18]
+                      tcp_over_ipv4_checksum_en       :  1, //[19]
+                      tcp_over_ipv6_checksum_en       :  1, //[20]
+                      to_fw                           :  1, //[21]
+                      dscp_to_tid_priority_table_id   :  1, //[22]
+                      packet_offset                   :  9; //[31:23]
+             uint32_t buffer_timestamp                : 19, //[18:0]
+                      buffer_timestamp_valid          :  1, //[19]
+                      mesh_enable                     :  1, //[20]
+                      hlos_tid_overwrite              :  1, //[21]
+                      hlos_tid                        :  4, //[25:22]
+                      reserved_4                      :  6; //[31:26]
+             uint32_t reserved_5                      : 32; //[31:0]
+             uint32_t reserved_6a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info buf_addr_info
+			
+			Details of the physical address for a single buffer
+			
+			It also contains return ownership info as well as some
+			meta data for SW related to this buffer.
+			
+			
+			
+			In case of Buf_or_ext_desc_type indicating
+			'MSDU_buffer', this address indicates the start of the meta
+			data that is preceding the actual packet data.
+			
+			The start of the actual packet data is provided by
+			field: Packet_offset
+
+buf_or_ext_desc_type
+			
+			<enum 0 MSDU_buffer> The address points to an MSDU
+			buffer. 
+			
+			<enum 1 extension_descriptor> The address points to an
+			MSDU link extension descriptor
+			
+			< legal all>
+
+epd
+			
+			When this bit is set then input packet is an EPD type
+			
+			<legal all>
+
+encap_type
+			
+			Indicates the encapsulation that HW will perform:
+			
+			<enum 0 RAW> No encapsulation
+			
+			<enum 1 Native_WiFi>
+			
+			<enum 2 Ethernet> Ethernet 2 (DIX)  
+			
+			<enum 3 802_3> 802.3 (uses SNAP/LLC)
+			
+			Used by the OLE during encapsulation.
+			
+			<legal all>
+
+encrypt_type
+			
+			Field only valid for encap_type: RAW 
+			
+			
+			
+			Indicates type of decrypt cipher used (as defined in the
+			peer entry)
+			
+			<enum 0 wep_40> WEP 40-bit
+			
+			<enum 1 wep_104> WEP 104-bit
+			
+			<enum 2 tkip_no_mic> TKIP without MIC
+			
+			<enum 3 wep_128> WEP 128-bit
+			
+			<enum 4 tkip_with_mic> TKIP with MIC
+			
+			<enum 5 wapi> WAPI
+			
+			<enum 6 aes_ccmp_128> AES CCMP 128
+			
+			<enum 7 no_cipher> No crypto
+			
+			<enum 8 aes_ccmp_256> AES CCMP 256
+			
+			<enum 9 aes_gcmp_128> AES CCMP 128
+			
+			<enum 10 aes_gcmp_256> AES CCMP 256
+			
+			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
+			
+			<legal 0-11>
+
+src_buffer_swap
+			
+			Treats source memory (packet buffer) organization as
+			big-endian. The packets are read and byte swapped.
+			
+			1'b0: Source memory is little endian
+			
+			1'b1: Source memory is big endian
+			
+			<legal all>
+
+link_meta_swap
+			
+			Treats link descriptor and Metadata as big-endian. The
+			link descriptor/Metadata is read and byte swapped.
+			
+			1'b0: Memory is little endian
+			
+			1'b1: Memory is big endian
+			
+			<legal all>
+
+reserved
+			
+			<legal 0>
+
+addrx_en
+			
+			Address X search enable in ASE
+			
+			1'b0: Search disable
+			
+			1'b1: Search Enable
+			
+			<legal all>
+
+addry_en
+			
+			Address Y search enable in ASE
+			
+			1'b0: Search disable
+			
+			1'b1: Search Enable
+			
+			<legal all>
+
+tcl_cmd_number
+			
+			This number can be used by SW to track, identify and
+			link the created commands with the command statuses
+			
+			
+			
+			Is set to the value 'TCL_CMD_Number' of the related
+			TCL_DATA command
+			
+			<legal all> 
+
+data_length
+			
+			Valid Data length in bytes. 
+			
+			
+			
+			MSDU length in case of direct descriptor.
+			
+			Length of link extension descriptor in case of Link
+			extension descriptor. This is used to know the size of
+			Metadata.
+			
+			<legal all>
+
+ipv4_checksum_en
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable IPv4 checksum replacement
+
+udp_over_ipv4_checksum_en
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable UDP over IPv4 checksum replacement.  UDP checksum
+			over IPv4 is optional for TCP/IP stacks.
+
+udp_over_ipv6_checksum_en
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable UDP over IPv6 checksum replacement.  UDP checksum
+			over IPv6 is mandatory for TCP/IP stacks.
+
+tcp_over_ipv4_checksum_en
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable TCP checksum over IPv4 replacement
+
+tcp_over_ipv6_checksum_en
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable TCP checksum over IPv6 replacement
+
+to_fw
+			
+			Forward packet to FW along with classification result.
+			The packet will not be forward to TQM when this bit is set
+			
+			1'b0: Use classification result to forward the packet.
+			
+			1'b1: Override classification result and forward packet
+			only to FW.
+
+dscp_to_tid_priority_table_id
+			
+			The DSCP to tid conversion table to be used for this
+			frame
+			
+			<legal all>
+
+packet_offset
+			
+			Packet offset from Metadata in case of direct buffer
+			descriptor. This field is valid when Buf_or_ext_desc_type is
+			reset(= 0).
+			
+			<legal all>
+
+buffer_timestamp
+			
+			Field only valid when 'Buffer_timestamp_valid ' is set.
+			
+			
+			
+			Frame system entrance timestamp. The timestamp is
+			related to the global system timer
+			
+			
+			
+			Generally the first module (SW, TCL or TQM). that sees
+			this frame and this timestamp field is not valid, shall fill
+			in this field.
+			
+			
+			
+			Timestamp in units of 1024 us
+
+buffer_timestamp_valid
+			
+			When set, the Buffer_timestamp field contains valid
+			info.
+
+mesh_enable
+			
+			If set to 1:
+			
+			* For raw WiFi frames, this indicates transmission to a
+			mesh STA, enabling the interpretation of the 'Mesh Control
+			Present' bit (bit 8) of QoS Control (otherwise this bit is
+			ignored),
+			
+			* For native WiFi frames, this indicates that a 'Mesh
+			Control' field is present between the header and the LLC.
+
+hlos_tid_overwrite
+			
+			When set, TCL shall ignore the IP DSCP and VLAN PCP
+			fields and use HLOS_TID as the final TID. Otherwise TCL
+			shall consider the DSCP and PCP fields as well as HLOS_TID
+			and choose a final TID based on the configured priority 
+			
+			<legal all>
+
+hlos_tid
+			
+			HLOS MSDU priority
+			
+			
+			
+			Field is used when HLOS_TID_overwrite is set.
+			
+			
+			
+			Field is also used when HLOS_TID_overwrite is not set
+			and DSCP/PCP is not available in the packet
+			
+			<legal all>
+
+reserved_4
+			
+			<legal 0>
+
+reserved_5
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET         0x00000000
+#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB            28
+#define TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK           0xffffffff
+#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET         0x00000004
+#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB            28
+#define TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK           0xffffffff
+
+/* Description		TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE
+			
+			<enum 0 MSDU_buffer> The address points to an MSDU
+			buffer. 
+			
+			<enum 1 extension_descriptor> The address points to an
+			MSDU link extension descriptor
+			
+			< legal all>
+*/
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET                   0x00000008
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB                      0
+#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK                     0x00000001
+
+/* Description		TCL_DATA_CMD_2_EPD
+			
+			When this bit is set then input packet is an EPD type
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_EPD_OFFSET                                    0x00000008
+#define TCL_DATA_CMD_2_EPD_LSB                                       1
+#define TCL_DATA_CMD_2_EPD_MASK                                      0x00000002
+
+/* Description		TCL_DATA_CMD_2_ENCAP_TYPE
+			
+			Indicates the encapsulation that HW will perform:
+			
+			<enum 0 RAW> No encapsulation
+			
+			<enum 1 Native_WiFi>
+			
+			<enum 2 Ethernet> Ethernet 2 (DIX)  
+			
+			<enum 3 802_3> 802.3 (uses SNAP/LLC)
+			
+			Used by the OLE during encapsulation.
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET                             0x00000008
+#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB                                2
+#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK                               0x0000000c
+
+/* Description		TCL_DATA_CMD_2_ENCRYPT_TYPE
+			
+			Field only valid for encap_type: RAW 
+			
+			
+			
+			Indicates type of decrypt cipher used (as defined in the
+			peer entry)
+			
+			<enum 0 wep_40> WEP 40-bit
+			
+			<enum 1 wep_104> WEP 104-bit
+			
+			<enum 2 tkip_no_mic> TKIP without MIC
+			
+			<enum 3 wep_128> WEP 128-bit
+			
+			<enum 4 tkip_with_mic> TKIP with MIC
+			
+			<enum 5 wapi> WAPI
+			
+			<enum 6 aes_ccmp_128> AES CCMP 128
+			
+			<enum 7 no_cipher> No crypto
+			
+			<enum 8 aes_ccmp_256> AES CCMP 256
+			
+			<enum 9 aes_gcmp_128> AES CCMP 128
+			
+			<enum 10 aes_gcmp_256> AES CCMP 256
+			
+			<enum 11 wapi_gcm_sm4> WAPI GCM SM4
+			
+			<legal 0-11>
+*/
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET                           0x00000008
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB                              4
+#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK                             0x000000f0
+
+/* Description		TCL_DATA_CMD_2_SRC_BUFFER_SWAP
+			
+			Treats source memory (packet buffer) organization as
+			big-endian. The packets are read and byte swapped.
+			
+			1'b0: Source memory is little endian
+			
+			1'b1: Source memory is big endian
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET                        0x00000008
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB                           8
+#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK                          0x00000100
+
+/* Description		TCL_DATA_CMD_2_LINK_META_SWAP
+			
+			Treats link descriptor and Metadata as big-endian. The
+			link descriptor/Metadata is read and byte swapped.
+			
+			1'b0: Memory is little endian
+			
+			1'b1: Memory is big endian
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET                         0x00000008
+#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB                            9
+#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK                           0x00000200
+
+/* Description		TCL_DATA_CMD_2_RESERVED
+			
+			<legal 0>
+*/
+#define TCL_DATA_CMD_2_RESERVED_OFFSET                               0x00000008
+#define TCL_DATA_CMD_2_RESERVED_LSB                                  10
+#define TCL_DATA_CMD_2_RESERVED_MASK                                 0x00003c00
+
+/* Description		TCL_DATA_CMD_2_ADDRX_EN
+			
+			Address X search enable in ASE
+			
+			1'b0: Search disable
+			
+			1'b1: Search Enable
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET                               0x00000008
+#define TCL_DATA_CMD_2_ADDRX_EN_LSB                                  14
+#define TCL_DATA_CMD_2_ADDRX_EN_MASK                                 0x00004000
+
+/* Description		TCL_DATA_CMD_2_ADDRY_EN
+			
+			Address Y search enable in ASE
+			
+			1'b0: Search disable
+			
+			1'b1: Search Enable
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET                               0x00000008
+#define TCL_DATA_CMD_2_ADDRY_EN_LSB                                  15
+#define TCL_DATA_CMD_2_ADDRY_EN_MASK                                 0x00008000
+
+/* Description		TCL_DATA_CMD_2_TCL_CMD_NUMBER
+			
+			This number can be used by SW to track, identify and
+			link the created commands with the command statuses
+			
+			
+			
+			Is set to the value 'TCL_CMD_Number' of the related
+			TCL_DATA command
+			
+			<legal all> 
+*/
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET                         0x00000008
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB                            16
+#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK                           0xffff0000
+
+/* Description		TCL_DATA_CMD_3_DATA_LENGTH
+			
+			Valid Data length in bytes. 
+			
+			
+			
+			MSDU length in case of direct descriptor.
+			
+			Length of link extension descriptor in case of Link
+			extension descriptor. This is used to know the size of
+			Metadata.
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET                            0x0000000c
+#define TCL_DATA_CMD_3_DATA_LENGTH_LSB                               0
+#define TCL_DATA_CMD_3_DATA_LENGTH_MASK                              0x0000ffff
+
+/* Description		TCL_DATA_CMD_3_IPV4_CHECKSUM_EN
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable IPv4 checksum replacement
+*/
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET                       0x0000000c
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB                          16
+#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK                         0x00010000
+
+/* Description		TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable UDP over IPv4 checksum replacement.  UDP checksum
+			over IPv4 is optional for TCP/IP stacks.
+*/
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB                 17
+#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK                0x00020000
+
+/* Description		TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable UDP over IPv6 checksum replacement.  UDP checksum
+			over IPv6 is mandatory for TCP/IP stacks.
+*/
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB                 18
+#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK                0x00040000
+
+/* Description		TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable TCP checksum over IPv4 replacement
+*/
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB                 19
+#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK                0x00080000
+
+/* Description		TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN
+			
+			Field only valid when msdu_buffer_type is set to
+			MSDU_buffer.
+			
+			
+			
+			OLE related control
+			
+			Enable TCP checksum over IPv6 replacement
+*/
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET              0x0000000c
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB                 20
+#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK                0x00100000
+
+/* Description		TCL_DATA_CMD_3_TO_FW
+			
+			Forward packet to FW along with classification result.
+			The packet will not be forward to TQM when this bit is set
+			
+			1'b0: Use classification result to forward the packet.
+			
+			1'b1: Override classification result and forward packet
+			only to FW.
+*/
+#define TCL_DATA_CMD_3_TO_FW_OFFSET                                  0x0000000c
+#define TCL_DATA_CMD_3_TO_FW_LSB                                     21
+#define TCL_DATA_CMD_3_TO_FW_MASK                                    0x00200000
+
+/* Description		TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID
+			
+			The DSCP to tid conversion table to be used for this
+			frame
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_OFFSET          0x0000000c
+#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_LSB             22
+#define TCL_DATA_CMD_3_DSCP_TO_TID_PRIORITY_TABLE_ID_MASK            0x00400000
+
+/* Description		TCL_DATA_CMD_3_PACKET_OFFSET
+			
+			Packet offset from Metadata in case of direct buffer
+			descriptor. This field is valid when Buf_or_ext_desc_type is
+			reset(= 0).
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET                          0x0000000c
+#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB                             23
+#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK                            0xff800000
+
+/* Description		TCL_DATA_CMD_4_BUFFER_TIMESTAMP
+			
+			Field only valid when 'Buffer_timestamp_valid ' is set.
+			
+			
+			
+			Frame system entrance timestamp. The timestamp is
+			related to the global system timer
+			
+			
+			
+			Generally the first module (SW, TCL or TQM). that sees
+			this frame and this timestamp field is not valid, shall fill
+			in this field.
+			
+			
+			
+			Timestamp in units of 1024 us
+*/
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET                       0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB                          0
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK                         0x0007ffff
+
+/* Description		TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID
+			
+			When set, the Buffer_timestamp field contains valid
+			info.
+*/
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET                 0x00000010
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB                    19
+#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK                   0x00080000
+
+/* Description		TCL_DATA_CMD_4_MESH_ENABLE
+			
+			If set to 1:
+			
+			* For raw WiFi frames, this indicates transmission to a
+			mesh STA, enabling the interpretation of the 'Mesh Control
+			Present' bit (bit 8) of QoS Control (otherwise this bit is
+			ignored),
+			
+			* For native WiFi frames, this indicates that a 'Mesh
+			Control' field is present between the header and the LLC.
+*/
+#define TCL_DATA_CMD_4_MESH_ENABLE_OFFSET                            0x00000010
+#define TCL_DATA_CMD_4_MESH_ENABLE_LSB                               20
+#define TCL_DATA_CMD_4_MESH_ENABLE_MASK                              0x00100000
+
+/* Description		TCL_DATA_CMD_4_HLOS_TID_OVERWRITE
+			
+			When set, TCL shall ignore the IP DSCP and VLAN PCP
+			fields and use HLOS_TID as the final TID. Otherwise TCL
+			shall consider the DSCP and PCP fields as well as HLOS_TID
+			and choose a final TID based on the configured priority 
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET                     0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB                        21
+#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK                       0x00200000
+
+/* Description		TCL_DATA_CMD_4_HLOS_TID
+			
+			HLOS MSDU priority
+			
+			
+			
+			Field is used when HLOS_TID_overwrite is set.
+			
+			
+			
+			Field is also used when HLOS_TID_overwrite is not set
+			and DSCP/PCP is not available in the packet
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_4_HLOS_TID_OFFSET                               0x00000010
+#define TCL_DATA_CMD_4_HLOS_TID_LSB                                  22
+#define TCL_DATA_CMD_4_HLOS_TID_MASK                                 0x03c00000
+
+/* Description		TCL_DATA_CMD_4_RESERVED_4
+			
+			<legal 0>
+*/
+#define TCL_DATA_CMD_4_RESERVED_4_OFFSET                             0x00000010
+#define TCL_DATA_CMD_4_RESERVED_4_LSB                                26
+#define TCL_DATA_CMD_4_RESERVED_4_MASK                               0xfc000000
+
+/* Description		TCL_DATA_CMD_5_RESERVED_5
+			
+			<legal 0>
+*/
+#define TCL_DATA_CMD_5_RESERVED_5_OFFSET                             0x00000014
+#define TCL_DATA_CMD_5_RESERVED_5_LSB                                0
+#define TCL_DATA_CMD_5_RESERVED_5_MASK                               0xffffffff
+
+/* Description		TCL_DATA_CMD_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET                            0x00000018
+#define TCL_DATA_CMD_6_RESERVED_6A_LSB                               0
+#define TCL_DATA_CMD_6_RESERVED_6A_MASK                              0x000fffff
+
+/* Description		TCL_DATA_CMD_6_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_6_RING_ID_OFFSET                                0x00000018
+#define TCL_DATA_CMD_6_RING_ID_LSB                                   20
+#define TCL_DATA_CMD_6_RING_ID_MASK                                  0x0ff00000
+
+/* Description		TCL_DATA_CMD_6_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET                          0x00000018
+#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB                             28
+#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK                            0xf0000000
+
+
+#endif // _TCL_DATA_CMD_H_

hw/qca6290/v1/tcl_gse_cmd.h

@@ -0,0 +1,408 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _TCL_GSE_CMD_H_
+#define _TCL_GSE_CMD_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	control_buffer_addr_31_0[31:0]
+//	1	control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], reserved_1a[31:15]
+//	2	cmd_meta_data_31_0[31:0]
+//	3	cmd_meta_data_63_32[31:0]
+//	4	reserved_4a[31:0]
+//	5	reserved_5a[31:0]
+//	6	reserved_6a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_GSE_CMD 7
+
+struct tcl_gse_cmd {
+             uint32_t control_buffer_addr_31_0        : 32; //[31:0]
+             uint32_t control_buffer_addr_39_32       :  8, //[7:0]
+                      gse_ctrl                        :  4, //[11:8]
+                      gse_sel                         :  1, //[12]
+                      status_destination_ring_id      :  1, //[13]
+                      swap                            :  1, //[14]
+                      reserved_1a                     : 17; //[31:15]
+             uint32_t cmd_meta_data_31_0              : 32; //[31:0]
+             uint32_t cmd_meta_data_63_32             : 32; //[31:0]
+             uint32_t reserved_4a                     : 32; //[31:0]
+             uint32_t reserved_5a                     : 32; //[31:0]
+             uint32_t reserved_6a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+control_buffer_addr_31_0
+			
+			Address (lower 32 bits) of a control buffer containing
+			additional info needed for this command execution.
+			
+			<legal all>
+
+control_buffer_addr_39_32
+			
+			Address (upper 8 bits) of a control buffer containing
+			additional info needed for this command execution.
+			
+			<legal all>
+
+gse_ctrl
+			
+			GSE control operations. This includes cache operations
+			and table entry statistics read/clear operation.
+			
+			<enum 0 rd_stat> Report or Read statistics
+			
+			<enum 1 srch_dis> Search disable. Report only Hash
+			
+			<enum 2 Wr_bk_single> Write Back single entry
+			
+			<enum 3 wr_bk_all> Write Back entire cache entry
+			
+			<enum 4 inval_single> Invalidate single cache entry
+			
+			<enum 5 inval_all> Invalidate entire cache
+			
+			<enum 6 wr_bk_inval_single> Write back and Invalidate 
+			single entry in cache
+			
+			<enum 7 wr_bk_inval_all> write back and invalidate
+			entire cache
+			
+			<enum 8 clr_stat_single> Clear statistics for single
+			entry
+			
+			<legal 0-8>
+			
+			Rest of the values reserved. 
+			
+			For all single entry control operations (write back,
+			Invalidate or both)Statistics will be reported
+
+gse_sel
+			
+			Bit to select the ASE or FSE to do the operation mention
+			by GSE_ctrl bit
+			
+			0: FSE select
+			
+			1: ASE select
+
+status_destination_ring_id
+			
+			The TCL status ring to which the GSE status needs to be
+			send.
+			
+			
+			
+			<enum 0 tcl_status_0_ring>
+			
+			<enum 1 tcl_status_1_ring>
+			
+			
+			
+			<legal all>
+
+swap
+			
+			Bit to enable byte swapping of contents of buffer
+			
+			<enum 0 Byte_swap_disable > 
+			
+			<enum 1 byte_swap_enable >
+			
+			<legal all>
+
+reserved_1a
+			
+			<legal 0>
+
+cmd_meta_data_31_0
+			
+			Meta data to be returned in the status descriptor
+			
+			<legal all>
+
+cmd_meta_data_63_32
+			
+			Meta data to be returned in the status descriptor
+			
+			<legal all>
+
+reserved_4a
+			
+			<legal 0>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+ring_id
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0
+			
+			Address (lower 32 bits) of a control buffer containing
+			additional info needed for this command execution.
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET                0x00000000
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB                   0
+#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK                  0xffffffff
+
+/* Description		TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32
+			
+			Address (upper 8 bits) of a control buffer containing
+			additional info needed for this command execution.
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET               0x00000004
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB                  0
+#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK                 0x000000ff
+
+/* Description		TCL_GSE_CMD_1_GSE_CTRL
+			
+			GSE control operations. This includes cache operations
+			and table entry statistics read/clear operation.
+			
+			<enum 0 rd_stat> Report or Read statistics
+			
+			<enum 1 srch_dis> Search disable. Report only Hash
+			
+			<enum 2 Wr_bk_single> Write Back single entry
+			
+			<enum 3 wr_bk_all> Write Back entire cache entry
+			
+			<enum 4 inval_single> Invalidate single cache entry
+			
+			<enum 5 inval_all> Invalidate entire cache
+			
+			<enum 6 wr_bk_inval_single> Write back and Invalidate 
+			single entry in cache
+			
+			<enum 7 wr_bk_inval_all> write back and invalidate
+			entire cache
+			
+			<enum 8 clr_stat_single> Clear statistics for single
+			entry
+			
+			<legal 0-8>
+			
+			Rest of the values reserved. 
+			
+			For all single entry control operations (write back,
+			Invalidate or both)Statistics will be reported
+*/
+#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET                                0x00000004
+#define TCL_GSE_CMD_1_GSE_CTRL_LSB                                   8
+#define TCL_GSE_CMD_1_GSE_CTRL_MASK                                  0x00000f00
+
+/* Description		TCL_GSE_CMD_1_GSE_SEL
+			
+			Bit to select the ASE or FSE to do the operation mention
+			by GSE_ctrl bit
+			
+			0: FSE select
+			
+			1: ASE select
+*/
+#define TCL_GSE_CMD_1_GSE_SEL_OFFSET                                 0x00000004
+#define TCL_GSE_CMD_1_GSE_SEL_LSB                                    12
+#define TCL_GSE_CMD_1_GSE_SEL_MASK                                   0x00001000
+
+/* Description		TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID
+			
+			The TCL status ring to which the GSE status needs to be
+			send.
+			
+			
+			
+			<enum 0 tcl_status_0_ring>
+			
+			<enum 1 tcl_status_1_ring>
+			
+			
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET              0x00000004
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB                 13
+#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK                0x00002000
+
+/* Description		TCL_GSE_CMD_1_SWAP
+			
+			Bit to enable byte swapping of contents of buffer
+			
+			<enum 0 Byte_swap_disable > 
+			
+			<enum 1 byte_swap_enable >
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_1_SWAP_OFFSET                                    0x00000004
+#define TCL_GSE_CMD_1_SWAP_LSB                                       14
+#define TCL_GSE_CMD_1_SWAP_MASK                                      0x00004000
+
+/* Description		TCL_GSE_CMD_1_RESERVED_1A
+			
+			<legal 0>
+*/
+#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET                             0x00000004
+#define TCL_GSE_CMD_1_RESERVED_1A_LSB                                15
+#define TCL_GSE_CMD_1_RESERVED_1A_MASK                               0xffff8000
+
+/* Description		TCL_GSE_CMD_2_CMD_META_DATA_31_0
+			
+			Meta data to be returned in the status descriptor
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET                      0x00000008
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB                         0
+#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK                        0xffffffff
+
+/* Description		TCL_GSE_CMD_3_CMD_META_DATA_63_32
+			
+			Meta data to be returned in the status descriptor
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET                     0x0000000c
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB                        0
+#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK                       0xffffffff
+
+/* Description		TCL_GSE_CMD_4_RESERVED_4A
+			
+			<legal 0>
+*/
+#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET                             0x00000010
+#define TCL_GSE_CMD_4_RESERVED_4A_LSB                                0
+#define TCL_GSE_CMD_4_RESERVED_4A_MASK                               0xffffffff
+
+/* Description		TCL_GSE_CMD_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET                             0x00000014
+#define TCL_GSE_CMD_5_RESERVED_5A_LSB                                0
+#define TCL_GSE_CMD_5_RESERVED_5A_MASK                               0xffffffff
+
+/* Description		TCL_GSE_CMD_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET                             0x00000018
+#define TCL_GSE_CMD_6_RESERVED_6A_LSB                                0
+#define TCL_GSE_CMD_6_RESERVED_6A_MASK                               0x000fffff
+
+/* Description		TCL_GSE_CMD_6_RING_ID
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_6_RING_ID_OFFSET                                 0x00000018
+#define TCL_GSE_CMD_6_RING_ID_LSB                                    20
+#define TCL_GSE_CMD_6_RING_ID_MASK                                   0x0ff00000
+
+/* Description		TCL_GSE_CMD_6_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET                           0x00000018
+#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB                              28
+#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK                             0xf0000000
+
+
+#endif // _TCL_GSE_CMD_H_

hw/qca6290/v1/tcl_status_ring.h

@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _TCL_STATUS_RING_H_
+#define _TCL_STATUS_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], reserved_0a[7], msdu_cnt_n[31:8]
+//	1	msdu_byte_cnt_n[31:0]
+//	2	msdu_timestmp_n[31:0]
+//	3	cmd_meta_data_31_0[31:0]
+//	4	cmd_meta_data_63_32[31:0]
+//	5	hash_indx_val[19:0], reserved_5a[31:20]
+//	6	reserved_6a[31:0]
+//	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TCL_STATUS_RING 8
+
+struct tcl_status_ring {
+             uint32_t gse_ctrl                        :  4, //[3:0]
+                      ase_fse_sel                     :  1, //[4]
+                      cache_op_res                    :  2, //[6:5]
+                      reserved_0a                     :  1, //[7]
+                      msdu_cnt_n                      : 24; //[31:8]
+             uint32_t msdu_byte_cnt_n                 : 32; //[31:0]
+             uint32_t msdu_timestmp_n                 : 32; //[31:0]
+             uint32_t cmd_meta_data_31_0              : 32; //[31:0]
+             uint32_t cmd_meta_data_63_32             : 32; //[31:0]
+             uint32_t hash_indx_val                   : 20, //[19:0]
+                      reserved_5a                     : 12; //[31:20]
+             uint32_t reserved_6a                     : 32; //[31:0]
+             uint32_t reserved_7a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+gse_ctrl
+			
+			GSE control operations. This includes cache operations
+			and table entry statistics read/clear operation.
+			
+			<enum 0 rd_stat> Report or Read statistics
+			
+			<enum 1 srch_dis> Search disable. Report only Hash
+			
+			<enum 2 Wr_bk_single> Write Back single entry
+			
+			<enum 3 wr_bk_all> Write Back entire cache entry
+			
+			<enum 4 inval_single> Invalidate single cache entry
+			
+			<enum 5 inval_all> Invalidate entire cache
+			
+			<enum 6 wr_bk_inval_single> Write back and Invalidate 
+			single entry in cache
+			
+			<enum 7 wr_bk_inval_all> write back and invalidate
+			entire cache
+			
+			<enum 8 clr_stat_single> Clear statistics for single
+			entry
+			
+			<legal 0-8>
+			
+			Rest of the values reserved. 
+			
+			For all single entry control operations (write back,
+			Invalidate or both)Statistics will be reported
+
+ase_fse_sel
+			
+			Search Engine for which operation is done.
+			
+			1'b0: Address Search Engine Result
+			
+			1'b1: Flow Search Engine result
+
+cache_op_res
+			
+			Cache operation result. Following are results of cache
+			operation.
+			
+			<enum 0 op_done>  Operation successful
+			
+			<enum 1 not_fnd> Entry not found in Table
+			
+			<enum 2 timeout_er>  Timeout Error
+			
+			<legal 0-2>
+
+reserved_0a
+			
+			<legal 0>
+
+msdu_cnt_n
+			
+			MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
+			4'b1000
+
+msdu_byte_cnt_n
+			
+			MSDU byte count for entry 1. Valid when GSE_CTRL is
+			4'b0111 and 4'b1000
+
+msdu_timestmp_n
+			
+			MSDU timestamp for entry 1. Valid when GSE_CTRL is
+			4'b0111 and 4'b1000
+
+cmd_meta_data_31_0
+			
+			Meta data from input ring
+			
+			<legal all>
+
+cmd_meta_data_63_32
+			
+			Meta data from input ring
+			
+			<legal all>
+
+hash_indx_val
+			
+			
+			Hash value of the entry in table in case of search
+			failed or search disable.
+			
+			<legal all>
+
+reserved_5a
+			
+			<legal 0>
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		TCL_STATUS_RING_0_GSE_CTRL
+			
+			GSE control operations. This includes cache operations
+			and table entry statistics read/clear operation.
+			
+			<enum 0 rd_stat> Report or Read statistics
+			
+			<enum 1 srch_dis> Search disable. Report only Hash
+			
+			<enum 2 Wr_bk_single> Write Back single entry
+			
+			<enum 3 wr_bk_all> Write Back entire cache entry
+			
+			<enum 4 inval_single> Invalidate single cache entry
+			
+			<enum 5 inval_all> Invalidate entire cache
+			
+			<enum 6 wr_bk_inval_single> Write back and Invalidate 
+			single entry in cache
+			
+			<enum 7 wr_bk_inval_all> write back and invalidate
+			entire cache
+			
+			<enum 8 clr_stat_single> Clear statistics for single
+			entry
+			
+			<legal 0-8>
+			
+			Rest of the values reserved. 
+			
+			For all single entry control operations (write back,
+			Invalidate or both)Statistics will be reported
+*/
+#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET                            0x00000000
+#define TCL_STATUS_RING_0_GSE_CTRL_LSB                               0
+#define TCL_STATUS_RING_0_GSE_CTRL_MASK                              0x0000000f
+
+/* Description		TCL_STATUS_RING_0_ASE_FSE_SEL
+			
+			Search Engine for which operation is done.
+			
+			1'b0: Address Search Engine Result
+			
+			1'b1: Flow Search Engine result
+*/
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET                         0x00000000
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB                            4
+#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK                           0x00000010
+
+/* Description		TCL_STATUS_RING_0_CACHE_OP_RES
+			
+			Cache operation result. Following are results of cache
+			operation.
+			
+			<enum 0 op_done>  Operation successful
+			
+			<enum 1 not_fnd> Entry not found in Table
+			
+			<enum 2 timeout_er>  Timeout Error
+			
+			<legal 0-2>
+*/
+#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET                        0x00000000
+#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB                           5
+#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK                          0x00000060
+
+/* Description		TCL_STATUS_RING_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define TCL_STATUS_RING_0_RESERVED_0A_OFFSET                         0x00000000
+#define TCL_STATUS_RING_0_RESERVED_0A_LSB                            7
+#define TCL_STATUS_RING_0_RESERVED_0A_MASK                           0x00000080
+
+/* Description		TCL_STATUS_RING_0_MSDU_CNT_N
+			
+			MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and
+			4'b1000
+*/
+#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET                          0x00000000
+#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB                             8
+#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK                            0xffffff00
+
+/* Description		TCL_STATUS_RING_1_MSDU_BYTE_CNT_N
+			
+			MSDU byte count for entry 1. Valid when GSE_CTRL is
+			4'b0111 and 4'b1000
+*/
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET                     0x00000004
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB                        0
+#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK                       0xffffffff
+
+/* Description		TCL_STATUS_RING_2_MSDU_TIMESTMP_N
+			
+			MSDU timestamp for entry 1. Valid when GSE_CTRL is
+			4'b0111 and 4'b1000
+*/
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET                     0x00000008
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB                        0
+#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK                       0xffffffff
+
+/* Description		TCL_STATUS_RING_3_CMD_META_DATA_31_0
+			
+			Meta data from input ring
+			
+			<legal all>
+*/
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET                  0x0000000c
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB                     0
+#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK                    0xffffffff
+
+/* Description		TCL_STATUS_RING_4_CMD_META_DATA_63_32
+			
+			Meta data from input ring
+			
+			<legal all>
+*/
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET                 0x00000010
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB                    0
+#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK                   0xffffffff
+
+/* Description		TCL_STATUS_RING_5_HASH_INDX_VAL
+			
+			
+			Hash value of the entry in table in case of search
+			failed or search disable.
+			
+			<legal all>
+*/
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET                       0x00000014
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB                          0
+#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK                         0x000fffff
+
+/* Description		TCL_STATUS_RING_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET                         0x00000014
+#define TCL_STATUS_RING_5_RESERVED_5A_LSB                            20
+#define TCL_STATUS_RING_5_RESERVED_5A_MASK                           0xfff00000
+
+/* Description		TCL_STATUS_RING_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET                         0x00000018
+#define TCL_STATUS_RING_6_RESERVED_6A_LSB                            0
+#define TCL_STATUS_RING_6_RESERVED_6A_MASK                           0xffffffff
+
+/* Description		TCL_STATUS_RING_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET                         0x0000001c
+#define TCL_STATUS_RING_7_RESERVED_7A_LSB                            0
+#define TCL_STATUS_RING_7_RESERVED_7A_MASK                           0x000fffff
+
+/* Description		TCL_STATUS_RING_7_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define TCL_STATUS_RING_7_RING_ID_OFFSET                             0x0000001c
+#define TCL_STATUS_RING_7_RING_ID_LSB                                20
+#define TCL_STATUS_RING_7_RING_ID_MASK                               0x0ff00000
+
+/* Description		TCL_STATUS_RING_7_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET                       0x0000001c
+#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB                          28
+#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK                         0xf0000000
+
+
+#endif // _TCL_STATUS_RING_H_

hw/qca6290/v1/tlv_hdr.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+#ifndef _TLV_HDR_H_
+#define _TLV_HDR_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+struct tlv_usr_16_hdr {
+   volatile uint16_t             tlv_cflg_reserved   :   1,
+                                 tlv_tag             :   5,
+                                 tlv_len             :   4,
+                                 tlv_usrid           :   6;
+};
+
+struct tlv_16_hdr {
+   volatile uint16_t             tlv_cflg_reserved   :   1,
+                                 tlv_tag             :   5,
+                                 tlv_len             :   4,
+                                 tlv_reserved        :   6;
+};
+
+struct tlv_usr_32_hdr {
+   volatile uint32_t             tlv_cflg_reserved   :   1,
+                                 tlv_tag             :   9,
+                                 tlv_len             :  16,
+                                 tlv_usrid           :   6;
+};
+
+struct tlv_32_hdr {
+   volatile uint32_t             tlv_cflg_reserved   :   1,
+                                 tlv_tag             :   9,
+                                 tlv_len             :  16,
+                                 tlv_reserved        :   6;
+};
+
+struct tlv_usr_42_hdr {
+   volatile uint64_t             tlv_compression     :   1,
+                                 tlv_tag             :   9,
+                                 tlv_len             :  16,
+                                 tlv_usrid           :   6,
+                                 tlv_reserved        :  10,
+                                 pad_42to64_bit      :  22;
+};
+
+struct tlv_42_hdr {
+   volatile uint64_t             tlv_compression     :   1,
+                                 tlv_tag             :   9,
+                                 tlv_len             :  16,
+                                 tlv_reserved        :  16,
+                                 pad_42to64_bit      :  22;
+};
+
+struct tlv_usr_c_42_hdr {
+   volatile uint64_t             tlv_compression     :   1,
+                                 tlv_ctag            :   3,
+                                 tlv_usrid           :   6,
+                                 tlv_cdata           :  32,
+                                 pad_42to64_bit      :  22;
+};
+
+#endif

hw/qca6290/v1/tlv_tag_def.h

@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+/**
+ * Generated file ... Do not hand edit ...
+ */
+
+#ifndef _TLV_TAG_DEF_
+#define _TLV_TAG_DEF_
+
+typedef enum {
+
+  WIFIMACTX_CBF_START_E                    =   0 /* 0x0 */,
+  WIFIPHYRX_DATA_E                         =   1 /* 0x1 */,
+  WIFIPHYRX_CBF_DATA_RESP_E                =   2 /* 0x2 */,
+  WIFIPHYRX_ABORT_REQUEST_E                =   3 /* 0x3 */,
+  WIFIPHYRX_USER_ABORT_NOTIFICATION_E      =   4 /* 0x4 */,
+  WIFIMACTX_DATA_RESP_E                    =   5 /* 0x5 */,
+  WIFIMACTX_CBF_DATA_E                     =   6 /* 0x6 */,
+  WIFIMACTX_CBF_DONE_E                     =   7 /* 0x7 */,
+  WIFIMACRX_CBF_READ_REQUEST_E             =   8 /* 0x8 */,
+  WIFIMACRX_CBF_DATA_REQUEST_E             =   9 /* 0x9 */,
+  WIFIMACRX_EXPECT_NDP_RECEPTION_E         =  10 /* 0xa */,
+  WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E       =  11 /* 0xb */,
+  WIFIMACRX_NDP_TIMEOUT_E                  =  12 /* 0xc */,
+  WIFIMACRX_ABORT_ACK_E                    =  13 /* 0xd */,
+  WIFIMACRX_REQ_IMPLICIT_FB_E              =  14 /* 0xe */,
+  WIFIMACRX_CHAIN_MASK_E                   =  15 /* 0xf */,
+  WIFIMACRX_NAP_USER_E                     =  16 /* 0x10 */,
+  WIFIMACRX_ABORT_REQUEST_E                =  17 /* 0x11 */,
+  WIFIPHYTX_OTHER_TRANSMIT_INFO16_E        =  18 /* 0x12 */,
+  WIFIPHYTX_ABORT_ACK_E                    =  19 /* 0x13 */,
+  WIFIPHYTX_ABORT_REQUEST_E                =  20 /* 0x14 */,
+  WIFIPHYTX_PKT_END_E                      =  21 /* 0x15 */,
+  WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E     =  22 /* 0x16 */,
+  WIFIPHYTX_REQUEST_CTRL_INFO_E            =  23 /* 0x17 */,
+  WIFIPHYTX_DATA_REQUEST_E                 =  24 /* 0x18 */,
+  WIFIPHYTX_BF_CV_LOADING_DONE_E           =  25 /* 0x19 */,
+  WIFIPHYTX_NAP_ACK_E                      =  26 /* 0x1a */,
+  WIFIPHYTX_NAP_DONE_E                     =  27 /* 0x1b */,
+  WIFIPHYTX_OFF_ACK_E                      =  28 /* 0x1c */,
+  WIFIPHYTX_ON_ACK_E                       =  29 /* 0x1d */,
+  WIFIPHYTX_SYNTH_OFF_ACK_E                =  30 /* 0x1e */,
+  WIFIPHYTX_DEBUG16_E                      =  31 /* 0x1f */,
+  WIFIMACTX_ABORT_REQUEST_E                =  32 /* 0x20 */,
+  WIFIMACTX_ABORT_ACK_E                    =  33 /* 0x21 */,
+  WIFIMACTX_PKT_END_E                      =  34 /* 0x22 */,
+  WIFIMACTX_PRE_PHY_DESC_E                 =  35 /* 0x23 */,
+  WIFIMACTX_BF_PARAMS_COMMON_E             =  36 /* 0x24 */,
+  WIFIMACTX_BF_PARAMS_PER_USER_E           =  37 /* 0x25 */,
+  WIFIMACTX_PREFETCH_CV_E                  =  38 /* 0x26 */,
+  WIFIMACTX_USER_DESC_COMMON_E             =  39 /* 0x27 */,
+  WIFIMACTX_USER_DESC_PER_USER_E           =  40 /* 0x28 */,
+  WIFIEXAMPLE_USER_TLV_16_E                =  41 /* 0x29 */,
+  WIFIEXAMPLE_TLV_16_E                     =  42 /* 0x2a */,
+  WIFIMACTX_PHY_OFF_E                      =  43 /* 0x2b */,
+  WIFIMACTX_PHY_ON_E                       =  44 /* 0x2c */,
+  WIFIMACTX_SYNTH_OFF_E                    =  45 /* 0x2d */,
+  WIFIMACTX_EXPECT_CBF_COMMON_E            =  46 /* 0x2e */,
+  WIFIMACTX_EXPECT_CBF_PER_USER_E          =  47 /* 0x2f */,
+  WIFIMACTX_PHY_DESC_E                     =  48 /* 0x30 */,
+  WIFIMACTX_L_SIG_A_E                      =  49 /* 0x31 */,
+  WIFIMACTX_L_SIG_B_E                      =  50 /* 0x32 */,
+  WIFIMACTX_HT_SIG_E                       =  51 /* 0x33 */,
+  WIFIMACTX_VHT_SIG_A_E                    =  52 /* 0x34 */,
+  WIFIMACTX_VHT_SIG_B_SU20_E               =  53 /* 0x35 */,
+  WIFIMACTX_VHT_SIG_B_SU40_E               =  54 /* 0x36 */,
+  WIFIMACTX_VHT_SIG_B_SU80_E               =  55 /* 0x37 */,
+  WIFIMACTX_VHT_SIG_B_SU160_E              =  56 /* 0x38 */,
+  WIFIMACTX_VHT_SIG_B_MU20_E               =  57 /* 0x39 */,
+  WIFIMACTX_VHT_SIG_B_MU40_E               =  58 /* 0x3a */,
+  WIFIMACTX_VHT_SIG_B_MU80_E               =  59 /* 0x3b */,
+  WIFIMACTX_VHT_SIG_B_MU160_E              =  60 /* 0x3c */,
+  WIFIMACTX_SERVICE_E                      =  61 /* 0x3d */,
+  WIFIMACTX_HE_SIG_A_SU_E                  =  62 /* 0x3e */,
+  WIFIMACTX_HE_SIG_A_MU_DL_E               =  63 /* 0x3f */,
+  WIFIMACTX_HE_SIG_A_MU_UL_E               =  64 /* 0x40 */,
+  WIFIMACTX_HE_SIG_B1_MU_E                 =  65 /* 0x41 */,
+  WIFIMACTX_HE_SIG_B2_MU_E                 =  66 /* 0x42 */,
+  WIFIMACTX_HE_SIG_B2_OFDMA_E              =  67 /* 0x43 */,
+  WIFIMACTX_DELETE_CV_E                    =  68 /* 0x44 */,
+  WIFIMACTX_MU_UPLINK_COMMON_E             =  69 /* 0x45 */,
+  WIFIMACTX_MU_UPLINK_USER_SETUP_E         =  70 /* 0x46 */,
+  WIFIMACTX_OTHER_TRANSMIT_INFO_E          =  71 /* 0x47 */,
+  WIFIMACTX_PHY_NAP_E                      =  72 /* 0x48 */,
+  WIFIMACTX_DEBUG_E                        =  73 /* 0x49 */,
+  WIFIPHYRX_ABORT_ACK_E                    =  74 /* 0x4a */,
+  WIFIPHYRX_GENERATED_CBF_DETAILS_E        =  75 /* 0x4b */,
+  WIFIPHYRX_RSSI_LEGACY_E                  =  76 /* 0x4c */,
+  WIFIPHYRX_RSSI_HT_E                      =  77 /* 0x4d */,
+  WIFIPHYRX_USER_INFO_E                    =  78 /* 0x4e */,
+  WIFIPHYRX_PKT_END_E                      =  79 /* 0x4f */,
+  WIFIPHYRX_DEBUG_E                        =  80 /* 0x50 */,
+  WIFIPHYRX_CBF_TRANSFER_DONE_E            =  81 /* 0x51 */,
+  WIFIPHYRX_CBF_TRANSFER_ABORT_E           =  82 /* 0x52 */,
+  WIFIPHYRX_L_SIG_A_E                      =  83 /* 0x53 */,
+  WIFIPHYRX_L_SIG_B_E                      =  84 /* 0x54 */,
+  WIFIPHYRX_HT_SIG_E                       =  85 /* 0x55 */,
+  WIFIPHYRX_VHT_SIG_A_E                    =  86 /* 0x56 */,
+  WIFIPHYRX_VHT_SIG_B_SU20_E               =  87 /* 0x57 */,
+  WIFIPHYRX_VHT_SIG_B_SU40_E               =  88 /* 0x58 */,
+  WIFIPHYRX_VHT_SIG_B_SU80_E               =  89 /* 0x59 */,
+  WIFIPHYRX_VHT_SIG_B_SU160_E              =  90 /* 0x5a */,
+  WIFIPHYRX_VHT_SIG_B_MU20_E               =  91 /* 0x5b */,
+  WIFIPHYRX_VHT_SIG_B_MU40_E               =  92 /* 0x5c */,
+  WIFIPHYRX_VHT_SIG_B_MU80_E               =  93 /* 0x5d */,
+  WIFIPHYRX_VHT_SIG_B_MU160_E              =  94 /* 0x5e */,
+  WIFIPHYRX_HE_SIG_A_SU_E                  =  95 /* 0x5f */,
+  WIFIPHYRX_HE_SIG_A_MU_DL_E               =  96 /* 0x60 */,
+  WIFIPHYRX_HE_SIG_A_MU_UL_E               =  97 /* 0x61 */,
+  WIFIPHYRX_HE_SIG_B1_MU_E                 =  98 /* 0x62 */,
+  WIFIPHYRX_HE_SIG_B2_MU_E                 =  99 /* 0x63 */,
+  WIFIPHYRX_HE_SIG_B2_OFDMA_E              = 100 /* 0x64 */,
+  WIFIPHYRX_OTHER_RECEIVE_INFO_E           = 101 /* 0x65 */,
+  WIFIPHYRX_COMMON_USER_INFO_E             = 102 /* 0x66 */,
+  WIFIPHYRX_DATA_DONE_E                    = 103 /* 0x67 */,
+  WIFIRECEIVE_RSSI_INFO_E                  = 104 /* 0x68 */,
+  WIFIRECEIVE_USER_INFO_E                  = 105 /* 0x69 */,
+  WIFIMIMO_CONTROL_INFO_E                  = 106 /* 0x6a */,
+  WIFIRX_LOCATION_INFO_E                   = 107 /* 0x6b */,
+  WIFICOEX_TX_REQ_E                        = 108 /* 0x6c */,
+  WIFIDUMMY_E                              = 109 /* 0x6d */,
+  WIFIRX_TIMING_OFFSET_INFO_E              = 110 /* 0x6e */,
+  WIFIEXAMPLE_TLV_32_NAME_E                = 111 /* 0x6f */,
+  WIFIMPDU_LIMIT_E                         = 112 /* 0x70 */,
+  WIFINA_LENGTH_END_E                      = 113 /* 0x71 */,
+  WIFIOLE_BUF_STATUS_E                     = 114 /* 0x72 */,
+  WIFIPCU_PPDU_SETUP_DONE_E                = 115 /* 0x73 */,
+  WIFIPCU_PPDU_SETUP_END_E                 = 116 /* 0x74 */,
+  WIFIPCU_PPDU_SETUP_INIT_E                = 117 /* 0x75 */,
+  WIFIPCU_PPDU_SETUP_START_E               = 118 /* 0x76 */,
+  WIFIPDG_FES_SETUP_E                      = 119 /* 0x77 */,
+  WIFIPDG_RESPONSE_E                       = 120 /* 0x78 */,
+  WIFIPDG_TX_REQ_E                         = 121 /* 0x79 */,
+  WIFISCH_WAIT_INSTR_E                     = 122 /* 0x7a */,
+  WIFISCHEDULER_TLV_E                      = 123 /* 0x7b */,
+  WIFITQM_FLOW_EMPTY_STATUS_E              = 124 /* 0x7c */,
+  WIFITQM_FLOW_NOT_EMPTY_STATUS_E          = 125 /* 0x7d */,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_E           = 126 /* 0x7e */,
+  WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E    = 127 /* 0x7f */,
+  WIFITQM_GEN_MPDUS_E                      = 128 /* 0x80 */,
+  WIFITQM_GEN_MPDUS_STATUS_E               = 129 /* 0x81 */,
+  WIFITQM_REMOVE_MPDU_E                    = 130 /* 0x82 */,
+  WIFITQM_REMOVE_MPDU_STATUS_E             = 131 /* 0x83 */,
+  WIFITQM_REMOVE_MSDU_E                    = 132 /* 0x84 */,
+  WIFITQM_REMOVE_MSDU_STATUS_E             = 133 /* 0x85 */,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_E           = 134 /* 0x86 */,
+  WIFITQM_WRITE_CMD_E                      = 135 /* 0x87 */,
+  WIFIOFDMA_TRIGGER_DETAILS_E              = 136 /* 0x88 */,
+  WIFITX_DATA_E                            = 137 /* 0x89 */,
+  WIFITX_FES_SETUP_E                       = 138 /* 0x8a */,
+  WIFIRX_PACKET_E                          = 139 /* 0x8b */,
+  WIFIEXPECTED_RESPONSE_E                  = 140 /* 0x8c */,
+  WIFITX_MPDU_END_E                        = 141 /* 0x8d */,
+  WIFITX_MPDU_START_E                      = 142 /* 0x8e */,
+  WIFITX_MSDU_END_E                        = 143 /* 0x8f */,
+  WIFITX_MSDU_START_E                      = 144 /* 0x90 */,
+  WIFITX_SW_MODE_SETUP_E                   = 145 /* 0x91 */,
+  WIFITXPCU_BUFFER_STATUS_E                = 146 /* 0x92 */,
+  WIFITXPCU_USER_BUFFER_STATUS_E           = 147 /* 0x93 */,
+  WIFIDATA_TO_TIME_CONFIG_E                = 148 /* 0x94 */,
+  WIFIEXAMPLE_USER_TLV_32_E                = 149 /* 0x95 */,
+  WIFIMPDU_INFO_E                          = 150 /* 0x96 */,
+  WIFIPDG_USER_SETUP_E                     = 151 /* 0x97 */,
+  WIFITX_11AH_SETUP_E                      = 152 /* 0x98 */,
+  WIFITX_CV_START_E                        = 153 /* 0x99 */,
+  WIFITX_PEER_ENTRY_E                      = 154 /* 0x9a */,
+  WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E       = 155 /* 0x9b */,
+  WIFIEXAMPLE_STRUCT_NAME_E                = 156 /* 0x9c */,
+  WIFIPCU_PPDU_SETUP_END_INFO_E            = 157 /* 0x9d */,
+  WIFIPPDU_RATE_SETTING_E                  = 158 /* 0x9e */,
+  WIFIPROT_RATE_SETTING_E                  = 159 /* 0x9f */,
+  WIFIRX_MPDU_DETAILS_E                    = 160 /* 0xa0 */,
+  WIFIEXAMPLE_USER_TLV_42_E                = 161 /* 0xa1 */,
+  WIFIRX_MSDU_LINK_E                       = 162 /* 0xa2 */,
+  WIFIRX_REO_QUEUE_E                       = 163 /* 0xa3 */,
+  WIFIADDR_SEARCH_ENTRY_E                  = 164 /* 0xa4 */,
+  WIFISCHEDULER_CMD_E                      = 165 /* 0xa5 */,
+  WIFITX_FLUSH_E                           = 166 /* 0xa6 */,
+  WIFITQM_ENTRANCE_RING_E                  = 167 /* 0xa7 */,
+  WIFITX_DATA_WORD_E                       = 168 /* 0xa8 */,
+  WIFITX_MPDU_DETAILS_E                    = 169 /* 0xa9 */,
+  WIFITX_MPDU_LINK_E                       = 170 /* 0xaa */,
+  WIFITX_MPDU_LINK_PTR_E                   = 171 /* 0xab */,
+  WIFITX_MPDU_QUEUE_HEAD_E                 = 172 /* 0xac */,
+  WIFITX_MPDU_QUEUE_EXT_E                  = 173 /* 0xad */,
+  WIFITX_MPDU_QUEUE_EXT_PTR_E              = 174 /* 0xae */,
+  WIFITX_MSDU_DETAILS_E                    = 175 /* 0xaf */,
+  WIFITX_MSDU_EXTENSION_E                  = 176 /* 0xb0 */,
+  WIFITX_MSDU_FLOW_E                       = 177 /* 0xb1 */,
+  WIFITX_MSDU_LINK_E                       = 178 /* 0xb2 */,
+  WIFITX_MSDU_LINK_ENTRY_PTR_E             = 179 /* 0xb3 */,
+  WIFIRESPONSE_RATE_SETTING_E              = 180 /* 0xb4 */,
+  WIFITXPCU_BUFFER_BASICS_E                = 181 /* 0xb5 */,
+  WIFIUNIFORM_DESCRIPTOR_HEADER_E          = 182 /* 0xb6 */,
+  WIFIUNIFORM_TQM_CMD_HEADER_E             = 183 /* 0xb7 */,
+  WIFIUNIFORM_TQM_STATUS_HEADER_E          = 184 /* 0xb8 */,
+  WIFIUSER_RATE_SETTING_E                  = 185 /* 0xb9 */,
+  WIFIWBM_BUFFER_RING_E                    = 186 /* 0xba */,
+  WIFIWBM_LINK_DESCRIPTOR_RING_E           = 187 /* 0xbb */,
+  WIFIWBM_RELEASE_RING_E                   = 188 /* 0xbc */,
+  WIFITX_FLUSH_REQ_E                       = 189 /* 0xbd */,
+  WIFIRX_MSDU_DETAILS_E                    = 190 /* 0xbe */,
+  WIFITQM_WRITE_CMD_STATUS_E               = 191 /* 0xbf */,
+  WIFITQM_GET_MPDU_QUEUE_STATS_E           = 192 /* 0xc0 */,
+  WIFITQM_GET_MSDU_FLOW_STATS_E            = 193 /* 0xc1 */,
+  WIFIEXAMPLE_USER_CTLV_32_E               = 194 /* 0xc2 */,
+  WIFITX_FES_STATUS_START_E                = 195 /* 0xc3 */,
+  WIFITX_FES_STATUS_USER_PPDU_E            = 196 /* 0xc4 */,
+  WIFITX_FES_STATUS_USER_RESPONSE_E        = 197 /* 0xc5 */,
+  WIFITX_FES_STATUS_END_E                  = 198 /* 0xc6 */,
+  WIFIRX_TRIG_INFO_E                       = 199 /* 0xc7 */,
+  WIFIRXPCU_TX_SETUP_CLEAR_E               = 200 /* 0xc8 */,
+  WIFIRX_FRAME_BITMAP_REQ_E                = 201 /* 0xc9 */,
+  WIFIRX_FRAME_BITMAP_ACK_E                = 202 /* 0xca */,
+  WIFICOEX_RX_STATUS_E                     = 203 /* 0xcb */,
+  WIFIRX_START_PARAM_E                     = 204 /* 0xcc */,
+  WIFIRX_PPDU_START_E                      = 205 /* 0xcd */,
+  WIFIRX_PPDU_END_E                        = 206 /* 0xce */,
+  WIFIRX_MPDU_START_E                      = 207 /* 0xcf */,
+  WIFIRX_MPDU_END_E                        = 208 /* 0xd0 */,
+  WIFIRX_MSDU_START_E                      = 209 /* 0xd1 */,
+  WIFIRX_MSDU_END_E                        = 210 /* 0xd2 */,
+  WIFIRX_ATTENTION_E                       = 211 /* 0xd3 */,
+  WIFIRECEIVED_RESPONSE_INFO_E             = 212 /* 0xd4 */,
+  WIFIRX_PHY_SLEEP_E                       = 213 /* 0xd5 */,
+  WIFIRX_HEADER_E                          = 214 /* 0xd6 */,
+  WIFIRX_PEER_ENTRY_E                      = 215 /* 0xd7 */,
+  WIFIRX_FLUSH_E                           = 216 /* 0xd8 */,
+  WIFIRX_RESPONSE_REQUIRED_INFO_E          = 217 /* 0xd9 */,
+  WIFIRX_FRAMELESS_BAR_DETAILS_E           = 218 /* 0xda */,
+  WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E    = 219 /* 0xdb */,
+  WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E     = 220 /* 0xdc */,
+  WIFITX_CBF_INFO_E                        = 221 /* 0xdd */,
+  WIFIPCU_PPDU_SETUP_USER_E                = 222 /* 0xde */,
+  WIFIRX_MPDU_PCU_START_E                  = 223 /* 0xdf */,
+  WIFIRX_PM_INFO_E                         = 224 /* 0xe0 */,
+  WIFIRX_USER_PPDU_END_E                   = 225 /* 0xe1 */,
+  WIFIRX_PRE_PPDU_START_E                  = 226 /* 0xe2 */,
+  WIFIRX_PREAMBLE_E                        = 227 /* 0xe3 */,
+  WIFITX_FES_SETUP_COMPLETE_E              = 228 /* 0xe4 */,
+  WIFITX_LAST_MPDU_FETCHED_E               = 229 /* 0xe5 */,
+  WIFITXDMA_STOP_REQUEST_E                 = 230 /* 0xe6 */,
+  WIFIRXPCU_SETUP_E                        = 231 /* 0xe7 */,
+  WIFIRXPCU_USER_SETUP_E                   = 232 /* 0xe8 */,
+  WIFITX_FES_STATUS_ACK_OR_BA_E            = 233 /* 0xe9 */,
+  WIFITQM_ACKED_MPDU_E                     = 234 /* 0xea */,
+  WIFICOEX_TX_RESP_E                       = 235 /* 0xeb */,
+  WIFICOEX_TX_STATUS_E                     = 236 /* 0xec */,
+  WIFIMACTX_COEX_PHY_CTRL_E                = 237 /* 0xed */,
+  WIFICOEX_STATUS_BROADCAST_E              = 238 /* 0xee */,
+  WIFIRESPONSE_START_STATUS_E              = 239 /* 0xef */,
+  WIFIRESPONSE_END_STATUS_E                = 240 /* 0xf0 */,
+  WIFICRYPTO_STATUS_E                      = 241 /* 0xf1 */,
+  WIFIRECEIVED_TRIGGER_INFO_E              = 242 /* 0xf2 */,
+  WIFIREO_ENTRANCE_RING_E                  = 243 /* 0xf3 */,
+  WIFIRX_MPDU_LINK_E                       = 244 /* 0xf4 */,
+  WIFICOEX_TX_STOP_CTRL_E                  = 245 /* 0xf5 */,
+  WIFIRX_PPDU_ACK_REPORT_E                 = 246 /* 0xf6 */,
+  WIFIRX_PPDU_NO_ACK_REPORT_E              = 247 /* 0xf7 */,
+  WIFISCH_COEX_STATUS_E                    = 248 /* 0xf8 */,
+  WIFISCHEDULER_COMMAND_STATUS_E           = 249 /* 0xf9 */,
+  WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */,
+  WIFITX_FES_STATUS_PROT_E                 = 251 /* 0xfb */,
+  WIFITX_FES_STATUS_START_PPDU_E           = 252 /* 0xfc */,
+  WIFITX_FES_STATUS_START_PROT_E           = 253 /* 0xfd */,
+  WIFITXPCU_PHYTX_DEBUG32_E                = 254 /* 0xfe */,
+  WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E  = 255 /* 0xff */,
+  WIFITX_MPDU_COUNT_TRANSFER_END_E         = 256 /* 0x100 */,
+  WIFIWHO_ANCHOR_OFFSET_E                  = 257 /* 0x101 */,
+  WIFIWHO_ANCHOR_VALUE_E                   = 258 /* 0x102 */,
+  WIFIWHO_CCE_INFO_E                       = 259 /* 0x103 */,
+  WIFIWHO_COMMIT_E                         = 260 /* 0x104 */,
+  WIFIWHO_COMMIT_DONE_E                    = 261 /* 0x105 */,
+  WIFIWHO_FLUSH_E                          = 262 /* 0x106 */,
+  WIFIWHO_L2_LLC_E                         = 263 /* 0x107 */,
+  WIFIWHO_L2_PAYLOAD_E                     = 264 /* 0x108 */,
+  WIFIWHO_L3_CHECKSUM_E                    = 265 /* 0x109 */,
+  WIFIWHO_L3_INFO_E                        = 266 /* 0x10a */,
+  WIFIWHO_L4_CHECKSUM_E                    = 267 /* 0x10b */,
+  WIFIWHO_L4_INFO_E                        = 268 /* 0x10c */,
+  WIFIWHO_MSDU_E                           = 269 /* 0x10d */,
+  WIFIWHO_MSDU_MISC_E                      = 270 /* 0x10e */,
+  WIFIWHO_PACKET_DATA_E                    = 271 /* 0x10f */,
+  WIFIWHO_PACKET_HDR_E                     = 272 /* 0x110 */,
+  WIFIWHO_PPDU_END_E                       = 273 /* 0x111 */,
+  WIFIWHO_PPDU_START_E                     = 274 /* 0x112 */,
+  WIFIWHO_TSO_E                            = 275 /* 0x113 */,
+  WIFIWHO_WMAC_HEADER_PV0_E                = 276 /* 0x114 */,
+  WIFIWHO_WMAC_HEADER_PV1_E                = 277 /* 0x115 */,
+  WIFIWHO_WMAC_IV_E                        = 278 /* 0x116 */,
+  WIFIMPDU_INFO_END_E                      = 279 /* 0x117 */,
+  WIFIMPDU_INFO_BITMAP_E                   = 280 /* 0x118 */,
+  WIFITX_QUEUE_EXTENSION_E                 = 281 /* 0x119 */,
+  WIFIRX_PEER_ENTRY_DETAILS_E              = 282 /* 0x11a */,
+  WIFIRX_REO_QUEUE_REFERENCE_E             = 283 /* 0x11b */,
+  WIFIRX_REO_QUEUE_EXT_E                   = 284 /* 0x11c */,
+  WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E  = 285 /* 0x11d */,
+  WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E    = 286 /* 0x11e */,
+  WIFITQM_ACKED_MPDU_STATUS_E              = 287 /* 0x11f */,
+  WIFITQM_ADD_MSDU_STATUS_E                = 288 /* 0x120 */,
+  WIFIRX_MPDU_LINK_PTR_E                   = 289 /* 0x121 */,
+  WIFIREO_DESTINATION_RING_E               = 290 /* 0x122 */,
+  WIFITQM_LIST_GEN_DONE_E                  = 291 /* 0x123 */,
+  WIFIWHO_TERMINATE_E                      = 292 /* 0x124 */,
+  WIFITX_LAST_MPDU_END_E                   = 293 /* 0x125 */,
+  WIFITX_CV_DATA_E                         = 294 /* 0x126 */,
+  WIFITCL_ENTRANCE_FROM_PPE_RING_E         = 295 /* 0x127 */,
+  WIFIPPDU_TX_END_E                        = 296 /* 0x128 */,
+  WIFIPROT_TX_END_E                        = 297 /* 0x129 */,
+  WIFIPDG_RESPONSE_RATE_SETTING_E          = 298 /* 0x12a */,
+  WIFIMPDU_INFO_GLOBAL_END_E               = 299 /* 0x12b */,
+  WIFITQM_SCH_INSTR_GLOBAL_END_E           = 300 /* 0x12c */,
+  WIFIRX_PPDU_END_USER_STATS_E             = 301 /* 0x12d */,
+  WIFIRX_PPDU_END_USER_STATS_EXT_E         = 302 /* 0x12e */,
+  WIFINO_ACK_REPORT_E                      = 303 /* 0x12f */,
+  WIFIACK_REPORT_E                         = 304 /* 0x130 */,
+  WIFIUNIFORM_REO_CMD_HEADER_E             = 305 /* 0x131 */,
+  WIFIREO_GET_QUEUE_STATS_E                = 306 /* 0x132 */,
+  WIFIREO_FLUSH_QUEUE_E                    = 307 /* 0x133 */,
+  WIFIREO_FLUSH_CACHE_E                    = 308 /* 0x134 */,
+  WIFIREO_UNBLOCK_CACHE_E                  = 309 /* 0x135 */,
+  WIFIUNIFORM_REO_STATUS_HEADER_E          = 310 /* 0x136 */,
+  WIFIREO_GET_QUEUE_STATS_STATUS_E         = 311 /* 0x137 */,
+  WIFIREO_FLUSH_QUEUE_STATUS_E             = 312 /* 0x138 */,
+  WIFIREO_FLUSH_CACHE_STATUS_E             = 313 /* 0x139 */,
+  WIFIREO_UNBLOCK_CACHE_STATUS_E           = 314 /* 0x13a */,
+  WIFITQM_FLUSH_CACHE_E                    = 315 /* 0x13b */,
+  WIFITQM_UNBLOCK_CACHE_E                  = 316 /* 0x13c */,
+  WIFITQM_FLUSH_CACHE_STATUS_E             = 317 /* 0x13d */,
+  WIFITQM_UNBLOCK_CACHE_STATUS_E           = 318 /* 0x13e */,
+  WIFIRX_PPDU_END_STATUS_DONE_E            = 319 /* 0x13f */,
+  WIFIRX_STATUS_BUFFER_DONE_E              = 320 /* 0x140 */,
+  WIFIBUFFER_ADDR_INFO_E                   = 321 /* 0x141 */,
+  WIFIRX_MSDU_DESC_INFO_E                  = 322 /* 0x142 */,
+  WIFIRX_MPDU_DESC_INFO_E                  = 323 /* 0x143 */,
+  WIFITCL_DATA_CMD_E                       = 324 /* 0x144 */,
+  WIFITCL_GSE_CMD_E                        = 325 /* 0x145 */,
+  WIFITCL_EXIT_BASE_E                      = 326 /* 0x146 */,
+  WIFITCL_COMPACT_EXIT_RING_E              = 327 /* 0x147 */,
+  WIFITCL_REGULAR_EXIT_RING_E              = 328 /* 0x148 */,
+  WIFITCL_EXTENDED_EXIT_RING_E             = 329 /* 0x149 */,
+  WIFIUPLINK_COMMON_INFO_E                 = 330 /* 0x14a */,
+  WIFIUPLINK_USER_SETUP_INFO_E             = 331 /* 0x14b */,
+  WIFITX_DATA_SYNC_E                       = 332 /* 0x14c */,
+  WIFIPHYRX_CBF_READ_REQUEST_ACK_E         = 333 /* 0x14d */,
+  WIFITCL_STATUS_RING_E                    = 334 /* 0x14e */,
+  WIFITQM_GET_MPDU_HEAD_INFO_E             = 335 /* 0x14f */,
+  WIFITQM_SYNC_CMD_E                       = 336 /* 0x150 */,
+  WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E      = 337 /* 0x151 */,
+  WIFITQM_SYNC_CMD_STATUS_E                = 338 /* 0x152 */,
+  WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */,
+  WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */,
+  WIFIREO_FLUSH_TIMEOUT_LIST_E             = 341 /* 0x155 */,
+  WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E      = 342 /* 0x156 */,
+  WIFIREO_TO_PPE_RING_E                    = 343 /* 0x157 */,
+  WIFIRX_MPDU_INFO_E                       = 344 /* 0x158 */,
+  WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */,
+  WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */,
+  WIFIEXAMPLE_USER_TLV_32_NAME_E           = 347 /* 0x15b */,
+  WIFIRX_PPDU_START_USER_INFO_E            = 348 /* 0x15c */,
+  WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E   = 349 /* 0x15d */,
+  WIFIRX_RING_MASK_E                       = 350 /* 0x15e */,
+  WIFIWHO_CLASSIFY_INFO_E                  = 351 /* 0x15f */,
+  WIFITXPT_CLASSIFY_INFO_E                 = 352 /* 0x160 */,
+  WIFIRXPT_CLASSIFY_INFO_E                 = 353 /* 0x161 */,
+  WIFITX_FLOW_SEARCH_ENTRY_E               = 354 /* 0x162 */,
+  WIFIRX_FLOW_SEARCH_ENTRY_E               = 355 /* 0x163 */,
+  WIFIRECEIVED_TRIGGER_INFO_DETAILS_E      = 356 /* 0x164 */,
+  WIFICOEX_MAC_NAP_E                       = 357 /* 0x165 */,
+  WIFIMACRX_ABORT_REQUEST_INFO_E           = 358 /* 0x166 */,
+  WIFIMACTX_ABORT_REQUEST_INFO_E           = 359 /* 0x167 */,
+  WIFIPHYRX_ABORT_REQUEST_INFO_E           = 360 /* 0x168 */,
+  WIFIPHYTX_ABORT_REQUEST_INFO_E           = 361 /* 0x169 */,
+  WIFIRXPCU_PPDU_END_INFO_E                = 362 /* 0x16a */,
+  WIFIWHO_MESH_CONTROL_E                   = 363 /* 0x16b */,
+  WIFIL_SIG_A_INFO_E                       = 364 /* 0x16c */,
+  WIFIL_SIG_B_INFO_E                       = 365 /* 0x16d */,
+  WIFIHT_SIG_INFO_E                        = 366 /* 0x16e */,
+  WIFIVHT_SIG_A_INFO_E                     = 367 /* 0x16f */,
+  WIFIVHT_SIG_B_SU20_INFO_E                = 368 /* 0x170 */,
+  WIFIVHT_SIG_B_SU40_INFO_E                = 369 /* 0x171 */,
+  WIFIVHT_SIG_B_SU80_INFO_E                = 370 /* 0x172 */,
+  WIFIVHT_SIG_B_SU160_INFO_E               = 371 /* 0x173 */,
+  WIFIVHT_SIG_B_MU20_INFO_E                = 372 /* 0x174 */,
+  WIFIVHT_SIG_B_MU40_INFO_E                = 373 /* 0x175 */,
+  WIFIVHT_SIG_B_MU80_INFO_E                = 374 /* 0x176 */,
+  WIFIVHT_SIG_B_MU160_INFO_E               = 375 /* 0x177 */,
+  WIFISERVICE_INFO_E                       = 376 /* 0x178 */,
+  WIFIHE_SIG_A_SU_INFO_E                   = 377 /* 0x179 */,
+  WIFIHE_SIG_A_MU_DL_INFO_E                = 378 /* 0x17a */,
+  WIFIHE_SIG_A_MU_UL_INFO_E                = 379 /* 0x17b */,
+  WIFIHE_SIG_B1_MU_INFO_E                  = 380 /* 0x17c */,
+  WIFIHE_SIG_B2_MU_INFO_E                  = 381 /* 0x17d */,
+  WIFIHE_SIG_B2_OFDMA_INFO_E               = 382 /* 0x17e */,
+  WIFIPDG_SW_MODE_BW_START_E               = 383 /* 0x17f */,
+  WIFIPDG_SW_MODE_BW_END_E                 = 384 /* 0x180 */,
+  WIFIPDG_WAIT_FOR_MAC_REQUEST_E           = 385 /* 0x181 */,
+  WIFIPDG_WAIT_FOR_PHY_REQUEST_E           = 386 /* 0x182 */,
+  WIFISCHEDULER_END_E                      = 387 /* 0x183 */,
+  WIFIPEER_TABLE_ENTRY_E                   = 388 /* 0x184 */,
+  WIFISW_PEER_INFO_E                       = 389 /* 0x185 */,
+  WIFIRXOLE_CCE_CLASSIFY_INFO_E            = 390 /* 0x186 */,
+  WIFITCL_CCE_CLASSIFY_INFO_E              = 391 /* 0x187 */,
+  WIFIRXOLE_CCE_INFO_E                     = 392 /* 0x188 */,
+  WIFITCL_CCE_INFO_E                       = 393 /* 0x189 */,
+  WIFITCL_CCE_SUPERRULE_E                  = 394 /* 0x18a */,
+  WIFICCE_RULE_E                           = 395 /* 0x18b */,
+  WIFIRX_PPDU_START_DROPPED_E              = 396 /* 0x18c */,
+  WIFIRX_PPDU_END_DROPPED_E                = 397 /* 0x18d */,
+  WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E    = 398 /* 0x18e */,
+  WIFIRX_MPDU_START_DROPPED_E              = 399 /* 0x18f */,
+  WIFIRX_MSDU_START_DROPPED_E              = 400 /* 0x190 */,
+  WIFIRX_MSDU_END_DROPPED_E                = 401 /* 0x191 */,
+  WIFIRX_MPDU_END_DROPPED_E                = 402 /* 0x192 */,
+  WIFIRX_ATTENTION_DROPPED_E               = 403 /* 0x193 */,
+  WIFITXPCU_USER_SETUP_E                   = 404 /* 0x194 */,
+  WIFIRXPCU_USER_SETUP_EXT_E               = 405 /* 0x195 */,
+  WIFICE_SRC_DESC_E                        = 406 /* 0x196 */,
+  WIFICE_STAT_DESC_E                       = 407 /* 0x197 */,
+  WIFIRXOLE_CCE_SUPERRULE_E                = 408 /* 0x198 */,
+  WIFITX_RATE_STATS_INFO_E                 = 409 /* 0x199 */,
+  WIFICMD_PART_0_END_E                     = 410 /* 0x19a */,
+  WIFIMACTX_SYNTH_ON_E                     = 411 /* 0x19b */,
+  WIFISCH_CRITICAL_TLV_REFERENCE_E         = 412 /* 0x19c */,
+  WIFITQM_MPDU_GLOBAL_START_E              = 413 /* 0x19d */,
+  WIFIEXAMPLE_TLV_32_E                     = 414 /* 0x19e */,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_E            = 415 /* 0x19f */,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E      = 416 /* 0x1a0 */,
+  WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E     = 417 /* 0x1a1 */,
+  WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */,
+  WIFIREO_UPDATE_RX_REO_QUEUE_E            = 419 /* 0x1a3 */,
+  WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E     = 420 /* 0x1a4 */,
+  WIFITLV_BASE_E                           = 511 /* 0x1ff */
+
+} tlv_tag_def__e; ///< tlv_tag_def Enum Type
+
+#endif // _TLV_TAG_DEF_

hw/qca6290/v1/tx_msdu_extension.h

@@ -0,0 +1,827 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _TX_MSDU_EXTENSION_H_
+#define _TX_MSDU_EXTENSION_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	tso_enable[0], ipv4_checksum_en[1], udp_over_ipv4_checksum_en[2], udp_over_ipv6_checksum_en[3], tcp_over_ipv4_checksum_en[4], tcp_over_ipv6_checksum_en[5], reserved_0a[6], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25]
+//	1	l2_length[15:0], ip_length[31:16]
+//	2	tcp_seq_number[31:0]
+//	3	ip_identification[15:0], udp_length[31:16]
+//	4	checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30]
+//	5	payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17]
+//	6	buf0_ptr_31_0[31:0]
+//	7	buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16]
+//	8	buf1_ptr_31_0[31:0]
+//	9	buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16]
+//	10	buf2_ptr_31_0[31:0]
+//	11	buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16]
+//	12	buf3_ptr_31_0[31:0]
+//	13	buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16]
+//	14	buf4_ptr_31_0[31:0]
+//	15	buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16]
+//	16	buf5_ptr_31_0[31:0]
+//	17	buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18
+
+struct tx_msdu_extension {
+             uint32_t tso_enable                      :  1, //[0]
+                      ipv4_checksum_en                :  1, //[1]
+                      udp_over_ipv4_checksum_en       :  1, //[2]
+                      udp_over_ipv6_checksum_en       :  1, //[3]
+                      tcp_over_ipv4_checksum_en       :  1, //[4]
+                      tcp_over_ipv6_checksum_en       :  1, //[5]
+                      reserved_0a                     :  1, //[6]
+                      tcp_flag                        :  9, //[15:7]
+                      tcp_flag_mask                   :  9, //[24:16]
+                      reserved_0b                     :  7; //[31:25]
+             uint32_t l2_length                       : 16, //[15:0]
+                      ip_length                       : 16; //[31:16]
+             uint32_t tcp_seq_number                  : 32; //[31:0]
+             uint32_t ip_identification               : 16, //[15:0]
+                      udp_length                      : 16; //[31:16]
+             uint32_t checksum_offset                 : 14, //[13:0]
+                      partial_checksum_en             :  1, //[14]
+                      reserved_4a                     :  1, //[15]
+                      payload_start_offset            : 14, //[29:16]
+                      reserved_4b                     :  2; //[31:30]
+             uint32_t payload_end_offset              : 14, //[13:0]
+                      reserved_5a                     :  2, //[15:14]
+                      wds                             :  1, //[16]
+                      reserved_5b                     : 15; //[31:17]
+             uint32_t buf0_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf0_ptr_39_32                  :  8, //[7:0]
+                      reserved_7a                     :  8, //[15:8]
+                      buf0_len                        : 16; //[31:16]
+             uint32_t buf1_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf1_ptr_39_32                  :  8, //[7:0]
+                      reserved_9a                     :  8, //[15:8]
+                      buf1_len                        : 16; //[31:16]
+             uint32_t buf2_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf2_ptr_39_32                  :  8, //[7:0]
+                      reserved_11a                    :  8, //[15:8]
+                      buf2_len                        : 16; //[31:16]
+             uint32_t buf3_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf3_ptr_39_32                  :  8, //[7:0]
+                      reserved_13a                    :  8, //[15:8]
+                      buf3_len                        : 16; //[31:16]
+             uint32_t buf4_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf4_ptr_39_32                  :  8, //[7:0]
+                      reserved_15a                    :  8, //[15:8]
+                      buf4_len                        : 16; //[31:16]
+             uint32_t buf5_ptr_31_0                   : 32; //[31:0]
+             uint32_t buf5_ptr_39_32                  :  8, //[7:0]
+                      reserved_17a                    :  8, //[15:8]
+                      buf5_len                        : 16; //[31:16]
+};
+
+/*
+
+tso_enable
+			
+			Enable transmit segmentation offload <legal all>
+
+ipv4_checksum_en
+			
+			Enable IPv4 checksum replacement
+
+udp_over_ipv4_checksum_en
+			
+			Enable UDP over IPv4 checksum replacement.  UDP checksum
+			over IPv4 is optional for TCP/IP stacks.
+
+udp_over_ipv6_checksum_en
+			
+			Enable UDP over IPv6 checksum replacement.  UDP checksum
+			over IPv6 is mandatory for TCP/IP stacks.
+
+tcp_over_ipv4_checksum_en
+			
+			Enable TCP checksum over IPv4 replacement
+
+tcp_over_ipv6_checksum_en
+			
+			Enable TCP checksum over IPv6 eplacement
+
+reserved_0a
+			
+			FW will set to 0, MAC will ignore.  <legal 0>
+
+tcp_flag
+			
+			TCP flags
+			
+			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
+
+tcp_flag_mask
+			
+			TCP flag mask. Tcp_flag is inserted into the header
+			based on the mask, if tso is enabled
+
+reserved_0b
+			
+			FW will set to 0, MAC will ignore.  <legal 0>
+
+l2_length
+			
+			L2 length for the msdu, if tso is enabled <legal all>
+
+ip_length
+			
+			Ip length for the msdu, if tso is enabled <legal all>
+
+tcp_seq_number
+			
+			Tcp_seq_number for the msdu, if tso is enabled <legal
+			all>
+
+ip_identification
+			
+			Ip_identification for the msdu, if tso is enabled <legal
+			all>
+
+udp_length
+			
+			TXDMA is copies this field into MSDU START TLV
+
+checksum_offset
+			
+			The calculated checksum from start offset to end offset
+			will be added to the checksum at the offset given by this
+			field<legal all>
+
+partial_checksum_en
+			
+			Partial Checksum Enable Bit.
+			
+			<legal 0-1>
+
+reserved_4a
+			
+			<Legal 0>
+
+payload_start_offset
+			
+			L4 checksum calculations will start fromt this offset
+			
+			<Legal all>
+
+reserved_4b
+			
+			<Legal 0>
+
+payload_end_offset
+			
+			L4 checksum calculations will end at this offset. 
+			
+			<Legal all>
+
+reserved_5a
+			
+			<Legal 0>
+
+wds
+			
+			If set the current packet is 4-address frame.  Required
+			because an aggregate can include some frames with 3 address
+			format and other frames with 4 address format.  Used by the
+			OLE during encapsulation.  
+			
+			Note: there is also global wds tx control in the
+			TX_PEER_ENTRY
+			
+			<legal all>
+
+reserved_5b
+			
+			<Legal 0>
+
+buf0_ptr_31_0
+			
+			Lower 32 bits of the first buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+
+buf0_ptr_39_32
+			
+			Upper 8 bits of the first buffer pointer <legal all>
+
+reserved_7a
+			
+			<Legal 0>
+
+buf0_len
+			
+			Length of the first buffer <legal all>
+
+buf1_ptr_31_0
+			
+			Lower 32 bits of the second buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+
+buf1_ptr_39_32
+			
+			Upper 8 bits of the second buffer pointer <legal all>
+
+reserved_9a
+			
+			<Legal 0>
+
+buf1_len
+			
+			Length of the second buffer <legal all>
+
+buf2_ptr_31_0
+			
+			Lower 32 bits of the third buffer pointer 
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+
+buf2_ptr_39_32
+			
+			Upper 8 bits of the third buffer pointer <legal all>
+
+reserved_11a
+			
+			<Legal 0>
+
+buf2_len
+			
+			Length of the third buffer <legal all>
+
+buf3_ptr_31_0
+			
+			Lower 32 bits of the fourth buffer pointer
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			 <legal all>
+
+buf3_ptr_39_32
+			
+			Upper 8 bits of the fourth buffer pointer <legal all>
+
+reserved_13a
+			
+			<Legal 0>
+
+buf3_len
+			
+			Length of the fourth buffer <legal all>
+
+buf4_ptr_31_0
+			
+			Lower 32 bits of the fifth buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+
+buf4_ptr_39_32
+			
+			Upper 8 bits of the fifth buffer pointer <legal all>
+
+reserved_15a
+			
+			<Legal 0>
+
+buf4_len
+			
+			Length of the fifth buffer <legal all>
+
+buf5_ptr_31_0
+			
+			Lower 32 bits of the sixth buffer pointer
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			 <legal all>
+
+buf5_ptr_39_32
+			
+			Upper 8 bits of the sixth buffer pointer <legal all>
+
+reserved_17a
+			
+			<Legal 0>
+
+buf5_len
+			
+			Length of the sixth buffer <legal all>
+*/
+
+
+/* Description		TX_MSDU_EXTENSION_0_TSO_ENABLE
+			
+			Enable transmit segmentation offload <legal all>
+*/
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET                        0x00000000
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB                           0
+#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK                          0x00000001
+
+/* Description		TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN
+			
+			Enable IPv4 checksum replacement
+*/
+#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_OFFSET                  0x00000000
+#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_LSB                     1
+#define TX_MSDU_EXTENSION_0_IPV4_CHECKSUM_EN_MASK                    0x00000002
+
+/* Description		TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN
+			
+			Enable UDP over IPv4 checksum replacement.  UDP checksum
+			over IPv4 is optional for TCP/IP stacks.
+*/
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET         0x00000000
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_LSB            2
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV4_CHECKSUM_EN_MASK           0x00000004
+
+/* Description		TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN
+			
+			Enable UDP over IPv6 checksum replacement.  UDP checksum
+			over IPv6 is mandatory for TCP/IP stacks.
+*/
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET         0x00000000
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_LSB            3
+#define TX_MSDU_EXTENSION_0_UDP_OVER_IPV6_CHECKSUM_EN_MASK           0x00000008
+
+/* Description		TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN
+			
+			Enable TCP checksum over IPv4 replacement
+*/
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET         0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_LSB            4
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV4_CHECKSUM_EN_MASK           0x00000010
+
+/* Description		TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN
+			
+			Enable TCP checksum over IPv6 eplacement
+*/
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET         0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_LSB            5
+#define TX_MSDU_EXTENSION_0_TCP_OVER_IPV6_CHECKSUM_EN_MASK           0x00000020
+
+/* Description		TX_MSDU_EXTENSION_0_RESERVED_0A
+			
+			FW will set to 0, MAC will ignore.  <legal 0>
+*/
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET                       0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB                          6
+#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK                         0x00000040
+
+/* Description		TX_MSDU_EXTENSION_0_TCP_FLAG
+			
+			TCP flags
+			
+			{NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}<legal all>
+*/
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET                          0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB                             7
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK                            0x0000ff80
+
+/* Description		TX_MSDU_EXTENSION_0_TCP_FLAG_MASK
+			
+			TCP flag mask. Tcp_flag is inserted into the header
+			based on the mask, if tso is enabled
+*/
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET                     0x00000000
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB                        16
+#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK                       0x01ff0000
+
+/* Description		TX_MSDU_EXTENSION_0_RESERVED_0B
+			
+			FW will set to 0, MAC will ignore.  <legal 0>
+*/
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET                       0x00000000
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB                          25
+#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK                         0xfe000000
+
+/* Description		TX_MSDU_EXTENSION_1_L2_LENGTH
+			
+			L2 length for the msdu, if tso is enabled <legal all>
+*/
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET                         0x00000004
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB                            0
+#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK                           0x0000ffff
+
+/* Description		TX_MSDU_EXTENSION_1_IP_LENGTH
+			
+			Ip length for the msdu, if tso is enabled <legal all>
+*/
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET                         0x00000004
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB                            16
+#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK                           0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER
+			
+			Tcp_seq_number for the msdu, if tso is enabled <legal
+			all>
+*/
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET                    0x00000008
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB                       0
+#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK                      0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_3_IP_IDENTIFICATION
+			
+			Ip_identification for the msdu, if tso is enabled <legal
+			all>
+*/
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET                 0x0000000c
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB                    0
+#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK                   0x0000ffff
+
+/* Description		TX_MSDU_EXTENSION_3_UDP_LENGTH
+			
+			TXDMA is copies this field into MSDU START TLV
+*/
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET                        0x0000000c
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB                           16
+#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK                          0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET
+			
+			The calculated checksum from start offset to end offset
+			will be added to the checksum at the offset given by this
+			field<legal all>
+*/
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET                   0x00000010
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB                      0
+#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK                     0x00003fff
+
+/* Description		TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN
+			
+			Partial Checksum Enable Bit.
+			
+			<legal 0-1>
+*/
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET               0x00000010
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB                  14
+#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK                 0x00004000
+
+/* Description		TX_MSDU_EXTENSION_4_RESERVED_4A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET                       0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB                          15
+#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK                         0x00008000
+
+/* Description		TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET
+			
+			L4 checksum calculations will start fromt this offset
+			
+			<Legal all>
+*/
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET              0x00000010
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB                 16
+#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK                0x3fff0000
+
+/* Description		TX_MSDU_EXTENSION_4_RESERVED_4B
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET                       0x00000010
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB                          30
+#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK                         0xc0000000
+
+/* Description		TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET
+			
+			L4 checksum calculations will end at this offset. 
+			
+			<Legal all>
+*/
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET                0x00000014
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB                   0
+#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK                  0x00003fff
+
+/* Description		TX_MSDU_EXTENSION_5_RESERVED_5A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET                       0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB                          14
+#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK                         0x0000c000
+
+/* Description		TX_MSDU_EXTENSION_5_WDS
+			
+			If set the current packet is 4-address frame.  Required
+			because an aggregate can include some frames with 3 address
+			format and other frames with 4 address format.  Used by the
+			OLE during encapsulation.  
+			
+			Note: there is also global wds tx control in the
+			TX_PEER_ENTRY
+			
+			<legal all>
+*/
+#define TX_MSDU_EXTENSION_5_WDS_OFFSET                               0x00000014
+#define TX_MSDU_EXTENSION_5_WDS_LSB                                  16
+#define TX_MSDU_EXTENSION_5_WDS_MASK                                 0x00010000
+
+/* Description		TX_MSDU_EXTENSION_5_RESERVED_5B
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET                       0x00000014
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB                          17
+#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK                         0xfffe0000
+
+/* Description		TX_MSDU_EXTENSION_6_BUF0_PTR_31_0
+			
+			Lower 32 bits of the first buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+*/
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET                     0x00000018
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB                        0
+#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK                       0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_7_BUF0_PTR_39_32
+			
+			Upper 8 bits of the first buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET                    0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB                       0
+#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK                      0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_7_RESERVED_7A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET                       0x0000001c
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB                          8
+#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK                         0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_7_BUF0_LEN
+			
+			Length of the first buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET                          0x0000001c
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB                             16
+#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK                            0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_8_BUF1_PTR_31_0
+			
+			Lower 32 bits of the second buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+*/
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET                     0x00000020
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB                        0
+#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK                       0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_9_BUF1_PTR_39_32
+			
+			Upper 8 bits of the second buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET                    0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB                       0
+#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK                      0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_9_RESERVED_9A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET                       0x00000024
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB                          8
+#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK                         0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_9_BUF1_LEN
+			
+			Length of the second buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET                          0x00000024
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB                             16
+#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK                            0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_10_BUF2_PTR_31_0
+			
+			Lower 32 bits of the third buffer pointer 
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+*/
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET                    0x00000028
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK                      0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_11_BUF2_PTR_39_32
+			
+			Upper 8 bits of the third buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET                   0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK                     0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_11_RESERVED_11A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET                     0x0000002c
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB                        8
+#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK                       0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_11_BUF2_LEN
+			
+			Length of the third buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET                         0x0000002c
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK                           0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_12_BUF3_PTR_31_0
+			
+			Lower 32 bits of the fourth buffer pointer
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			 <legal all>
+*/
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET                    0x00000030
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK                      0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_13_BUF3_PTR_39_32
+			
+			Upper 8 bits of the fourth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET                   0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK                     0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_13_RESERVED_13A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET                     0x00000034
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB                        8
+#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK                       0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_13_BUF3_LEN
+			
+			Length of the fourth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET                         0x00000034
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK                           0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_14_BUF4_PTR_31_0
+			
+			Lower 32 bits of the fifth buffer pointer 
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			<legal all>
+*/
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET                    0x00000038
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK                      0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_15_BUF4_PTR_39_32
+			
+			Upper 8 bits of the fifth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET                   0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK                     0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_15_RESERVED_15A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET                     0x0000003c
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB                        8
+#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK                       0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_15_BUF4_LEN
+			
+			Length of the fifth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET                         0x0000003c
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK                           0xffff0000
+
+/* Description		TX_MSDU_EXTENSION_16_BUF5_PTR_31_0
+			
+			Lower 32 bits of the sixth buffer pointer
+			
+			
+			
+			NOTE: SW/FW manages the 'cookie' info related to this
+			buffer together with the 'cookie' info for this
+			MSDU_EXTENSION descriptor
+			
+			 <legal all>
+*/
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET                    0x00000040
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB                       0
+#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK                      0xffffffff
+
+/* Description		TX_MSDU_EXTENSION_17_BUF5_PTR_39_32
+			
+			Upper 8 bits of the sixth buffer pointer <legal all>
+*/
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET                   0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB                      0
+#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK                     0x000000ff
+
+/* Description		TX_MSDU_EXTENSION_17_RESERVED_17A
+			
+			<Legal 0>
+*/
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET                     0x00000044
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB                        8
+#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK                       0x0000ff00
+
+/* Description		TX_MSDU_EXTENSION_17_BUF5_LEN
+			
+			Length of the sixth buffer <legal all>
+*/
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET                         0x00000044
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB                            16
+#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK                           0xffff0000
+
+
+#endif // _TX_MSDU_EXTENSION_H_

hw/qca6290/v1/tx_rate_stats_info.h

@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _TX_RATE_STATS_INFO_H_
+#define _TX_RATE_STATS_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28]
+//	1	tsf_directly_after_ppdu_transmission[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2
+
+struct tx_rate_stats_info {
+             uint32_t tx_rate_stats_info_valid        :  1, //[0]
+                      transmit_bw                     :  2, //[2:1]
+                      transmit_pkt_type               :  4, //[6:3]
+                      transmit_stbc                   :  1, //[7]
+                      transmit_ldpc                   :  1, //[8]
+                      transmit_sgi                    :  2, //[10:9]
+                      transmit_mcs                    :  4, //[14:11]
+                      ofdma_transmission              :  1, //[15]
+                      tones_in_ru                     : 12, //[27:16]
+                      reserved_0a                     :  4; //[31:28]
+             uint32_t tsf_directly_after_ppdu_transmission: 32; //[31:0]
+};
+
+/*
+
+tx_rate_stats_info_valid
+			
+			When set all other fields in this STRUCT contain valid
+			info.
+			
+			
+			
+			
+			<legal all>
+
+transmit_bw
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Indicates the BW of the upcoming transmission that shall
+			likely start in about 3 -4 us on the medium
+			
+			
+			
+			<enum 0 transmit_bw_20_MHz>
+			
+			<enum 1 transmit_bw_40_MHz>
+			
+			<enum 2 transmit_bw_80_MHz>
+			
+			<enum 3 transmit_bw_160_MHz>
+			
+			
+			
+			<legal all>
+
+transmit_pkt_type
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			The packet type
+			
+			<enum 0 dot11a>802.11a PPDU type
+			
+			<enum 1 dot11b>802.11b PPDU type
+			
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+			
+			<enum 3 dot11ac>802.11ac PPDU type
+			
+			<enum 4 dot11ax>802.11ax PPDU type
+
+transmit_stbc
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			When set, STBC transmission rate was used.
+
+transmit_ldpc
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			When set, use LDPC transmission rates
+
+transmit_sgi
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			<enum 0     0_8_us_sgi > Legacy normal GI
+			
+			<enum 1     0_4_us_sgi > Legacy short GI
+			
+			<enum 2     1_6_us_sgi > HE related GI
+			
+			<enum 3     3_2_us_sgi > HE related GI
+			
+			<legal 0 - 3>
+
+transmit_mcs
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			For details, refer to  MCS_TYPE description
+			
+			<legal all>
+
+ofdma_transmission
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			
+			
+			Set when the transmission was an OFDMA transmission (DL
+			or UL).
+			
+			<legal all>
+
+tones_in_ru
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			The number of tones in the RU used.
+			
+			
+			
+			TODO: not clear yet what the number of tones is for RUs
+			of 160 or 80 + 80 ???
+			
+			For now assumption is that this value for this scenario
+			will indicate: 0x7FF
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+
+tsf_directly_after_ppdu_transmission
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Lower 32 bits of the TSF, snapshot of this value when
+			transmission of the PPDU containing the frame finished.
+			
+			<legal all>
+*/
+
+
+/* Description		TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID
+			
+			When set all other fields in this STRUCT contain valid
+			info.
+			
+			
+			
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET         0x00000000
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB            0
+#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK           0x00000001
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_BW
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Indicates the BW of the upcoming transmission that shall
+			likely start in about 3 -4 us on the medium
+			
+			
+			
+			<enum 0 transmit_bw_20_MHz>
+			
+			<enum 1 transmit_bw_40_MHz>
+			
+			<enum 2 transmit_bw_80_MHz>
+			
+			<enum 3 transmit_bw_160_MHz>
+			
+			
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB                         1
+#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK                        0x00000006
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			The packet type
+			
+			<enum 0 dot11a>802.11a PPDU type
+			
+			<enum 1 dot11b>802.11b PPDU type
+			
+			<enum 2 dot11n_mm>802.11n Mixed Mode PPDU type
+			
+			<enum 3 dot11ac>802.11ac PPDU type
+			
+			<enum 4 dot11ax>802.11ax PPDU type
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET                0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB                   3
+#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK                  0x00000078
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_STBC
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			When set, STBC transmission rate was used.
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET                    0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB                       7
+#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK                      0x00000080
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_LDPC
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			When set, use LDPC transmission rates
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET                    0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB                       8
+#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK                      0x00000100
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_SGI
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			<enum 0     0_8_us_sgi > Legacy normal GI
+			
+			<enum 1     0_4_us_sgi > Legacy short GI
+			
+			<enum 2     1_6_us_sgi > HE related GI
+			
+			<enum 3     3_2_us_sgi > HE related GI
+			
+			<legal 0 - 3>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET                     0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB                        9
+#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK                       0x00000600
+
+/* Description		TX_RATE_STATS_INFO_0_TRANSMIT_MCS
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			For details, refer to  MCS_TYPE description
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET                     0x00000000
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB                        11
+#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK                       0x00007800
+
+/* Description		TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			
+			
+			Set when the transmission was an OFDMA transmission (DL
+			or UL).
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET               0x00000000
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB                  15
+#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK                 0x00008000
+
+/* Description		TX_RATE_STATS_INFO_0_TONES_IN_RU
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Field filled in by PDG.
+			
+			Not valid when in SW transmit mode
+			
+			
+			
+			The number of tones in the RU used.
+			
+			
+			
+			TODO: not clear yet what the number of tones is for RUs
+			of 160 or 80 + 80 ???
+			
+			For now assumption is that this value for this scenario
+			will indicate: 0x7FF
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB                         16
+#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK                        0x0fff0000
+
+/* Description		TX_RATE_STATS_INFO_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET                      0x00000000
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB                         28
+#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK                        0xf0000000
+
+/* Description		TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION
+			
+			Field only valid when Tx_rate_stats_info_valid is set
+			
+			
+			
+			Lower 32 bits of the TSF, snapshot of this value when
+			transmission of the PPDU containing the frame finished.
+			
+			<legal all>
+*/
+#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_OFFSET 0x00000004
+#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_LSB 0
+#define TX_RATE_STATS_INFO_1_TSF_DIRECTLY_AFTER_PPDU_TRANSMISSION_MASK 0xffffffff
+
+
+#endif // _TX_RATE_STATS_INFO_H_

hw/qca6290/v1/uniform_descriptor_header.h

@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_
+#define _UNIFORM_DESCRIPTOR_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	owner[3:0], buffer_type[7:4], reserved_0a[31:8]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1
+
+struct uniform_descriptor_header {
+             uint32_t owner                           :  4, //[3:0]
+                      buffer_type                     :  4, //[7:4]
+                      reserved_0a                     : 24; //[31:8]
+};
+
+/*
+
+owner
+			
+			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+			
+			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 
+			
+			
+			
+			The owner of this data structure:
+			
+			<enum 0 WBM_owned> Buffer Manager currently owns this
+			data structure.
+			
+			<enum 1 SW_OR_FW_owned> Software of FW currently owns
+			this data structure.
+			
+			<enum 2 TQM_owned> Transmit Queue Manager currently owns
+			this data structure.
+			
+			<enum 3 RXDMA_owned> Receive DMA currently owns this
+			data structure.
+			
+			<enum 4 REO_owned> Reorder currently owns this data
+			structure.
+			
+			<enum 5 SWITCH_owned> SWITCH currently owns this data
+			structure.
+			
+			
+			
+			<legal 0-5> 
+
+buffer_type
+			
+			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+			
+			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 
+			
+			
+			
+			Field describing what contents format is of this
+			descriptor
+			
+			
+			
+			<enum 0 Transmit_MSDU_Link_descriptor > 
+			
+			<enum 1 Transmit_MPDU_Link_descriptor > 
+			
+			<enum 2 Transmit_MPDU_Queue_head_descriptor>
+			
+			<enum 3 Transmit_MPDU_Queue_ext_descriptor>
+			
+			<enum 4 Transmit_flow_descriptor>
+			
+			<enum 5 Transmit_buffer > 
+			
+			
+			
+			<enum 6 Receive_MSDU_Link_descriptor >
+			
+			<enum 7 Receive_MPDU_Link_descriptor >
+			
+			<enum 8 Receive_REO_queue_descriptor >
+			
+			<enum 9 Receive_REO_queue_ext_descriptor >
+			
+			
+			
+			<enum 10 Receive_buffer >
+			
+			
+			
+			<enum 11 Idle_link_list_entry>
+			
+			
+			
+			<legal 0-11> 
+
+reserved_0a
+			
+			<legal 0>
+*/
+
+
+/* Description		UNIFORM_DESCRIPTOR_HEADER_0_OWNER
+			
+			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+			
+			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 
+			
+			
+			
+			The owner of this data structure:
+			
+			<enum 0 WBM_owned> Buffer Manager currently owns this
+			data structure.
+			
+			<enum 1 SW_OR_FW_owned> Software of FW currently owns
+			this data structure.
+			
+			<enum 2 TQM_owned> Transmit Queue Manager currently owns
+			this data structure.
+			
+			<enum 3 RXDMA_owned> Receive DMA currently owns this
+			data structure.
+			
+			<enum 4 REO_owned> Reorder currently owns this data
+			structure.
+			
+			<enum 5 SWITCH_owned> SWITCH currently owns this data
+			structure.
+			
+			
+			
+			<legal 0-5> 
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET                     0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB                        0
+#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK                       0x0000000f
+
+/* Description		UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE
+			
+			Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO
+			
+			Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO 
+			
+			
+			
+			Field describing what contents format is of this
+			descriptor
+			
+			
+			
+			<enum 0 Transmit_MSDU_Link_descriptor > 
+			
+			<enum 1 Transmit_MPDU_Link_descriptor > 
+			
+			<enum 2 Transmit_MPDU_Queue_head_descriptor>
+			
+			<enum 3 Transmit_MPDU_Queue_ext_descriptor>
+			
+			<enum 4 Transmit_flow_descriptor>
+			
+			<enum 5 Transmit_buffer > 
+			
+			
+			
+			<enum 6 Receive_MSDU_Link_descriptor >
+			
+			<enum 7 Receive_MPDU_Link_descriptor >
+			
+			<enum 8 Receive_REO_queue_descriptor >
+			
+			<enum 9 Receive_REO_queue_ext_descriptor >
+			
+			
+			
+			<enum 10 Receive_buffer >
+			
+			
+			
+			<enum 11 Idle_link_list_entry>
+			
+			
+			
+			<legal 0-11> 
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET               0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB                  4
+#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK                 0x000000f0
+
+/* Description		UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET               0x00000000
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB                  8
+#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK                 0xffffff00
+
+
+#endif // _UNIFORM_DESCRIPTOR_HEADER_H_

hw/qca6290/v1/uniform_reo_cmd_header.h

@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _UNIFORM_REO_CMD_HEADER_H_
+#define _UNIFORM_REO_CMD_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1
+
+struct uniform_reo_cmd_header {
+             uint32_t reo_cmd_number                  : 16, //[15:0]
+                      reo_status_required             :  1, //[16]
+                      reserved_0a                     : 15; //[31:17]
+};
+
+/*
+
+reo_cmd_number
+			
+			Consumer: REO/SW/DEBUG
+			
+			Producer: SW 
+			
+			
+			
+			This number can be used by SW to track, identify and
+			link the created commands with the command statusses
+			
+			
+			
+			
+			
+			<legal all> 
+
+reo_status_required
+			
+			Consumer: REO
+			
+			Producer: SW 
+			
+			
+			
+			<enum 0 NoStatus> REO does not need to generate a status
+			TLV for the execution of this command
+			
+			<enum 1 StatusRequired> REO shall generate a status TLV
+			for the execution of this command
+			
+			
+			
+			<legal all>
+
+reserved_0a
+			
+			<legal 0>
+*/
+
+
+/* Description		UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER
+			
+			Consumer: REO/SW/DEBUG
+			
+			Producer: SW 
+			
+			
+			
+			This number can be used by SW to track, identify and
+			link the created commands with the command statusses
+			
+			
+			
+			
+			
+			<legal all> 
+*/
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET               0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB                  0
+#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK                 0x0000ffff
+
+/* Description		UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED
+			
+			Consumer: REO
+			
+			Producer: SW 
+			
+			
+			
+			<enum 0 NoStatus> REO does not need to generate a status
+			TLV for the execution of this command
+			
+			<enum 1 StatusRequired> REO shall generate a status TLV
+			for the execution of this command
+			
+			
+			
+			<legal all>
+*/
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET          0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB             16
+#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK            0x00010000
+
+/* Description		UNIFORM_REO_CMD_HEADER_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET                  0x00000000
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB                     17
+#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK                    0xfffe0000
+
+
+#endif // _UNIFORM_REO_CMD_HEADER_H_

hw/qca6290/v1/uniform_reo_status_header.h

@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _UNIFORM_REO_STATUS_HEADER_H_
+#define _UNIFORM_REO_STATUS_HEADER_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28]
+//	1	timestamp[31:0]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2
+
+struct uniform_reo_status_header {
+             uint32_t reo_status_number               : 16, //[15:0]
+                      cmd_execution_time              : 10, //[25:16]
+                      reo_cmd_execution_status        :  2, //[27:26]
+                      reserved_0a                     :  4; //[31:28]
+             uint32_t timestamp                       : 32; //[31:0]
+};
+
+/*
+
+reo_status_number
+			
+			Consumer: SW , DEBUG
+			
+			Producer: REO
+			
+			
+			
+			The value in this field is equal to value of the
+			'REO_CMD_Number' field the REO command 
+			
+			
+			
+			This field helps to correlate the statuses with the REO
+			commands.
+			
+			
+			
+			<legal all> 
+
+cmd_execution_time
+			
+			Consumer: DEBUG
+			
+			Producer: REO 
+			
+			
+			
+			The amount of time REO took to excecute the command.
+			Note that this time does not include the duration of the
+			command waiting in the command ring, before the execution
+			started.
+			
+			
+			
+			In us.
+			
+			
+			
+			<legal all>
+
+reo_cmd_execution_status
+			
+			Consumer: DEBUG
+			
+			Producer: REO 
+			
+			
+			
+			Execution status of the command.
+			
+			
+			
+			<enum 0 reo_successful_execution> Command has
+			successfully be executed
+			
+			<enum 1 reo_blocked_execution> Command could not be
+			executed as the queue or cache was blocked
+			
+			<enum 2 reo_failed_execution> Command has encountered
+			problems when executing, like the queue descriptor not being
+			valid. None of the status fields in the entire STATUS TLV
+			are valid.
+			
+			<enum 3 reo_resource_blocked> Command is NOT  executed
+			because one or more descriptors were blocked. This is SW
+			programming mistake.
+			
+			None of the status fields in the entire STATUS TLV are
+			valid.
+			
+			
+			
+			<legal  0-3>
+
+reserved_0a
+			
+			<legal 0>
+
+timestamp
+			
+			Timestamp at the moment that this status report is
+			written.
+			
+			
+			
+			<legal all>
+*/
+
+
+/* Description		UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER
+			
+			Consumer: SW , DEBUG
+			
+			Producer: REO
+			
+			
+			
+			The value in this field is equal to value of the
+			'REO_CMD_Number' field the REO command 
+			
+			
+			
+			This field helps to correlate the statuses with the REO
+			commands.
+			
+			
+			
+			<legal all> 
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET         0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB            0
+#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK           0x0000ffff
+
+/* Description		UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME
+			
+			Consumer: DEBUG
+			
+			Producer: REO 
+			
+			
+			
+			The amount of time REO took to excecute the command.
+			Note that this time does not include the duration of the
+			command waiting in the command ring, before the execution
+			started.
+			
+			
+			
+			In us.
+			
+			
+			
+			<legal all>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET        0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB           16
+#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK          0x03ff0000
+
+/* Description		UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS
+			
+			Consumer: DEBUG
+			
+			Producer: REO 
+			
+			
+			
+			Execution status of the command.
+			
+			
+			
+			<enum 0 reo_successful_execution> Command has
+			successfully be executed
+			
+			<enum 1 reo_blocked_execution> Command could not be
+			executed as the queue or cache was blocked
+			
+			<enum 2 reo_failed_execution> Command has encountered
+			problems when executing, like the queue descriptor not being
+			valid. None of the status fields in the entire STATUS TLV
+			are valid.
+			
+			<enum 3 reo_resource_blocked> Command is NOT  executed
+			because one or more descriptors were blocked. This is SW
+			programming mistake.
+			
+			None of the status fields in the entire STATUS TLV are
+			valid.
+			
+			
+			
+			<legal  0-3>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET  0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB     26
+#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK    0x0c000000
+
+/* Description		UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A
+			
+			<legal 0>
+*/
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET               0x00000000
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB                  28
+#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK                 0xf0000000
+
+/* Description		UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP
+			
+			Timestamp at the moment that this status report is
+			written.
+			
+			
+			
+			<legal all>
+*/
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET                 0x00000004
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB                    0
+#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK                   0xffffffff
+
+
+#endif // _UNIFORM_REO_STATUS_HEADER_H_

hw/qca6290/v1/wbm_buffer_ring.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _WBM_BUFFER_RING_H_
+#define _WBM_BUFFER_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info buf_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_BUFFER_RING 2
+
+struct wbm_buffer_ring {
+    struct            buffer_addr_info                       buf_addr_info;
+};
+
+/*
+
+struct buffer_addr_info buf_addr_info
+			
+			Consumer: WBM
+			
+			Producer: WBM
+			
+			
+			
+			Details of the physical address of the buffer + source
+			buffer owner +  some SW meta data.
+			
+			All modules getting this buffer address info, shall keep
+			all the 64 bits of info in this descriptor together and
+			eventually all 64 bits shall be given back to WMB when the
+			buffer is released.
+*/
+
+#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET      0x00000000
+#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB         0
+#define WBM_BUFFER_RING_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK        0xffffffff
+#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET      0x00000004
+#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_LSB         0
+#define WBM_BUFFER_RING_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_MASK        0xffffffff
+
+
+#endif // _WBM_BUFFER_RING_H_

hw/qca6290/v1/wbm_link_descriptor_ring.h

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _WBM_LINK_DESCRIPTOR_RING_H_
+#define _WBM_LINK_DESCRIPTOR_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info desc_addr_info;
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2
+
+struct wbm_link_descriptor_ring {
+    struct            buffer_addr_info                       desc_addr_info;
+};
+
+/*
+
+struct buffer_addr_info desc_addr_info
+			
+			Consumer: WBM
+			
+			Producer: WBM
+			
+			
+			
+			Details of the physical address of the buffer + source
+			buffer owner +  some SW meta data
+			
+			All modules getting this link descriptor address info,
+			shall keep all the 64 bits in this descriptor together and
+			eventually all 64 bits shall be given back to WBM when the
+			link descriptor is released.
+*/
+
+#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000000
+#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_0_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff
+#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_OFFSET 0x00000004
+#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_LSB 0
+#define WBM_LINK_DESCRIPTOR_RING_1_BUFFER_ADDR_INFO_DESC_ADDR_INFO_MASK 0xffffffff
+
+
+#endif // _WBM_LINK_DESCRIPTOR_RING_H_

hw/qca6290/v1/wbm_reg_seq_hwiobase.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WBM_REG_SEQ_BASE_H__
+#define __WBM_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+#endif
+

hw/qca6290/v1/wbm_reg_seq_hwioreg.h

@@ -0,0 +1,12394 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WBM_REG_SEQ_REG_H__
+#define __WBM_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "wbm_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WBM_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register WBM_R0_GENERAL_ENABLE ////
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x)                           (x+0x00000000)
+#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x)                           (x+0x00000000)
+#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK                              0x000000ff
+#define HWIO_WBM_R0_GENERAL_ENABLE_SHFT                                       0
+#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK)
+#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT        0x7
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK     0x00000040
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT            0x6
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK   0x00000020
+#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT          0x5
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK      0x00000010
+#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT             0x4
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000008
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT        0x3
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000004
+#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT        0x2
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT        0x1
+
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT        0x0
+
+//// Register WBM_R0_RELEASE_RING_ENABLE ////
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x)                      (x+0x00000004)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x)                      (x+0x00000004)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK                         0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SHFT                                  0
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_BMSK                   0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_ENABLE_VALUE_SHFT                          0x0
+
+//// Register WBM_R0_MSDU_BUFFER_RING_ENABLE ////
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x)                  (x+0x00000008)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x)                  (x+0x00000008)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK                     0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_SHFT                              0
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_BMSK               0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_VALUE_SHFT                      0x0
+
+//// Register WBM_R0_LINK_DESC_RING_ENABLE ////
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x)                    (x+0x0000000c)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x)                    (x+0x0000000c)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK                       0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_SHFT                                0
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_BMSK                 0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_VALUE_SHFT                        0x0
+
+//// Register WBM_R0_MISC_RING_ENABLE ////
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x)                         (x+0x00000010)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x)                         (x+0x00000010)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK                            0x0000001f
+#define HWIO_WBM_R0_MISC_RING_ENABLE_SHFT                                     0
+#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)                           \
+	in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask)                    \
+	in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val)                     \
+	out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_BMSK     0x00000010
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW3_BUFFER_RING_SHFT            0x4
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_BMSK     0x00000008
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW2_BUFFER_RING_SHFT            0x3
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_BMSK     0x00000004
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW1_BUFFER_RING_SHFT            0x2
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_BMSK     0x00000002
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_SW0_BUFFER_RING_SHFT            0x1
+
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_BMSK      0x00000001
+#define HWIO_WBM_R0_MISC_RING_ENABLE_ENABLE_FW_BUFFER_RING_SHFT             0x0
+
+//// Register WBM_R0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x)                      (x+0x00000014)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x)                      (x+0x00000014)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK                         0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_SHFT                                  0
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_BMSK   0x000000ff
+#define HWIO_WBM_R0_RELEASE_RING_STATUS_RELEASE_RING_NOT_IDLE_SHFT          0x0
+
+//// Register WBM_R0_MSDU_BUFFER_RING_STATUS ////
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x)                  (x+0x00000018)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x)                  (x+0x00000018)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK                     0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_BMSK 0x0000003f
+#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_MSDU_BUFFER_RING_NOT_IDLE_SHFT        0x0
+
+//// Register WBM_R0_LINK_DESC_RING_STATUS ////
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x)                    (x+0x0000001c)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x)                    (x+0x0000001c)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK                       0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_SHFT                                0
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_BMSK 0x0000007f
+#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_LINK_DESC_RING_NOT_IDLE_SHFT        0x0
+
+//// Register WBM_R0_MISC_RING_STATUS ////
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x)                         (x+0x00000020)
+#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x)                         (x+0x00000020)
+#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK                            0x000001ff
+#define HWIO_WBM_R0_MISC_RING_STATUS_SHFT                                     0
+#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x)                           \
+	in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask)                    \
+	in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val)                     \
+	out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK   0x00000100
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT          0x8
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK   0x00000080
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT          0x7
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK   0x00000040
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT          0x6
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK   0x00000020
+#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT          0x5
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK    0x00000010
+#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT           0x4
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT        0x3
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT        0x2
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT        0x1
+
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000001
+#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT        0x0
+
+//// Register WBM_R0_RELEASE_RING_FLUSH ////
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x)                       (x+0x00000024)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x)                       (x+0x00000024)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK                          0x00013fff
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SHFT                                   0
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) 
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val)
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT       0x10
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK    0x00002000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT           0xd
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x00001000
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT        0xc
+
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0x00000fff
+#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT        0x0
+
+//// Register WBM_R0_IDLE_STATUS ////
+
+#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x)                              (x+0x00000028)
+#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x)                              (x+0x00000028)
+#define HWIO_WBM_R0_IDLE_STATUS_RMSK                                 0x00007fff
+#define HWIO_WBM_R0_IDLE_STATUS_SHFT                                          0
+#define HWIO_WBM_R0_IDLE_STATUS_IN(x)                                \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK)
+#define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask)                         \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val)                          \
+	out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK                     0x00004000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT                            0xe
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK   0x00002000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT          0xd
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK      0x00001000
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT             0xc
+
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK      0x00000800
+#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT             0xb
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK    0x00000400
+#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT           0xa
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK    0x00000200
+#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT           0x9
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK    0x00000100
+#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT           0x8
+
+#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK    0x00000080
+#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT           0x7
+
+#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK     0x00000040
+#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT            0x6
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x00000020
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT        0x5
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000010
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT        0x4
+
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000008
+#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT        0x3
+
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000004
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT        0x2
+
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000002
+#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT        0x1
+
+#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK     0x00000001
+#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT            0x0
+
+//// Register WBM_R0_IDLE_SEQUENCE ////
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x)                            (x+0x0000002c)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x)                            (x+0x0000002c)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK                               0x0000003f
+#define HWIO_WBM_R0_IDLE_SEQUENCE_SHFT                                        0
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)                              \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask)                       \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) 
+#define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val)                        \
+	out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK    0x00000020
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT           0x5
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK                   0x00000010
+#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT                          0x4
+
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK           0x0000000f
+#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT                  0x0
+
+//// Register WBM_R0_MSDU_PARSER_CONTROL ////
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x)                      (x+0x00000030)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x)                      (x+0x00000030)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK                         0x00000007
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_SHFT                                  0
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK         0x00000004
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT                0x2
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK           0x00000002
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT                  0x1
+
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK           0x00000001
+#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT                  0x0
+
+//// Register WBM_R0_MSDU_PARSER_STATUS ////
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x)                       (x+0x00000034)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x)                       (x+0x00000034)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK                          0x0007ffff
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT                                   0
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x00078000
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT        0xf
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x00004000
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT        0xe
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_BMSK         0x00003c00
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_MAIN_STATE_SHFT                0xa
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_BMSK            0x000003e0
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_2_STATE_SHFT                   0x5
+
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK            0x0000001f
+#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT                   0x0
+
+//// Register WBM_R0_MISC_CONTROL ////
+
+#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x)                             (x+0x00000038)
+#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x)                             (x+0x00000038)
+#define HWIO_WBM_R0_MISC_CONTROL_RMSK                                0x0000ffff
+#define HWIO_WBM_R0_MISC_CONTROL_SHFT                                         0
+#define HWIO_WBM_R0_MISC_CONTROL_IN(x)                               \
+	in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK)
+#define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask)                        \
+	in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val)                         \
+	out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK                  0x0000fffc
+#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT                         0x2
+
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK          0x00000002
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT                 0x1
+
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK           0x00000001
+#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT                  0x0
+
+//// Register WBM_R0_WATCHDOG_TIMEOUT ////
+
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x)                         (x+0x0000003c)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x)                         (x+0x0000003c)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK                            0x00000fff
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_SHFT                                     0
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)                           \
+	in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask)                    \
+	in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) 
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val)                     \
+	out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val)
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK                      0x00000fff
+#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT                             0x0
+
+//// Register WBM_R0_INTERRUPT_DATA_CAPTURE ////
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x)                   (x+0x00000040)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x)                   (x+0x00000040)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK                      0x000001ff
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SHFT                               0
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) 
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val)
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_BMSK 0x000001ff
+#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_MSDU_PARSER_ERROR_1_DATA_SHFT        0x0
+
+//// Register WBM_R0_INVALID_APB_ACC_ADDR ////
+
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x)                     (x+0x00000044)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x)                     (x+0x00000044)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK                        0x0001ffff
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_SHFT                                 0
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val)
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK               0x0001ffff
+#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT                      0x0
+
+//// Register WBM_R0_IDLE_LIST_CONTROL ////
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x)                        (x+0x00000048)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x)                        (x+0x00000048)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK                           0x000007ff
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SHFT                                    0
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)                          \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val)                    \
+	out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK       0x000007fc
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT              0x2
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK  0x00000002
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT         0x1
+
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK     0x00000001
+#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT            0x0
+
+//// Register WBM_R0_IDLE_LIST_SIZE ////
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x)                           (x+0x0000004c)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x)                           (x+0x0000004c)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK                              0xffffffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SHFT                                       0
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) 
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val)
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT       0x10
+
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0x0000ffff
+#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_LSB ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x)              (x+0x00000050)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_PHYS(x)              (x+0x00000050)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_SHFT                          0
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_MSB ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x)              (x+0x00000054)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_PHYS(x)              (x+0x00000054)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_SHFT                          0
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x)        (x+0x00000058)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x)        (x+0x00000058)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK           0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_SHFT                    0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x)        (x+0x0000005c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x)        (x+0x0000005c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK           0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_SHFT                    0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x)          (x+0x00000060)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_PHYS(x)          (x+0x00000060)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK             0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_SHFT                      0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x)          (x+0x00000064)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_PHYS(x)          (x+0x00000064)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK             0x001fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_SHFT                      0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x)    (x+0x00000068)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x)    (x+0x00000068)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK       0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_SHFT                0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x)    (x+0x0000006c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x)    (x+0x0000006c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK       0x001fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_SHFT                0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x)          (x+0x00000070)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_PHYS(x)          (x+0x00000070)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK             0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_SHFT                      0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x)          (x+0x00000074)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_PHYS(x)          (x+0x00000074)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK             0x001fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_SHFT                      0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x)    (x+0x00000078)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x)    (x+0x00000078)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK       0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_SHFT                0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x)    (x+0x0000007c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x)    (x+0x0000007c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK       0x001fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_SHFT                0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT        0x8
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT        0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_HP ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x)                     (x+0x00000080)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_PHYS(x)                     (x+0x00000080)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK                        0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SHFT                                 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK          0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT                 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HP ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x)               (x+0x00000084)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x)               (x+0x00000084)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK                  0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SHFT                           0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK    0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT           0x0
+
+//// Register WBM_R0_SCATTERED_BUF_PTR_TP ////
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x)                     (x+0x00000088)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_PHYS(x)                     (x+0x00000088)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK                        0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SHFT                                 0
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK          0x000fffff
+#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT                 0x0
+
+//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TP ////
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x)               (x+0x0000008c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x)               (x+0x0000008c)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK                  0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SHFT                           0
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) 
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val)
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK    0x000fffff
+#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT           0x0
+
+//// Register WBM_R0_CLK_GATE_CTRL ////
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x)                            (x+0x00000090)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x)                            (x+0x00000090)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK                               0x0003ffff
+#define HWIO_WBM_R0_CLK_GATE_CTRL_SHFT                                        0
+#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)                              \
+	in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask)                       \
+	in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) 
+#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val)                        \
+	out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val)
+#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK                0x00020000
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT                      0x11
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK          0x00010000
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT                0x10
+
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK              0x0000ffff
+#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT                     0x0
+
+//// Register WBM_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x)                        (x+0x00000094)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_PHYS(x)                        (x+0x00000094)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK                           0xffffffff
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_SHFT                                    0
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)                          \
+	in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val)                    \
+	out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK                     0xffffffff
+#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT                            0x0
+
+//// Register WBM_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x)                        (x+0x00000098)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_PHYS(x)                        (x+0x00000098)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK                           0x000000ff
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_SHFT                                    0
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)                          \
+	in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val)                    \
+	out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK                     0x000000ff
+#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT                            0x0
+
+//// Register WBM_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x)                       (x+0x0000009c)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_PHYS(x)                       (x+0x0000009c)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK                          0x00000fff
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SHFT                                   0
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK         0x00000e00
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                0x9
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK         0x000001f0
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                0x4
+
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK         0x0000000f
+#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                0x0
+
+//// Register WBM_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000000a0)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000000a0)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register WBM_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x)                   (x+0x000000a4)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x)                   (x+0x000000a4)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK                      0x80000fff
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SHFT                               0
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK    0x80000000
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT          0x1f
+
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK   0x00000fff
+#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x)                         (x+0x000000a8)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_PHYS(x)                         (x+0x000000a8)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK                            0x01010101
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_SHFT                                     0
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)                           \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask)                    \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val)                     \
+	out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK        0x01000000
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT              0x18
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK         0x00010000
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT               0x10
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK         0x00000100
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                0x8
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK          0x00000001
+#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                 0x0
+
+//// Register WBM_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x)                        (x+0x000000ac)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_PHYS(x)                        (x+0x000000ac)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK                           0x003f3f3f
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_SHFT                                    0
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)                          \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask)                   \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val)                    \
+	out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK      0x003f0000
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT            0x10
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK           0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                  0x8
+
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK           0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                  0x0
+
+//// Register WBM_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                  (x+0x000000b0)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                  (x+0x000000b0)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_SHFT                              0
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register WBM_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x)                  (x+0x000000b4)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x)                  (x+0x000000b4)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_SHFT                              0
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register WBM_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x)                     (x+0x000000b8)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_PHYS(x)                     (x+0x000000b8)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK                        0x007fffff
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_SHFT                                 0
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK   0x00700000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT         0x14
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK    0x000e0000
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT          0x11
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1
+
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK        0x00000001
+#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT               0x0
+
+//// Register WBM_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x)                     (x+0x000000bc)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_PHYS(x)                     (x+0x000000bc)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK                        0xffff0001
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_SHFT                                 0
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK         0xffff0000
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT               0x10
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x)                      (x+0x000000c0)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_PHYS(x)                      (x+0x000000c0)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_SHFT                                  0
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK         0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                0x0
+
+//// Register WBM_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x)                    (x+0x000000c4)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x)                    (x+0x000000c4)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK                       0xffffffff
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_SHFT                                0
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK     0xffff0000
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT           0x10
+
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK    0x0000ffff
+#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT           0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x)                (x+0x000000c8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x)                (x+0x000000c8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x)                (x+0x000000cc)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x)                (x+0x000000cc)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x)                      (x+0x000000d0)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x)                      (x+0x000000d0)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x)                  (x+0x000000d4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x)                  (x+0x000000d4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x)                    (x+0x000000d8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x)                    (x+0x000000d8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x)             (x+0x000000e4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x)             (x+0x000000e4)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x)             (x+0x000000e8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x)             (x+0x000000e8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)  (x+0x000000f8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)  (x+0x000000f8)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK     0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT              0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)  (x+0x000000fc)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)  (x+0x000000fc)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK     0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT              0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)     (x+0x00000100)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)     (x+0x00000100)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)  (x+0x00000104)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)  (x+0x00000104)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT              0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000108)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000108)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK    0x00000007
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT             0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000010c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000010c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK   0x00ffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT            0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x0000011c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x0000011c)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x)                (x+0x00000120)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x)                (x+0x00000120)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x)                (x+0x00000124)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x)                (x+0x00000124)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x)                      (x+0x00000128)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x)                      (x+0x00000128)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x)                  (x+0x0000012c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x)                  (x+0x0000012c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x)                    (x+0x00000130)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x)                    (x+0x00000130)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x)             (x+0x0000013c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x)             (x+0x0000013c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x)             (x+0x00000140)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x)             (x+0x00000140)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)  (x+0x00000150)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)  (x+0x00000150)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK     0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT              0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)  (x+0x00000154)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)  (x+0x00000154)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK     0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT              0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)     (x+0x00000158)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)     (x+0x00000158)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)  (x+0x0000015c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)  (x+0x0000015c)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT              0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000160)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000160)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK    0x00000007
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT             0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000164)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000164)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK   0x00ffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT            0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000174)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000174)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x)                (x+0x00000178)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x)                (x+0x00000178)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x)                (x+0x0000017c)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x)                (x+0x0000017c)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x)                      (x+0x00000180)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x)                      (x+0x00000180)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x)                  (x+0x00000184)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x)                  (x+0x00000184)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x)                    (x+0x00000188)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x)                    (x+0x00000188)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x)             (x+0x00000194)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x)             (x+0x00000194)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x)             (x+0x00000198)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x)             (x+0x00000198)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)  (x+0x000001a8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)  (x+0x000001a8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK     0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT              0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)  (x+0x000001ac)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)  (x+0x000001ac)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK     0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT              0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)     (x+0x000001b0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)     (x+0x000001b0)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)  (x+0x000001b4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)  (x+0x000001b4)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT              0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001b8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001b8)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK    0x00000007
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT             0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001bc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001bc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK   0x00ffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT            0
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x000001cc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x000001cc)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x)                 (x+0x000001d0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x)                 (x+0x000001d0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_SHFT                             0
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x)                 (x+0x000001d4)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x)                 (x+0x000001d4)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_SHFT                             0
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x)                       (x+0x000001d8)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x)                       (x+0x000001d8)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK                          0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT                                   0
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x)                   (x+0x000001dc)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x)                   (x+0x000001dc)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_SHFT                               0
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x)                     (x+0x000001e0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x)                     (x+0x000001e0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK                        0x0000003f
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SHFT                                 0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)              (x+0x000001ec)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x)              (x+0x000001ec)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)              (x+0x000001f0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x)              (x+0x000001f0)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x00000200)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x00000200)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000204)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000204)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x00000208)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x00000208)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x0000020c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x0000020c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x00000210)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x00000210)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000214)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000214)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000218)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000218)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x0000021c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x0000021c)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x)                (x+0x00000220)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x)                (x+0x00000220)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_SHFT                            0
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000224)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000224)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x)                 (x+0x00000228)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x)                 (x+0x00000228)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_SHFT                             0
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x)                 (x+0x0000022c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x)                 (x+0x0000022c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_SHFT                             0
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x)                       (x+0x00000230)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x)                       (x+0x00000230)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK                          0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT                                   0
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x)                   (x+0x00000234)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x)                   (x+0x00000234)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_SHFT                               0
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x)                     (x+0x00000238)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x)                     (x+0x00000238)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK                        0x0000003f
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SHFT                                 0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x)              (x+0x00000244)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x)              (x+0x00000244)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x)              (x+0x00000248)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x)              (x+0x00000248)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x00000258)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x00000258)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x0000025c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x0000025c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x00000260)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x00000260)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000264)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000264)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x00000268)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x00000268)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000026c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000026c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000270)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000270)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000274)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000274)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x)                (x+0x00000278)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x)                (x+0x00000278)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_SHFT                            0
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x0000027c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x0000027c)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x)             (x+0x00000280)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x)             (x+0x00000280)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x)             (x+0x00000284)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x)             (x+0x00000284)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x)                   (x+0x00000288)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x)                   (x+0x00000288)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x)               (x+0x0000028c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x)               (x+0x0000028c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x)                 (x+0x00000290)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x)                 (x+0x00000290)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x)          (x+0x0000029c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x)          (x+0x0000029c)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x)          (x+0x000002a0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x)          (x+0x000002a0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000002b0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000002b0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK  0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT           0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000002b4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000002b4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT           0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)  (x+0x000002b8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)  (x+0x000002b8)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002bc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002bc)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT           0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000002c0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000002c0)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000002c4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000002c4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x000002d4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x000002d4)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x)             (x+0x000002d8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_PHYS(x)             (x+0x000002d8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x)             (x+0x000002dc)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_PHYS(x)             (x+0x000002dc)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x)                   (x+0x000002e0)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_PHYS(x)                   (x+0x000002e0)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x)               (x+0x000002e4)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_PHYS(x)               (x+0x000002e4)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x)                 (x+0x000002e8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_PHYS(x)                 (x+0x000002e8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x)          (x+0x000002f4)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_PHYS(x)          (x+0x000002f4)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x)          (x+0x000002f8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_PHYS(x)          (x+0x000002f8)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000308)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000308)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK  0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT           0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000030c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000030c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT           0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)  (x+0x00000310)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)  (x+0x00000310)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000314)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000314)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT           0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000318)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000318)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000031c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000031c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x0000032c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x0000032c)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x)             (x+0x00000330)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_PHYS(x)             (x+0x00000330)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x)             (x+0x00000334)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_PHYS(x)             (x+0x00000334)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x)                   (x+0x00000338)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_PHYS(x)                   (x+0x00000338)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x)               (x+0x0000033c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_PHYS(x)               (x+0x0000033c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x)                 (x+0x00000340)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_PHYS(x)                 (x+0x00000340)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x)          (x+0x0000034c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_PHYS(x)          (x+0x0000034c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x)          (x+0x00000350)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_PHYS(x)          (x+0x00000350)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000360)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000360)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK  0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT           0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000364)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000364)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT           0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x)  (x+0x00000368)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x)  (x+0x00000368)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000036c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000036c)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT           0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000370)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000370)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000374)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000374)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x00000384)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x00000384)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_RXDMA2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x)                (x+0x00000388)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_PHYS(x)                (x+0x00000388)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x)                (x+0x0000038c)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_PHYS(x)                (x+0x0000038c)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x)                      (x+0x00000390)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_PHYS(x)                      (x+0x00000390)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x)                  (x+0x00000394)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_PHYS(x)                  (x+0x00000394)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x)                    (x+0x00000398)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_PHYS(x)                    (x+0x00000398)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x)             (x+0x0000039c)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_PHYS(x)             (x+0x0000039c)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x)             (x+0x000003a0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_PHYS(x)             (x+0x000003a0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x000003ac)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x000003ac)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x000003b0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x000003b0)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x000003b4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x000003b4)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x000003dc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x000003dc)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x)                 (x+0x000003e0)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_PHYS(x)                 (x+0x000003e0)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_SHFT                             0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x)                 (x+0x000003e4)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_PHYS(x)                 (x+0x000003e4)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_SHFT                             0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x)                       (x+0x000003e8)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_PHYS(x)                       (x+0x000003e8)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK                          0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_SHFT                                   0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x)                   (x+0x000003ec)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_PHYS(x)                   (x+0x000003ec)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_SHFT                               0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x)                     (x+0x000003f0)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_PHYS(x)                     (x+0x000003f0)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK                        0x0000003f
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SHFT                                 0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x)              (x+0x000003f4)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_PHYS(x)              (x+0x000003f4)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x)              (x+0x000003f8)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_PHYS(x)              (x+0x000003f8)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)       (x+0x00000404)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)       (x+0x00000404)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)      (x+0x00000408)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)      (x+0x00000408)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_SHFT                  0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x)    (x+0x0000040c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x)    (x+0x0000040c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK       0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT                0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000428)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000428)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x0000042c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x0000042c)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x)                (x+0x00000430)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_PHYS(x)                (x+0x00000430)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000434)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000434)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x)                 (x+0x00000438)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_PHYS(x)                 (x+0x00000438)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_SHFT                             0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x)                 (x+0x0000043c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_PHYS(x)                 (x+0x0000043c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_SHFT                             0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x)                       (x+0x00000440)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_PHYS(x)                       (x+0x00000440)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK                          0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_SHFT                                   0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x)                   (x+0x00000444)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_PHYS(x)                   (x+0x00000444)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_SHFT                               0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x)                     (x+0x00000448)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_PHYS(x)                     (x+0x00000448)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK                        0x0000003f
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SHFT                                 0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x)              (x+0x0000044c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_PHYS(x)              (x+0x0000044c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_SHFT                          0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x)              (x+0x00000450)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_PHYS(x)              (x+0x00000450)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_SHFT                          0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)       (x+0x0000045c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)       (x+0x0000045c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SHFT                   0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)      (x+0x00000460)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)      (x+0x00000460)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_SHFT                  0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x)    (x+0x00000464)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x)    (x+0x00000464)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK       0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT                0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000480)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000480)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000484)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000484)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x)                (x+0x00000488)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_PHYS(x)                (x+0x00000488)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_SHFT                            0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x0000048c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x0000048c)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x)             (x+0x00000490)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_PHYS(x)             (x+0x00000490)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x)             (x+0x00000494)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_PHYS(x)             (x+0x00000494)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x)                   (x+0x00000498)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_PHYS(x)                   (x+0x00000498)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x)               (x+0x0000049c)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_PHYS(x)               (x+0x0000049c)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x)                 (x+0x000004a0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_PHYS(x)                 (x+0x000004a0)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x)          (x+0x000004a4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_PHYS(x)          (x+0x000004a4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x)          (x+0x000004a8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_PHYS(x)          (x+0x000004a8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)   (x+0x000004b4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)   (x+0x000004b4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SHFT               0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)  (x+0x000004b8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)  (x+0x000004b8)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004bc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004bc)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT            0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x000004e4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x000004e4)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x)             (x+0x000004e8)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_PHYS(x)             (x+0x000004e8)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x)             (x+0x000004ec)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_PHYS(x)             (x+0x000004ec)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x)                   (x+0x000004f0)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_PHYS(x)                   (x+0x000004f0)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x)               (x+0x000004f4)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_PHYS(x)               (x+0x000004f4)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x)                 (x+0x000004f8)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_PHYS(x)                 (x+0x000004f8)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x)          (x+0x000004fc)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_PHYS(x)          (x+0x000004fc)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x)          (x+0x00000500)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_PHYS(x)          (x+0x00000500)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)   (x+0x0000050c)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)   (x+0x0000050c)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SHFT               0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)  (x+0x00000510)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)  (x+0x00000510)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000514)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000514)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_SHFT            0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x0000053c)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x0000053c)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x)             (x+0x00000540)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_PHYS(x)             (x+0x00000540)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x)             (x+0x00000544)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_PHYS(x)             (x+0x00000544)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x)                   (x+0x00000548)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_PHYS(x)                   (x+0x00000548)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x)               (x+0x0000054c)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_PHYS(x)               (x+0x0000054c)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x)                 (x+0x00000550)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_PHYS(x)                 (x+0x00000550)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x)          (x+0x00000554)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_PHYS(x)          (x+0x00000554)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x)          (x+0x00000558)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_PHYS(x)          (x+0x00000558)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)   (x+0x00000564)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)   (x+0x00000564)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SHFT               0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)  (x+0x00000568)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)  (x+0x00000568)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000056c)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000056c)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_SHFT            0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x00000594)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x00000594)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x)               (x+0x00000598)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x)               (x+0x00000598)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_SHFT                           0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x)               (x+0x0000059c)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x)               (x+0x0000059c)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK                  0x00ffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_SHFT                           0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK        0x00ffff00
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT               0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x)                     (x+0x000005a0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x)                     (x+0x000005a0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK                        0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_SHFT                                 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK                0x0000ff00
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT                       0x8
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT                    0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x)                 (x+0x000005a4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x)                 (x+0x000005a4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK                    0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_SHFT                             0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK    0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT          0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT           0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x)                   (x+0x000005a8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x)                   (x+0x000005a8)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK                      0x0000003f
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SHFT                               0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK    0x00000020
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT           0x5
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK     0x00000010
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT            0x4
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK         0x00000008
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                0x3
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK         0x00000004
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT                0x2
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK      0x00000002
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT             0x1
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK      0x00000001
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT             0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x)            (x+0x000005ac)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x)            (x+0x000005ac)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x)            (x+0x000005b0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x)            (x+0x000005b0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK               0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)     (x+0x000005bc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)     (x+0x000005bc)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SHFT                 0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)    (x+0x000005c0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x)    (x+0x000005c0)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK       0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_SHFT                0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)  (x+0x000005c4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x)  (x+0x000005c4)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT              0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)        (x+0x000005ec)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)        (x+0x000005ec)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK           0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT                    0
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x)               (x+0x000005f0)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x)               (x+0x000005f0)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT                           0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x)               (x+0x000005f4)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x)               (x+0x000005f4)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK                  0x00ffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT                           0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK        0x00ffff00
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT               0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x)                     (x+0x000005f8)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x)                     (x+0x000005f8)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK                        0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_SHFT                                 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK                0x0000ff00
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT                       0x8
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT                    0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x)                 (x+0x000005fc)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x)                 (x+0x000005fc)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK                    0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_SHFT                             0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK    0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT          0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT           0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x)                   (x+0x00000600)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x)                   (x+0x00000600)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK                      0x0000003f
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SHFT                               0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK    0x00000020
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT           0x5
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK     0x00000010
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT            0x4
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK         0x00000008
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                0x3
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK         0x00000004
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT                0x2
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK      0x00000002
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT             0x1
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK      0x00000001
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT             0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x)            (x+0x00000604)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x)            (x+0x00000604)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x)            (x+0x00000608)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x)            (x+0x00000608)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK               0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)     (x+0x00000614)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)     (x+0x00000614)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SHFT                 0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)    (x+0x00000618)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x)    (x+0x00000618)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK       0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_SHFT                0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)  (x+0x0000061c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x)  (x+0x0000061c)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT              0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)        (x+0x00000644)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)        (x+0x00000644)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK           0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT                    0
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x)                (x+0x00000648)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x)                (x+0x00000648)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x)                (x+0x0000064c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x)                (x+0x0000064c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x)                      (x+0x00000650)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x)                      (x+0x00000650)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x)                  (x+0x00000654)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x)                  (x+0x00000654)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x)                    (x+0x00000658)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x)                    (x+0x00000658)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x)             (x+0x0000065c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x)             (x+0x0000065c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x)             (x+0x00000660)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x)             (x+0x00000660)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x0000066c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x0000066c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x00000670)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x00000670)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000674)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000674)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x00000690)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x00000690)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x00000694)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x00000694)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x)               (x+0x00000698)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x)               (x+0x00000698)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_SHFT                           0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x0000069c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x0000069c)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x)                (x+0x000006a0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x)                (x+0x000006a0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x)                (x+0x000006a4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x)                (x+0x000006a4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_SHFT                            0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x)                      (x+0x000006a8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x)                      (x+0x000006a8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK                         0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_SHFT                                  0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x)                  (x+0x000006ac)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x)                  (x+0x000006ac)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_SHFT                              0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x)                    (x+0x000006b0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x)                    (x+0x000006b0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK                       0x0000003f
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SHFT                                0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x)             (x+0x000006b4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x)             (x+0x000006b4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x)             (x+0x000006b8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x)             (x+0x000006b8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x000006c4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x000006c4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x000006c8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x000006c8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x000006cc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x000006cc)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x000006e8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x000006e8)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x000006ec)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x000006ec)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x)               (x+0x000006f0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x)               (x+0x000006f0)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_SHFT                           0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x000006f4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x000006f4)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x)            (x+0x000006f8)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x)            (x+0x000006f8)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x)            (x+0x000006fc)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x)            (x+0x000006fc)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x)                  (x+0x00000700)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x)                  (x+0x00000700)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x)              (x+0x00000704)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x)              (x+0x00000704)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x)                (x+0x00000708)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x)                (x+0x00000708)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x)         (x+0x0000070c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x)         (x+0x0000070c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x)         (x+0x00000710)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x)         (x+0x00000710)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x0000071c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x0000071c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000720)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000720)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000724)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000724)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x0000074c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x0000074c)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x)            (x+0x00000750)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_PHYS(x)            (x+0x00000750)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x)            (x+0x00000754)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_PHYS(x)            (x+0x00000754)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x)                  (x+0x00000758)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_PHYS(x)                  (x+0x00000758)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x)              (x+0x0000075c)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_PHYS(x)              (x+0x0000075c)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x)                (x+0x00000760)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_PHYS(x)                (x+0x00000760)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x)         (x+0x00000764)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_PHYS(x)         (x+0x00000764)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x)         (x+0x00000768)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_PHYS(x)         (x+0x00000768)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x00000774)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x00000774)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000778)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000778)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000077c)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000077c)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x000007a4)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x000007a4)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA1_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x)            (x+0x000007a8)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_PHYS(x)            (x+0x000007a8)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x)            (x+0x000007ac)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_PHYS(x)            (x+0x000007ac)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x)                  (x+0x000007b0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_PHYS(x)                  (x+0x000007b0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x)              (x+0x000007b4)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_PHYS(x)              (x+0x000007b4)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x)                (x+0x000007b8)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_PHYS(x)                (x+0x000007b8)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x)         (x+0x000007bc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_PHYS(x)         (x+0x000007bc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x)         (x+0x000007c0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_PHYS(x)         (x+0x000007c0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x000007cc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x000007cc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000007d0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000007d0)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000007d4)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000007d4)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x000007fc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x000007fc)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2RXDMA2_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x)               (x+0x00000800)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_PHYS(x)               (x+0x00000800)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_SHFT                           0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x)               (x+0x00000804)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_PHYS(x)               (x+0x00000804)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK                  0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_SHFT                           0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK        0x00ffff00
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT               0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_ID ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x)                     (x+0x00000808)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_PHYS(x)                     (x+0x00000808)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK                        0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_SHFT                                 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK                0x0000ff00
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT                       0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_BMSK             0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_SHFT                    0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x)                 (x+0x0000080c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_PHYS(x)                 (x+0x0000080c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK                    0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_SHFT                             0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK    0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT          0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT           0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x)                   (x+0x00000810)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_PHYS(x)                   (x+0x00000810)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK                      0x0000003f
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SHFT                               0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK    0x00000020
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT           0x5
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK     0x00000010
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT            0x4
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK         0x00000008
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT                0x3
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_BMSK         0x00000004
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_SHFT                0x2
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK      0x00000002
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT             0x1
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_BMSK      0x00000001
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_SHFT             0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x)            (x+0x00000814)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_PHYS(x)            (x+0x00000814)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x)            (x+0x00000818)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_PHYS(x)            (x+0x00000818)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK               0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x)            (x+0x0000081c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_PHYS(x)            (x+0x0000081c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x)            (x+0x00000820)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_PHYS(x)            (x+0x00000820)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK               0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x)     (x+0x00000824)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x)     (x+0x00000824)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SHFT                 0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x)    (x+0x00000828)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x)    (x+0x00000828)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK       0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_SHFT                0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x)  (x+0x0000082c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x)  (x+0x0000082c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK     0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT              0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000830)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000830)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SHFT             0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000834)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000834)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_SHFT             0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x)    (x+0x00000838)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_PHYS(x)    (x+0x00000838)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK       0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_SHFT                0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000083c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000083c)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT             0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000840)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000840)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK   0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_SHFT            0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000844)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000844)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK  0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_SHFT           0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x)        (x+0x00000854)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x)        (x+0x00000854)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK           0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT                    0
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x)              (x+0x00000858)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x)              (x+0x00000858)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_SHFT                          0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x)              (x+0x0000085c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x)              (x+0x0000085c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK                 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_SHFT                          0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK       0x00ffff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT              0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_ID ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x)                    (x+0x00000860)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x)                    (x+0x00000860)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK                       0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_SHFT                                0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val)                \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK               0x0000ff00
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT                      0x8
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK            0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT                   0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x)                (x+0x00000864)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x)                (x+0x00000864)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK                   0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_SHFT                            0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK   0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT         0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT          0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x)                  (x+0x00000868)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x)                  (x+0x00000868)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK                     0x0000003f
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SHFT                              0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK   0x00000020
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT          0x5
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK    0x00000010
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT           0x4
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK        0x00000008
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT               0x3
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK        0x00000004
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT               0x2
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK     0x00000002
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT            0x1
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK     0x00000001
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT            0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x)           (x+0x0000086c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x)           (x+0x0000086c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_SHFT                       0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x)           (x+0x00000870)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x)           (x+0x00000870)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK              0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_SHFT                       0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x)           (x+0x00000874)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x)           (x+0x00000874)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_SHFT                       0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x)           (x+0x00000878)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x)           (x+0x00000878)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK              0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_SHFT                       0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x)    (x+0x0000087c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x)    (x+0x0000087c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK       0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SHFT                0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x)   (x+0x00000880)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x)   (x+0x00000880)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_SHFT               0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000884)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000884)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK    0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT             0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000888)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000888)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK   0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT            0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000088c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000088c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT            0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x)   (x+0x00000890)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x)   (x+0x00000890)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_SHFT               0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000894)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000894)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT            0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000898)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000898)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK  0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT           0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000089c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000089c)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x)       (x+0x000008ac)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x)       (x+0x000008ac)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT                   0
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x)             (x+0x000008b0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x)             (x+0x000008b0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK                0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x)             (x+0x000008b4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x)             (x+0x000008b4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK                0x00ffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_SHFT                         0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)               \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val)         \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK      0x00ffff00
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT             0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x)                   (x+0x000008b8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x)                   (x+0x000008b8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK                      0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_SHFT                               0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val)               \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK              0x0000ff00
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT                     0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK           0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT                  0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x)               (x+0x000008bc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x)               (x+0x000008bc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK                  0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_SHFT                           0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)                 \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val)           \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK  0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT        0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT         0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x)                 (x+0x000008c0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x)                 (x+0x000008c0)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK                    0x0000003f
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SHFT                             0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)                   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val)             \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK  0x00000020
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT         0x5
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK   0x00000010
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT          0x4
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK       0x00000008
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT              0x3
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK       0x00000004
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT              0x2
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK    0x00000002
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT           0x1
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK    0x00000001
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT           0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x)          (x+0x000008c4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x)          (x+0x000008c4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK             0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x)          (x+0x000008c8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x)          (x+0x000008c8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK             0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_SHFT                      0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)            \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)      \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)   (x+0x000008d4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)   (x+0x000008d4)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK      0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SHFT               0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)     \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x)  (x+0x000008d8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x)  (x+0x000008d8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_SHFT              0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008dc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008dc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK   0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT            0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)        (x+0x000008f8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)        (x+0x000008f8)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK           0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_SHFT                    0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK      0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT             0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)        (x+0x000008fc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)        (x+0x000008fc)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK           0x000001ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_SHFT                    0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)          \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)    \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK      0x000000ff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT             0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x)            (x+0x00000900)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x)            (x+0x00000900)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_SHFT                        0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT                0x0
+
+//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)      (x+0x00000904)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)      (x+0x00000904)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK         0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                  0
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)        \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val)  \
+	out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x)            (x+0x00000908)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x)            (x+0x00000908)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x)            (x+0x0000090c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x)            (x+0x0000090c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x)                  (x+0x00000910)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x)                  (x+0x00000910)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x)              (x+0x00000914)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x)              (x+0x00000914)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x)                (x+0x00000918)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x)                (x+0x00000918)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x)         (x+0x0000091c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x)         (x+0x0000091c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x)         (x+0x00000920)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x)         (x+0x00000920)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x0000092c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x0000092c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000930)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000930)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000934)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000934)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)       (x+0x00000950)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)       (x+0x00000950)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)       (x+0x00000954)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)       (x+0x00000954)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK          0x000001ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK     0x000000ff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x)           (x+0x00000958)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x)           (x+0x00000958)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT               0x0
+
+//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x0000095c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x0000095c)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x)            (x+0x00000960)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x)            (x+0x00000960)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x)            (x+0x00000964)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x)            (x+0x00000964)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x)                  (x+0x00000968)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x)                  (x+0x00000968)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x)              (x+0x0000096c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x)              (x+0x0000096c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x)                (x+0x00000970)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x)                (x+0x00000970)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x)         (x+0x00000974)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x)         (x+0x00000974)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x)         (x+0x00000978)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x)         (x+0x00000978)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x00000984)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x00000984)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000988)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000988)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000098c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000098c)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)       (x+0x000009a8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)       (x+0x000009a8)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)       (x+0x000009ac)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)       (x+0x000009ac)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK          0x000001ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK     0x000000ff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x)           (x+0x000009b0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x)           (x+0x000009b0)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT               0x0
+
+//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x000009b4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x000009b4)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x)            (x+0x000009b8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x)            (x+0x000009b8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x)            (x+0x000009bc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x)            (x+0x000009bc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x)                  (x+0x000009c0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x)                  (x+0x000009c0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x)              (x+0x000009c4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x)              (x+0x000009c4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x)                (x+0x000009c8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x)                (x+0x000009c8)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x)         (x+0x000009cc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x)         (x+0x000009cc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x)         (x+0x000009d0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x)         (x+0x000009d0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x000009dc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x000009dc)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009e0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009e0)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009e4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009e4)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)       (x+0x00000a00)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)       (x+0x00000a00)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)       (x+0x00000a04)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)       (x+0x00000a04)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK          0x000001ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK     0x000000ff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x)           (x+0x00000a08)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x)           (x+0x00000a08)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT               0x0
+
+//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x00000a0c)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x00000a0c)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x)            (x+0x00000a10)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x)            (x+0x00000a10)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK               0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x)            (x+0x00000a14)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x)            (x+0x00000a14)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK               0x00ffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_SHFT                        0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK     0x00ffff00
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT            0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_ID ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x)                  (x+0x00000a18)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x)                  (x+0x00000a18)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK                     0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_SHFT                              0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val)              \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK             0x0000ff00
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT                    0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK          0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT                 0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x)              (x+0x00000a1c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x)              (x+0x00000a1c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK                 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_SHFT                          0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)                \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val)          \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MISC ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x)                (x+0x00000a20)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x)                (x+0x00000a20)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK                   0x0000003f
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SHFT                            0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val)            \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK  0x00000010
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT         0x4
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK      0x00000008
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT             0x3
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK      0x00000004
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT             0x2
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK   0x00000002
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT          0x1
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK   0x00000001
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT          0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x)         (x+0x00000a24)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x)         (x+0x00000a24)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK            0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x)         (x+0x00000a28)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x)         (x+0x00000a28)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK            0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_SHFT                     0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)           \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val)     \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x)  (x+0x00000a34)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x)  (x+0x00000a34)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SHFT              0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)    \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000a38)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000a38)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK    0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_SHFT             0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a3c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a3c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK  0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT           0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x)       (x+0x00000a58)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x)       (x+0x00000a58)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK          0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK     0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x)       (x+0x00000a5c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x)       (x+0x00000a5c)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK          0x000001ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_SHFT                   0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)         \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val)   \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK     0x000000ff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT            0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x)           (x+0x00000a60)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x)           (x+0x00000a60)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK              0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_SHFT                       0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)             \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask)      \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val)       \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT               0x0
+
+//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x)     (x+0x00000a64)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x)     (x+0x00000a64)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK        0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT                 0
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)       \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WBM_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00002000)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00002000)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_SHFT                                    0
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)                          \
+	in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask)                   \
+	in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val)                    \
+	out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK    0x00000001
+#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT           0x0
+
+//// Register WBM_R1_TESTBUS_CTRL ////
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x)                             (x+0x00002004)
+#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x)                             (x+0x00002004)
+#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK                                0x00001f3f
+#define HWIO_WBM_R1_TESTBUS_CTRL_SHFT                                         0
+#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x)                               \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask)                        \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) 
+#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val)                         \
+	out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK                     0x00001f00
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT                            0x8
+
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK                     0x0000003f
+#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT                            0x0
+
+//// Register WBM_R1_TESTBUS_LOWER ////
+
+#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x)                            (x+0x00002008)
+#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x)                            (x+0x00002008)
+#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK                               0xffffffff
+#define HWIO_WBM_R1_TESTBUS_LOWER_SHFT                                        0
+#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x)                              \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK)
+#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask)                       \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val)                        \
+	out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK                         0xffffffff
+#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT                                0x0
+
+//// Register WBM_R1_TESTBUS_HIGHER ////
+
+#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x)                           (x+0x0000200c)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x)                           (x+0x0000200c)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK                              0x000000ff
+#define HWIO_WBM_R1_TESTBUS_HIGHER_SHFT                                       0
+#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) 
+#define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val)
+#define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK                        0x000000ff
+#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT                               0x0
+
+//// Register WBM_R1_SM_STATES_IX_0 ////
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00002010)
+#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00002010)
+#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK                              0x7fffffff
+#define HWIO_WBM_R1_SM_STATES_IX_0_SHFT                                       0
+#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK           0x60000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT                 0x1d
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK           0x18000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT                 0x1b
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK           0x06000000
+#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT                 0x19
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK            0x01800000
+#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT                  0x17
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK            0x00600000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT                  0x15
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK            0x00180000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT                  0x13
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK          0x00060000
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT                0x11
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK          0x00018000
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT                 0xf
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK  0x00007000
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT         0xc
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK  0x00000c00
+#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT         0xa
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x00000380
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT        0x7
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x00000060
+#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT        0x5
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK        0x0000001c
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT               0x2
+
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK        0x00000003
+#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT               0x0
+
+//// Register WBM_R1_SM_STATES_IX_1 ////
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00002014)
+#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00002014)
+#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK                              0x0000ffff
+#define HWIO_WBM_R1_SM_STATES_IX_1_SHFT                                       0
+#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) 
+#define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK  0x0000e000
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT         0xd
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK  0x00001c00
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT         0xa
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK   0x00000380
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT          0x7
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK   0x00000070
+#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT          0x4
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK          0x0000000c
+#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT                 0x2
+
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK           0x00000003
+#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT                  0x0
+
+//// Register WBM_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x)                           (x+0x00002018)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x)                           (x+0x00002018)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK                              0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_0_SHFT                                       0
+#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) 
+#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK                         0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT                                0x0
+
+//// Register WBM_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x)                           (x+0x0000201c)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x)                           (x+0x0000201c)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK                              0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_1_SHFT                                       0
+#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) 
+#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK                         0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT                                0x0
+
+//// Register WBM_R1_EVENTMASK_IX_2 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x)                           (x+0x00002020)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x)                           (x+0x00002020)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK                              0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_2_SHFT                                       0
+#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) 
+#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK                         0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT                                0x0
+
+//// Register WBM_R1_EVENTMASK_IX_3 ////
+
+#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x)                           (x+0x00002024)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x)                           (x+0x00002024)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK                              0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_3_SHFT                                       0
+#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)                             \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask)                      \
+	in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) 
+#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val)                       \
+	out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK                         0xffffffff
+#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT                                0x0
+
+//// Register WBM_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)                (x+0x00002028)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x)                (x+0x00002028)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK                   0xffffffff
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT                            0
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)                  \
+	in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask)           \
+	in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val)            \
+	out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT       0x11
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT        0x2
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT        0x1
+
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT        0x0
+
+//// Register WBM_R2_PPE_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x)                      (x+0x00003000)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x)                      (x+0x00003000)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_PPE_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x)                      (x+0x00003004)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x)                      (x+0x00003004)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_TQM_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x)                      (x+0x00003008)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x)                      (x+0x00003008)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_TQM_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x)                      (x+0x0000300c)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x)                      (x+0x0000300c)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_REO_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x)                      (x+0x00003010)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x)                      (x+0x00003010)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_REO_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x)                      (x+0x00003014)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x)                      (x+0x00003014)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_SW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x)                       (x+0x00003018)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x)                       (x+0x00003018)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_SHFT                                   0
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register WBM_R2_SW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x)                       (x+0x0000301c)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x)                       (x+0x0000301c)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_SHFT                                   0
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register WBM_R2_FW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x)                       (x+0x00003020)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x)                       (x+0x00003020)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_SHFT                                   0
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register WBM_R2_FW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x)                       (x+0x00003024)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x)                       (x+0x00003024)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_SHFT                                   0
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register WBM_R2_RXDMA0_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x)                   (x+0x00003028)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x)                   (x+0x00003028)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_RXDMA0_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x)                   (x+0x0000302c)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x)                   (x+0x0000302c)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_RXDMA1_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x)                   (x+0x00003030)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_PHYS(x)                   (x+0x00003030)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_RXDMA1_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x)                   (x+0x00003034)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_PHYS(x)                   (x+0x00003034)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA1_RELEASE_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_RXDMA2_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x)                   (x+0x00003038)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_PHYS(x)                   (x+0x00003038)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_RXDMA2_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x)                   (x+0x0000303c)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_PHYS(x)                   (x+0x0000303c)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_RXDMA2_RELEASE_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2PPE_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x)                      (x+0x00003040)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_PHYS(x)                      (x+0x00003040)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2PPE_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x)                      (x+0x00003044)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_PHYS(x)                      (x+0x00003044)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2SW_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x)                       (x+0x00003048)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_PHYS(x)                       (x+0x00003048)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_SHFT                                   0
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register WBM_R2_WBM2SW_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x)                       (x+0x0000304c)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_PHYS(x)                       (x+0x0000304c)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_SHFT                                   0
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register WBM_R2_WBM2FW_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x)                       (x+0x00003050)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_PHYS(x)                       (x+0x00003050)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_SHFT                                   0
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register WBM_R2_WBM2FW_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x)                       (x+0x00003054)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_PHYS(x)                       (x+0x00003054)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK                          0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_SHFT                                   0
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register WBM_R2_WBM2RXDMA0_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x)                   (x+0x00003058)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_PHYS(x)                   (x+0x00003058)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2RXDMA0_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x)                   (x+0x0000305c)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_PHYS(x)                   (x+0x0000305c)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2RXDMA1_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x)                   (x+0x00003060)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_PHYS(x)                   (x+0x00003060)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2RXDMA1_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x)                   (x+0x00003064)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_PHYS(x)                   (x+0x00003064)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_BUF_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2RXDMA2_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x)                   (x+0x00003068)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_PHYS(x)                   (x+0x00003068)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2RXDMA2_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x)                   (x+0x0000306c)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_PHYS(x)                   (x+0x0000306c)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_BUF_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2TQM_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x)                     (x+0x00003070)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x)                     (x+0x00003070)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_SHFT                                 0
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM2TQM_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x)                     (x+0x00003074)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x)                     (x+0x00003074)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_SHFT                                 0
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM2REO_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x)                     (x+0x00003078)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x)                     (x+0x00003078)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_SHFT                                 0
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM2REO_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x)                     (x+0x0000307c)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x)                     (x+0x0000307c)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_SHFT                                 0
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM2SW_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x)                      (x+0x00003080)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x)                      (x+0x00003080)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2SW_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x)                      (x+0x00003084)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x)                      (x+0x00003084)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2FW_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x)                      (x+0x00003088)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x)                      (x+0x00003088)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2FW_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x)                      (x+0x0000308c)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x)                      (x+0x0000308c)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK                         0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_SHFT                                  0
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register WBM_R2_WBM2RXDMA0_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x)                  (x+0x00003090)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x)                  (x+0x00003090)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2RXDMA0_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x)                  (x+0x00003094)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x)                  (x+0x00003094)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2RXDMA1_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x)                  (x+0x00003098)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_PHYS(x)                  (x+0x00003098)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2RXDMA1_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x)                  (x+0x0000309c)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_PHYS(x)                  (x+0x0000309c)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA1_LINK_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2RXDMA2_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x)                  (x+0x000030a0)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_PHYS(x)                  (x+0x000030a0)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2RXDMA2_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x)                  (x+0x000030a4)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_PHYS(x)                  (x+0x000030a4)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2RXDMA2_LINK_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM_IDLE_BUF_RING_HP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x)                     (x+0x000030a8)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_PHYS(x)                     (x+0x000030a8)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_SHFT                                 0
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM_IDLE_BUF_RING_TP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x)                     (x+0x000030ac)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_PHYS(x)                     (x+0x000030ac)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK                        0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_SHFT                                 0
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)                       \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask)                \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val)                 \
+	out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK               0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT                      0x0
+
+//// Register WBM_R2_WBM_IDLE_LINK_RING_HP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x)                    (x+0x000030b0)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x)                    (x+0x000030b0)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK                       0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_SHFT                                0
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val)                \
+	out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK              0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT                     0x0
+
+//// Register WBM_R2_WBM_IDLE_LINK_RING_TP ////
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x)                    (x+0x000030b4)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x)                    (x+0x000030b4)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK                       0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_SHFT                                0
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)                      \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask)               \
+	in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val)                \
+	out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK              0x0000ffff
+#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT                     0x0
+
+//// Register WBM_R2_WBM2FW_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x)                   (x+0x000030b8)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x)                   (x+0x000030b8)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_SHFT                               0
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2FW_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x)                   (x+0x000030bc)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x)                   (x+0x000030bc)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK                      0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_SHFT                               0
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)                     \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask)              \
+	in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val)               \
+	out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK             0x0000ffff
+#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT                    0x0
+
+//// Register WBM_R2_WBM2SW0_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x)                  (x+0x000030c0)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x)                  (x+0x000030c0)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW0_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x)                  (x+0x000030c4)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x)                  (x+0x000030c4)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW1_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x)                  (x+0x000030c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x)                  (x+0x000030c8)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW1_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x)                  (x+0x000030cc)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x)                  (x+0x000030cc)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW2_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x)                  (x+0x000030d0)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x)                  (x+0x000030d0)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW2_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x)                  (x+0x000030d4)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x)                  (x+0x000030d4)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW3_RELEASE_RING_HP ////
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x)                  (x+0x000030d8)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x)                  (x+0x000030d8)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT                   0x0
+
+//// Register WBM_R2_WBM2SW3_RELEASE_RING_TP ////
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x)                  (x+0x000030dc)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x)                  (x+0x000030dc)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK                     0x0000ffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_SHFT                              0
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)                    \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask)             \
+	in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) 
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val)              \
+	out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val)
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK            0x0000ffff
+#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT                   0x0
+
+
+#endif
+

hw/qca6290/v1/wbm_release_ring.h

@@ -0,0 +1,1418 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _WBM_RELEASE_RING_H_
+#define _WBM_RELEASE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "tx_rate_stats_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info released_buff_or_desc_addr_info;
+//	2	release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[15:13], rxdma_push_reason[17:16], rxdma_error_code[22:18], reo_push_reason[24:23], reo_error_code[29:25], wbm_internal_error[30], reserved_2[31]
+//	3	tqm_status_number[23:0], transmit_count[30:24], reserved_3a[31]
+//	4	ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13]
+//	5-6	struct tx_rate_stats_info tx_rate_stats;
+//	7	sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_WBM_RELEASE_RING 8
+
+struct wbm_release_ring {
+    struct            buffer_addr_info                       released_buff_or_desc_addr_info;
+             uint32_t release_source_module           :  3, //[2:0]
+                      bm_action                       :  3, //[5:3]
+                      buffer_or_desc_type             :  3, //[8:6]
+                      first_msdu_index                :  4, //[12:9]
+                      tqm_release_reason              :  3, //[15:13]
+                      rxdma_push_reason               :  2, //[17:16]
+                      rxdma_error_code                :  5, //[22:18]
+                      reo_push_reason                 :  2, //[24:23]
+                      reo_error_code                  :  5, //[29:25]
+                      wbm_internal_error              :  1, //[30]
+                      reserved_2                      :  1; //[31]
+             uint32_t tqm_status_number               : 24, //[23:0]
+                      transmit_count                  :  7, //[30:24]
+                      reserved_3a                     :  1; //[31]
+             uint32_t ack_frame_rssi                  :  8, //[7:0]
+                      sw_release_details_valid        :  1, //[8]
+                      first_msdu                      :  1, //[9]
+                      last_msdu                       :  1, //[10]
+                      msdu_part_of_amsdu              :  1, //[11]
+                      fw_tx_notify_frame              :  1, //[12]
+                      buffer_timestamp                : 19; //[31:13]
+    struct            tx_rate_stats_info                       tx_rate_stats;
+             uint32_t sw_peer_id                      : 16, //[15:0]
+                      tid                             :  4, //[19:16]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info released_buff_or_desc_addr_info
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Details of the physical address of the buffer or link
+			descriptor that is being released. Note that within this
+			descriptor, WBM will look at the 'owner' of the released
+			buffer/descriptor and forward it to SW/FW is WBM is not the
+			owner.
+
+release_source_module
+			
+			Indicates which module initiated the release of this
+			buffer or descriptor
+			
+			
+			
+			<enum 0 release_source_TQM> TQM released this buffer or
+			descriptor
+			
+			<enum 1 release_source_RXDMA> RXDMA released this buffer
+			or descriptor
+			
+			<enum 2 release_source_REO> REO released this buffer or
+			descriptor
+			
+			<enum 3 release_source_FW> FW released this buffer or
+			descriptor
+			
+			<enum 4 release_source_SW> SW released this buffer or
+			descriptor
+			
+			<legal 0-4>
+
+bm_action
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid when the field return_buffer_manager in
+			the Released_buff_or_desc_addr_info indicates:
+			
+			WBM_IDLE_BUF_LIST or
+			
+			WBM_IDLE_DESC_LIST
+			
+			
+			
+			An MSDU extension descriptor shall never be marked as
+			
+			
+			
+			<enum 0 Put_in_idle_list> Put the buffer or descriptor
+			back in the idle list. In case of MSDU or MDPU link
+			descriptor, BM does not need to check to release any
+			individual MSDU buffers
+			
+			
+			
+			<enum 1 release_msdu_list > This BM action can only be
+			used in combination with buffer_or_desc_type being
+			msdu_link_descriptor. Field first_msdu_index points out
+			which MSDU pointer in the MSDU link descriptor is the first
+			of an MPDU that is released.
+			
+			BM shall release all the MSDU buffers linked to this
+			first MSDU buffer pointer. All related MSDU buffer pointer
+			entries shall be set to value 0, which represents the 'NULL
+			pointer. When all MSDU buffer pointers in the MSDU link
+			descriptor are 'NULL', the MSDU link descriptor itself shall
+			also be released.
+			
+			
+			
+			<enum 2 Put_in_idle_list_expanded> CURRENTLY NOT
+			IMPLEMENTED....
+			
+			Put the buffer or descriptor back in the idle list. Only
+			valid in combination with buffer_or_desc_type indicating
+			MDPU_link_descriptor.
+			
+			BM shall release the MPDU link descriptor as well as all
+			MSDUs that are linked to the MPDUs in this descriptor. 
+			
+			
+			
+			<legal 0-2>
+
+buffer_or_desc_type
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid when WBM is marked as the
+			return_buffer_manager in the Released_Buffer_address_info
+			
+			
+			
+			Indicates that type of buffer or descriptor is being
+			released
+			
+			
+			
+			<enum 0 MSDU_rel_buffer> The address points to an MSDU
+			buffer 
+			
+			<enum 1 msdu_link_descriptor> The address points to an
+			TX MSDU link descriptor
+			
+			<enum 2 mpdu_link_descriptor> The address points to an
+			MPDU link descriptor
+			
+			<enum 3 msdu_ext_descriptor > The address points to an
+			MSDU extension descriptor.
+			
+			In case BM finds this one in a release ring, it passes
+			it on to FW...
+			
+			<enum 4 queue_ext_descriptor> The address points to an
+			TQM queue extension descriptor. WBM should treat this is the
+			same way as a link descriptor. That is, put the 128 byte
+			buffer back in the link buffer idle list.
+			
+			
+			
+			<legal 0-4>
+
+first_msdu_index
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid for the bm_action release_msdu_list.
+			
+			
+			
+			The index of the first MSDU in an MSDU link descriptor
+			all belonging to the same MPDU.
+			
+			
+			
+			<legal 0-6>
+
+tqm_release_reason
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: TQM
+			
+			
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			(rr = Release Reason)
+			
+			<enum 0 tqm_rr_frame_acked> frame is removed because an
+			ACK of BA for it was received 
+			
+			<enum 1 tqm_rr_rem_cmd_rem> frame is removed because a
+			remove command of type Remove_mpdus initiated by SW
+			
+			<enum 2 tqm_rr_rem_cmd_tx> frame is removed because a
+			remove command of type Remove_transmitted_mpdus initiated by
+			SW
+			
+			<enum 3 tqm_rr_rem_cmd_notx> frame is removed because a
+			remove command of type Remove_untransmitted_mpdus initiated
+			by SW
+			
+			<enum 4 tqm_rr_rem_cmd_aged> frame is removed because a
+			remove command of type Remove_aged_mpdus or
+			Remove_aged_msdus initiated by SW
+			
+			<enum 5 tqm_fw_reason1> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			<enum 6 tqm_fw_reason2> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			<enum 7 tqm_fw_reason3> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			
+			
+			<legal 0-7>
+
+rxdma_push_reason
+			
+			Field only valid when Release_source_module is set to
+			release_source_RXDMA
+			
+			
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			<legal 0 - 1>
+
+rxdma_error_code
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+
+reo_push_reason
+			
+			Field only valid when Release_source_module is set to
+			release_source_REO
+			
+			
+			
+			Indicates why REO pushed the frame to this release ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			<legal 0 - 1>
+
+reo_error_code
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+
+wbm_internal_error
+			
+			Can only be set by WBM.
+			
+			
+			
+			Is set when WBM got a buffer pointer but the action was
+			to push it to the idle link descriptor ring or do link
+			related activity
+			
+			OR
+			
+			Is set when WBM got a link buffer pointer but the action
+			was to push it to the buffer  descriptor ring 
+			
+			
+			
+			<legal all>
+
+reserved_2
+			
+			<legal 0>
+
+tqm_status_number
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			The value in this field is equal to value of the
+			'TQM_CMD_Number' field the TQM command or the
+			'TQM_add_cmd_Number' field from the TQM entrance ring
+			descriptor
+			
+			
+			
+			This field helps to correlate the statuses with the TQM
+			commands.
+			
+			
+			
+			NOTE that SW could program this number to be equal to
+			the PPDU_ID number in case direct correlation with the PPDU
+			ID is desired
+			
+			
+			
+			<legal all> 
+
+transmit_count
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			The number of times this frame has been transmitted
+
+reserved_3a
+			
+			<legal 0>
+
+ack_frame_rssi
+			
+			This field is only valid when the source is TQM.
+			
+			
+			
+			If this frame is removed as the result of the reception
+			of an ACK or BA, this field indicates the RSSI of the
+			received ACK or BA frame. 
+			
+			
+			
+			When the frame is removed as result of a direct remove
+			command from the SW,  this field is set to 0x0 (which is
+			never a valid value when real RSSI is available)
+			
+			
+			
+			<legal all>
+
+sw_release_details_valid
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, some WBM specific release info for SW is
+			valid.
+			
+			This is set when WMB got a 'release_msdu_list' command
+			from TQM and the return buffer manager is not WMB. WBM will
+			then de-aggregate all the MSDUs and pass them one at a time
+			on to the 'buffer owner'
+			
+			
+			
+			<legal all>
+
+first_msdu
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU is the first MSDU pointed to in the
+			'release_msdu_list' command.
+			
+			
+			
+			<legal all>
+
+last_msdu
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU is the last MSDU pointed to in the
+			'release_msdu_list' command.
+			
+			
+			
+			<legal all>
+
+msdu_part_of_amsdu
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU was part of an A-MSDU in MPDU
+			
+			<legal all>
+
+fw_tx_notify_frame
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			This is the FW_tx_notify_frame field from the
+			
+			<legal all>
+
+buffer_timestamp
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			This is the Buffer_timestamp field from the
+			
+			<legal all>
+
+struct tx_rate_stats_info tx_rate_stats
+			
+			Consumer: TQM
+			
+			Producer: SW/SCH(from TXPCU, PDG)
+			
+			
+			
+			Details for command execution tracking purposes. 
+
+sw_peer_id
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			Sw_peer_id from the TX_MSDU_FLOW descriptor or
+			TX_MPDU_QUEUE descriptor
+			
+			<legal all>
+
+tid
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			TID of the flow or MPDU queue
+			
+			<legal all>
+
+ring_id
+			
+			Consumer: TQM/REO/RXDMA/SW
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+
+looping_count
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into the Buffer Manager Ring has looped
+			around the ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000000
+#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28
+#define WBM_RELEASE_RING_0_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff
+#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_OFFSET 0x00000004
+#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_LSB 28
+#define WBM_RELEASE_RING_1_BUFFER_ADDR_INFO_RELEASED_BUFF_OR_DESC_ADDR_INFO_MASK 0xffffffff
+
+/* Description		WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE
+			
+			Indicates which module initiated the release of this
+			buffer or descriptor
+			
+			
+			
+			<enum 0 release_source_TQM> TQM released this buffer or
+			descriptor
+			
+			<enum 1 release_source_RXDMA> RXDMA released this buffer
+			or descriptor
+			
+			<enum 2 release_source_REO> REO released this buffer or
+			descriptor
+			
+			<enum 3 release_source_FW> FW released this buffer or
+			descriptor
+			
+			<enum 4 release_source_SW> SW released this buffer or
+			descriptor
+			
+			<legal 0-4>
+*/
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET              0x00000008
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB                 0
+#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK                0x00000007
+
+/* Description		WBM_RELEASE_RING_2_BM_ACTION
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid when the field return_buffer_manager in
+			the Released_buff_or_desc_addr_info indicates:
+			
+			WBM_IDLE_BUF_LIST or
+			
+			WBM_IDLE_DESC_LIST
+			
+			
+			
+			An MSDU extension descriptor shall never be marked as
+			
+			
+			
+			<enum 0 Put_in_idle_list> Put the buffer or descriptor
+			back in the idle list. In case of MSDU or MDPU link
+			descriptor, BM does not need to check to release any
+			individual MSDU buffers
+			
+			
+			
+			<enum 1 release_msdu_list > This BM action can only be
+			used in combination with buffer_or_desc_type being
+			msdu_link_descriptor. Field first_msdu_index points out
+			which MSDU pointer in the MSDU link descriptor is the first
+			of an MPDU that is released.
+			
+			BM shall release all the MSDU buffers linked to this
+			first MSDU buffer pointer. All related MSDU buffer pointer
+			entries shall be set to value 0, which represents the 'NULL
+			pointer. When all MSDU buffer pointers in the MSDU link
+			descriptor are 'NULL', the MSDU link descriptor itself shall
+			also be released.
+			
+			
+			
+			<enum 2 Put_in_idle_list_expanded> CURRENTLY NOT
+			IMPLEMENTED....
+			
+			Put the buffer or descriptor back in the idle list. Only
+			valid in combination with buffer_or_desc_type indicating
+			MDPU_link_descriptor.
+			
+			BM shall release the MPDU link descriptor as well as all
+			MSDUs that are linked to the MPDUs in this descriptor. 
+			
+			
+			
+			<legal 0-2>
+*/
+#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET                          0x00000008
+#define WBM_RELEASE_RING_2_BM_ACTION_LSB                             3
+#define WBM_RELEASE_RING_2_BM_ACTION_MASK                            0x00000038
+
+/* Description		WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid when WBM is marked as the
+			return_buffer_manager in the Released_Buffer_address_info
+			
+			
+			
+			Indicates that type of buffer or descriptor is being
+			released
+			
+			
+			
+			<enum 0 MSDU_rel_buffer> The address points to an MSDU
+			buffer 
+			
+			<enum 1 msdu_link_descriptor> The address points to an
+			TX MSDU link descriptor
+			
+			<enum 2 mpdu_link_descriptor> The address points to an
+			MPDU link descriptor
+			
+			<enum 3 msdu_ext_descriptor > The address points to an
+			MSDU extension descriptor.
+			
+			In case BM finds this one in a release ring, it passes
+			it on to FW...
+			
+			<enum 4 queue_ext_descriptor> The address points to an
+			TQM queue extension descriptor. WBM should treat this is the
+			same way as a link descriptor. That is, put the 128 byte
+			buffer back in the link buffer idle list.
+			
+			
+			
+			<legal 0-4>
+*/
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET                0x00000008
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB                   6
+#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK                  0x000001c0
+
+/* Description		WBM_RELEASE_RING_2_FIRST_MSDU_INDEX
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			Field only valid for the bm_action release_msdu_list.
+			
+			
+			
+			The index of the first MSDU in an MSDU link descriptor
+			all belonging to the same MPDU.
+			
+			
+			
+			<legal 0-6>
+*/
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET                   0x00000008
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB                      9
+#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK                     0x00001e00
+
+/* Description		WBM_RELEASE_RING_2_TQM_RELEASE_REASON
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: TQM
+			
+			
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			(rr = Release Reason)
+			
+			<enum 0 tqm_rr_frame_acked> frame is removed because an
+			ACK of BA for it was received 
+			
+			<enum 1 tqm_rr_rem_cmd_rem> frame is removed because a
+			remove command of type Remove_mpdus initiated by SW
+			
+			<enum 2 tqm_rr_rem_cmd_tx> frame is removed because a
+			remove command of type Remove_transmitted_mpdus initiated by
+			SW
+			
+			<enum 3 tqm_rr_rem_cmd_notx> frame is removed because a
+			remove command of type Remove_untransmitted_mpdus initiated
+			by SW
+			
+			<enum 4 tqm_rr_rem_cmd_aged> frame is removed because a
+			remove command of type Remove_aged_mpdus or
+			Remove_aged_msdus initiated by SW
+			
+			<enum 5 tqm_fw_reason1> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			<enum 6 tqm_fw_reason2> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			<enum 7 tqm_fw_reason3> frame is removed because a
+			remove command where fw indicated that remove reason is
+			fw_reason1
+			
+			
+			
+			<legal 0-7>
+*/
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET                 0x00000008
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB                    13
+#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK                   0x0000e000
+
+/* Description		WBM_RELEASE_RING_2_RXDMA_PUSH_REASON
+			
+			Field only valid when Release_source_module is set to
+			release_source_RXDMA
+			
+			
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			<legal 0 - 1>
+*/
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET                  0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB                     16
+#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK                    0x00030000
+
+/* Description		WBM_RELEASE_RING_2_RXDMA_ERROR_CODE
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+*/
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET                   0x00000008
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB                      18
+#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK                     0x007c0000
+
+/* Description		WBM_RELEASE_RING_2_REO_PUSH_REASON
+			
+			Field only valid when Release_source_module is set to
+			release_source_REO
+			
+			
+			
+			Indicates why REO pushed the frame to this release ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			<legal 0 - 1>
+*/
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET                    0x00000008
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB                       23
+#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK                      0x01800000
+
+/* Description		WBM_RELEASE_RING_2_REO_ERROR_CODE
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+*/
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET                     0x00000008
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB                        25
+#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK                       0x3e000000
+
+/* Description		WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR
+			
+			Can only be set by WBM.
+			
+			
+			
+			Is set when WBM got a buffer pointer but the action was
+			to push it to the idle link descriptor ring or do link
+			related activity
+			
+			OR
+			
+			Is set when WBM got a link buffer pointer but the action
+			was to push it to the buffer  descriptor ring 
+			
+			
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET                 0x00000008
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB                    30
+#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK                   0x40000000
+
+/* Description		WBM_RELEASE_RING_2_RESERVED_2
+			
+			<legal 0>
+*/
+#define WBM_RELEASE_RING_2_RESERVED_2_OFFSET                         0x00000008
+#define WBM_RELEASE_RING_2_RESERVED_2_LSB                            31
+#define WBM_RELEASE_RING_2_RESERVED_2_MASK                           0x80000000
+
+/* Description		WBM_RELEASE_RING_3_TQM_STATUS_NUMBER
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			The value in this field is equal to value of the
+			'TQM_CMD_Number' field the TQM command or the
+			'TQM_add_cmd_Number' field from the TQM entrance ring
+			descriptor
+			
+			
+			
+			This field helps to correlate the statuses with the TQM
+			commands.
+			
+			
+			
+			NOTE that SW could program this number to be equal to
+			the PPDU_ID number in case direct correlation with the PPDU
+			ID is desired
+			
+			
+			
+			<legal all> 
+*/
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET                  0x0000000c
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB                     0
+#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK                    0x00ffffff
+
+/* Description		WBM_RELEASE_RING_3_TRANSMIT_COUNT
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			The number of times this frame has been transmitted
+*/
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET                     0x0000000c
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB                        24
+#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK                       0x7f000000
+
+/* Description		WBM_RELEASE_RING_3_RESERVED_3A
+			
+			<legal 0>
+*/
+#define WBM_RELEASE_RING_3_RESERVED_3A_OFFSET                        0x0000000c
+#define WBM_RELEASE_RING_3_RESERVED_3A_LSB                           31
+#define WBM_RELEASE_RING_3_RESERVED_3A_MASK                          0x80000000
+
+/* Description		WBM_RELEASE_RING_4_ACK_FRAME_RSSI
+			
+			This field is only valid when the source is TQM.
+			
+			
+			
+			If this frame is removed as the result of the reception
+			of an ACK or BA, this field indicates the RSSI of the
+			received ACK or BA frame. 
+			
+			
+			
+			When the frame is removed as result of a direct remove
+			command from the SW,  this field is set to 0x0 (which is
+			never a valid value when real RSSI is available)
+			
+			
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET                     0x00000010
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB                        0
+#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK                       0x000000ff
+
+/* Description		WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, some WBM specific release info for SW is
+			valid.
+			
+			This is set when WMB got a 'release_msdu_list' command
+			from TQM and the return buffer manager is not WMB. WBM will
+			then de-aggregate all the MSDUs and pass them one at a time
+			on to the 'buffer owner'
+			
+			
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET           0x00000010
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB              8
+#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK             0x00000100
+
+/* Description		WBM_RELEASE_RING_4_FIRST_MSDU
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU is the first MSDU pointed to in the
+			'release_msdu_list' command.
+			
+			
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET                         0x00000010
+#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB                            9
+#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK                           0x00000200
+
+/* Description		WBM_RELEASE_RING_4_LAST_MSDU
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU is the last MSDU pointed to in the
+			'release_msdu_list' command.
+			
+			
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET                          0x00000010
+#define WBM_RELEASE_RING_4_LAST_MSDU_LSB                             10
+#define WBM_RELEASE_RING_4_LAST_MSDU_MASK                            0x00000400
+
+/* Description		WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			When set, this MSDU was part of an A-MSDU in MPDU
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET                 0x00000010
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB                    11
+#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK                   0x00000800
+
+/* Description		WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			This is the FW_tx_notify_frame field from the
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET                 0x00000010
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB                    12
+#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK                   0x00001000
+
+/* Description		WBM_RELEASE_RING_4_BUFFER_TIMESTAMP
+			
+			Field only valid when SW_release_details_valid is set.
+			
+			
+			
+			Consumer: SW
+			
+			Producer: WBM
+			
+			
+			
+			This is the Buffer_timestamp field from the
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET                   0x00000010
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB                      13
+#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK                     0xffffe000
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET   0x00000014
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB      13
+#define WBM_RELEASE_RING_5_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK     0xffffffff
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET   0x00000018
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB      13
+#define WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK     0xffffffff
+
+/* Description		WBM_RELEASE_RING_7_SW_PEER_ID
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			Sw_peer_id from the TX_MSDU_FLOW descriptor or
+			TX_MPDU_QUEUE descriptor
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET                         0x0000001c
+#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB                            0
+#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK                           0x0000ffff
+
+/* Description		WBM_RELEASE_RING_7_TID
+			
+			Field only valid when Release_source_module is set to
+			release_source_TQM
+			
+			
+			
+			TID of the flow or MPDU queue
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_7_TID_OFFSET                                0x0000001c
+#define WBM_RELEASE_RING_7_TID_LSB                                   16
+#define WBM_RELEASE_RING_7_TID_MASK                                  0x000f0000
+
+/* Description		WBM_RELEASE_RING_7_RING_ID
+			
+			Consumer: TQM/REO/RXDMA/SW
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+*/
+#define WBM_RELEASE_RING_7_RING_ID_OFFSET                            0x0000001c
+#define WBM_RELEASE_RING_7_RING_ID_LSB                               20
+#define WBM_RELEASE_RING_7_RING_ID_MASK                              0x0ff00000
+
+/* Description		WBM_RELEASE_RING_7_LOOPING_COUNT
+			
+			Consumer: WBM/SW/FW
+			
+			Producer: SW/TQM/RXDMA/REO/SWITCH
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into the Buffer Manager Ring has looped
+			around the ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET                      0x0000001c
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB                         28
+#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK                        0xf0000000
+
+
+#endif // _WBM_RELEASE_RING_H_

hw/qca6290/v1/wcss_seq_hwiobase.h

@@ -0,0 +1,731 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wcss_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WCSS_SEQ_BASE_H__
+#define __WCSS_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wcss
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WCSS_ECAHB_OFFSET                                        0x00008000
+#define SEQ_WCSS_ECAHB_TSLV_OFFSET                                   0x00009000
+#define SEQ_WCSS_UMAC_NOC_OFFSET                                     0x00140000
+#define SEQ_WCSS_MPSS_PCSS_PDMEM_B_REG_MAP_OFFSET                    0x00240000
+#define SEQ_WCSS_MPSS_PCSS_B_REG_MAP_OFFSET                          0x00250000
+#define SEQ_WCSS_PHYA0_OFFSET                                        0x00400000
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                0x00400000
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_REG_MAP_OFFSET                      0x00480000
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                0x00480400
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                0x00480800
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                0x00480c00
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                0x00481000
+#define SEQ_WCSS_PHYA0_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                0x00481400
+#define SEQ_WCSS_PHYA0_WFAX_NOC_REG_MAP_OFFSET                       0x00484000
+#define SEQ_WCSS_PHYA0_WFAX_TXTD_REG_MAP_OFFSET                      0x00488000
+#define SEQ_WCSS_PHYA0_WFAX_TXFD_REG_MAP_OFFSET                      0x00500000
+#define SEQ_WCSS_PHYA0_WFAX_ROBE_REG_MAP_OFFSET                      0x00520000
+#define SEQ_WCSS_PHYA0_WFAX_RXTD_REG_MAP_OFFSET                      0x00528000
+#define SEQ_WCSS_PHYA0_WFAX_DEMFRONT_REG_MAP_OFFSET                  0x00530000
+#define SEQ_WCSS_PHYA0_WFAX_PHYRF_REG_MAP_OFFSET                     0x005a0000
+#define SEQ_WCSS_PHYA1_OFFSET                                        0x00600000
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                0x00600000
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_REG_MAP_OFFSET                      0x00680000
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                0x00680400
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                0x00680800
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                0x00680c00
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                0x00681000
+#define SEQ_WCSS_PHYA1_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                0x00681400
+#define SEQ_WCSS_PHYA1_WFAX_NOC_REG_MAP_OFFSET                       0x00684000
+#define SEQ_WCSS_PHYA1_WFAX_TXTD_REG_MAP_OFFSET                      0x00688000
+#define SEQ_WCSS_PHYA1_WFAX_TXFD_REG_MAP_OFFSET                      0x00700000
+#define SEQ_WCSS_PHYA1_WFAX_ROBE_REG_MAP_OFFSET                      0x00720000
+#define SEQ_WCSS_PHYA1_WFAX_RXTD_REG_MAP_OFFSET                      0x00728000
+#define SEQ_WCSS_PHYA1_WFAX_DEMFRONT_REG_MAP_OFFSET                  0x00730000
+#define SEQ_WCSS_PHYA1_WFAX_PHYRF_REG_MAP_OFFSET                     0x007a0000
+#define SEQ_WCSS_PHYB_OFFSET                                         0x00800000
+#define SEQ_WCSS_PHYB_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET               0x00800000
+#define SEQ_WCSS_PHYB_WFAX_PCSS_B_REG_MAP_OFFSET                     0x00880000
+#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET               0x00880400
+#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET               0x00880800
+#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET               0x00880c00
+#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET               0x00881000
+#define SEQ_WCSS_PHYB_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET               0x00881400
+#define SEQ_WCSS_PHYB_WFAX_NOC_B_REG_MAP_OFFSET                      0x00884000
+#define SEQ_WCSS_PHYB_WFAX_TXTD_B_REG_MAP_OFFSET                     0x00888000
+#define SEQ_WCSS_PHYB_WFAX_TXFD_B_REG_MAP_OFFSET                     0x00900000
+#define SEQ_WCSS_PHYB_WFAX_ROBE_B_REG_MAP_OFFSET                     0x00920000
+#define SEQ_WCSS_PHYB_WFAX_RXTD_B_REG_MAP_OFFSET                     0x00928000
+#define SEQ_WCSS_PHYB_WFAX_DEMFRONT_B_REG_MAP_OFFSET                 0x00930000
+#define SEQ_WCSS_PHYB_WFAX_PHYRF_B_REG_MAP_OFFSET                    0x009a0000
+#define SEQ_WCSS_UMAC_OFFSET                                         0x00a00000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_OFFSET                           0x00a00000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00a00000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00a01000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00a02000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00a03000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00a04000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00a05000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00a06000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00a07000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00a08000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00a09000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x00a0a000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x00a0b000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x00a0c000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x00a0d000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x00a0e000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x00a0f000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00a10000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00a11000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00a12000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00a13000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00a14000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00a15000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00a16000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00a17000
+#define SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET        0x00a18000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET                             0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET                 0x00a20000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET                0x00a22000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET            0x00a24000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET                 0x00a26000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET                 0x00a28000
+#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET                 0x00a2a000
+#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET                          0x00a30000
+#define SEQ_WCSS_UMAC_WBM_REG_OFFSET                                 0x00a34000
+#define SEQ_WCSS_UMAC_REO_REG_OFFSET                                 0x00a38000
+#define SEQ_WCSS_UMAC_TQM_REG_OFFSET                                 0x00a3c000
+#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET                           0x00a40000
+#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET                             0x00a44000
+#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_REG_OFFSET                      0x00a47000
+#define SEQ_WCSS_UMAC_MAC_CCE_REG_OFFSET                             0x00a4a000
+#define SEQ_WCSS_WMAC0_OFFSET                                        0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET                            0x00a80000
+#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET                          0x00a83000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET                          0x00a86000
+#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET                           0x00a89000
+#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET                          0x00a8c000
+#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET                          0x00a8f000
+#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET                           0x00a92000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET                          0x00a95000
+#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET                   0x00a98000
+#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET                            0x00a9b000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET                          0x00a9e000
+#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET                   0x00aa1000
+#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET                            0x00aa4000
+#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET                         0x00aa7000
+#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET                          0x00aaa000
+#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET                            0x00ab0000
+#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET                            0x00ab3000
+#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET                         0x00ab6000
+#define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET                           0x00ab9000
+#define SEQ_WCSS_WMAC1_OFFSET                                        0x00ac0000
+#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET                            0x00ac0000
+#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET                          0x00ac3000
+#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET                          0x00ac6000
+#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET                           0x00ac9000
+#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET                          0x00acc000
+#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET                          0x00acf000
+#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET                           0x00ad2000
+#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET                          0x00ad5000
+#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET                   0x00ad8000
+#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET                            0x00adb000
+#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET                          0x00ade000
+#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET                   0x00ae1000
+#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET                            0x00ae4000
+#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET                         0x00ae7000
+#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET                          0x00aea000
+#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET                            0x00af0000
+#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET                            0x00af3000
+#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET                         0x00af6000
+#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET                           0x00af9000
+#define SEQ_WCSS_WMAC2_OFFSET                                        0x00b00000
+#define SEQ_WCSS_WMAC2_MAC_PDG_REG_OFFSET                            0x00b00000
+#define SEQ_WCSS_WMAC2_MAC_TXDMA_REG_OFFSET                          0x00b03000
+#define SEQ_WCSS_WMAC2_MAC_RXDMA_REG_OFFSET                          0x00b06000
+#define SEQ_WCSS_WMAC2_MAC_MCMN_REG_OFFSET                           0x00b09000
+#define SEQ_WCSS_WMAC2_MAC_RXPCU_REG_OFFSET                          0x00b0c000
+#define SEQ_WCSS_WMAC2_MAC_TXPCU_REG_OFFSET                          0x00b0f000
+#define SEQ_WCSS_WMAC2_MAC_AMPI_REG_OFFSET                           0x00b12000
+#define SEQ_WCSS_WMAC2_MAC_RXOLE_REG_OFFSET                          0x00b15000
+#define SEQ_WCSS_WMAC2_MAC_RXOLE_PARSER_REG_OFFSET                   0x00b18000
+#define SEQ_WCSS_WMAC2_MAC_CCE_REG_OFFSET                            0x00b1b000
+#define SEQ_WCSS_WMAC2_MAC_TXOLE_REG_OFFSET                          0x00b1e000
+#define SEQ_WCSS_WMAC2_MAC_TXOLE_PARSER_REG_OFFSET                   0x00b21000
+#define SEQ_WCSS_WMAC2_MAC_RRI_REG_OFFSET                            0x00b24000
+#define SEQ_WCSS_WMAC2_MAC_CRYPTO_REG_OFFSET                         0x00b27000
+#define SEQ_WCSS_WMAC2_MAC_HWSCH_REG_OFFSET                          0x00b2a000
+#define SEQ_WCSS_WMAC2_MAC_MXI_REG_OFFSET                            0x00b30000
+#define SEQ_WCSS_WMAC2_MAC_SFM_REG_OFFSET                            0x00b33000
+#define SEQ_WCSS_WMAC2_MAC_RXDMA1_REG_OFFSET                         0x00b36000
+#define SEQ_WCSS_WMAC2_MAC_LPEC_REG_OFFSET                           0x00b39000
+#define SEQ_WCSS_APB_TSLV_OFFSET                                     0x00b40000
+#define SEQ_WCSS_WCMN_OFFSET                                         0x00b50000
+#define SEQ_WCSS_WFSS_PMM_OFFSET                                     0x00b60000
+#define SEQ_WCSS_PMM_OFFSET                                          0x00b70000
+#define SEQ_WCSS_ZINC_RFA_CMN_OFFSET                                 0x00b80000
+#define SEQ_WCSS_ZINC_RFA_CMN_PLL_A_OFFSET                           0x00b80000
+#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_A_OFFSET                      0x00b80100
+#define SEQ_WCSS_ZINC_RFA_CMN_PLL_B_OFFSET                           0x00b82000
+#define SEQ_WCSS_ZINC_RFA_CMN_BIASCLKS_B_OFFSET                      0x00b82100
+#define SEQ_WCSS_ZINC_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET                 0x00b84000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET     0x00b88000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET              0x00b88100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET                0x00b88200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET                0x00b88300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET 0x00b88400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET 0x00b88440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET 0x00b88480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET 0x00b884c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET    0x00b88500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET          0x00b88600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET     0x00b88800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET              0x00b88900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET                0x00b88a00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET                0x00b88b00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET 0x00b88c00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET 0x00b88c40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET 0x00b88c80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET 0x00b88cc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET    0x00b88d00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET          0x00b88e00
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET     0x00b89000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET              0x00b89100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET                0x00b89200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET                0x00b89300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET 0x00b89400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET 0x00b89440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET 0x00b89480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET 0x00b894c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET    0x00b89500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET          0x00b89600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET     0x00b89800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET              0x00b89900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET                0x00b89a00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET                0x00b89b00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET 0x00b89c00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET 0x00b89c40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET 0x00b89c80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET 0x00b89cc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET    0x00b89d00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET          0x00b89e00
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET     0x00b8a000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET              0x00b8a100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET                0x00b8a200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET                0x00b8a300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET 0x00b8a400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET 0x00b8a440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET 0x00b8a480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET 0x00b8a4c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET    0x00b8a500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET          0x00b8a600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET     0x00b8a800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET              0x00b8a900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET                0x00b8aa00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET                0x00b8ab00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET 0x00b8ac00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET 0x00b8ac40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET 0x00b8ac80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET 0x00b8acc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET    0x00b8ad00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET          0x00b8ae00
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET     0x00b8b000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET              0x00b8b100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET                0x00b8b200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET                0x00b8b300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET 0x00b8b400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET 0x00b8b440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET 0x00b8b480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET 0x00b8b4c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET    0x00b8b500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET          0x00b8b600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET     0x00b8b800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET              0x00b8b900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET                0x00b8ba00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET                0x00b8bb00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET 0x00b8bc00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET 0x00b8bc40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET 0x00b8bc80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET 0x00b8bcc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET    0x00b8bd00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET          0x00b8be00
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET      0x00b8c000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET               0x00b8c100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET                 0x00b8c200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET                 0x00b8c300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET 0x00b8c400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET  0x00b8c440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET 0x00b8c480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET  0x00b8c4c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET     0x00b8c500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET           0x00b8c600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET      0x00b8c800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET               0x00b8c900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET                 0x00b8ca00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET                 0x00b8cb00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET 0x00b8cc00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET  0x00b8cc40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET 0x00b8cc80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET  0x00b8ccc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET     0x00b8cd00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET           0x00b8ce00
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET      0x00b8d000
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET               0x00b8d100
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET                 0x00b8d200
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET                 0x00b8d300
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET 0x00b8d400
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET  0x00b8d440
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET 0x00b8d480
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET  0x00b8d4c0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET     0x00b8d500
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET           0x00b8d600
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET      0x00b8d800
+#define SEQ_WCSS_ZINC_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET               0x00b8d900
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET                 0x00b8da00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET                 0x00b8db00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET 0x00b8dc00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET  0x00b8dc40
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET 0x00b8dc80
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET  0x00b8dcc0
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET     0x00b8dd00
+#define SEQ_WCSS_ZINC_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET           0x00b8de00
+#define SEQ_WCSS_DBG_OFFSET                                          0x00b90000
+#define SEQ_WCSS_DBG_ROM_WCSS_DBG_DAPROM_OFFSET                      0x00b90000
+#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET                         0x00b91000
+#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET                            0x00b92000
+#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_24T_8CH_OFFSET                    0x00b94000
+#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET                     0x00b95000
+#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                    0x00b96000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET  0x00b98000
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00b98280
+#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00b98000
+#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET     0x00b99000
+#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00b99280
+#define SEQ_WCSS_DBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00b99000
+#define SEQ_WCSS_DBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET        0x00b9a000
+#define SEQ_WCSS_DBG_FUN_CXATBFUNNEL_128W8SP_OFFSET                  0x00b9b000
+#define SEQ_WCSS_DBG_TMC_CXTMC_F128W8K_OFFSET                        0x00b9c000
+#define SEQ_WCSS_DBG_UMAC_NOC_UMAC_NOC_OFFSET                        0x00ba0000
+#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bb0000
+#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET                   0x00bb1000
+#define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET                        0x00bb6000
+#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET                         0x00bbe000
+#define SEQ_WCSS_DBG_PHYA_CPU1_AHB_AP_OFFSET                         0x00bbf000
+#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET              0x00bc0000
+#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET                   0x00bc1000
+#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET                        0x00bc6000
+#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET                         0x00bce000
+#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET                          0x00bf0000
+#define SEQ_WCSS_RET_AHB_OFFSET                                      0x00c10000
+#define SEQ_WCSS_WAHB_TSLV_OFFSET                                    0x00c20000
+#define SEQ_WCSS_CC_OFFSET                                           0x00c30000
+#define SEQ_WCSS_ACMT_OFFSET                                         0x00c40000
+#define SEQ_WCSS_WRAPPER_ACMT_OFFSET                                 0x00c60000
+#define SEQ_WCSS_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET                    0x00c60000
+#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET                                  0x00d00000
+#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET                      0x00d00000
+#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET                                 0x00d80000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET                     0x00d80000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET                   0x00d90000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET                 0x00da0000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET                         0x00da1000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET                         0x00da2000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET                         0x00da3000
+#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET                    0x00db0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wfax_top
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET                  0x00000000
+#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET                        0x00080000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET                  0x00080400
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET                  0x00080800
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET                  0x00080c00
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET                  0x00081000
+#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET                  0x00081400
+#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET                         0x00084000
+#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET                        0x00088000
+#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET                        0x00100000
+#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET                        0x00120000
+#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET                        0x00128000
+#define SEQ_WFAX_TOP_WFAX_DEMFRONT_REG_MAP_OFFSET                    0x00130000
+#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET                       0x001a0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wfax_top_b
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_PDMEM_B_REG_MAP_OFFSET              0x00000000
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_B_REG_MAP_OFFSET                    0x00080000
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC0_B_REG_MAP_OFFSET              0x00080400
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC1_B_REG_MAP_OFFSET              0x00080800
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC2_B_REG_MAP_OFFSET              0x00080c00
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC3_B_REG_MAP_OFFSET              0x00081000
+#define SEQ_WFAX_TOP_B_WFAX_PCSS_DMAC4_B_REG_MAP_OFFSET              0x00081400
+#define SEQ_WFAX_TOP_B_WFAX_NOC_B_REG_MAP_OFFSET                     0x00084000
+#define SEQ_WFAX_TOP_B_WFAX_TXTD_B_REG_MAP_OFFSET                    0x00088000
+#define SEQ_WFAX_TOP_B_WFAX_TXFD_B_REG_MAP_OFFSET                    0x00100000
+#define SEQ_WFAX_TOP_B_WFAX_ROBE_B_REG_MAP_OFFSET                    0x00120000
+#define SEQ_WFAX_TOP_B_WFAX_RXTD_B_REG_MAP_OFFSET                    0x00128000
+#define SEQ_WFAX_TOP_B_WFAX_DEMFRONT_B_REG_MAP_OFFSET                0x00130000
+#define SEQ_WFAX_TOP_B_WFAX_PHYRF_B_REG_MAP_OFFSET                   0x001a0000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block umac_top_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_OFFSET                        0x00000000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET 0x00000000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET 0x00001000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET 0x00002000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET 0x00003000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET 0x00004000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET 0x00005000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET 0x00006000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET 0x00007000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET 0x00008000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET 0x00009000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET 0x0000a000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET 0x0000b000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET 0x0000c000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET 0x0000d000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET 0x0000e000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET 0x0000f000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET 0x00010000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET 0x00011000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET 0x00012000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET 0x00013000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET 0x00014000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET 0x00015000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET 0x00016000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET 0x00017000
+#define SEQ_UMAC_TOP_REG_WFSS_CE_0_REG_WFSS_CE_COMMON_REG_OFFSET     0x00018000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET                          0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET              0x00020000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET             0x00022000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET         0x00024000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET              0x00026000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET              0x00028000
+#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET              0x0002a000
+#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET                       0x00030000
+#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET                              0x00034000
+#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET                              0x00038000
+#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET                              0x0003c000
+#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET                        0x00040000
+#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET                          0x00044000
+#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_REG_OFFSET                   0x00047000
+#define SEQ_UMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0004a000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wfss_ce_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET             0x00000000
+#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET             0x00001000
+#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET             0x00002000
+#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET             0x00003000
+#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET             0x00004000
+#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET             0x00005000
+#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET             0x00006000
+#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET             0x00007000
+#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET             0x00008000
+#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET             0x00009000
+#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET             0x0000a000
+#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET             0x0000b000
+#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET             0x0000c000
+#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET             0x0000d000
+#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET             0x0000e000
+#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET             0x0000f000
+#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET             0x00010000
+#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET             0x00011000
+#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET             0x00012000
+#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET             0x00013000
+#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET            0x00014000
+#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET            0x00015000
+#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET            0x00016000
+#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET            0x00017000
+#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET                    0x00018000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block cxc_top_reg_14lpp
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_CXC_TOP_REG_14LPP_CXC_BMH_REG_OFFSET                     0x00000000
+#define SEQ_CXC_TOP_REG_14LPP_CXC_LCMH_REG_OFFSET                    0x00002000
+#define SEQ_CXC_TOP_REG_14LPP_CXC_MCIBASIC_REG_OFFSET                0x00004000
+#define SEQ_CXC_TOP_REG_14LPP_CXC_LMH_REG_OFFSET                     0x00006000
+#define SEQ_CXC_TOP_REG_14LPP_CXC_SMH_REG_OFFSET                     0x00008000
+#define SEQ_CXC_TOP_REG_14LPP_CXC_PMH_REG_OFFSET                     0x0000a000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wmac_top_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET                          0x00000000
+#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET                        0x00003000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET                        0x00006000
+#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET                         0x00009000
+#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET                        0x0000c000
+#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET                        0x0000f000
+#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET                         0x00012000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET                        0x00015000
+#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET                 0x00018000
+#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET                          0x0001b000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET                        0x0001e000
+#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET                 0x00021000
+#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET                          0x00024000
+#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET                       0x00027000
+#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET                        0x0002a000
+#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET                          0x00030000
+#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET                          0x00033000
+#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET                       0x00036000
+#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET                         0x00039000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block rfa_cmn
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_RFA_CMN_PLL_A_OFFSET                                     0x00000000
+#define SEQ_RFA_CMN_BIASCLKS_A_OFFSET                                0x00000100
+#define SEQ_RFA_CMN_PLL_B_OFFSET                                     0x00002000
+#define SEQ_RFA_CMN_BIASCLKS_B_OFFSET                                0x00002100
+#define SEQ_RFA_CMN_PHYB_ROOTCLKGEN_OFFSET                           0x00004000
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH0_OFFSET               0x00008000
+#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH0_OFFSET                        0x00008100
+#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH0_OFFSET                          0x00008200
+#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH0_OFFSET                          0x00008300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH0_OFFSET          0x00008400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH0_OFFSET           0x00008440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH0_OFFSET          0x00008480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH0_OFFSET           0x000084c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH0_OFFSET              0x00008500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH0_OFFSET                    0x00008600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH1_OFFSET               0x00008800
+#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH1_OFFSET                        0x00008900
+#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH1_OFFSET                          0x00008a00
+#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH1_OFFSET                          0x00008b00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH1_OFFSET          0x00008c00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH1_OFFSET           0x00008c40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH1_OFFSET          0x00008c80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH1_OFFSET           0x00008cc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH1_OFFSET              0x00008d00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH1_OFFSET                    0x00008e00
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH2_OFFSET               0x00009000
+#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH2_OFFSET                        0x00009100
+#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH2_OFFSET                          0x00009200
+#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH2_OFFSET                          0x00009300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH2_OFFSET          0x00009400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH2_OFFSET           0x00009440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH2_OFFSET          0x00009480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH2_OFFSET           0x000094c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH2_OFFSET              0x00009500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH2_OFFSET                    0x00009600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA0_CH3_OFFSET               0x00009800
+#define SEQ_RFA_CMN_RBIST_RX_PHYA0_CH3_OFFSET                        0x00009900
+#define SEQ_RFA_CMN_WL_DAC_PHYA0_CH3_OFFSET                          0x00009a00
+#define SEQ_RFA_CMN_WL_ADC_PHYA0_CH3_OFFSET                          0x00009b00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA0_CH3_OFFSET          0x00009c00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA0_CH3_OFFSET           0x00009c40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA0_CH3_OFFSET          0x00009c80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA0_CH3_OFFSET           0x00009cc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA0_CH3_OFFSET              0x00009d00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA0_CH3_OFFSET                    0x00009e00
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH0_OFFSET               0x0000a000
+#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH0_OFFSET                        0x0000a100
+#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH0_OFFSET                          0x0000a200
+#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH0_OFFSET                          0x0000a300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH0_OFFSET          0x0000a400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH0_OFFSET           0x0000a440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH0_OFFSET          0x0000a480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH0_OFFSET           0x0000a4c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH0_OFFSET              0x0000a500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH0_OFFSET                    0x0000a600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH1_OFFSET               0x0000a800
+#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH1_OFFSET                        0x0000a900
+#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH1_OFFSET                          0x0000aa00
+#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH1_OFFSET                          0x0000ab00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH1_OFFSET          0x0000ac00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH1_OFFSET           0x0000ac40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH1_OFFSET          0x0000ac80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH1_OFFSET           0x0000acc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH1_OFFSET              0x0000ad00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH1_OFFSET                    0x0000ae00
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH2_OFFSET               0x0000b000
+#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH2_OFFSET                        0x0000b100
+#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH2_OFFSET                          0x0000b200
+#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH2_OFFSET                          0x0000b300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH2_OFFSET          0x0000b400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH2_OFFSET           0x0000b440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH2_OFFSET          0x0000b480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH2_OFFSET           0x0000b4c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH2_OFFSET              0x0000b500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH2_OFFSET                    0x0000b600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYA1_CH3_OFFSET               0x0000b800
+#define SEQ_RFA_CMN_RBIST_RX_PHYA1_CH3_OFFSET                        0x0000b900
+#define SEQ_RFA_CMN_WL_DAC_PHYA1_CH3_OFFSET                          0x0000ba00
+#define SEQ_RFA_CMN_WL_ADC_PHYA1_CH3_OFFSET                          0x0000bb00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYA1_CH3_OFFSET          0x0000bc00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYA1_CH3_OFFSET           0x0000bc40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYA1_CH3_OFFSET          0x0000bc80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYA1_CH3_OFFSET           0x0000bcc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYA1_CH3_OFFSET              0x0000bd00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYA1_CH3_OFFSET                    0x0000be00
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH0_OFFSET                0x0000c000
+#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH0_OFFSET                         0x0000c100
+#define SEQ_RFA_CMN_WL_DAC_PHYB_CH0_OFFSET                           0x0000c200
+#define SEQ_RFA_CMN_WL_ADC_PHYB_CH0_OFFSET                           0x0000c300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH0_OFFSET           0x0000c400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH0_OFFSET            0x0000c440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH0_OFFSET           0x0000c480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH0_OFFSET            0x0000c4c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH0_OFFSET               0x0000c500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH0_OFFSET                     0x0000c600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH1_OFFSET                0x0000c800
+#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH1_OFFSET                         0x0000c900
+#define SEQ_RFA_CMN_WL_DAC_PHYB_CH1_OFFSET                           0x0000ca00
+#define SEQ_RFA_CMN_WL_ADC_PHYB_CH1_OFFSET                           0x0000cb00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH1_OFFSET           0x0000cc00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH1_OFFSET            0x0000cc40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH1_OFFSET           0x0000cc80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH1_OFFSET            0x0000ccc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH1_OFFSET               0x0000cd00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH1_OFFSET                     0x0000ce00
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH2_OFFSET                0x0000d000
+#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH2_OFFSET                         0x0000d100
+#define SEQ_RFA_CMN_WL_DAC_PHYB_CH2_OFFSET                           0x0000d200
+#define SEQ_RFA_CMN_WL_ADC_PHYB_CH2_OFFSET                           0x0000d300
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH2_OFFSET           0x0000d400
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH2_OFFSET            0x0000d440
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH2_OFFSET           0x0000d480
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH2_OFFSET            0x0000d4c0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH2_OFFSET               0x0000d500
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH2_OFFSET                     0x0000d600
+#define SEQ_RFA_CMN_RBIST_TX_BAREBONE_PHYB_CH3_OFFSET                0x0000d800
+#define SEQ_RFA_CMN_RBIST_RX_PHYB_CH3_OFFSET                         0x0000d900
+#define SEQ_RFA_CMN_WL_DAC_PHYB_CH3_OFFSET                           0x0000da00
+#define SEQ_RFA_CMN_WL_ADC_PHYB_CH3_OFFSET                           0x0000db00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_EVEN_PHYB_CH3_OFFSET           0x0000dc00
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_I_ODD_PHYB_CH3_OFFSET            0x0000dc40
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_EVEN_PHYB_CH3_OFFSET           0x0000dc80
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_Q_ODD_PHYB_CH3_OFFSET            0x0000dcc0
+#define SEQ_RFA_CMN_WL_ADC_POSTPROC_RO_PHYB_CH3_OFFSET               0x0000dd00
+#define SEQ_RFA_CMN_WL_BB_CLKGEN_PHYB_CH3_OFFSET                     0x0000de00
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wcssdbg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WCSSDBG_ROM_WCSS_DBG_DAPROM_OFFSET                       0x00000000
+#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET                          0x00001000
+#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET                             0x00002000
+#define SEQ_WCSSDBG_CTIDBG_QC_CTI_24T_8CH_OFFSET                     0x00004000
+#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET                      0x00005000
+#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET                     0x00006000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_OFFSET   0x00008000
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00008280
+#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00008000
+#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_OFFSET      0x00009000
+#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00009280
+#define SEQ_WCSSDBG_PHY_TPDM_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00009000
+#define SEQ_WCSSDBG_TPDA_TPDA_S2_W64_D2_M64_CS4C2456A_OFFSET         0x0000a000
+#define SEQ_WCSSDBG_FUN_CXATBFUNNEL_128W8SP_OFFSET                   0x0000b000
+#define SEQ_WCSSDBG_TMC_CXTMC_F128W8K_OFFSET                         0x0000c000
+#define SEQ_WCSSDBG_UMAC_NOC_UMAC_NOC_OFFSET                         0x00010000
+#define SEQ_WCSSDBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET               0x00020000
+#define SEQ_WCSSDBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET                    0x00021000
+#define SEQ_WCSSDBG_PHYA_NOC_PHYA_NOC_OFFSET                         0x00026000
+#define SEQ_WCSSDBG_PHYA_CPU0_AHB_AP_OFFSET                          0x0002e000
+#define SEQ_WCSSDBG_PHYA_CPU1_AHB_AP_OFFSET                          0x0002f000
+#define SEQ_WCSSDBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET               0x00030000
+#define SEQ_WCSSDBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET                    0x00031000
+#define SEQ_WCSSDBG_PHYB_NOC_PHYB_NOC_OFFSET                         0x00036000
+#define SEQ_WCSSDBG_PHYB_CPU0_AHB_AP_OFFSET                          0x0003e000
+#define SEQ_WCSSDBG_UMAC_CPU_AHB_AP_OFFSET                           0x00060000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block tpdm_atb32_dsb64_csf49237bd
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_SUB_OFFSET 0x00000280
+#define SEQ_TPDM_ATB32_DSB64_CSF49237BD_TPDM_ATB32_DSB64_CSF49237BD_GPR_OFFSET 0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wrapper_acmt
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WRAPPER_ACMT_WRAPPER_ACMT_OFFSET                         0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6ss_public
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6SS_PUBLIC_QDSP6SS_PUB_OFFSET                        0x00000000
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block qdsp6ss_private
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_CSR_OFFSET                       0x00000000
+#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_L2VIC_OFFSET                     0x00010000
+#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_QTMR_AC_OFFSET                   0x00020000
+#define SEQ_QDSP6SS_PRIVATE_QTMR_F0_OFFSET                           0x00021000
+#define SEQ_QDSP6SS_PRIVATE_QTMR_F1_OFFSET                           0x00022000
+#define SEQ_QDSP6SS_PRIVATE_QTMR_F2_OFFSET                           0x00023000
+#define SEQ_QDSP6SS_PRIVATE_QDSP6SS_SAW2_OFFSET                      0x00030000
+
+
+#endif
+

hw/qca6290/v1/wfss_ce_reg_seq_hwiobase.h

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WFSS_CE_REG_SEQ_BASE_H__
+#define __WFSS_CE_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Instance Relative Offsets from Block wfss_ce_reg
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET             0x00000000
+#define SEQ_WFSS_CE_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET             0x00001000
+#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET             0x00002000
+#define SEQ_WFSS_CE_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET             0x00003000
+#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_SRC_REG_OFFSET             0x00004000
+#define SEQ_WFSS_CE_REG_WFSS_CE_2_CHANNEL_DST_REG_OFFSET             0x00005000
+#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_SRC_REG_OFFSET             0x00006000
+#define SEQ_WFSS_CE_REG_WFSS_CE_3_CHANNEL_DST_REG_OFFSET             0x00007000
+#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_SRC_REG_OFFSET             0x00008000
+#define SEQ_WFSS_CE_REG_WFSS_CE_4_CHANNEL_DST_REG_OFFSET             0x00009000
+#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_SRC_REG_OFFSET             0x0000a000
+#define SEQ_WFSS_CE_REG_WFSS_CE_5_CHANNEL_DST_REG_OFFSET             0x0000b000
+#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_SRC_REG_OFFSET             0x0000c000
+#define SEQ_WFSS_CE_REG_WFSS_CE_6_CHANNEL_DST_REG_OFFSET             0x0000d000
+#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_SRC_REG_OFFSET             0x0000e000
+#define SEQ_WFSS_CE_REG_WFSS_CE_7_CHANNEL_DST_REG_OFFSET             0x0000f000
+#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_SRC_REG_OFFSET             0x00010000
+#define SEQ_WFSS_CE_REG_WFSS_CE_8_CHANNEL_DST_REG_OFFSET             0x00011000
+#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_SRC_REG_OFFSET             0x00012000
+#define SEQ_WFSS_CE_REG_WFSS_CE_9_CHANNEL_DST_REG_OFFSET             0x00013000
+#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_SRC_REG_OFFSET            0x00014000
+#define SEQ_WFSS_CE_REG_WFSS_CE_10_CHANNEL_DST_REG_OFFSET            0x00015000
+#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_SRC_REG_OFFSET            0x00016000
+#define SEQ_WFSS_CE_REG_WFSS_CE_11_CHANNEL_DST_REG_OFFSET            0x00017000
+#define SEQ_WFSS_CE_REG_WFSS_CE_COMMON_REG_OFFSET                    0x00018000
+
+
+#endif
+

hw/qca6290/v1/wfss_ce_reg_seq_hwioreg.h

@@ -0,0 +1,2361 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// wfss_ce_reg_seq_hwioreg.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __WFSS_CE_REG_SEQ_REG_H__
+#define __WFSS_CE_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "wfss_ce_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WFSS_CE_CHANNEL_DST_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x)       (x+0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_PHYS(x)       (x+0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK          0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_SHFT                   0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x)       (x+0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_PHYS(x)       (x+0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK          0x00ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_SHFT                   0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x)             (x+0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_PHYS(x)             (x+0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK                0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_SHFT                         0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_BMSK        0x0000ff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RING_ID_SHFT               0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK     0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT            0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x)         (x+0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_PHYS(x)         (x+0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK            0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_SHFT                     0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUT(x, val)     \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x)           (x+0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_PHYS(x)           (x+0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK              0x0000003f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SHFT                       0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT        0x3
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT        0x2
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x)    (x+0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_PHYS(x)    (x+0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK       0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_SHFT                0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x)    (x+0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_PHYS(x)    (x+0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK       0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_SHFT                0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x)  (x+0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_PHYS(x)  (x+0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK     0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_SHFT              0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x)  (x+0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_PHYS(x)  (x+0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK     0x000001ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_SHFT              0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x)      (x+0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_PHYS(x)      (x+0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK         0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_SHFT                  0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(x, val)  \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK   0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT          0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK   0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_SHFT            0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x)     (x+0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_PHYS(x)     (x+0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK        0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_SHFT                 0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)       \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x)     (x+0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_PHYS(x)     (x+0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK        0x00ffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_SHFT                 0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)       \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x)           (x+0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_PHYS(x)           (x+0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK              0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_SHFT                       0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK      0x0000ff00
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT             0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK   0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT          0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x)       (x+0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_PHYS(x)       (x+0x00000064)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK          0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_SHFT                   0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x)         (x+0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_PHYS(x)         (x+0x00000068)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK            0x0000003f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SHFT                     0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)           \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(x, mask)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(x, val)     \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT        0x3
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT        0x2
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x)  (x+0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_PHYS(x)  (x+0x0000006c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK     0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_SHFT              0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x)  (x+0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_PHYS(x)  (x+0x00000070)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK     0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_SHFT              0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000007c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000080)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000084)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000a0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK   0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_SHFT            0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000a4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK   0x000001ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_SHFT            0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x)    (x+0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_PHYS(x)    (x+0x000000a8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK       0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_SHFT                0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000ac)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_DEST_CTRL ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x)                (x+0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_PHYS(x)                (x+0x000000b0)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK                   0x0001ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_SHFT                            0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x00010000
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK   0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT          0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x)             (x+0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_PHYS(x)             (x+0x000000b4)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK                0x0000003f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_SHFT                         0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK        0x00000020
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT               0x5
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x00000010
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT        0x4
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x00000008
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT        0x3
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK     0x00000004
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT            0x2
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK     0x00000002
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT            0x1
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK        0x00000001
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT               0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2 ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x)         (x+0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_PHYS(x)         (x+0x000000b8)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK            0x0000000f
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_SHFT                     0
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)           \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(x, mask)    \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(x, val)     \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x00000008
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT        0x3
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x00000004
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT        0x2
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x00000002
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT        0x1
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK   0x00000001
+#define HWIO_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT          0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x)             (x+0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_PHYS(x)             (x+0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK                0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_SHFT                         0
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK       0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT              0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x)             (x+0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_PHYS(x)             (x+0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK                0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_SHFT                         0
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK       0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT              0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x)           (x+0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_PHYS(x)           (x+0x00000408)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK              0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_SHFT                       0
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK     0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT            0x0
+
+//// Register WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP ////
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x)           (x+0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_PHYS(x)           (x+0x0000040c)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK              0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_SHFT                       0
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK     0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT            0x0
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WFSS_CE_CHANNEL_SRC_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x)        (x+0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_PHYS(x)        (x+0x00000000)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK           0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_SHFT                    0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)          \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(x, val)    \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x)        (x+0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_PHYS(x)        (x+0x00000004)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK           0x00ffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_SHFT                    0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)          \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(x, mask)   \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(x, val)    \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x)              (x+0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_PHYS(x)              (x+0x00000008)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK                 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_SHFT                          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_BMSK         0x0000ff00
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RING_ID_SHFT                0x8
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK      0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT             0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x)          (x+0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_PHYS(x)          (x+0x0000000c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK             0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_SHFT                      0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)            \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(x, mask)     \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUT(x, val)      \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x)            (x+0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_PHYS(x)            (x+0x00000010)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK               0x0000003f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SHFT                        0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)              \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(x, mask)       \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(x, val)        \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT        0x5
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT        0x4
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK  0x00000008
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT         0x3
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK  0x00000004
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT         0x2
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT        0x1
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x)     (x+0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_PHYS(x)     (x+0x0000001c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK        0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_SHFT                 0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)       \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x)     (x+0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_PHYS(x)     (x+0x00000020)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK        0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_SHFT                 0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)       \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000030)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000034)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000038)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000003c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000040)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000044)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_SHFT          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x)   (x+0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_PHYS(x)   (x+0x00000048)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK      0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_SHFT               0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)     \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x)   (x+0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_PHYS(x)   (x+0x0000004c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK      0x000001ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_SHFT               0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)     \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT        0x8
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x)       (x+0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_PHYS(x)       (x+0x00000050)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK          0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_SHFT                   0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK    0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT           0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000054)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK    0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_SHFT             0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)   \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x)                 (x+0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_PHYS(x)                 (x+0x00000058)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK                    0x0000001f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SHFT                             0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)                   \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(x, mask)            \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(x, val)             \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK          0x00000010
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT                 0x4
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK      0x00000008
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT             0x3
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK           0x00000004
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT                  0x2
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK        0x00000002
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT               0x1
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x00000001
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT        0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x)             (x+0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_PHYS(x)             (x+0x0000005c)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK                0x0000001f
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SHFT                         0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK        0x00000010
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT               0x4
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x00000008
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT        0x3
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x00000004
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT        0x2
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK     0x00000002
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT            0x1
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK        0x00000001
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT               0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x)              (x+0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_PHYS(x)              (x+0x00000060)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK                 0xffffffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_SHFT                          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK          0xffff0000
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT                0x10
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK           0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT                  0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x)              (x+0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_PHYS(x)              (x+0x00000400)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK                 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_SHFT                          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK        0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT               0x0
+
+//// Register WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP ////
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x)              (x+0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_PHYS(x)              (x+0x00000404)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK                 0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_SHFT                          0
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask) 
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), val)
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR(x), mask, val, HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK        0x0000ffff
+#define HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT               0x0
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WFSS_CE_COMMON_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x)              (x+0x00000000)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_PHYS(x)              (x+0x00000000)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK                 0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_SHFT                          0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK           0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT                  0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x)              (x+0x00000004)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_PHYS(x)              (x+0x00000004)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK                 0x000000ff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_SHFT                          0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK           0x000000ff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT                  0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x)             (x+0x00000008)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_PHYS(x)             (x+0x00000008)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK                0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SHFT                         0
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT        0x9
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT        0x4
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f
+#define HWIO_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x)          (x+0x0000000c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_PHYS(x)          (x+0x0000000c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK             0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_SHFT                      0
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)            \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(x, mask)     \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(x, val)      \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x)         (x+0x00000010)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_PHYS(x)         (x+0x00000010)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK            0x80000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SHFT                     0
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(x, mask)    \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(x, val)     \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT       0x1f
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK 0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x)               (x+0x00000014)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_PHYS(x)               (x+0x00000014)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK                  0x01010101
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_SHFT                           0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)                 \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUT(x, val)           \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT       0x18
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT        0x8
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x)              (x+0x00000018)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_PHYS(x)              (x+0x00000018)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK                 0x003f3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_SHFT                          0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)                \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(x, mask)         \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUT(x, val)          \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT        0x8
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x)        (x+0x0000001c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_PHYS(x)        (x+0x0000001c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK           0xffff3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_SHFT                    0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)          \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(x, mask)   \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(x, val)    \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x)        (x+0x00000020)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_PHYS(x)        (x+0x00000020)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK           0xffff3f3f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_SHFT                    0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)          \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(x, mask)   \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(x, val)    \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x)           (x+0x00000024)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_PHYS(x)           (x+0x00000024)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK              0x007fffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_SHFT                       0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT       0x14
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT       0x11
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x)           (x+0x00000028)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_PHYS(x)           (x+0x00000028)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK              0xffff0001
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_SHFT                       0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(x, mask)      \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(x, val)       \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x)            (x+0x0000002c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_PHYS(x)            (x+0x0000002c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK               0x0000ffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_SHFT                        0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)              \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(x, mask)       \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUT(x, val)        \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x)          (x+0x00000030)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_PHYS(x)          (x+0x00000030)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK             0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_SHFT                      0
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)            \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(x, mask)     \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUT(x, val)      \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT       0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x)                  (x+0x00000034)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_PHYS(x)                  (x+0x00000034)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK                     0x01ffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SHFT                              0
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)                    \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(x, mask)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(x, val)              \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK             0x01000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT                   0x18
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK         0x00fff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT                0xc
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK         0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT                0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_HOST_IE_1 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x)                  (x+0x00000038)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_PHYS(x)                  (x+0x00000038)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK                     0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_SHFT                              0
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)                    \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(x, mask)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(x, val)              \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK         0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT                0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_SECURITY ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x)                   (x+0x0000003c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_PHYS(x)                   (x+0x0000003c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK                      0x00ffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SHFT                               0
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)                     \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_INM(x, mask)              \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(x, val)               \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK                 0x00fff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT                        0xc
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK                  0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT                         0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x)                (x+0x00000040)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_PHYS(x)                (x+0x00000040)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK                   0x01ffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK           0x01000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT                 0x18
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK       0x00fff000
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT              0xc
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK       0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT              0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_TARGET_IE_1 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x)                (x+0x00000044)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_PHYS(x)                (x+0x00000044)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK                   0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK       0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT              0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x)       (x+0x00000048)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_PHYS(x)       (x+0x00000048)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK          0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SHFT                   0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT          0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x)       (x+0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_PHYS(x)       (x+0x0000004c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK          0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SHFT                   0
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)         \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(x, mask)  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(x, val)   \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK   0x00000001
+#define HWIO_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT          0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x)                (x+0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_PHYS(x)                (x+0x00000050)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK             0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT                    0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x)                (x+0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_PHYS(x)                (x+0x00000054)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK             0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT                    0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x)                (x+0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_PHYS(x)                (x+0x00000058)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK             0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT                    0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3 ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x)                (x+0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_PHYS(x)                (x+0x0000005c)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK             0xffffffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT                    0x0
+
+//// Register WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS ////
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x)               (x+0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_PHYS(x)               (x+0x00000060)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK                  0xfffdffff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_SHFT                           0
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)                 \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_RMSK)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_INM(x, mask)          \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUT(x, val)           \
+	out_dword( HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_BMSK       0x80000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CLK_EXTEND_SHFT             0x1f
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_BMSK  0x40000000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_WRAPPER_REG_CLK_SHFT        0x1e
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_BMSK      0x3ffc0000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_REG_CLK_SHFT            0x12
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_BMSK           0x00010000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_IC_CLK_SHFT                 0x10
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_BMSK          0x0000f000
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_DMA_CLK_SHFT                 0xc
+
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_BMSK     0x00000fff
+#define HWIO_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_CSM_CORE_CLK_SHFT            0x0
+
+//// Register WFSS_CE_COMMON_R1_TESTBUS_CTRL ////
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x)                  (x+0x00000400)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_PHYS(x)                  (x+0x00000400)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK                     0x000000ff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_SHFT                              0
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)                    \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(x, mask)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(x, val)              \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK  0x000000ff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT         0x0
+
+//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x)                (x+0x00000404)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_PHYS(x)                (x+0x00000404)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK              0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT                     0x0
+
+//// Register WFSS_CE_COMMON_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x)                (x+0x00000408)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_PHYS(x)                (x+0x00000408)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK                   0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_SHFT                            0
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)                  \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(x, mask)           \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(x, val)            \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK              0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT                     0x0
+
+//// Register WFSS_CE_COMMON_R1_TESTBUS_LOW ////
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x)                   (x+0x0000040c)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_PHYS(x)                   (x+0x0000040c)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK                      0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_SHFT                               0
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)                     \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(x, mask)              \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUT(x, val)               \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK                  0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT                         0x0
+
+//// Register WFSS_CE_COMMON_R1_TESTBUS_HIGH ////
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x)                  (x+0x00000410)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_PHYS(x)                  (x+0x00000410)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK                     0x000000ff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_SHFT                              0
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)                    \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(x, mask)             \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUT(x, val)              \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK                 0x000000ff
+#define HWIO_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT                        0x0
+
+//// Register WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)     (x+0x00000414)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x)     (x+0x00000414)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK        0xffffffff
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT                 0
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)       \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT       0x11
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT        0x2
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT        0x1
+
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT        0x0
+
+//// Register WFSS_CE_COMMON_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x)             (x+0x00000418)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_PHYS(x)             (x+0x00000418)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK                0x00000001
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_SHFT                         0
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)               \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(x, mask)        \
+	in_dword_masked ( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(x, val)         \
+	out_dword( HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block WFSS_CE_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+
+#endif
+

hw/qca6290/v1/wfss_pmm_base_struct.h

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//////////////////////////////////////////////////////////////////////////////
+// wfss_pmm_base_struct.h generated by: GenCStruct.pm 
+//////////////////////////////////////////////////////////////////////////////
+// **** W A R N I N G ****  THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
+//////////////////////////////////////////////////////////////////////////////
+// RCS File        : -USE CVS LOG-
+// Revision        : -USE CVS LOG-
+// Last Check In   : -USE CVS LOG-
+//////////////////////////////////////////////////////////////////////////////
+// Description     : Top C Struct file
+//
+//////////////////////////////////////////////////////////////////////////////
+
+#ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+   #ifdef _LSB_TO_MSB_REGS
+      #ifdef _MSB_TO_LSB_REGS
+         #error You can not define both _LSB_TO_MSB_REGS and _MSB_TO_LSB_REGS!
+      #endif
+
+      #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+      #include "wfss_pmm_base_struct_ltm.h"
+   #endif
+
+   #ifdef _MSB_TO_LSB_REGS
+      #define WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+      #include "wfss_pmm_base_struct_mtl.h"
+   #endif
+
+   #ifndef WFSS_PMM_BASE_STUCT_HEADER_INCLUDED
+      #error You have to define _LSB_TO_MSB_REGS or _MSB_TO_LSB_REGS
+   #endif
+
+#endif
+

hw/qca8074/v1/HALcomdef.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_COMDEF_H
+#define HAL_COMDEF_H
+/*
+==============================================================================
+
+FILE:         HALcomdef.h
+
+DESCRIPTION:
+
+==============================================================================
+
+                             Edit History
+
+$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/HALcomdef.h,v 1.1.1.1 2012/09/19 22:33:29 rjindal Exp $
+
+when       who     what, where, why
+--------   ---     -----------------------------------------------------------
+06/17/10   sc      Included com_dtypes.h and cleaned up typedefs
+05/15/08   gfr     Added HAL_ENUM_32BITS macro.
+02/14/08   gfr     Added bool32 type.
+11/13/07   gfr     Removed dependency on comdef.h
+01/08/07   hxw     Created
+
+*/
+
+
+/*
+ * Assembly wrapper
+ */
+#ifndef _ARM_ASM_
+
+/*
+ * C++ wrapper
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "com_dtypes.h"
+
+/* -----------------------------------------------------------------------
+** Types
+** ----------------------------------------------------------------------- */
+
+/*
+ * Standard integer types.
+ *
+ * bool32  - boolean, 32 bit (TRUE or FALSE)
+ */
+#ifndef _BOOL32_DEFINED
+typedef  unsigned long int  bool32;
+#define _BOOL32_DEFINED
+#endif
+
+/*
+ * Macro to allow forcing an enum to 32 bits.  The argument should be
+ * an identifier in the namespace of the enumeration in question, i.e.
+ * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
+ */
+#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF
+
+/*===========================================================================
+
+FUNCTION inp, outp, inpw, outpw, inpdw, outpdw
+
+DESCRIPTION
+  IN/OUT port macros for byte and word ports, typically inlined by compilers
+  which support these routines
+
+PARAMETERS
+  inp(   xx_addr )
+  inpw(  xx_addr )
+  inpdw( xx_addr )
+  outp(   xx_addr, xx_byte_val  )
+  outpw(  xx_addr, xx_word_val  )
+  outpdw( xx_addr, xx_dword_val )
+      xx_addr      - Address of port to read or write (may be memory mapped)
+      xx_byte_val  - 8 bit value to write
+      xx_word_val  - 16 bit value to write
+      xx_dword_val - 32 bit value to write
+
+DEPENDENCIES
+  None
+
+RETURN VALUE
+  inp/inpw/inpdw: the byte, word or dword read from the given address
+  outp/outpw/outpdw: the byte, word or dword written to the given address
+
+SIDE EFFECTS
+  None.
+
+===========================================================================*/
+
+  /* ARM based targets use memory mapped i/o, so the inp/outp calls are
+  ** macroized to access memory directly
+  */
+
+  #define inp(port)         (*((volatile byte *) (port)))
+  #define inpw(port)        (*((volatile word *) (port)))
+  #define inpdw(port)       (*((volatile dword *)(port)))
+
+  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
+  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
+  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ARM_ASM_ */
+
+#endif /* HAL_COMDEF_H */
+

hw/qca8074/v1/HALhwio.h

@@ -0,0 +1,490 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef HAL_HWIO_H
+#define HAL_HWIO_H
+/*
+===========================================================================
+*/
+/**
+  @file HALhwio.h 
+  
+  Public interface include file for accessing the HWIO HAL definitions.
+  
+  The HALhwio.h file is the public API interface to the HW I/O (HWIO)
+  register access definitions.
+*/
+
+/*=========================================================================
+      Include Files
+==========================================================================*/
+
+
+/*
+ * Common types.
+ */
+#include "HALcomdef.h"
+
+
+
+/* -----------------------------------------------------------------------
+** Macros
+** ----------------------------------------------------------------------- */
+
+/** 
+  @addtogroup macros
+  @{ 
+*/ 
+
+/**
+ * Map a base name to the pointer to access the base.
+ *
+ * This macro maps a base name to the pointer to access the base.
+ * This is generally just used internally.
+ *
+ */
+#define HWIO_BASE_PTR(base) base##_BASE_PTR
+
+
+/**
+ * Declare a HWIO base pointer.
+ *
+ * This macro will declare a HWIO base pointer data structure.  The pointer
+ * will always be declared as a weak symbol so multiple declarations will
+ * resolve correctly to the same data at link-time.
+ */
+#ifdef __ARMCC_VERSION
+  #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base)
+#else
+  #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base)
+#endif
+
+/**
+  @}
+*/
+
+
+/** 
+  @addtogroup hwio_macros
+  @{ 
+*/ 
+
+/**
+ * @name Address Macros
+ *
+ * Macros for getting register addresses.
+ * These macros are used for retrieving the address of a register.
+ * HWIO_ADDR* will return the directly accessible address (virtual or physical based
+ * on environment), HWIO_PHYS* will always return the physical address.
+ * The offset from the base region can be retrieved using HWIO_OFFS*.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * @{
+ */
+#define HWIO_ADDR(hwiosym)                               __msmhwio_addr(hwiosym)
+#define HWIO_ADDRI(hwiosym, index)                       __msmhwio_addri(hwiosym, index)
+#define HWIO_ADDRI2(hwiosym, index1, index2)             __msmhwio_addri2(hwiosym, index1, index2)
+#define HWIO_ADDRI3(hwiosym, index1, index2, index3)     __msmhwio_addri3(hwiosym, index1, index2, index3)
+
+#define HWIO_ADDRX(base, hwiosym)                           __msmhwio_addrx(base, hwiosym)
+#define HWIO_ADDRXI(base, hwiosym, index)                   __msmhwio_addrxi(base, hwiosym, index)
+#define HWIO_ADDRXI2(base, hwiosym, index1, index2)         __msmhwio_addrxi2(base, hwiosym, index1, index2)
+#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_PHYS(hwiosym)                               __msmhwio_phys(hwiosym)
+#define HWIO_PHYSI(hwiosym, index)                       __msmhwio_physi(hwiosym, index)
+#define HWIO_PHYSI2(hwiosym, index1, index2)             __msmhwio_physi2(hwiosym, index1, index2)
+#define HWIO_PHYSI3(hwiosym, index1, index2, index3)     __msmhwio_physi3(hwiosym, index1, index2, index3)
+
+#define HWIO_PHYSX(base, hwiosym)                           __msmhwio_physx(base, hwiosym)
+#define HWIO_PHYSXI(base, hwiosym, index)                   __msmhwio_physxi(base, hwiosym, index)
+#define HWIO_PHYSXI2(base, hwiosym, index1, index2)         __msmhwio_physxi2(base, hwiosym, index1, index2)
+#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_OFFS(hwiosym)                               __msmhwio_offs(hwiosym)
+#define HWIO_OFFSI(hwiosym, index)                       __msmhwio_offsi(hwiosym, index)
+#define HWIO_OFFSI2(hwiosym, index1, index2)             __msmhwio_offsi2(hwiosym, index1, index2)
+#define HWIO_OFFSI3(hwiosym, index1, index2, index3)     __msmhwio_offsi3(hwiosym, index1, index2, index3)
+/** @} */
+
+/**
+ * @name Input Macros
+ *
+ * These macros are used for reading from a named hardware register.  Register
+ * arrays ("indexed") use the macros with the "I" suffix.  The "M" suffix
+ * indicates that the input will be masked with the supplied mask.  The HWIO_INF*
+ * macros take a field name and will do the appropriate masking and shifting
+ * to return just the value of that field.
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ *
+ * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_IN(hwiosym)                                         __msmhwio_in(hwiosym)
+#define HWIO_INI(hwiosym, index)                                 __msmhwio_ini(hwiosym, index)
+#define HWIO_INI2(hwiosym, index1, index2)                       __msmhwio_ini2(hwiosym, index1, index2)
+#define HWIO_INI3(hwiosym, index1, index2, index3)               __msmhwio_ini3(hwiosym, index1, index2, index3)
+
+#define HWIO_INM(hwiosym, mask)                                  __msmhwio_inm(hwiosym, mask)
+#define HWIO_INMI(hwiosym, index, mask)                          __msmhwio_inmi(hwiosym, index, mask)
+#define HWIO_INMI2(hwiosym, index1, index2, mask)                __msmhwio_inmi2(hwiosym, index1, index2, mask)
+#define HWIO_INMI3(hwiosym, index1, index2, index3, mask)        __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INF(io, field)                                      (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI(io, index, field)                              (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI2(io, index1, index2, field)                    (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INFI3(io, index1, index2, index3, field)            (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+
+#define HWIO_INX(base, hwiosym)                                  __msmhwio_inx(base, hwiosym)
+#define HWIO_INXI(base, hwiosym, index)                          __msmhwio_inxi(base, hwiosym, index)
+#define HWIO_INXI2(base, hwiosym, index1, index2)                __msmhwio_inxi2(base, hwiosym, index1, index2)
+#define HWIO_INXI3(base, hwiosym, index1, index2, index3)        __msmhwio_inxi3(base, hwiosym, index1, index2, index3)
+
+#define HWIO_INXM(base, hwiosym, mask)                           __msmhwio_inxm(base, hwiosym, mask)
+#define HWIO_INXMI(base, hwiosym, index, mask)                   __msmhwio_inxmi(base, hwiosym, index, mask)
+#define HWIO_INXMI2(base, hwiosym, index1, index2, mask)         __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)
+#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask)
+
+#define HWIO_INXF(base, io, field)                               (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI(base, io, index, field)                       (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI2(base, io, index1, index2, field)             (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+#define HWIO_INXFI3(base, io, index1, index2, index3, field)     (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Output Macros
+ *
+ * These macros are used for writing to a named hardware register.  Register
+ * arrays ("indexed") use the macros with the "I" suffix.  The "M" suffix
+ * indicates that the output will be masked with the supplied mask (meaning these
+ * macros do a read first, mask in the supplied data, then write it back).
+ * The "X" extension is used for explicit addressing where the base address of
+ * the module in question is provided as an argument to the macro.
+ * The HWIO_OUTF* macros take a field name and will do the appropriate masking
+ * and shifting to output just the value of that field.
+ * HWIO_OUTV* registers take a named value instead of a numeric value and
+ * do the same masking/shifting as HWIO_OUTF.
+ *
+ * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing).
+ *
+ * @{
+ */
+#define HWIO_OUT(hwiosym, val)                                   __msmhwio_out(hwiosym, val)
+#define HWIO_OUTI(hwiosym, index, val)                           __msmhwio_outi(hwiosym, index, val)
+#define HWIO_OUTI2(hwiosym, index1, index2, val)                 __msmhwio_outi2(hwiosym, index1, index2, val)
+#define HWIO_OUTI3(hwiosym, index1, index2, index3, val)         __msmhwio_outi3(hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTM(hwiosym, mask, val)                            __msmhwio_outm(hwiosym, mask, val)
+#define HWIO_OUTMI(hwiosym, index, mask, val)                    __msmhwio_outmi(hwiosym, index, mask, val)
+#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val)          __msmhwio_outmi2(hwiosym, index1, index2, mask, val)
+#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val)  __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTF(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTFI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTV(io, field, val)                                HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI(io, index, field, val)                        HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI2(io, index1, index2, field, val)              HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTVI3(io, index1, index2, index3, field, val)      HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTX(base, hwiosym, val)                                   __msmhwio_outx(base, hwiosym, val)
+#define HWIO_OUTXI(base, hwiosym, index, val)                           __msmhwio_outxi(base, hwiosym, index, val)
+#define HWIO_OUTXI2(base, hwiosym, index1, index2, val)                 __msmhwio_outxi2(base, hwiosym, index1, index2, val)
+#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val)         __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)
+
+#define HWIO_OUTXM(base, hwiosym, mask, val)                            __msmhwio_outxm(base, hwiosym, mask, val)
+#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2)  __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)
+#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3)
+#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4)
+#define HWIO_OUTXMI(base, hwiosym, index, mask, val)                    __msmhwio_outxmi(base, hwiosym, index, mask, val)
+#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val)          __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val)
+#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val)  __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val)
+
+#define HWIO_OUTXF(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTX2F(base, io, field1, field2, val1, val2)                                HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2))
+#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3)                                HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) )
+#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4)                                HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1),  HWIO_FMSK(io, field2),  HWIO_FMSK(io, field3),  HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) )
+
+#define HWIO_OUTXFI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field))
+
+#define HWIO_OUTXV(base, io, field, val)                                HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI(base, io, index, field, val)                        HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI2(base, io, index1, index2, field, val)              HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val)      HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field))
+/** @} */
+
+/**
+ * @name Shift and Mask Macros
+ *
+ * Macros for getting shift and mask values for fields and registers.
+ *  HWIO_RMSK: The mask value for accessing an entire register.  For example:
+ *             @code
+ *             HWIO_RMSK(REG) -> 0xFFFFFFFF
+ *             @endcode
+ *  HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n
+ *  HWIO_SHFT: The right-shift value for accessing a field in a register.  For example:
+ *             @code
+ *             HWIO_SHFT(REG, FLD) -> 8
+ *             @endcode
+ *  HWIO_FMSK: The mask value for accessing a field in a register.  For example:
+ *             @code
+ *             HWIO_FMSK(REG, FLD) -> 0xFF00
+ *             @endcode
+ *  HWIO_VAL:  The value for a field in a register.  For example:
+ *             @code
+ *             HWIO_VAL(REG, FLD, ON) -> 0x1
+ *             @endcode
+ *  HWIO_FVAL: This macro takes a numerical value and will shift and mask it into
+ *             the given field position.  For example:
+ *             @code
+ *             HWIO_FVAL(REG, FLD, 0x1) -> 0x100
+ *             @endcode
+ *  HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it
+ *              into the given field position.  For example:
+ *              @code
+ *              HWIO_FVALV(REG, FLD, ON) -> 0x100
+ *              @endcode
+ *
+ * @{
+ */
+#define HWIO_RMSK(hwiosym)                               __msmhwio_rmsk(hwiosym)
+#define HWIO_RMSKI(hwiosym, index)                       __msmhwio_rmski(hwiosym, index)
+#define HWIO_RSHFT(hwiosym)                              __msmhwio_rshft(hwiosym)
+#define HWIO_SHFT(hwio_regsym, hwio_fldsym)              __msmhwio_shft(hwio_regsym, hwio_fldsym)
+#define HWIO_FMSK(hwio_regsym, hwio_fldsym)              __msmhwio_fmsk(hwio_regsym, hwio_fldsym)
+#define HWIO_VAL(io, field, val)                         __msmhwio_val(io, field, val)
+#define HWIO_FVAL(io, field, val)                        (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+#define HWIO_FVALV(io, field, val)                       (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field))
+/** @} */
+
+/**
+ * @name Shadow Register Macros
+ *
+ * These macros are used for directly reading the value stored in a 
+ * shadow register.
+ * Shadow registers are defined for write-only registers.  Generally these
+ * macros should not be necessary as HWIO_OUTM* macros will automatically use
+ * the shadow values internally.
+ *
+ * @{
+ */
+#define HWIO_SHDW(hwiosym)                               __msmhwio_shdw(hwiosym)
+#define HWIO_SHDWI(hwiosym, index)                       __msmhwio_shdwi(hwiosym, index)
+/** @} */
+
+/** 
+  @}
+*/ /* end_group */
+
+
+/** @cond */
+
+/*
+ * Map to final symbols.  This remapping is done to allow register 
+ * redefinitions.  If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN
+ * then remappings like "#define xreg xregnew" do not work as expected.
+ */
+#define __msmhwio_in(hwiosym)                                   HWIO_##hwiosym##_IN
+#define __msmhwio_ini(hwiosym, index)                           HWIO_##hwiosym##_INI(index)
+#define __msmhwio_ini2(hwiosym, index1, index2)                 HWIO_##hwiosym##_INI2(index1, index2)
+#define __msmhwio_ini3(hwiosym, index1, index2, index3)         HWIO_##hwiosym##_INI3(index1, index2, index3)
+#define __msmhwio_inm(hwiosym, mask)                            HWIO_##hwiosym##_INM(mask)
+#define __msmhwio_inmi(hwiosym, index, mask)                    HWIO_##hwiosym##_INMI(index, mask)
+#define __msmhwio_inmi2(hwiosym, index1, index2, mask)          HWIO_##hwiosym##_INMI2(index1, index2, mask)
+#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask)  HWIO_##hwiosym##_INMI3(index1, index2, index3, mask)
+#define __msmhwio_out(hwiosym, val)                             HWIO_##hwiosym##_OUT(val)
+#define __msmhwio_outi(hwiosym, index, val)                     HWIO_##hwiosym##_OUTI(index,val)
+#define __msmhwio_outi2(hwiosym, index1, index2, val)           HWIO_##hwiosym##_OUTI2(index1, index2, val)
+#define __msmhwio_outi3(hwiosym, index1, index2, index3, val)   HWIO_##hwiosym##_OUTI2(index1, index2, index3, val)
+#define __msmhwio_outm(hwiosym, mask, val)                      HWIO_##hwiosym##_OUTM(mask, val)
+#define __msmhwio_outmi(hwiosym, index, mask, val)              HWIO_##hwiosym##_OUTMI(index, mask, val)
+#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val)        HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val)
+#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val)  HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val)
+#define __msmhwio_addr(hwiosym)                                 HWIO_##hwiosym##_ADDR
+#define __msmhwio_addri(hwiosym, index)                         HWIO_##hwiosym##_ADDR(index)
+#define __msmhwio_addri2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_ADDR(idx1, idx2)
+#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_ADDR(idx1, idx2, idx3)
+#define __msmhwio_phys(hwiosym)                                 HWIO_##hwiosym##_PHYS
+#define __msmhwio_physi(hwiosym, index)                         HWIO_##hwiosym##_PHYS(index)
+#define __msmhwio_physi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_PHYS(idx1, idx2)
+#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_PHYS(idx1, idx2, idx3)
+#define __msmhwio_offs(hwiosym)                                 HWIO_##hwiosym##_OFFS 
+#define __msmhwio_offsi(hwiosym, index)                         HWIO_##hwiosym##_OFFS(index)
+#define __msmhwio_offsi2(hwiosym, idx1, idx2)                   HWIO_##hwiosym##_OFFS(idx1, idx2)
+#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3)             HWIO_##hwiosym##_OFFS(idx1, idx2, idx3)
+#define __msmhwio_rmsk(hwiosym)                                 HWIO_##hwiosym##_RMSK
+#define __msmhwio_rmski(hwiosym, index)                         HWIO_##hwiosym##_RMSK(index)
+#define __msmhwio_fmsk(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_BMSK
+#define __msmhwio_rshft(hwiosym)                                HWIO_##hwiosym##_SHFT
+#define __msmhwio_shft(hwiosym, hwiofldsym)                     HWIO_##hwiosym##_##hwiofldsym##_SHFT
+#define __msmhwio_shdw(hwiosym)                                 HWIO_##hwiosym##_shadow
+#define __msmhwio_shdwi(hwiosym, index)                         HWIO_##hwiosym##_SHDW(index)
+#define __msmhwio_val(hwiosym, hwiofld, hwioval)                HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL
+
+#define __msmhwio_inx(base, hwiosym)                                  HWIO_##hwiosym##_IN(base)
+#define __msmhwio_inxi(base, hwiosym, index)                          HWIO_##hwiosym##_INI(base, index)
+#define __msmhwio_inxi2(base, hwiosym, index1, index2)                HWIO_##hwiosym##_INI2(base, index1, index2)
+#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3)        HWIO_##hwiosym##_INI3(base, index1, index2, index3)
+#define __msmhwio_inxm(base, hwiosym, mask)                           HWIO_##hwiosym##_INM(base, mask)
+#define __msmhwio_inxmi(base, hwiosym, index, mask)                   HWIO_##hwiosym##_INMI(base, index, mask)
+#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask)         HWIO_##hwiosym##_INMI2(base, index1, index2, mask)
+#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask)
+#define __msmhwio_outx(base, hwiosym, val)                            HWIO_##hwiosym##_OUT(base, val)
+#define __msmhwio_outxi(base, hwiosym, index, val)                    HWIO_##hwiosym##_OUTI(base, index,val)
+#define __msmhwio_outxi2(base, hwiosym, index1, index2, val)          HWIO_##hwiosym##_OUTI2(base, index1, index2, val)
+#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val)  HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val)
+#define __msmhwio_outxm(base, hwiosym, mask, val)                     HWIO_##hwiosym##_OUTM(base, mask, val)
+#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2)  {	\
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                               }
+#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3,  val1, val2, val3) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                               }  
+#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask1, val1); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask2, val2); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask3, val3); \
+                                                                                HWIO_##hwiosym##_OUTM(base, mask4, val4); \
+                                                                               } 
+
+
+#define __msmhwio_outxmi(base, hwiosym, index, mask, val)             HWIO_##hwiosym##_OUTMI(base, index, mask, val)
+#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val)       HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val)
+#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val)
+#define __msmhwio_addrx(base, hwiosym)                                HWIO_##hwiosym##_ADDR(base)
+#define __msmhwio_addrxi(base, hwiosym, index)                        HWIO_##hwiosym##_ADDR(base, index)
+#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_ADDR(base, idx1, idx2)
+#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3)
+#define __msmhwio_physx(base, hwiosym)                                HWIO_##hwiosym##_PHYS(base)
+#define __msmhwio_physxi(base, hwiosym, index)                        HWIO_##hwiosym##_PHYS(base, index)
+#define __msmhwio_physxi2(base, hwiosym, idx1, idx2)                  HWIO_##hwiosym##_PHYS(base, idx1, idx2)
+#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3)            HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3)
+
+
+/*
+ * HWIO_INTLOCK
+ *
+ * Macro used by autogenerated code for mutual exclusion around
+ * read-mask-write operations.  This is not supported in HAL
+ * code but can be overridden by non-HAL code.
+ */
+#define HWIO_INTLOCK()
+#define HWIO_INTFREE()
+
+
+/*
+ * Input/output port macros for memory mapped IO.
+ */
+#define __inp(port)         (*((volatile uint8 *) (port)))
+#define __inpw(port)        (*((volatile uint16 *) (port)))
+#define __inpdw(port)       (*((volatile uint32 *) (port)))
+#define __outp(port, val)   (*((volatile uint8 *) (port)) = ((uint8) (val)))
+#define __outpw(port, val)  (*((volatile uint16 *) (port)) = ((uint16) (val)))
+#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val)))
+
+
+#ifdef HAL_HWIO_EXTERNAL
+
+/*
+ * Replace macros with externally supplied functions.
+ */
+#undef  __inp
+#undef  __inpw
+#undef  __inpdw
+#undef  __outp
+#undef  __outpw
+#undef  __outpdw
+
+#define  __inp(port)          __inp_extern(port)         
+#define  __inpw(port)         __inpw_extern(port)
+#define  __inpdw(port)        __inpdw_extern(port)
+#define  __outp(port, val)    __outp_extern(port, val)
+#define  __outpw(port, val)   __outpw_extern(port, val)
+#define  __outpdw(port, val)  __outpdw_extern(port, val)
+
+extern uint8   __inp_extern      ( uint32 nAddr );
+extern uint16  __inpw_extern     ( uint32 nAddr );
+extern uint32  __inpdw_extern    ( uint32 nAddr );
+extern void    __outp_extern     ( uint32 nAddr, uint8  nData );
+extern void    __outpw_extern    ( uint32 nAddr, uint16 nData );
+extern void    __outpdw_extern   ( uint32 nAddr, uint32 nData );
+
+#endif /* HAL_HWIO_EXTERNAL */
+
+
+/*
+ * Base 8-bit byte accessing macros.
+ */
+#define in_byte(addr)               (__inp(addr))
+#define in_byte_masked(addr, mask)  (__inp(addr) & (mask)) 
+#define out_byte(addr, val)         __outp(addr,val)
+#define out_byte_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK();    \
+  out_byte( io, shadow); \
+  shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \
+  HWIO_INTFREE()
+#define out_byte_masked_ns(io, mask, val, current_reg_content)  \
+  out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 16-bit word accessing macros.
+ */
+#define in_word(addr)              (__inpw(addr))
+#define in_word_masked(addr, mask) (__inpw(addr) & (mask))
+#define out_word(addr, val)        __outpw(addr,val)
+#define out_word_masked(io, mask, val, shadow)  \
+  HWIO_INTLOCK( ); \
+  shadow = (shadow & (uint16)(~(mask))) |  ((uint16)((val) & (mask))); \
+  out_word( io, shadow); \
+  HWIO_INTFREE( )
+#define out_word_masked_ns(io, mask, val, current_reg_content)  \
+  out_word( io, ((current_reg_content & (uint16)(~(mask))) | \
+                ((uint16)((val) & (mask)))) )
+
+
+/*
+ * Base 32-bit double-word accessing macros.
+ */
+#define in_dword(addr)              (__inpdw(addr))
+#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask))
+#define out_dword(addr, val)        __outpdw(addr,val)
+#define out_dword_masked(io, mask, val, shadow)  \
+   HWIO_INTLOCK(); \
+   shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \
+   out_dword( io, shadow); \
+   HWIO_INTFREE()
+#define out_dword_masked_ns(io, mask, val, current_reg_content) \
+  out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \
+                 ((uint32)((val) & (mask)))) )
+
+/** @endcond */
+
+#endif /* HAL_HWIO_H */
+

hw/qca8074/v1/buffer_addr_info.h

@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _BUFFER_ADDR_INFO_H_
+#define _BUFFER_ADDR_INFO_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	buffer_addr_31_0[31:0]
+//	1	buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2
+
+struct buffer_addr_info {
+             uint32_t buffer_addr_31_0                : 32; //[31:0]
+             uint32_t buffer_addr_39_32               :  8, //[7:0]
+                      return_buffer_manager           :  3, //[10:8]
+                      sw_buffer_cookie                : 21; //[31:11]
+};
+
+/*
+
+buffer_addr_31_0
+			
+			Address (lower 32 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+
+buffer_addr_39_32
+			
+			Address (upper 8 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+
+return_buffer_manager
+			
+			Consumer: WBM
+			
+			Producer: SW/FW
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			Indicates to which buffer manager the buffer OR
+			MSDU_EXTENSION descriptor OR link descriptor that is being
+			pointed to shall be returned after the frame has been
+			processed. It is used by WBM for routing purposes.
+			
+			
+			
+			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+			to the WMB buffer idle list
+			
+			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+			returned to the WMB idle link descriptor idle list
+			
+			<enum 2 FW_BM> This buffer shall be returned to the FW
+			
+			<enum 3 SW0_BM> This buffer shall be returned to the SW,
+			ring 0
+			
+			<enum 4 SW1_BM> This buffer shall be returned to the SW,
+			ring 1
+			
+			<enum 5 SW2_BM> This buffer shall be returned to the SW,
+			ring 2
+			
+			<enum 6 SW3_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			
+			
+			<legal 0-6>
+
+sw_buffer_cookie
+			
+			Cookie field exclusively used by SW. 
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			HW ignores the contents, accept that it passes the
+			programmed value on to other descriptors together with the
+			physical address 
+			
+			
+			
+			Field can be used by SW to for example associate the
+			buffers physical address with the virtual address
+			
+			The bit definitions as used by SW are within SW HLD
+			specification
+			
+			
+			
+			NOTE:
+			
+			The two most significant bits can have a special meaning
+			in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
+			and field transmit_bw_restriction is set
+			
+			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+			
+			
+			
+			<legal all>
+*/
+
+
+/* Description		BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0
+			
+			Address (lower 32 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET                   0x00000000
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB                      0
+#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK                     0xffffffff
+
+/* Description		BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32
+			
+			Address (upper 8 bits) of the MSDU buffer OR
+			MSDU_EXTENSION descriptor OR Link Descriptor
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET                  0x00000004
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB                     0
+#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK                    0x000000ff
+
+/* Description		BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER
+			
+			Consumer: WBM
+			
+			Producer: SW/FW
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			Indicates to which buffer manager the buffer OR
+			MSDU_EXTENSION descriptor OR link descriptor that is being
+			pointed to shall be returned after the frame has been
+			processed. It is used by WBM for routing purposes.
+			
+			
+			
+			<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
+			to the WMB buffer idle list
+			
+			<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
+			returned to the WMB idle link descriptor idle list
+			
+			<enum 2 FW_BM> This buffer shall be returned to the FW
+			
+			<enum 3 SW0_BM> This buffer shall be returned to the SW,
+			ring 0
+			
+			<enum 4 SW1_BM> This buffer shall be returned to the SW,
+			ring 1
+			
+			<enum 5 SW2_BM> This buffer shall be returned to the SW,
+			ring 2
+			
+			<enum 6 SW3_BM> This buffer shall be returned to the SW,
+			ring 3
+			
+			
+			
+			<legal 0-6>
+*/
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET              0x00000004
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB                 8
+#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK                0x00000700
+
+/* Description		BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE
+			
+			Cookie field exclusively used by SW. 
+			
+			
+			
+			In case of 'NULL' pointer, this field is set to 0
+			
+			
+			
+			HW ignores the contents, accept that it passes the
+			programmed value on to other descriptors together with the
+			physical address 
+			
+			
+			
+			Field can be used by SW to for example associate the
+			buffers physical address with the virtual address
+			
+			The bit definitions as used by SW are within SW HLD
+			specification
+			
+			
+			
+			NOTE:
+			
+			The two most significant bits can have a special meaning
+			in case this struct is embedded in a TX_MPDU_DETAILS STRUCT,
+			and field transmit_bw_restriction is set
+			
+			Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only
+			
+			Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only
+			
+			
+			
+			<legal all>
+*/
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET                   0x00000004
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB                      11
+#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK                     0xfffff800
+
+
+#endif // _BUFFER_ADDR_INFO_H_

hw/qca8074/v1/ce_src_desc.h

@@ -0,0 +1,360 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _CE_SRC_DESC_H_
+#define _CE_SRC_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	src_buffer_low[31:0]
+//	1	src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
+//	2	fw_metadata[15:0], ce_res_1[31:16]
+//	3	ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_SRC_DESC 4
+
+struct ce_src_desc {
+             uint32_t src_buffer_low                  : 32; //[31:0]
+             uint32_t src_buffer_high                 :  8, //[7:0]
+                      toeplitz_en                     :  1, //[8]
+                      src_swap                        :  1, //[9]
+                      dest_swap                       :  1, //[10]
+                      gather                          :  1, //[11]
+                      ce_res_0                        :  4, //[15:12]
+                      length                          : 16; //[31:16]
+             uint32_t fw_metadata                     : 16, //[15:0]
+                      ce_res_1                        : 16; //[31:16]
+             uint32_t ce_res_2                        : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+src_buffer_low
+			
+			LSB 32 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+
+src_buffer_high
+			
+			MSB 8 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+
+toeplitz_en
+			
+			Enable generation of 32-bit Toeplitz-LFSR hash for the
+			data transfer
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+src_swap
+			
+			Treats source memory organization as big-endian. For
+			each dword read (4 bytes), the byte 0 is swapped with byte 3
+			and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+dest_swap
+			
+			Treats destination memory organization as big-endian.
+			For each dword write (4 bytes), the byte 0 is swapped with
+			byte 3 and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+gather
+			
+			Enables gather of multiple copy engine source
+			descriptors to one destination.
+			
+			<legal all>
+
+ce_res_0
+			
+			Reserved
+			
+			<legal all>
+
+length
+			
+			Length of the buffer in units of octets of the current
+			descriptor
+			
+			<legal all>
+
+fw_metadata
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+ce_res_1
+			
+			Reserved
+			
+			<legal all>
+
+ce_res_2
+			
+			Reserved 
+			
+			<legal all>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		CE_SRC_DESC_0_SRC_BUFFER_LOW
+			
+			LSB 32 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET                          0x00000000
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB                             0
+#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK                            0xffffffff
+
+/* Description		CE_SRC_DESC_1_SRC_BUFFER_HIGH
+			
+			MSB 8 bits of the 40 Bit Pointer to the source buffer
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET                         0x00000004
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB                            0
+#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK                           0x000000ff
+
+/* Description		CE_SRC_DESC_1_TOEPLITZ_EN
+			
+			Enable generation of 32-bit Toeplitz-LFSR hash for the
+			data transfer
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET                             0x00000004
+#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB                                8
+#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK                               0x00000100
+
+/* Description		CE_SRC_DESC_1_SRC_SWAP
+			
+			Treats source memory organization as big-endian. For
+			each dword read (4 bytes), the byte 0 is swapped with byte 3
+			and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_SRC_SWAP_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_SRC_SWAP_LSB                                   9
+#define CE_SRC_DESC_1_SRC_SWAP_MASK                                  0x00000200
+
+/* Description		CE_SRC_DESC_1_DEST_SWAP
+			
+			Treats destination memory organization as big-endian.
+			For each dword write (4 bytes), the byte 0 is swapped with
+			byte 3 and byte 1 is swapped with byte 2.
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_DEST_SWAP_OFFSET                               0x00000004
+#define CE_SRC_DESC_1_DEST_SWAP_LSB                                  10
+#define CE_SRC_DESC_1_DEST_SWAP_MASK                                 0x00000400
+
+/* Description		CE_SRC_DESC_1_GATHER
+			
+			Enables gather of multiple copy engine source
+			descriptors to one destination.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_GATHER_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_GATHER_LSB                                     11
+#define CE_SRC_DESC_1_GATHER_MASK                                    0x00000800
+
+/* Description		CE_SRC_DESC_1_CE_RES_0
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_CE_RES_0_OFFSET                                0x00000004
+#define CE_SRC_DESC_1_CE_RES_0_LSB                                   12
+#define CE_SRC_DESC_1_CE_RES_0_MASK                                  0x0000f000
+
+/* Description		CE_SRC_DESC_1_LENGTH
+			
+			Length of the buffer in units of octets of the current
+			descriptor
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_1_LENGTH_OFFSET                                  0x00000004
+#define CE_SRC_DESC_1_LENGTH_LSB                                     16
+#define CE_SRC_DESC_1_LENGTH_MASK                                    0xffff0000
+
+/* Description		CE_SRC_DESC_2_FW_METADATA
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_2_FW_METADATA_OFFSET                             0x00000008
+#define CE_SRC_DESC_2_FW_METADATA_LSB                                0
+#define CE_SRC_DESC_2_FW_METADATA_MASK                               0x0000ffff
+
+/* Description		CE_SRC_DESC_2_CE_RES_1
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_2_CE_RES_1_OFFSET                                0x00000008
+#define CE_SRC_DESC_2_CE_RES_1_LSB                                   16
+#define CE_SRC_DESC_2_CE_RES_1_MASK                                  0xffff0000
+
+/* Description		CE_SRC_DESC_3_CE_RES_2
+			
+			Reserved 
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_CE_RES_2_OFFSET                                0x0000000c
+#define CE_SRC_DESC_3_CE_RES_2_LSB                                   0
+#define CE_SRC_DESC_3_CE_RES_2_MASK                                  0x000fffff
+
+/* Description		CE_SRC_DESC_3_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_RING_ID_OFFSET                                 0x0000000c
+#define CE_SRC_DESC_3_RING_ID_LSB                                    20
+#define CE_SRC_DESC_3_RING_ID_MASK                                   0x0ff00000
+
+/* Description		CE_SRC_DESC_3_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET                           0x0000000c
+#define CE_SRC_DESC_3_LOOPING_COUNT_LSB                              28
+#define CE_SRC_DESC_3_LOOPING_COUNT_MASK                             0xf0000000
+
+
+#endif // _CE_SRC_DESC_H_

hw/qca8074/v1/ce_stat_desc.h

@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _CE_STAT_DESC_H_
+#define _CE_STAT_DESC_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0	ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16]
+//	1	toeplitz_hash_0[31:0]
+//	2	toeplitz_hash_1[31:0]
+//	3	fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_CE_STAT_DESC 4
+
+struct ce_stat_desc {
+             uint32_t ce_res_5                        :  8, //[7:0]
+                      toeplitz_en                     :  1, //[8]
+                      src_swap                        :  1, //[9]
+                      dest_swap                       :  1, //[10]
+                      gather                          :  1, //[11]
+                      ce_res_6                        :  4, //[15:12]
+                      length                          : 16; //[31:16]
+             uint32_t toeplitz_hash_0                 : 32; //[31:0]
+             uint32_t toeplitz_hash_1                 : 32; //[31:0]
+             uint32_t fw_metadata                     : 16, //[15:0]
+                      ce_res_7                        :  4, //[19:16]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+ce_res_5
+			
+			Reserved
+			
+			<legal all>
+
+toeplitz_en
+			
+			
+			<legal all>
+
+src_swap
+			
+			Source memory buffer swapped
+			
+			<legal all>
+
+dest_swap
+			
+			Destination  memory buffer swapped
+			
+			<legal all>
+
+gather
+			
+			Gather of multiple copy engine source descriptors to one
+			destination enabled
+			
+			<legal all>
+
+ce_res_6
+			
+			Reserved
+			
+			<legal all>
+
+length
+			
+			Sum of all the Lengths of the source descriptor in the
+			gather chain
+			
+			<legal all>
+
+toeplitz_hash_0
+			
+			32 LS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+
+toeplitz_hash_1
+			
+			32 MS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+
+fw_metadata
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+
+ce_res_7
+			
+			Reserved 
+			
+			<legal all>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+
+/* Description		CE_STAT_DESC_0_CE_RES_5
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_5_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_5_LSB                                  0
+#define CE_STAT_DESC_0_CE_RES_5_MASK                                 0x000000ff
+
+/* Description		CE_STAT_DESC_0_TOEPLITZ_EN
+			
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET                            0x00000000
+#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB                               8
+#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK                              0x00000100
+
+/* Description		CE_STAT_DESC_0_SRC_SWAP
+			
+			Source memory buffer swapped
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_SRC_SWAP_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_SRC_SWAP_LSB                                  9
+#define CE_STAT_DESC_0_SRC_SWAP_MASK                                 0x00000200
+
+/* Description		CE_STAT_DESC_0_DEST_SWAP
+			
+			Destination  memory buffer swapped
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_DEST_SWAP_OFFSET                              0x00000000
+#define CE_STAT_DESC_0_DEST_SWAP_LSB                                 10
+#define CE_STAT_DESC_0_DEST_SWAP_MASK                                0x00000400
+
+/* Description		CE_STAT_DESC_0_GATHER
+			
+			Gather of multiple copy engine source descriptors to one
+			destination enabled
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_GATHER_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_GATHER_LSB                                    11
+#define CE_STAT_DESC_0_GATHER_MASK                                   0x00000800
+
+/* Description		CE_STAT_DESC_0_CE_RES_6
+			
+			Reserved
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_CE_RES_6_OFFSET                               0x00000000
+#define CE_STAT_DESC_0_CE_RES_6_LSB                                  12
+#define CE_STAT_DESC_0_CE_RES_6_MASK                                 0x0000f000
+
+/* Description		CE_STAT_DESC_0_LENGTH
+			
+			Sum of all the Lengths of the source descriptor in the
+			gather chain
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_0_LENGTH_OFFSET                                 0x00000000
+#define CE_STAT_DESC_0_LENGTH_LSB                                    16
+#define CE_STAT_DESC_0_LENGTH_MASK                                   0xffff0000
+
+/* Description		CE_STAT_DESC_1_TOEPLITZ_HASH_0
+			
+			32 LS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET                        0x00000004
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB                           0
+#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK                          0xffffffff
+
+/* Description		CE_STAT_DESC_2_TOEPLITZ_HASH_1
+			
+			32 MS bits of 64 bit Toeplitz LFSR hash result
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET                        0x00000008
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB                           0
+#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK                          0xffffffff
+
+/* Description		CE_STAT_DESC_3_FW_METADATA
+			
+			Meta data used by FW
+			
+			In case of gather field in first source ring entry of
+			the gather copy cycle in taken into account.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_FW_METADATA_OFFSET                            0x0000000c
+#define CE_STAT_DESC_3_FW_METADATA_LSB                               0
+#define CE_STAT_DESC_3_FW_METADATA_MASK                              0x0000ffff
+
+/* Description		CE_STAT_DESC_3_CE_RES_7
+			
+			Reserved 
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_CE_RES_7_OFFSET                               0x0000000c
+#define CE_STAT_DESC_3_CE_RES_7_LSB                                  16
+#define CE_STAT_DESC_3_CE_RES_7_MASK                                 0x000f0000
+
+/* Description		CE_STAT_DESC_3_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_RING_ID_OFFSET                                0x0000000c
+#define CE_STAT_DESC_3_RING_ID_LSB                                   20
+#define CE_STAT_DESC_3_RING_ID_MASK                                  0x0ff00000
+
+/* Description		CE_STAT_DESC_3_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into the Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET                          0x0000000c
+#define CE_STAT_DESC_3_LOOPING_COUNT_LSB                             28
+#define CE_STAT_DESC_3_LOOPING_COUNT_MASK                            0xf0000000
+
+
+#endif // _CE_STAT_DESC_H_

hw/qca8074/v1/com_dtypes.h

@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef COM_DTYPES_H
+#define COM_DTYPES_H
+
+/**
+  @file com_dtypes.h
+  @brief This header file contains general data types that are of use to all 
+  modules.  
+
+*/
+/*===========================================================================
+NOTE: The @brief description and any detailed descriptions above do not appear 
+      in the PDF. 
+
+      The Utility_Services_API_mainpage.dox file contains all file/group 
+      descriptions that are in the output PDF generated using Doxygen and 
+      Latex. To edit or update any of the file/group text in the PDF, edit 
+      the Utility_Services_API_mainpage.dox file or contact Tech Pubs.
+
+      The above description for this file is part of the "utils_services" 
+	  group description in the Utility_Services_API_mainpage.dox file. 
+===========================================================================*/
+/*===========================================================================
+
+                   S T A N D A R D    D E C L A R A T I O N S
+
+DESCRIPTION
+  This header file contains general data types that are of use to all modules.  
+  The values or definitions are dependent on the specified
+  target.  T_WINNT specifies Windows NT based targets, otherwise the
+  default is for ARM targets.
+
+  T_WINNT  Software is hosted on an NT platforn, triggers macro and
+           type definitions, unlike definition above which triggers
+           actual OS calls
+
+===========================================================================*/
+
+
+/*===========================================================================
+
+                      EDIT HISTORY FOR FILE
+
+This section contains comments describing changes made to this file.
+Notice that changes are listed in reverse chronological order.
+
+$Header: /prj/iceng/SCALe/repository/cvs/scale/source/data/com_dtypes.h,v 1.1.1.1 2012/09/19 22:33:30 rjindal Exp $
+
+when       who     what, where, why
+--------   ---     ----------------------------------------------------------
+03/21/11   llg     (Tech Pubs) Edited/added Doxygen comments and markup.
+11/09/10   EBR     Doxygenated file.
+09/15/09   pc      Created file.
+===========================================================================*/
+
+
+/*===========================================================================
+
+                            Data Declarations
+
+===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* For NT apps we want to use the Win32 definitions and/or those
+ supplied by the Win32 compiler for things like NULL, MAX, MIN
+ abs, labs, etc.
+*/
+#ifdef T_WINNT
+   #ifndef WIN32
+      #define WIN32
+   #endif
+   #include <stdlib.h>
+#endif
+
+/* ------------------------------------------------------------------------
+** Constants
+** ------------------------------------------------------------------------ */
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+/** @addtogroup utils_services
+@{ */
+
+/** @name Macros for Common Data Types
+@{ */
+#define TRUE   1   /**< Boolean TRUE value. */
+#define FALSE  0   /**< Boolean FALSE value. */
+
+#define  ON   1    /**< ON value. */
+#define  OFF  0    /**< OFF value. */
+
+#ifndef NULL
+  #define NULL  0  /**< NULL value. */  
+#endif
+/** @} */ /* end_name_group Macros for Common Data Types */
+
+/* -----------------------------------------------------------------------
+** Standard Types
+** ----------------------------------------------------------------------- */
+
+/** @} */ /* end_addtogroup utils_services */
+
+/* The following definitions are the same across platforms.  This first
+ group are the sanctioned types.
+*/
+#ifndef _ARM_ASM_
+#ifndef _BOOLEAN_DEFINED
+
+/** @addtogroup utils_services
+@{ */
+/** Boolean value type. 
+*/
+typedef  unsigned char      boolean;     
+#define _BOOLEAN_DEFINED
+#endif
+
+/** @cond 
+*/
+#if defined(DALSTDDEF_H) /* guards against a known re-definer */
+#define _BOOLEAN_DEFINED
+#define _UINT32_DEFINED
+#define _UINT16_DEFINED
+#define _UINT8_DEFINED
+#define _INT32_DEFINED
+#define _INT16_DEFINED
+#define _INT8_DEFINED
+#define _UINT64_DEFINED
+#define _INT64_DEFINED
+#define _BYTE_DEFINED
+#endif /* #if !defined(DALSTDDEF_H) */
+/** @endcond */
+
+#ifndef _UINT32_DEFINED
+/** Unsigned 32-bit value.
+*/
+typedef  unsigned long int  uint32;      
+#define _UINT32_DEFINED
+#endif
+
+#ifndef _UINT16_DEFINED
+/** Unsigned 16-bit value.
+*/
+typedef  unsigned short     uint16;      
+#define _UINT16_DEFINED
+#endif
+
+#ifndef _UINT8_DEFINED
+/** Unsigned 8-bit value. 
+*/
+typedef  unsigned char      uint8;       
+#define _UINT8_DEFINED
+#endif
+
+#ifndef _INT32_DEFINED
+/** Signed 32-bit value.
+*/
+typedef  signed long int    int32;
+#define _INT32_DEFINED
+#endif
+
+#ifndef _INT16_DEFINED
+/** Signed 16-bit value.
+*/
+typedef  signed short       int16;
+#define _INT16_DEFINED
+#endif
+
+#ifndef _INT8_DEFINED
+/** Signed 8-bit value.
+*/
+typedef  signed char        int8;        
+#define _INT8_DEFINED
+#endif
+
+/** @cond
+*/
+/* This group are the deprecated types.  Their use should be
+** discontinued and new code should use the types above
+*/
+#ifndef _BYTE_DEFINED
+/** DEPRECATED: Unsigned 8  bit value type.
+*/
+typedef  unsigned char      byte;         
+#define  _BYTE_DEFINED
+#endif
+
+/** DEPRECATED: Unsinged 16 bit value type.
+*/
+typedef  unsigned short     word;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef  unsigned long      dword;        
+
+/** DEPRECATED: Unsigned 8  bit value type.
+*/
+typedef  unsigned char      uint1;
+/** DEPRECATED: Unsigned 16 bit value type.
+*/
+typedef  unsigned short     uint2;
+/** DEPRECATED: Unsigned 32 bit value type.
+*/
+typedef  unsigned long      uint4;        
+
+/** DEPRECATED: Signed 8  bit value type. 
+*/
+typedef  signed char        int1;
+/** DEPRECATED: Signed 16 bit value type.
+*/         
+typedef  signed short       int2;
+/** DEPRECATED: Signed 32 bit value type. 
+*/     
+typedef  long int           int4;         
+
+/** DEPRECATED: Signed 32 bit value.
+*/
+typedef  signed long        sint31;
+/** DEPRECATED: Signed 16 bit value. 
+*/       
+typedef  signed short       sint15;
+/** DEPRECATED: Signed 8  bit value.
+*/       
+typedef  signed char        sint7; 
+
+typedef uint16 UWord16 ;
+typedef uint32 UWord32 ;
+typedef int32  Word32 ;
+typedef int16  Word16 ;
+typedef uint8  UWord8 ;
+typedef int8   Word8 ;
+typedef int32  Vect32 ;
+/** @endcond */
+
+#if (! defined T_WINNT) && (! defined __GNUC__)
+  /* Non WinNT Targets */
+  #ifndef _INT64_DEFINED
+    /** Signed 64-bit value.
+	*/
+    typedef long long     int64;       
+    #define _INT64_DEFINED
+  #endif
+  #ifndef _UINT64_DEFINED
+    /** Unsigned 64-bit value.
+	*/
+    typedef  unsigned long long  uint64;      
+    #define _UINT64_DEFINED
+  #endif
+#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */
+  /* WINNT or SOLARIS based targets */
+  #if (defined __GNUC__) 
+    #ifndef _INT64_DEFINED
+      typedef long long           int64;
+      #define _INT64_DEFINED
+    #endif
+    #ifndef _UINT64_DEFINED
+      typedef unsigned long long  uint64;
+      #define _UINT64_DEFINED
+    #endif
+  #else
+    typedef  __int64              int64;       /* Signed 64-bit value */
+    #ifndef _UINT64_DEFINED
+      typedef  unsigned __int64   uint64;      /* Unsigned 64-bit value */
+      #define _UINT64_DEFINED
+    #endif
+  #endif
+#endif /* T_WINNT */
+
+#endif /* _ARM_ASM_ */
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */ /* end_addtogroup utils_services */
+#endif  /* COM_DTYPES_H */

hw/qca8074/v1/lithium_top_reg.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+//////////////////////////////////////////////////////////////////////////////
+// lithium_top_reg.h generated by: GenArmCHeader.pl
+//////////////////////////////////////////////////////////////////////////////
+// **** W A R N I N G ****  THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!!
+//////////////////////////////////////////////////////////////////////////////
+// RCS File        : -USE CVS LOG-
+// Revision        : -USE CVS LOG-
+// Last Check In   : -USE CVS LOG-
+//////////////////////////////////////////////////////////////////////////////
+// Description     : Constants related to Hardware Registers
+//
+// Byte Addresses are used for all BASES and ADDRESSES
+//////////////////////////////////////////////////////////////////////////////
+#ifndef LITHIUM_TOP_REG_H
+#define LITHIUM_TOP_REG_H
+
+#define UMAC_CE_COMMON_CE_HOST_IE_0               (0x00A18034)
+#define UMAC_CE_COMMON_CE_HOST_IE_1               (0x00A18038)
+
+#endif

hw/qca8074/v1/mac_tcl_reg_seq_hwiobase.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_BASE_H__
+#define __MAC_TCL_REG_SEQ_BASE_H__
+
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+#endif
+

hw/qca8074/v1/mac_tcl_reg_seq_hwioreg.h

@@ -0,0 +1,6821 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+//
+// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq  3.3 7/29/2016 
+// User Name:pgohil
+//
+// !! WARNING !!  DO NOT MANUALLY EDIT THIS FILE.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __MAC_TCL_REG_SEQ_REG_H__
+#define __MAC_TCL_REG_SEQ_REG_H__
+
+#include "seq_hwio.h"
+#include "mac_tcl_reg_seq_hwiobase.h"
+#ifdef SCALE_INCLUDES
+	#include "HALhwio.h"
+#else
+	#include "msmhwio.h"
+#endif
+
+
+///////////////////////////////////////////////////////////////////////////////////////////////
+// Register Data for Block MAC_TCL_REG
+///////////////////////////////////////////////////////////////////////////////////////////////
+
+//// Register TCL_R0_SW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x)                        (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x)                        (x+0x00000000)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x)                        (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x)                        (x+0x00000004)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x)                        (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x)                        (x+0x00000008)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CTRL ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x)                        (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x)                        (x+0x0000000c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK                           0x0007ffe1
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_BMSK             0x00040000
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_STAT_SHFT                   0x12
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK               0x0003ffc0
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT                      0x6
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK                  0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT                         0x5
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_BMSK                  0x00000001
+#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_HALT_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CTRL ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x)                     (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_PHYS(x)                     (x+0x00000010)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK                        0x0007ffe1
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_SHFT                                 0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_BMSK          0x00040000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_STAT_SHFT                0x12
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_BMSK            0x0003ffc0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_TIMEOUT_VAL_SHFT                   0x6
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_BMSK               0x00000020
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_PRTY_SHFT                      0x5
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_BMSK               0x00000001
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CTRL_RNG_HALT_SHFT                      0x0
+
+//// Register TCL_R0_CONS_RING_CMN_CTRL_REG ////
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x)                   (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x)                   (x+0x00000014)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK                      0x00000007
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT                               0
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val)
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK           0x00000004
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT                  0x2
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK     0x00000002
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT            0x1
+
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK             0x00000001
+#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT                    0x0
+
+//// Register TCL_R0_TCL2TQM_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x)                        (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x)                        (x+0x00000018)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK                           0x00000fff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT                                    0
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK               0x00000fff
+#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT                      0x0
+
+//// Register TCL_R0_TCL2FW_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x)                         (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x)                         (x+0x0000001c)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK                            0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT                                     0
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK                0x00000fff
+#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT                       0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x)                    (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x)                    (x+0x00000020)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK                       0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK           0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT                  0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_CTRL ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x)                    (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x)                    (x+0x00000024)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK                       0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK           0x00000fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT                  0x0
+
+//// Register TCL_R0_GEN_CTRL ////
+
+#define HWIO_TCL_R0_GEN_CTRL_ADDR(x)                                 (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_PHYS(x)                                 (x+0x00000028)
+#define HWIO_TCL_R0_GEN_CTRL_RMSK                                    0xffff7e1d
+#define HWIO_TCL_R0_GEN_CTRL_SHFT                                             0
+#define HWIO_TCL_R0_GEN_CTRL_IN(x)                                   \
+	in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK)
+#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask)                            \
+	in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val)                             \
+	out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val)                      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK           0xffff0000
+#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT                 0x10
+
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK            0x00004000
+#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT                   0xe
+
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK                0x00002000
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT                       0xd
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK                    0x00001000
+#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT                           0xc
+
+#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_BMSK                             0x00000e00
+#define HWIO_TCL_R0_GEN_CTRL_MAC_ID_SHFT                                    0x9
+
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK                             0x00000010
+#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT                                    0x4
+
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK                             0x00000008
+#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT                                    0x3
+
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_BMSK                         0x00000004
+#define HWIO_TCL_R0_GEN_CTRL_FLOW_ID_EN_SHFT                                0x2
+
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK                            0x00000001
+#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT                                   0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_0 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x)                          (x+0x0000002c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_PHYS(x)                          (x+0x0000002c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_0_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_BMSK                      0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_9_SHFT                            0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_BMSK                      0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_8_SHFT                            0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_BMSK                      0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_7_SHFT                            0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_BMSK                      0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_6_SHFT                            0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_5_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_4_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_3_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_2_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_1_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_0_DSCP_0_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_1 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x)                          (x+0x00000030)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_PHYS(x)                          (x+0x00000030)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_13_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_12_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_11_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_10_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_F_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_E_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_D_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_C_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_B_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_1_DSCP_A_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_2 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x)                          (x+0x00000034)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_PHYS(x)                          (x+0x00000034)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_2_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1D_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1C_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1B_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_1A_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_19_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_18_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_17_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_16_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_15_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_2_DSCP_14_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_3 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x)                          (x+0x00000038)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_PHYS(x)                          (x+0x00000038)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_3_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_27_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_26_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_25_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_24_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_23_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_22_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_21_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_20_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1F_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_3_DSCP_1E_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_4 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x)                          (x+0x0000003c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_PHYS(x)                          (x+0x0000003c)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_4_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_4_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_31_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_30_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2F_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2E_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2D_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2C_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2B_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_2A_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_29_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_4_DSCP_28_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_5 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x)                          (x+0x00000040)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_PHYS(x)                          (x+0x00000040)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_5_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_5_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3B_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_3A_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_39_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_38_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_37_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_36_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_35_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_34_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_33_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_5_DSCP_32_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID1_MAP_6 ////
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x)                          (x+0x00000044)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_PHYS(x)                          (x+0x00000044)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK                             0x00000fff
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID1_MAP_6_RMSK)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID1_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID1_MAP_6_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3F_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3E_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3D_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID1_MAP_6_DSCP_3C_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_0 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x)                          (x+0x00000048)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_PHYS(x)                          (x+0x00000048)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_0_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_0_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_BMSK                      0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_9_SHFT                            0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_BMSK                      0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_8_SHFT                            0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_BMSK                      0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_7_SHFT                            0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_BMSK                      0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_6_SHFT                            0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_5_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_4_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_3_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_2_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_1_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_0_DSCP_0_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_1 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x)                          (x+0x0000004c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_PHYS(x)                          (x+0x0000004c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_1_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_1_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_13_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_12_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_11_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_10_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_BMSK                      0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_F_SHFT                             0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_BMSK                      0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_E_SHFT                             0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_BMSK                      0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_D_SHFT                             0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_BMSK                      0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_C_SHFT                             0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_BMSK                      0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_B_SHFT                             0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_BMSK                      0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_1_DSCP_A_SHFT                             0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_2 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x)                          (x+0x00000050)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_PHYS(x)                          (x+0x00000050)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_2_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_2_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1D_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1C_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1B_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_1A_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_19_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_18_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_17_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_16_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_15_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_2_DSCP_14_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_3 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x)                          (x+0x00000054)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_PHYS(x)                          (x+0x00000054)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_3_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_3_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_27_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_26_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_25_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_24_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_23_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_22_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_21_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_20_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1F_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_3_DSCP_1E_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_4 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x)                          (x+0x00000058)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_PHYS(x)                          (x+0x00000058)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_4_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_4_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_4_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_31_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_30_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2F_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2E_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2D_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2C_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2B_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_2A_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_29_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_4_DSCP_28_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_5 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x)                          (x+0x0000005c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_PHYS(x)                          (x+0x0000005c)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK                             0x3fffffff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_5_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_5_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_5_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_BMSK                     0x38000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3B_SHFT                           0x1b
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_BMSK                     0x07000000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_3A_SHFT                           0x18
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_BMSK                     0x00e00000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_39_SHFT                           0x15
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_BMSK                     0x001c0000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_38_SHFT                           0x12
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_BMSK                     0x00038000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_37_SHFT                            0xf
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_BMSK                     0x00007000
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_36_SHFT                            0xc
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_35_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_34_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_33_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_5_DSCP_32_SHFT                            0x0
+
+//// Register TCL_R0_DSCP_TID2_MAP_6 ////
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x)                          (x+0x00000060)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_PHYS(x)                          (x+0x00000060)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK                             0x00000fff
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_SHFT                                      0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), HWIO_TCL_R0_DSCP_TID2_MAP_6_RMSK)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask) 
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), val)
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID2_MAP_6_ADDR(x), mask, val, HWIO_TCL_R0_DSCP_TID2_MAP_6_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_BMSK                     0x00000e00
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3F_SHFT                            0x9
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_BMSK                     0x000001c0
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3E_SHFT                            0x6
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_BMSK                     0x00000038
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3D_SHFT                            0x3
+
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_BMSK                     0x00000007
+#define HWIO_TCL_R0_DSCP_TID2_MAP_6_DSCP_3C_SHFT                            0x0
+
+//// Register TCL_R0_PCP_TID_MAP ////
+
+#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x)                              (x+0x00000064)
+#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x)                              (x+0x00000064)
+#define HWIO_TCL_R0_PCP_TID_MAP_RMSK                                 0x00ffffff
+#define HWIO_TCL_R0_PCP_TID_MAP_SHFT                                          0
+#define HWIO_TCL_R0_PCP_TID_MAP_IN(x)                                \
+	in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK)
+#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask)                         \
+	in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) 
+#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val)                          \
+	out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val)
+#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK                           0x00e00000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT                                 0x15
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK                           0x001c0000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT                                 0x12
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK                           0x00038000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT                                  0xf
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK                           0x00007000
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT                                  0xc
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK                           0x00000e00
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT                                  0x9
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK                           0x000001c0
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT                                  0x6
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK                           0x00000038
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT                                  0x3
+
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK                           0x00000007
+#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT                                  0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_31_0 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x)                        (x+0x00000068)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x)                        (x+0x00000068)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK                           0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT                                    0
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK                       0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT                              0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_63_32 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x)                       (x+0x0000006c)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x)                       (x+0x0000006c)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK                          0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT                                   0
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT                             0x0
+
+//// Register TCL_R0_ASE_HASH_KEY_64 ////
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x)                          (x+0x00000070)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x)                          (x+0x00000070)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK                             0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT                                      0
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK                         0x00000001
+#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT                                0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_31_0 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x)                        (x+0x00000074)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_PHYS(x)                        (x+0x00000074)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK                           0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_SHFT                                    0
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_31_0_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_31_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_BMSK                       0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_31_0_VAL_SHFT                              0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_63_32 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x)                       (x+0x00000078)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_PHYS(x)                       (x+0x00000078)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK                          0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_SHFT                                   0
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_63_32_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_63_32_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_63_32_VAL_SHFT                             0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_95_64 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x)                       (x+0x0000007c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_PHYS(x)                       (x+0x0000007c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK                          0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_SHFT                                   0
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_95_64_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_95_64_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_95_64_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_BMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_95_64_VAL_SHFT                             0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_127_96 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x)                      (x+0x00000080)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_PHYS(x)                      (x+0x00000080)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_SHFT                                  0
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_127_96_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_127_96_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_127_96_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_127_96_VAL_SHFT                            0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_159_128 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x)                     (x+0x00000084)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_PHYS(x)                     (x+0x00000084)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_159_128_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_159_128_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_159_128_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_159_128_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_191_160 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x)                     (x+0x00000088)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_PHYS(x)                     (x+0x00000088)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_191_160_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_191_160_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_191_160_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_191_160_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_223_192 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x)                     (x+0x0000008c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_PHYS(x)                     (x+0x0000008c)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_223_192_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_223_192_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_223_192_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_223_192_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_255_224 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x)                     (x+0x00000090)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_PHYS(x)                     (x+0x00000090)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_255_224_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_255_224_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_255_224_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_255_224_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_287_256 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x)                     (x+0x00000094)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_PHYS(x)                     (x+0x00000094)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK                        0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_287_256_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_287_256_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_287_256_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_287_256_VAL_SHFT                           0x0
+
+//// Register TCL_R0_FSE_HASH_KEY_314_288 ////
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x)                     (x+0x00000098)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_PHYS(x)                     (x+0x00000098)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK                        0x07ffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_SHFT                                 0
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), HWIO_TCL_R0_FSE_HASH_KEY_314_288_RMSK)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_HASH_KEY_314_288_ADDR(x), mask, val, HWIO_TCL_R0_FSE_HASH_KEY_314_288_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_BMSK                    0x07ffffff
+#define HWIO_TCL_R0_FSE_HASH_KEY_314_288_VAL_SHFT                           0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_QUEUE ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x)                      (x+0x0000009c)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x)                      (x+0x0000009c)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK                         0x00003dfc
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT                                  2
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK           0x00002000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT                  0xd
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK           0x00001000
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT                  0xc
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK           0x00000800
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT                  0xb
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK           0x00000400
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT                  0xa
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK                0x000001c0
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT                       0x6
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK        0x00000030
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT               0x4
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK        0x0000000c
+#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT               0x2
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x)                   (x+0x000000a0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x)                   (x+0x000000a0)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK                      0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT                               0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK                  0xffffffff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT                         0x0
+
+//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x)                  (x+0x000000a4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x)                  (x+0x000000a4)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK                     0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT                              0
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK                 0x000000ff
+#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT                        0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x)                   (x+0x000000a8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x)                   (x+0x000000a8)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK                      0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT                               0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK                  0xffffffff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT                         0x0
+
+//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH ////
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x)                  (x+0x000000ac)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x)                  (x+0x000000ac)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK                     0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT                              0
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK                 0x000000ff
+#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT                        0x0
+
+//// Register TCL_R0_CONFIG_SEARCH_METADATA ////
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x)                   (x+0x000000b0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x)                   (x+0x000000b0)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT                               0
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val)
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK         0xffff0000
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT               0x10
+
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK         0x0000ffff
+#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT                0x0
+
+//// Register TCL_R0_TID_MAP_PRTY ////
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x)                             (x+0x000000b4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x)                             (x+0x000000b4)
+#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK                                0x000000ef
+#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT                                         0
+#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK)
+#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) 
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val)
+#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK                        0x000000e0
+#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT                               0x5
+
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK                            0x0000000f
+#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_INVALID_APB_ACC_ADDR ////
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x)                     (x+0x000000b8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x)                     (x+0x000000b8)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK                        0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT                                 0
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) 
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val)
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK                    0xffffffff
+#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT                           0x0
+
+//// Register TCL_R0_WATCHDOG ////
+
+#define HWIO_TCL_R0_WATCHDOG_ADDR(x)                                 (x+0x000000bc)
+#define HWIO_TCL_R0_WATCHDOG_PHYS(x)                                 (x+0x000000bc)
+#define HWIO_TCL_R0_WATCHDOG_RMSK                                    0xffffffff
+#define HWIO_TCL_R0_WATCHDOG_SHFT                                             0
+#define HWIO_TCL_R0_WATCHDOG_IN(x)                                   \
+	in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_WATCHDOG_INM(x, mask)                            \
+	in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_WATCHDOG_OUT(x, val)                             \
+	out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val)                      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK                             0xffff0000
+#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT                                   0x10
+
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK                              0x0000ffff
+#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT                                     0x0
+
+//// Register TCL_R0_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x)                          (x+0x000000c0)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x)                          (x+0x000000c0)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK                             0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT                                      0
+#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_BMSK                         0xffffffff
+#define HWIO_TCL_R0_CLKGATE_DISABLE_VAL_SHFT                                0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x)                    (x+0x000000c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x)                    (x+0x000000c4)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x)                    (x+0x000000c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x)                    (x+0x000000c8)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x)                          (x+0x000000cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x)                          (x+0x000000cc)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x)                      (x+0x000000d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x)                      (x+0x000000d0)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x)                        (x+0x000000d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x)                        (x+0x000000d4)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x000000e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x000000e0)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x000000e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x000000e4)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000000f4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000000f4)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000000f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000000f8)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000000fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000000fc)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000100)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000100)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x00000104)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x00000104)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000108)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000108)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000010c)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000010c)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000110)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000110)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x)                   (x+0x00000114)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x)                   (x+0x00000114)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000118)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000118)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x)                    (x+0x0000011c)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x)                    (x+0x0000011c)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x)                    (x+0x00000120)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x)                    (x+0x00000120)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL2_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x)                          (x+0x00000124)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x)                          (x+0x00000124)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL2_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x)                      (x+0x00000128)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x)                      (x+0x00000128)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x)                        (x+0x0000012c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x)                        (x+0x0000012c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000138)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000138)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x0000013c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x0000013c)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x0000014c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x0000014c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x00000150)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x00000150)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x00000154)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x00000154)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000158)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000158)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x0000015c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x0000015c)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000160)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000160)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x00000164)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x00000164)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000168)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000168)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x)                   (x+0x0000016c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x)                   (x+0x0000016c)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000170)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000170)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x)                    (x+0x00000174)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x)                    (x+0x00000174)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL3_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x)                    (x+0x00000178)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x)                    (x+0x00000178)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_SW2TCL3_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x)                          (x+0x0000017c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x)                          (x+0x0000017c)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_SW2TCL3_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x)                      (x+0x00000180)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x)                      (x+0x00000180)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x)                        (x+0x00000184)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x)                        (x+0x00000184)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000190)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000190)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x00000194)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x00000194)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x000001a4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x000001a4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x000001a8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x000001a8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x000001ac)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x000001ac)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x000001b0)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x000001b0)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x000001b4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x000001b4)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x000001b8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x000001b8)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x000001bc)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x000001bc)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x000001c0)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x000001c0)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x)                   (x+0x000001c4)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x)                   (x+0x000001c4)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000001c8)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000001c8)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x)                 (x+0x000001cc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_PHYS(x)                 (x+0x000001cc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x)                 (x+0x000001d0)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_PHYS(x)                 (x+0x000001d0)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK                    0x00ffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_SHFT                             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK          0x00ffff00
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT                 0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_ID ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x)                       (x+0x000001d4)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_PHYS(x)                       (x+0x000001d4)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK                          0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_SHFT                                   0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_BMSK                  0x0000ff00
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_RING_ID_SHFT                         0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_BMSK               0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_ID_ENTRY_SIZE_SHFT                      0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x)                   (x+0x000001d8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_PHYS(x)                   (x+0x000001d8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK                      0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_SHFT                               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK      0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT            0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT             0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MISC ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x)                     (x+0x000001dc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_PHYS(x)                     (x+0x000001dc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK                        0x0000003f
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SHFT                                 0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK      0x00000020
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT             0x5
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK       0x00000010
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT              0x4
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_BMSK           0x00000008
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_MSI_SWAP_BIT_SHFT                  0x3
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_BMSK           0x00000004
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_SECURITY_BIT_SHFT                  0x2
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK        0x00000002
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT               0x1
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_BMSK        0x00000001
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MISC_RING_ID_DISABLE_SHFT               0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x)              (x+0x000001e8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_PHYS(x)              (x+0x000001e8)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK                 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_SHFT                          0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x)              (x+0x000001ec)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_PHYS(x)              (x+0x000001ec)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK                 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_SHFT                          0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)   (x+0x000001fc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)   (x+0x000001fc)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK      0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)   (x+0x00000200)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)   (x+0x00000200)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x)      (x+0x00000204)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_PHYS(x)      (x+0x00000204)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK         0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_SHFT                  0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)   (x+0x00000208)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)   (x+0x00000208)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT               0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)  (x+0x0000020c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)  (x+0x0000020c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK     0x00000007
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT              0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)    \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000210)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000210)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK    0x00ffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT             0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)   \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x)            (x+0x00000214)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_PHYS(x)            (x+0x00000214)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK               0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_SHFT                        0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUT(x, val)        \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK          0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT                 0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x)            (x+0x00000218)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_PHYS(x)            (x+0x00000218)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK               0x000001ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_SHFT                        0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUT(x, val)        \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK   0x00000100
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT          0x8
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK          0x000000ff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT                 0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x)                (x+0x0000021c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_PHYS(x)                (x+0x0000021c)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK                   0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_SHFT                            0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_BMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_MSI1_DATA_VALUE_SHFT                    0x0
+
+//// Register TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x)          (x+0x00000220)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_PHYS(x)          (x+0x00000220)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK             0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_SHFT                      0
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_SW2TCL_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x)                    (x+0x00000224)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x)                    (x+0x00000224)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_FW2TCL1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x)                    (x+0x00000228)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x)                    (x+0x00000228)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_FW2TCL1_RING_ID ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x)                          (x+0x0000022c)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x)                          (x+0x0000022c)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_FW2TCL1_RING_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x)                      (x+0x00000230)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x)                      (x+0x00000230)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MISC ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x)                        (x+0x00000234)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x)                        (x+0x00000234)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x)                 (x+0x00000240)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x)                 (x+0x00000240)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x)                 (x+0x00000244)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x)                 (x+0x00000244)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x)      (x+0x00000254)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x)      (x+0x00000254)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK         0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x)      (x+0x00000258)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x)      (x+0x00000258)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x)         (x+0x0000025c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x)         (x+0x0000025c)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x)      (x+0x00000260)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x)      (x+0x00000260)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK         0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT                  0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x)     (x+0x00000264)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x)     (x+0x00000264)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK        0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT                 0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK   0x00000007
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT          0x0
+
+//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x)    (x+0x00000268)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x)    (x+0x00000268)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK       0x00ffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT                0
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)      \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT       0x10
+
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff
+#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT        0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x)               (x+0x0000026c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x)               (x+0x0000026c)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK                  0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT                           0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK             0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x)               (x+0x00000270)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x)               (x+0x00000270)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK                  0x000001ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT                           0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK      0x00000100
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT             0x8
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK             0x000000ff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT                    0x0
+
+//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x)                   (x+0x00000274)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x)                   (x+0x00000274)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK                      0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT                               0
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK                0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT                       0x0
+
+//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x00000278)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x00000278)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x)                    (x+0x0000027c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x)                    (x+0x0000027c)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK                       0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT                                0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK    0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT           0x0
+
+//// Register TCL_R0_TCL2TQM_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x)                    (x+0x00000280)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x)                    (x+0x00000280)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK                       0x00ffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT                                0
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK             0x00ffff00
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT                    0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK    0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT           0x0
+
+//// Register TCL_R0_TCL2TQM_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x)                          (x+0x00000284)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x)                          (x+0x00000284)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK                             0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT                                      0
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK                     0x0000ff00
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT                            0x8
+
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK                  0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT                         0x0
+
+//// Register TCL_R0_TCL2TQM_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x)                      (x+0x00000288)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x)                      (x+0x00000288)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK                         0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK         0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT               0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT                0x0
+
+//// Register TCL_R0_TCL2TQM_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x)                        (x+0x0000028c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x)                        (x+0x0000028c)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK                           0x0000003f
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT                                    0
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK         0x00000020
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                0x5
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK          0x00000010
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT                 0x4
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK              0x00000008
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT                     0x3
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK              0x00000004
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT                     0x2
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK           0x00000002
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT                  0x1
+
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK           0x00000001
+#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT                  0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x)                 (x+0x00000290)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x)                 (x+0x00000290)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK                    0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT                             0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x)                 (x+0x00000294)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x)                 (x+0x00000294)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK                    0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT                             0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val)             \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x)          (x+0x000002a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x)          (x+0x000002a0)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK             0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT                      0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x)         (x+0x000002a4)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x)         (x+0x000002a4)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT                     0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x)       (x+0x000002a8)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x)       (x+0x000002a8)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK          0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT                   0
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask)  \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val)   \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x)             (x+0x000002d0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x)             (x+0x000002d0)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT                         0
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x)                (x+0x000002d4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x)                (x+0x000002d4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x)                (x+0x000002d8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x)                (x+0x000002d8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x)                      (x+0x000002dc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x)                      (x+0x000002dc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT                                  0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x)                  (x+0x000002e0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x)                  (x+0x000002e0)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT                              0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x)                    (x+0x000002e4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x)                    (x+0x000002e4)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK                       0x0000003f
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x)             (x+0x000002e8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x)             (x+0x000002e8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x)             (x+0x000002ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x)             (x+0x000002ec)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x000002f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x000002f8)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x000002fc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x000002fc)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000300)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000300)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x0000031c)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x0000031c)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x00000320)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x00000320)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x)               (x+0x00000324)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x)               (x+0x00000324)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT                           0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000328)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000328)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x)                (x+0x0000032c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x)                (x+0x0000032c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK                   0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x)                (x+0x00000330)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x)                (x+0x00000330)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK                   0x00ffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT                            0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val)            \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK         0x00ffff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT                0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_ID ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x)                      (x+0x00000334)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x)                      (x+0x00000334)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT                                  0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK                 0x0000ff00
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT                        0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK              0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT                     0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x)                  (x+0x00000338)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x)                  (x+0x00000338)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT                              0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK     0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT           0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK     0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT            0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x)                    (x+0x0000033c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x)                    (x+0x0000033c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK                       0x0000003f
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT                                0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK     0x00000020
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT            0x5
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK      0x00000010
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT             0x4
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK          0x00000008
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT                 0x3
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK          0x00000004
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT                 0x2
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK       0x00000002
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT              0x1
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x)             (x+0x00000340)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x)             (x+0x00000340)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK                0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x)             (x+0x00000344)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x)             (x+0x00000344)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK                0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT                         0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)               \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val)         \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val)  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x)      (x+0x00000350)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x)      (x+0x00000350)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT                  0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)        \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val)  \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x)     (x+0x00000354)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x)     (x+0x00000354)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK        0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT                 0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)       \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x)   (x+0x00000358)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x)   (x+0x00000358)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK      0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT               0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x)           (x+0x00000374)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x)           (x+0x00000374)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK         0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x)           (x+0x00000378)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x)           (x+0x00000378)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK              0x000001ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT                       0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK  0x00000100
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT         0x8
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK         0x000000ff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT                0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x)               (x+0x0000037c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x)               (x+0x0000037c)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK                  0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT                           0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)                 \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val)           \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val)    \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT                   0x0
+
+//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x)         (x+0x00000380)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x)         (x+0x00000380)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK            0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT                     0
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val)     \
+	out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x)                     (x+0x00000384)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x)                     (x+0x00000384)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK                        0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT                                 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK     0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT            0x0
+
+//// Register TCL_R0_TCL2FW_RING_BASE_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x)                     (x+0x00000388)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x)                     (x+0x00000388)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK                        0x00ffffff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT                                 0
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK              0x00ffff00
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT                     0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK     0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT            0x0
+
+//// Register TCL_R0_TCL2FW_RING_ID ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x)                           (x+0x0000038c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x)                           (x+0x0000038c)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK                              0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT                                       0
+#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK                      0x0000ff00
+#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT                             0x8
+
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK                   0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT                          0x0
+
+//// Register TCL_R0_TCL2FW_RING_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x)                       (x+0x00000390)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x)                       (x+0x00000390)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK                          0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT                                   0
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK          0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT                0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK          0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT                 0x0
+
+//// Register TCL_R0_TCL2FW_RING_MISC ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x)                         (x+0x00000394)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x)                         (x+0x00000394)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK                            0x0000003f
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT                                     0
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK          0x00000020
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT                 0x5
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK           0x00000010
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT                  0x4
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK               0x00000008
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT                      0x3
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK               0x00000004
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT                      0x2
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK            0x00000002
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT                   0x1
+
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK            0x00000001
+#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT                   0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x)                  (x+0x00000398)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x)                  (x+0x00000398)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK                     0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT                              0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x)                  (x+0x0000039c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x)                  (x+0x0000039c)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK                     0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT                              0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x)           (x+0x000003a8)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x)           (x+0x000003a8)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK              0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT                       0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val)       \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x)          (x+0x000003ac)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x)          (x+0x000003ac)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK             0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT                      0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)            \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask)     \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val)      \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT       0x10
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT        0xf
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x)        (x+0x000003b0)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x)        (x+0x000003b0)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK           0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT                    0
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x0000ffff
+#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT        0x0
+
+//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET ////
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x)              (x+0x000003d8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x)              (x+0x000003d8)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK                 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT                          0
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) 
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val)          \
+	out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val)
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffffffff
+#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT        0x0
+
+//// Register TCL_R0_GXI_TESTBUS_LOWER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x)                        (x+0x000003dc)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x)                        (x+0x000003dc)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK                           0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT                                    0
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK                     0xffffffff
+#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT                            0x0
+
+//// Register TCL_R0_GXI_TESTBUS_UPPER ////
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x)                        (x+0x000003e0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x)                        (x+0x000003e0)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK                           0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT                                    0
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK                     0x000000ff
+#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT                            0x0
+
+//// Register TCL_R0_GXI_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x)                       (x+0x000003e4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x)                       (x+0x000003e4)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK                          0x00000fff
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT                                   0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK         0x00000e00
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT                0x9
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK         0x000001f0
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT                0x4
+
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK         0x0000000f
+#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT                0x0
+
+//// Register TCL_R0_GXI_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000003e8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000003e8)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE ////
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x)                   (x+0x000003ec)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x)                   (x+0x000003ec)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK                      0x80000fff
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT                               0
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK    0x80000000
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT          0x1f
+
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_BMSK   0x00000fff
+#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_DISABLE_SHFT          0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_INTS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x)                         (x+0x000003f0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x)                         (x+0x000003f0)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK                            0x01010101
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT                                     0
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)                           \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val)                     \
+	out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val)              \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK        0x01000000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT              0x18
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK         0x00010000
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT               0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK         0x00000100
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT                0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK          0x00000001
+#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT                 0x0
+
+//// Register TCL_R0_GXI_GXI_ERR_STATS ////
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x)                        (x+0x000003f4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x)                        (x+0x000003f4)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK                           0x003f3f3f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT                                    0
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK      0x003f0000
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT            0x10
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK           0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT                  0x8
+
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK           0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT                  0x0
+
+//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x)                  (x+0x000003f8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x)                  (x+0x000003f8)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT                              0
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x)                  (x+0x000003fc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x)                  (x+0x000003fc)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK                     0xffff3f3f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT                              0
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)                    \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask)             \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val)              \
+	out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val)       \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT       0x18
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT       0x10
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT        0x8
+
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f
+#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT        0x0
+
+//// Register TCL_R0_GXI_GXI_MISC_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x)                     (x+0x00000400)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x)                     (x+0x00000400)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK                        0x007fffff
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT                                 0
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK   0x00700000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT         0x14
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK    0x000e0000
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT          0x11
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT        0x9
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT        0x1
+
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK        0x00000001
+#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT               0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_CONTROL ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x)                     (x+0x00000404)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x)                     (x+0x00000404)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK                        0xffff0001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT                                 0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)                       \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask)                \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val)                 \
+	out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val)          \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK         0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT               0x10
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK       0x00000001
+#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT              0x0
+
+//// Register TCL_R0_GXI_GXI_WDOG_STATUS ////
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x)                      (x+0x00000408)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x)                      (x+0x00000408)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK                         0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT                                  0
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK         0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT                0x0
+
+//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS ////
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x)                    (x+0x0000040c)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x)                    (x+0x0000040c)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK                       0xffffffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT                                0
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK     0xffff0000
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT           0x10
+
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK    0x0000ffff
+#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT           0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x)                    (x+0x00000410)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x)                    (x+0x00000410)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK                       0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT                                0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK                   0xffffffff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT                          0x0
+
+//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH ////
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x)                   (x+0x00000414)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x)                   (x+0x00000414)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK                      0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT                               0
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK                  0x000000ff
+#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT                         0x0
+
+//// Register TCL_R0_ASE_GST_SIZE ////
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x)                             (x+0x00000418)
+#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x)                             (x+0x00000418)
+#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK                                0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT                                         0
+#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK)
+#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK                            0x000fffff
+#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_ASE_SEARCH_CTRL ////
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x)                          (x+0x0000041c)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x)                          (x+0x0000041c)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK                             0xffff03ff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT                                      0
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK              0xffff0000
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT                    0x10
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK               0x00000200
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT                      0x9
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK                 0x00000100
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT                        0x8
+
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK                  0x000000ff
+#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT                         0x0
+
+//// Register TCL_R0_ASE_WATCHDOG ////
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x)                             (x+0x00000420)
+#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x)                             (x+0x00000420)
+#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK                                0xffffffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT                                         0
+#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK                         0xffff0000
+#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT                               0x10
+
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK                          0x0000ffff
+#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT                                 0x0
+
+//// Register TCL_R0_ASE_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x)                      (x+0x00000424)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x)                      (x+0x00000424)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK                         0xffffffff
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT                                  0
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_VAL_SHFT                            0x0
+
+//// Register TCL_R0_ASE_WRITE_BACK_PENDING ////
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x)                   (x+0x00000428)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x)                   (x+0x00000428)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK                      0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT                               0
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) 
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val)
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK               0x00000001
+#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT                      0x0
+
+//// Register TCL_R0_FSE_GST_BASE_ADDR_LOW ////
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x)                    (x+0x0000042c)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_PHYS(x)                    (x+0x0000042c)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK                       0xffffffff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_SHFT                                0
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_RMSK)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUT(x, val)                \
+	out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_BMSK                   0xffffffff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_LOW_VAL_SHFT                          0x0
+
+//// Register TCL_R0_FSE_GST_BASE_ADDR_HIGH ////
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x)                   (x+0x00000430)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_PHYS(x)                   (x+0x00000430)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK                      0x000000ff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_SHFT                               0
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_RMSK)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FSE_GST_BASE_ADDR_HIGH_VAL_SHFT                         0x0
+
+//// Register TCL_R0_FSE_GST_SIZE ////
+
+#define HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x)                             (x+0x00000434)
+#define HWIO_TCL_R0_FSE_GST_SIZE_PHYS(x)                             (x+0x00000434)
+#define HWIO_TCL_R0_FSE_GST_SIZE_RMSK                                0x000fffff
+#define HWIO_TCL_R0_FSE_GST_SIZE_SHFT                                         0
+#define HWIO_TCL_R0_FSE_GST_SIZE_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), HWIO_TCL_R0_FSE_GST_SIZE_RMSK)
+#define HWIO_TCL_R0_FSE_GST_SIZE_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_GST_SIZE_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_GST_SIZE_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_GST_SIZE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_BMSK                            0x000fffff
+#define HWIO_TCL_R0_FSE_GST_SIZE_VAL_SHFT                                   0x0
+
+//// Register TCL_R0_FSE_SEARCH_CTRL ////
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x)                          (x+0x00000438)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_PHYS(x)                          (x+0x00000438)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK                             0xffff03ff
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SHFT                                      0
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_FSE_SEARCH_CTRL_RMSK)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FSE_SEARCH_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK              0xffff0000
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT                    0x10
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_BMSK               0x00000200
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_CACHE_DISABLE_SHFT                      0x9
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_BMSK                 0x00000100
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_SEARCH_SWAP_SHFT                        0x8
+
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_BMSK                  0x000000ff
+#define HWIO_TCL_R0_FSE_SEARCH_CTRL_MAX_SEARCH_SHFT                         0x0
+
+//// Register TCL_R0_FSE_WATCHDOG ////
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x)                             (x+0x0000043c)
+#define HWIO_TCL_R0_FSE_WATCHDOG_PHYS(x)                             (x+0x0000043c)
+#define HWIO_TCL_R0_FSE_WATCHDOG_RMSK                                0xffffffff
+#define HWIO_TCL_R0_FSE_WATCHDOG_SHFT                                         0
+#define HWIO_TCL_R0_FSE_WATCHDOG_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), HWIO_TCL_R0_FSE_WATCHDOG_RMSK)
+#define HWIO_TCL_R0_FSE_WATCHDOG_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_WATCHDOG_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_WATCHDOG_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WATCHDOG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_BMSK                         0xffff0000
+#define HWIO_TCL_R0_FSE_WATCHDOG_STATUS_SHFT                               0x10
+
+#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_BMSK                          0x0000ffff
+#define HWIO_TCL_R0_FSE_WATCHDOG_LIMIT_SHFT                                 0x0
+
+//// Register TCL_R0_FSE_CLKGATE_DISABLE ////
+
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x)                      (x+0x00000440)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_PHYS(x)                      (x+0x00000440)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK                         0xffffffff
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_SHFT                                  0
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_FSE_CLKGATE_DISABLE_RMSK)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_FSE_CLKGATE_DISABLE_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_BMSK                     0xffffffff
+#define HWIO_TCL_R0_FSE_CLKGATE_DISABLE_VAL_SHFT                            0x0
+
+//// Register TCL_R0_FSE_WRITE_BACK_PENDING ////
+
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x)                   (x+0x00000444)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_PHYS(x)                   (x+0x00000444)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK                      0x00000001
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_SHFT                               0
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)                     \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_RMSK)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_INM(x, mask)              \
+	in_dword_masked ( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask) 
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUT(x, val)               \
+	out_dword( HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), val)
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_OUTM(x, mask, val)        \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_BMSK               0x00000001
+#define HWIO_TCL_R0_FSE_WRITE_BACK_PENDING_STATUS_SHFT                      0x0
+
+//// Register TCL_R1_SM_STATES_IX_0 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x)                           (x+0x00001000)
+#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x)                           (x+0x00001000)
+#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK                              0x07ffffff
+#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT                                       0
+#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK                     0x07000000
+#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT                           0x18
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK                      0x00e00000
+#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT                            0x15
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK              0x001c0000
+#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT                    0x12
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK                   0x00038000
+#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT                          0xf
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_BMSK              0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CMD_RING_SHFT                     0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK                 0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT                        0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK                 0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT                        0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK                 0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT                        0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK                 0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT                        0x0
+
+//// Register TCL_R1_SM_STATES_IX_1 ////
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x)                           (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x)                           (x+0x00001004)
+#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK                              0x00007fff
+#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT                                       0
+#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK)
+#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) 
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK                    0x00007000
+#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT                           0xc
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK                  0x00000e00
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT                         0x9
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK                  0x000001c0
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT                         0x6
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK                       0x00000038
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT                              0x3
+
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK                      0x00000007
+#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT                             0x0
+
+//// Register TCL_R1_TESTBUS_CTRL_0 ////
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x)                           (x+0x00001008)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x)                           (x+0x00001008)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK                              0x1fffffff
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT                                       0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK              0x1f800000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT                    0x17
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK                   0x007c0000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT                         0x12
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK                   0x0003c000
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT                          0xe
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK                   0x00003c00
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT                          0xa
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK                0x000003e0
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT                       0x5
+
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK                   0x0000001f
+#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT                          0x0
+
+//// Register TCL_R1_TESTBUS_LOW ////
+
+#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x)                              (x+0x0000100c)
+#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x)                              (x+0x0000100c)
+#define HWIO_TCL_R1_TESTBUS_LOW_RMSK                                 0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_SHFT                                          0
+#define HWIO_TCL_R1_TESTBUS_LOW_IN(x)                                \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK)
+#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask)                         \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val)                          \
+	out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val)                   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK                             0xffffffff
+#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT                                    0x0
+
+//// Register TCL_R1_TESTBUS_HIGH ////
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x)                             (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x)                             (x+0x00001010)
+#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK                                0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT                                         0
+#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x)                               \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK)
+#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask)                        \
+	in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) 
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val)                         \
+	out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val)
+#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val)                  \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK                            0x000000ff
+#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT                                   0x0
+
+//// Register TCL_R1_EVENTMASK_IX_0 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x)                           (x+0x00001014)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x)                           (x+0x00001014)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_1 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x)                           (x+0x00001018)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x)                           (x+0x00001018)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_2 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x)                           (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x)                           (x+0x0000101c)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_EVENTMASK_IX_3 ////
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x)                           (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x)                           (x+0x00001020)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK                              0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT                                       0
+#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) 
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val)
+#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK                          0xffffffff
+#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT                                 0x0
+
+//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL ////
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x)                (x+0x00001024)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x)                (x+0x00001024)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK                   0xffffffff
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT                            0
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)                  \
+	in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask)           \
+	in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) 
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val)            \
+	out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val)
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val)     \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT       0x11
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT        0x2
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT        0x1
+
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001
+#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT        0x0
+
+//// Register TCL_R1_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x)                        (x+0x00001028)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x)                        (x+0x00001028)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK                           0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT                                    0
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)                          \
+	in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask)                   \
+	in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val)                    \
+	out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val)             \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK    0x00000001
+#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT           0x0
+
+//// Register TCL_R1_ASE_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x)                    (x+0x0000102c)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x)                    (x+0x0000102c)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x)                 (x+0x00001030)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x)                 (x+0x00001030)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK                    0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT                             0
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val)             \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK                 0x00000001
+#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT                        0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)         (x+0x00001034)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x)         (x+0x00001034)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK            0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT                     0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val)     \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK        0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT               0x0
+
+//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)           (x+0x00001038)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x)           (x+0x00001038)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK              0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT                       0
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val)       \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK          0xffffffff
+#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT                 0x0
+
+//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)        (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x)        (x+0x0000103c)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK           0x000fffff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT                    0
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK      0x000ffc00
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT             0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK      0x000003ff
+#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT             0x0
+
+//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER ////
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)            (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x)            (x+0x00001040)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK               0x03ffffff
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT                        0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val)        \
+	out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT        0xa
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT        0x5
+
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f
+#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT        0x0
+
+//// Register TCL_R1_ASE_SM_STATES ////
+
+#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x)                            (x+0x00001044)
+#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x)                            (x+0x00001044)
+#define HWIO_TCL_R1_ASE_SM_STATES_RMSK                               0x003fffff
+#define HWIO_TCL_R1_ASE_SM_STATES_SHFT                                        0
+#define HWIO_TCL_R1_ASE_SM_STATES_IN(x)                              \
+	in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK)
+#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask)                       \
+	in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val)                        \
+	out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK                0x00300000
+#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT                      0x14
+
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK               0x000c0000
+#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT                     0x12
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK                0x00030000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT                      0x10
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK                0x0000c000
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT                       0xe
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK               0x00003800
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT                      0xb
+
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK               0x00000700
+#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT                      0x8
+
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_BMSK                0x000000c0
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_ISS_STATE_SHFT                       0x6
+
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_BMSK               0x00000030
+#define HWIO_TCL_R1_ASE_SM_STATES_PEER_RESP_STATE_SHFT                      0x4
+
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK              0x0000000f
+#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT                     0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x)                          (x+0x00001048)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x)                          (x+0x00001048)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK                             0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT                                      0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK                    0x000003ff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT                           0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)              (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x)              (x+0x0000104c)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK                 0x007fffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT                          0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val)          \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK         0x007ffff8
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT                0x3
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK      0x00000004
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT             0x2
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK           0x00000002
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT                  0x1
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK           0x00000001
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT                  0x0
+
+//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n ////
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n)            (base+0x1050+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n)            (base+0x1050+0x4*n)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK                     0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT                              0
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn                             31
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)             \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val)       \
+	out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val)
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK                 0xffffffff
+#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT                        0x0
+
+//// Register TCL_R1_FSE_END_OF_TEST_CHECK ////
+
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x)                    (x+0x000010d0)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_PHYS(x)                    (x+0x000010d0)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK                       0x00000001
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_SHFT                                0
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)                      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_RMSK)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_INM(x, mask)               \
+	in_dword_masked ( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUT(x, val)                \
+	out_dword( HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_OUTM(x, mask, val)         \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001
+#define HWIO_TCL_R1_FSE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT        0x0
+
+//// Register TCL_R1_FSE_DEBUG_CLEAR_COUNTERS ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x)                 (x+0x000010d4)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_PHYS(x)                 (x+0x000010d4)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK                    0x00000001
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_SHFT                             0
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)                   \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_INM(x, mask)            \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUT(x, val)             \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val)      \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_BMSK                 0x00000001
+#define HWIO_TCL_R1_FSE_DEBUG_CLEAR_COUNTERS_EN_SHFT                        0x0
+
+//// Register TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x)         (x+0x000010d8)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x)         (x+0x000010d8)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK            0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT                     0
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)           \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask)    \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val)     \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK        0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT               0x0
+
+//// Register TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x)           (x+0x000010dc)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x)           (x+0x000010dc)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK              0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_SHFT                       0
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)             \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val)       \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK          0xffffffff
+#define HWIO_TCL_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT                 0x0
+
+//// Register TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x)        (x+0x000010e0)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x)        (x+0x000010e0)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK           0x000fffff
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT                    0
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)          \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask)   \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val)    \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK      0x000ffc00
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT             0xa
+
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK      0x000003ff
+#define HWIO_TCL_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT             0x0
+
+//// Register TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER ////
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x)            (x+0x000010e4)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x)            (x+0x000010e4)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK               0x03ffffff
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SHFT                        0
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)              \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_RMSK)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask)       \
+	in_dword_masked ( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val)        \
+	out_dword( HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT        0xa
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT        0x5
+
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f
+#define HWIO_TCL_R1_FSE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT        0x0
+
+//// Register TCL_R1_FSE_SM_STATES ////
+
+#define HWIO_TCL_R1_FSE_SM_STATES_ADDR(x)                            (x+0x000010e8)
+#define HWIO_TCL_R1_FSE_SM_STATES_PHYS(x)                            (x+0x000010e8)
+#define HWIO_TCL_R1_FSE_SM_STATES_RMSK                               0x003fffff
+#define HWIO_TCL_R1_FSE_SM_STATES_SHFT                                        0
+#define HWIO_TCL_R1_FSE_SM_STATES_IN(x)                              \
+	in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), HWIO_TCL_R1_FSE_SM_STATES_RMSK)
+#define HWIO_TCL_R1_FSE_SM_STATES_INM(x, mask)                       \
+	in_dword_masked ( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_SM_STATES_OUT(x, val)                        \
+	out_dword( HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_SM_STATES_OUTM(x, mask, val)                 \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_FSE_SM_STATES_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_BMSK                0x00300000
+#define HWIO_TCL_R1_FSE_SM_STATES_GSE_CTRL_STATE_SHFT                      0x14
+
+#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_BMSK               0x000c0000
+#define HWIO_TCL_R1_FSE_SM_STATES_CACHE_CHK_STATE_SHFT                     0x12
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_BMSK                0x00030000
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS1_STATE_SHFT                      0x10
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_BMSK                0x0000c000
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_ISS2_STATE_SHFT                       0xe
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_BMSK               0x00003800
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP1_STATE_SHFT                      0xb
+
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_BMSK               0x00000700
+#define HWIO_TCL_R1_FSE_SM_STATES_MEM_RESP2_STATE_SHFT                      0x8
+
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_BMSK                0x000000c0
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_ISS_STATE_SHFT                       0x6
+
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_BMSK               0x00000030
+#define HWIO_TCL_R1_FSE_SM_STATES_PEER_RESP_STATE_SHFT                      0x4
+
+#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_BMSK              0x0000000f
+#define HWIO_TCL_R1_FSE_SM_STATES_APP_RETURN_STATE_SHFT                     0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x)                          (x+0x000010ec)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_PHYS(x)                          (x+0x000010ec)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK                             0x000003ff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_SHFT                                      0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_BMSK                    0x000003ff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_READ_IDX_SHFT                           0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x)              (x+0x000010f0)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_PHYS(x)              (x+0x000010f0)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK                 0x007fffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_SHFT                          0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)                \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask)         \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val)          \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val)   \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK         0x007ffff8
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT                0x3
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK      0x00000004
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT             0x2
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK           0x00000002
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT                  0x1
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK           0x00000001
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT                  0x0
+
+//// Register TCL_R1_FSE_CACHE_DEBUG_ENTRY_n ////
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n)            (base+0x10F4+0x4*n)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_PHYS(base, n)            (base+0x10F4+0x4*n)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK                     0xffffffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_SHFT                              0
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_MAXn                             31
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)             \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_RMSK)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask)      \
+	in_dword_masked ( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) 
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val)       \
+	out_dword( HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val)
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_BMSK                 0xffffffff
+#define HWIO_TCL_R1_FSE_CACHE_DEBUG_ENTRY_n_VAL_SHFT                        0x0
+
+//// Register TCL_R2_SW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x)                          (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x)                          (x+0x00002000)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x)                          (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x)                          (x+0x00002004)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL2_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x)                          (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x)                          (x+0x00002008)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL2_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x)                          (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x)                          (x+0x0000200c)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL3_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x)                          (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x)                          (x+0x00002010)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL3_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x)                          (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x)                          (x+0x00002014)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_SW2TCL_CMD_RING_HP ////
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x)                       (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_PHYS(x)                       (x+0x00002018)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK                          0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_SHFT                                   0
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_HP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_BMSK                 0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_HP_HEAD_PTR_SHFT                        0x0
+
+//// Register TCL_R2_SW2TCL_CMD_RING_TP ////
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x)                       (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_PHYS(x)                       (x+0x0000201c)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK                          0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_SHFT                                   0
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)                         \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CMD_RING_TP_RMSK)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_INM(x, mask)                  \
+	in_dword_masked ( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUT(x, val)                   \
+	out_dword( HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_OUTM(x, mask, val)            \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CMD_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CMD_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_BMSK                 0x0000ffff
+#define HWIO_TCL_R2_SW2TCL_CMD_RING_TP_TAIL_PTR_SHFT                        0x0
+
+//// Register TCL_R2_FW2TCL1_RING_HP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x)                          (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x)                          (x+0x00002020)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_FW2TCL1_RING_TP ////
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x)                          (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x)                          (x+0x00002024)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL2TQM_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x)                          (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x)                          (x+0x00002028)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT                                      0
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL2TQM_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x)                          (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x)                          (x+0x0000202c)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK                             0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT                                      0
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)                            \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask)                     \
+	in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val)                      \
+	out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val)               \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK                    0x0000ffff
+#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT                           0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x)                      (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x)                      (x+0x00002030)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS1_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x)                      (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x)                      (x+0x00002034)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_HP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x)                      (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x)                      (x+0x00002038)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL_STATUS2_RING_TP ////
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x)                      (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x)                      (x+0x0000203c)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK                         0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT                                  0
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)                        \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask)                 \
+	in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val)                  \
+	out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val)           \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK                0x0000ffff
+#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT                       0x0
+
+//// Register TCL_R2_TCL2FW_RING_HP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x)                           (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x)                           (x+0x00002040)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK                              0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT                                       0
+#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK                     0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT                            0x0
+
+//// Register TCL_R2_TCL2FW_RING_TP ////
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x)                           (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x)                           (x+0x00002044)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK                              0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT                                       0
+#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)                             \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask)                      \
+	in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) 
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val)                       \
+	out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val)
+#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val)                \
+	do {\
+		HWIO_INTLOCK(); \
+		out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \
+		HWIO_INTFREE();\
+	} while (0) 
+
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK                     0x0000ffff
+#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT                            0x0
+
+
+#endif
+

hw/qca8074/v1/msmhwio.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef MSMHWIO_H
+#define MSMHWIO_H
+/*
+===========================================================================
+*/
+/**
+  @file msmhwio.h 
+
+  Deprecated public interface include file for accessing the HWIO macro
+  definitions.
+
+  The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO)
+  register access definitions.  See HALhwio.h and DDIHWIO.h for the new
+  interfaces.
+*/
+/*  
+  ==================================================================== 
+  $Header: //components/rel/core.mpss/3.9.2/api/systemdrivers/msmhwio.h#1 $ $DateTime: 2016/01/19 23:36:58 $ $Author: pwbldsvc $
+  ====================================================================
+*/ 
+
+/*=========================================================================
+      Include Files
+==========================================================================*/
+
+/*
+ * Include main HWIO macros.
+ */
+#include "HALhwio.h"
+
+
+#endif /* MSMHWIO_H */
+

hw/qca8074/v1/reo_destination_ring.h

@@ -0,0 +1,730 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_DESTINATION_RING_H_
+#define _REO_DESTINATION_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "buffer_addr_info.h"
+#include "rx_mpdu_desc_info.h"
+#include "rx_msdu_desc_info.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-1	struct buffer_addr_info buf_or_link_desc_addr_info;
+//	2-3	struct rx_mpdu_desc_info rx_mpdu_desc_info_details;
+//	4-5	struct rx_msdu_desc_info rx_msdu_desc_info_details;
+//	6	rx_reo_queue_desc_addr_31_0[31:0]
+//	7	rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16]
+//	8	soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], reserved_8a[31:13]
+//	9	reserved_9a[31:0]
+//	10	reserved_10a[31:0]
+//	11	reserved_11a[31:0]
+//	12	reserved_12a[31:0]
+//	13	reserved_13a[31:0]
+//	14	reserved_14a[31:0]
+//	15	reserved_15[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_DESTINATION_RING 16
+
+struct reo_destination_ring {
+    struct            buffer_addr_info                       buf_or_link_desc_addr_info;
+    struct            rx_mpdu_desc_info                       rx_mpdu_desc_info_details;
+    struct            rx_msdu_desc_info                       rx_msdu_desc_info_details;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      reo_dest_buffer_type            :  1, //[8]
+                      reo_push_reason                 :  2, //[10:9]
+                      reo_error_code                  :  5, //[15:11]
+                      receive_queue_number            : 16; //[31:16]
+             uint32_t soft_reorder_info_valid         :  1, //[0]
+                      reorder_opcode                  :  4, //[4:1]
+                      reorder_slot_index              :  8, //[12:5]
+                      reserved_8a                     : 19; //[31:13]
+             uint32_t reserved_9a                     : 32; //[31:0]
+             uint32_t reserved_10a                    : 32; //[31:0]
+             uint32_t reserved_11a                    : 32; //[31:0]
+             uint32_t reserved_12a                    : 32; //[31:0]
+             uint32_t reserved_13a                    : 32; //[31:0]
+             uint32_t reserved_14a                    : 32; //[31:0]
+             uint32_t reserved_15                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct buffer_addr_info buf_or_link_desc_addr_info
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			Details of the physical address of the a buffer or MSDU
+			link descriptor
+
+struct rx_mpdu_desc_info rx_mpdu_desc_info_details
+			
+			Consumer: REO/SW/FW
+			
+			Producer: RXDMA
+			
+			
+			
+			General information related to the MPDU that is passed
+			on from REO entrance ring to the REO destination ring
+
+struct rx_msdu_desc_info rx_msdu_desc_info_details
+			
+			General information related to the MSDU that is passed
+			on from RXDMA all the way to to the REO destination ring.
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+reo_dest_buffer_type
+			
+			Indicates the type of address provided in the
+			'Buf_or_link_desc_addr_info'
+			
+			
+			
+			<enum 0 MSDU_buf_address> The address of an MSDU buffer
+			
+			<enum 1 MSDU_link_desc_address> The address of the MSDU
+			link descriptor. 
+			
+			
+			
+			<legal all>
+
+reo_push_reason
+			
+			Indicates why REO pushed the frame to this exit ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			
+			
+			<legal 0 - 1>
+
+reo_error_code
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+
+receive_queue_number
+			
+			This field indicates the REO MPDU reorder queue ID from
+			which this frame originated. This field is populated from a
+			field with the same name in the RX_REO_QUEUE descriptor.
+			
+			<legal all>
+
+soft_reorder_info_valid
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes
+			
+			<legal all>
+
+reorder_opcode
+			
+			Field is valid when 'Soft_reorder_info_valid' is set.
+			This field is always valid for debug purpose as well.
+			
+			Details are in the MLD.
+			
+			
+			
+			<enum 0 invalid>
+			
+			<enum 1 fwdcur_fwdbuf>
+			
+			<enum 2 fwdbuf_fwdcur>
+			
+			<enum 3 qcur>
+			
+			<enum 4 fwdbuf_qcur>
+			
+			<enum 5 fwdbuf_drop>
+			
+			<enum 6 fwdall_drop>
+			
+			<enum 7 fwdall_qcur>
+			
+			<enum 8 reserved_reo_opcode_1>
+			
+			<enum 9 dropcur>  the error reason code is in
+			reo_error_code field.
+			
+			<enum 10 reserved_reo_opcode_2>
+			
+			<enum 11 reserved_reo_opcode_3>
+			
+			<enum 12 reserved_reo_opcode_4>
+			
+			<enum 13 reserved_reo_opcode_5>
+			
+			<enum 14 reserved_reo_opcode_6>
+			
+			<enum 15 reserved_reo_opcode_7>
+			
+			
+			
+			<legal all>
+
+reorder_slot_index
+			
+			Field only valid when 'Soft_reorder_info_valid' is set.
+			
+			
+			
+			TODO: add description
+			
+			
+			
+			<legal all>
+
+reserved_8a
+			
+			<legal 0>
+
+reserved_9a
+			
+			<legal 0>
+
+reserved_10a
+			
+			<legal 0>
+
+reserved_11a
+			
+			<legal 0>
+
+reserved_12a
+			
+			<legal 0>
+
+reserved_13a
+			
+			<legal 0>
+
+reserved_14a
+			
+			<legal 0>
+
+reserved_15
+			
+			<legal 0>
+
+ring_id
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+
+looping_count
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000000
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
+#define REO_DESTINATION_RING_0_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_OFFSET 0x00000004
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_LSB 28
+#define REO_DESTINATION_RING_1_BUFFER_ADDR_INFO_BUF_OR_LINK_DESC_ADDR_INFO_MASK 0xffffffff
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x00000008
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 0x0000000c
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000010
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 0x00000014
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_LSB 28
+#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_MASK 0xffffffff
+
+/* Description		REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET    0x00000018
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB       0
+#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK      0xffffffff
+
+/* Description		REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET   0x0000001c
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB      0
+#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK     0x000000ff
+
+/* Description		REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE
+			
+			Indicates the type of address provided in the
+			'Buf_or_link_desc_addr_info'
+			
+			
+			
+			<enum 0 MSDU_buf_address> The address of an MSDU buffer
+			
+			<enum 1 MSDU_link_desc_address> The address of the MSDU
+			link descriptor. 
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB              8
+#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK             0x00000100
+
+/* Description		REO_DESTINATION_RING_7_REO_PUSH_REASON
+			
+			Indicates why REO pushed the frame to this exit ring
+			
+			
+			
+			<enum 0 reo_error_detected> Reo detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 reo_routing_instruction> Reo pushed the frame to
+			this queue per received routing instructions. No error
+			within REO was detected
+			
+			
+			
+			
+			
+			<legal 0 - 1>
+*/
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET                0x0000001c
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB                   9
+#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK                  0x00000600
+
+/* Description		REO_DESTINATION_RING_7_REO_ERROR_CODE
+			
+			Field only valid when 'Reo_push_reason' set to
+			'reo_error_detected'.
+			
+			
+			
+			<enum 0 reo_queue_desc_addr_zero> Reo queue descriptor
+			provided in the REO_ENTRANCE ring is set to 0
+			
+			<enum 1 reo_queue_desc_not_valid> Reo queue descriptor
+			valid bit is NOT set
+			
+			<enum 2 ampdu_in_non_ba> AMPDU frame received without BA
+			session having been setup.
+			
+			<enum 3 non_ba_duplicate> Non-BA session, SN equal to
+			SSN, Retry bit set: duplicate frame
+			
+			<enum 4 ba_duplicate> BA session, duplicate frame
+			
+			<enum 5 regular_frame_2k_jump> A normal (management/data
+			frame) received with 2K jump in SN
+			
+			<enum 6 bar_frame_2k_jump> A bar received with 2K jump
+			in SSN
+			
+			<enum 7 regular_frame_OOR> A normal (management/data
+			frame) received with SN falling within the OOR window
+			
+			<enum 8 bar_frame_OOR> A bar received with SSN falling
+			within the OOR window
+			
+			<enum 9 bar_frame_no_ba_session> A bar received without
+			a BA session
+			
+			<enum 10 bar_frame_sn_equals_ssn> A bar received with
+			SSN equal to SN
+			
+			<enum 11 pn_check_failed> PN Check Failed packet.
+			
+			<enum 12 2k_error_handling_flag_set> Frame is forwarded
+			as a result of the 'Seq_2k_error_detected_flag' been set in
+			the REO Queue descriptor
+			
+			<enum 13 pn_error_handling_flag_set> Frame is forwarded
+			as a result of the 'pn_error_detected_flag' been set in the
+			REO Queue descriptor
+			
+			<enum 14 queue_descriptor_blocked_set> Frame is
+			forwarded as a result of the queue descriptor(address) being
+			blocked as SW/FW seems to be currently in the process of
+			making updates to this descriptor...
+			
+			
+			
+			<legal 0-14>
+*/
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET                 0x0000001c
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB                    11
+#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK                   0x0000f800
+
+/* Description		REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER
+			
+			This field indicates the REO MPDU reorder queue ID from
+			which this frame originated. This field is populated from a
+			field with the same name in the RX_REO_QUEUE descriptor.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET           0x0000001c
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB              16
+#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK             0xffff0000
+
+/* Description		REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID
+			
+			When set, REO has been instructed to not perform the
+			actual re-ordering of frames for this queue, but just to
+			insert the reorder opcodes
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET        0x00000020
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB           0
+#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK          0x00000001
+
+/* Description		REO_DESTINATION_RING_8_REORDER_OPCODE
+			
+			Field is valid when 'Soft_reorder_info_valid' is set.
+			This field is always valid for debug purpose as well.
+			
+			Details are in the MLD.
+			
+			
+			
+			<enum 0 invalid>
+			
+			<enum 1 fwdcur_fwdbuf>
+			
+			<enum 2 fwdbuf_fwdcur>
+			
+			<enum 3 qcur>
+			
+			<enum 4 fwdbuf_qcur>
+			
+			<enum 5 fwdbuf_drop>
+			
+			<enum 6 fwdall_drop>
+			
+			<enum 7 fwdall_qcur>
+			
+			<enum 8 reserved_reo_opcode_1>
+			
+			<enum 9 dropcur>  the error reason code is in
+			reo_error_code field.
+			
+			<enum 10 reserved_reo_opcode_2>
+			
+			<enum 11 reserved_reo_opcode_3>
+			
+			<enum 12 reserved_reo_opcode_4>
+			
+			<enum 13 reserved_reo_opcode_5>
+			
+			<enum 14 reserved_reo_opcode_6>
+			
+			<enum 15 reserved_reo_opcode_7>
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET                 0x00000020
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB                    1
+#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK                   0x0000001e
+
+/* Description		REO_DESTINATION_RING_8_REORDER_SLOT_INDEX
+			
+			Field only valid when 'Soft_reorder_info_valid' is set.
+			
+			
+			
+			TODO: add description
+			
+			
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET             0x00000020
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB                5
+#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK               0x00001fe0
+
+/* Description		REO_DESTINATION_RING_8_RESERVED_8A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET                    0x00000020
+#define REO_DESTINATION_RING_8_RESERVED_8A_LSB                       13
+#define REO_DESTINATION_RING_8_RESERVED_8A_MASK                      0xffffe000
+
+/* Description		REO_DESTINATION_RING_9_RESERVED_9A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_9_RESERVED_9A_OFFSET                    0x00000024
+#define REO_DESTINATION_RING_9_RESERVED_9A_LSB                       0
+#define REO_DESTINATION_RING_9_RESERVED_9A_MASK                      0xffffffff
+
+/* Description		REO_DESTINATION_RING_10_RESERVED_10A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET                  0x00000028
+#define REO_DESTINATION_RING_10_RESERVED_10A_LSB                     0
+#define REO_DESTINATION_RING_10_RESERVED_10A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_11_RESERVED_11A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET                  0x0000002c
+#define REO_DESTINATION_RING_11_RESERVED_11A_LSB                     0
+#define REO_DESTINATION_RING_11_RESERVED_11A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_12_RESERVED_12A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET                  0x00000030
+#define REO_DESTINATION_RING_12_RESERVED_12A_LSB                     0
+#define REO_DESTINATION_RING_12_RESERVED_12A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_13_RESERVED_13A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET                  0x00000034
+#define REO_DESTINATION_RING_13_RESERVED_13A_LSB                     0
+#define REO_DESTINATION_RING_13_RESERVED_13A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_14_RESERVED_14A
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET                  0x00000038
+#define REO_DESTINATION_RING_14_RESERVED_14A_LSB                     0
+#define REO_DESTINATION_RING_14_RESERVED_14A_MASK                    0xffffffff
+
+/* Description		REO_DESTINATION_RING_15_RESERVED_15
+			
+			<legal 0>
+*/
+#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET                   0x0000003c
+#define REO_DESTINATION_RING_15_RESERVED_15_LSB                      0
+#define REO_DESTINATION_RING_15_RESERVED_15_MASK                     0x000fffff
+
+/* Description		REO_DESTINATION_RING_15_RING_ID
+			
+			The buffer pointer ring ID.
+			
+			0 refers to the IDLE ring
+			
+			1 - N refers to other rings
+			
+			
+			
+			Helps with debugging when dumping ring contents.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_15_RING_ID_OFFSET                       0x0000003c
+#define REO_DESTINATION_RING_15_RING_ID_LSB                          20
+#define REO_DESTINATION_RING_15_RING_ID_MASK                         0x0ff00000
+
+/* Description		REO_DESTINATION_RING_15_LOOPING_COUNT
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET                 0x0000003c
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB                    28
+#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK                   0xf0000000
+
+
+#endif // _REO_DESTINATION_RING_H_

hw/qca8074/v1/reo_entrance_ring.h

@@ -0,0 +1,722 @@
+/*
+ * Copyright (c) 2016 The Linux Foundation. All rights reserved.
+ *
+ * Permission to use, copy, modify, and/or distribute this software for
+ * any purpose with or without fee is hereby granted, provided that the
+ * above copyright notice and this permission notice appear in all
+ * copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
+ * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
+ * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
+ * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
+ * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
+ * PERFORMANCE OF THIS SOFTWARE.
+ */
+
+// $ATH_LICENSE_HW_HDR_C$
+//
+// DO NOT EDIT!  This file is automatically generated
+//               These definitions are tied to a particular hardware layout
+
+
+#ifndef _REO_ENTRANCE_RING_H_
+#define _REO_ENTRANCE_RING_H_
+#if !defined(__ASSEMBLER__)
+#endif
+
+#include "rx_mpdu_details.h"
+
+// ################ START SUMMARY #################
+//
+//	Dword	Fields
+//	0-3	struct rx_mpdu_details reo_level_mpdu_frame_info;
+//	4	rx_reo_queue_desc_addr_31_0[31:0]
+//	5	rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28]
+//	6	rxdma_push_reason[1:0], rxdma_error_code[6:2], reserved_6a[31:7]
+//	7	reserved_7a[19:0], ring_id[27:20], looping_count[31:28]
+//
+// ################ END SUMMARY #################
+
+#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8
+
+struct reo_entrance_ring {
+    struct            rx_mpdu_details                       reo_level_mpdu_frame_info;
+             uint32_t rx_reo_queue_desc_addr_31_0     : 32; //[31:0]
+             uint32_t rx_reo_queue_desc_addr_39_32    :  8, //[7:0]
+                      rounded_mpdu_byte_count         : 14, //[21:8]
+                      reo_destination_indication      :  5, //[26:22]
+                      frameless_bar                   :  1, //[27]
+                      reserved_5a                     :  4; //[31:28]
+             uint32_t rxdma_push_reason               :  2, //[1:0]
+                      rxdma_error_code                :  5, //[6:2]
+                      reserved_6a                     : 25; //[31:7]
+             uint32_t reserved_7a                     : 20, //[19:0]
+                      ring_id                         :  8, //[27:20]
+                      looping_count                   :  4; //[31:28]
+};
+
+/*
+
+struct rx_mpdu_details reo_level_mpdu_frame_info
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Details related to the MPDU being pushed into the REO
+
+rx_reo_queue_desc_addr_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rx_reo_queue_desc_addr_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+
+rounded_mpdu_byte_count
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+
+reo_destination_indication
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+
+frameless_bar
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+
+reserved_5a
+			
+			<legal 0>
+
+rxdma_push_reason
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			This field is ignored by REO. 
+			
+			<legal 0 - 1>
+
+rxdma_error_code
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+
+reserved_6a
+			
+			<legal 0>
+
+reserved_7a
+			
+			<legal 0>
+
+ring_id
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+
+looping_count
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000000
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_0_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000004
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_1_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x00000008
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_2_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_OFFSET 0x0000000c
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_LSB 28
+#define REO_ENTRANCE_RING_3_RX_MPDU_DETAILS_REO_LEVEL_MPDU_FRAME_INFO_MASK 0xffffffff
+
+/* Description		REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (lower 32 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET       0x00000010
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB          0
+#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK         0xffffffff
+
+/* Description		REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32
+			
+			Consumer: REO
+			
+			Producer: RXDMA
+			
+			
+			
+			Address (upper 8 bits) of the REO queue descriptor. 
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET      0x00000014
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB         0
+#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK        0x000000ff
+
+/* Description		REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT
+			
+			An approximation of the number of bytes received in this
+			MPDU. 
+			
+			Used to keeps stats on the amount of data flowing
+			through a queue.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET           0x00000014
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB              8
+#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK             0x003fff00
+
+/* Description		REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION
+			
+			RXDMA copy the MPDU's first MSDU's destination
+			indication field here. This is used for REO to be able to
+			re-route the packet to a different SW destination ring if
+			the packet is detected as error in REO.
+			
+			
+			
+			The ID of the REO exit ring where the MSDU frame shall
+			push after (MPDU level) reordering has finished.
+			
+			
+			
+			<enum 0 reo_destination_tcl> Reo will push the frame
+			into the REO2TCL ring
+			
+			<enum 1 reo_destination_sw1> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 2 reo_destination_sw2> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 3 reo_destination_sw3> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 4 reo_destination_sw4> Reo will push the frame
+			into the REO2SW1 ring
+			
+			<enum 5 reo_destination_release> Reo will push the frame
+			into the REO_release ring
+			
+			<enum 6 reo_destination_fw> Reo will push the frame into
+			the REO2FW ring
+			
+			<enum 7 reo_destination_7> REO remaps this
+			
+			<enum 8 reo_destination_8> REO remaps this <enum 9
+			reo_destination_9> REO remaps this <enum 10
+			reo_destination_10> REO remaps this 
+			
+			<enum 11 reo_destination_11> REO remaps this 
+			
+			<enum 12 reo_destination_12> REO remaps this <enum 13
+			reo_destination_13> REO remaps this 
+			
+			<enum 14 reo_destination_14> REO remaps this 
+			
+			<enum 15 reo_destination_15> REO remaps this 
+			
+			<enum 16 reo_destination_16> REO remaps this 
+			
+			<enum 17 reo_destination_17> REO remaps this 
+			
+			<enum 18 reo_destination_18> REO remaps this 
+			
+			<enum 19 reo_destination_19> REO remaps this 
+			
+			<enum 20 reo_destination_20> REO remaps this 
+			
+			<enum 21 reo_destination_21> REO remaps this 
+			
+			<enum 22 reo_destination_22> REO remaps this 
+			
+			<enum 23 reo_destination_23> REO remaps this 
+			
+			<enum 24 reo_destination_24> REO remaps this 
+			
+			<enum 25 reo_destination_25> REO remaps this 
+			
+			<enum 26 reo_destination_26> REO remaps this 
+			
+			<enum 27 reo_destination_27> REO remaps this 
+			
+			<enum 28 reo_destination_28> REO remaps this 
+			
+			<enum 29 reo_destination_29> REO remaps this 
+			
+			<enum 30 reo_destination_30> REO remaps this 
+			
+			<enum 31 reo_destination_31> REO remaps this 
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET        0x00000014
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB           22
+#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK          0x07c00000
+
+/* Description		REO_ENTRANCE_RING_5_FRAMELESS_BAR
+			
+			When set, this REO entrance ring struct contains BAR
+			info from a multi TID BAR frame. The original multi TID BAR
+			frame itself contained all the REO info for the first TID,
+			but all the subsequent TID info and their linkage to the REO
+			descriptors is passed down as 'frameless' BAR info.
+			
+			
+			
+			The only fields valid in this descriptor when this bit
+			is set are:
+			
+			Rx_reo_queue_desc_addr_31_0
+			
+			RX_reo_queue_desc_addr_39_32
+			
+			
+			
+			And within the
+			
+			Reo_level_mpdu_frame_info:    
+			
+			   Within Rx_mpdu_desc_info_details:
+			
+			Mpdu_Sequence_number
+			
+			BAR_frame
+			
+			Peer_meta_data
+			
+			All other fields shall be set to 0
+			
+			
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET                     0x00000014
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB                        27
+#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK                       0x08000000
+
+/* Description		REO_ENTRANCE_RING_5_RESERVED_5A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET                       0x00000014
+#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB                          28
+#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK                         0xf0000000
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON
+			
+			Indicates why rxdma pushed the frame to this ring
+			
+			
+			
+			<enum 0 rxdma_error_detected> RXDMA detected an error an
+			pushed this frame to this queue
+			
+			<enum 1 rxdma_routing_instruction> RXDMA pushed the
+			frame to this queue per received routing instructions. No
+			error within RXDMA was detected
+			
+			
+			
+			This field is ignored by REO. 
+			
+			<legal 0 - 1>
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET                 0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB                    0
+#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK                   0x00000003
+
+/* Description		REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE
+			
+			Field only valid when 'rxdma_push_reason' set to
+			'rxdma_error_detected'.
+			
+			
+			
+			This field is ignored by REO.
+			
+			
+			
+			<enum 0 rxdma_overflow_err>MPDU frame is not complete
+			due to a FIFO overflow error in RXPCU.
+			
+			<enum 1 rxdma_mpdu_length_err>MPDU frame is not complete
+			due to receiving incomplete MPDU from the PHY
+			
+			
+			<enum 3 rxdma_decrypt_err>CRYPTO reported a decryption
+			error
+			
+			<enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC
+			error
+			
+			<enum 5 rxdma_unecrypted_err>CRYPTO reported an
+			unencrypted frame error when encrypted was expected
+			
+			<enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU
+			length error
+			
+			<enum 7 rxdma_msdu_limit_err>RX OLE reported that max
+			number of MSDUs allowed in an MPDU got exceeded
+			
+			<enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing
+			error
+			
+			<enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU
+			parsing error
+			
+			<enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout
+			during SA search
+			
+			<enum 11 rxdma_da_timeout_err>RX OLE reported a timeout
+			during DA search
+			
+			<enum 12 rxdma_flow_timeout_err>RX OLE reported a
+			timeout during flow search
+			
+			<enum 13 Rxdma_flush_request>RXDMA received a flush
+			request
+*/
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET                  0x00000018
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB                     2
+#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK                    0x0000007c
+
+/* Description		REO_ENTRANCE_RING_6_RESERVED_6A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET                       0x00000018
+#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB                          7
+#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK                         0xffffff80
+
+/* Description		REO_ENTRANCE_RING_7_RESERVED_7A
+			
+			<legal 0>
+*/
+#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET                       0x0000001c
+#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB                          0
+#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK                         0x000fffff
+
+/* Description		REO_ENTRANCE_RING_7_RING_ID
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			It help to identify the ring that is being looked <legal
+			all>
+*/
+#define REO_ENTRANCE_RING_7_RING_ID_OFFSET                           0x0000001c
+#define REO_ENTRANCE_RING_7_RING_ID_LSB                              20
+#define REO_ENTRANCE_RING_7_RING_ID_MASK                             0x0ff00000
+
+/* Description		REO_ENTRANCE_RING_7_LOOPING_COUNT
+			
+			Consumer: SW/REO/DEBUG
+			
+			Producer: SRNG (of RXDMA)
+			
+			
+			
+			For debugging. 
+			
+			This field is filled in by the SRNG module.
+			
+			
+			
+			A count value that indicates the number of times the
+			producer of entries into this Ring has looped around the
+			ring.
+			
+			At initialization time, this value is set to 0. On the
+			first loop, this value is set to 1. After the max value is
+			reached allowed by the number of bits for this field, the
+			count value continues with 0 again.
+			
+			
+			
+			In case SW is the consumer of the ring entries, it can
+			use this field to figure out up to where the producer of
+			entries has created new entries. This eliminates the need to
+			check where the head pointer' of the ring is located once
+			the SW starts processing an interrupt indicating that new
+			entries have been put into this ring...
+			
+			
+			
+			Also note that SW if it wants only needs to look at the
+			LSB bit of this count value.
+			
+			<legal all>
+*/
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET                     0x0000001c
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB                        28
+#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK                       0xf0000000
+
+
+#endif // _REO_ENTRANCE_RING_H_