qcacmn: [1/2] Support both qca8074v1 and qca8074v2 from hal
Some of the macro names defined in qca8074v1, are defined with a slightly different name in qca8074v2, and few macros have the same name in both headers but are defined with different values. Fixed the same. Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
This commit is contained in:
Balamurugan Mahalingam
committed by
nshrivas
nshrivas
vanhempi
31c991610b
commit
5d80641550
@@ -277,47 +277,6 @@ enum hal_tx_dscp_tid_table_id {
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/*---------------------------------------------------------------------------
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TCL Descriptor accessor APIs
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---------------------------------------------------------------------------*/
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/**
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* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @paddr: Physical Address
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* @pool_id: Return Buffer Manager ID
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* @desc_id: Descriptor ID
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* @type: 0 - Address points to a MSDU buffer
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* 1 - Address points to MSDU extension descriptor
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_buf_addr(void *desc,
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dma_addr_t paddr, uint8_t pool_id,
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uint32_t desc_id, uint8_t type)
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{
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/* Set buffer_addr_info.buffer_addr_31_0 */
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HAL_SET_FLD(desc, TCL_DATA_CMD_0, BUFFER_ADDR_INFO_BUF_ADDR_INFO) =
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HAL_TX_SM(BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, paddr);
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/* Set buffer_addr_info.buffer_addr_39_32 */
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HAL_SET_FLD(desc, TCL_DATA_CMD_1,
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BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
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HAL_TX_SM(BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
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(((uint64_t) paddr) >> 32));
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/* Set buffer_addr_info.return_buffer_manager = pool id */
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HAL_SET_FLD(desc, TCL_DATA_CMD_1,
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BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
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HAL_TX_SM(BUFFER_ADDR_INFO_1,
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RETURN_BUFFER_MANAGER, (pool_id + HAL_WBM_SW0_BM_ID));
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/* Set buffer_addr_info.sw_buffer_cookie = desc_id */
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HAL_SET_FLD(desc, TCL_DATA_CMD_1,
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BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
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HAL_TX_SM(BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, desc_id);
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/* Set Buffer or Ext Descriptor Type */
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HAL_SET_FLD(desc, TCL_DATA_CMD_2,
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BUF_OR_EXT_DESC_TYPE) |=
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HAL_TX_SM(TCL_DATA_CMD_2, BUF_OR_EXT_DESC_TYPE, type);
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}
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/**
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* hal_tx_desc_set_buf_length - Set Data length in bytes in Tx Descriptor
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@@ -830,90 +789,6 @@ static inline uint8_t hal_tx_comp_get_release_reason(void *hal_desc)
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WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB;
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}
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/**
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* hal_tx_comp_get_status() - TQM Release reason
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* @hal_desc: completion ring Tx status
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*
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* This function will parse the WBM completion descriptor and populate in
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* HAL structure
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*
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* Return: none
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*/
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#if defined(WCSS_VERSION) && \
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((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
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(defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
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static inline void hal_tx_comp_get_status(void *desc,
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struct hal_tx_completion_status *ts)
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{
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uint8_t rate_stats_valid = 0;
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uint32_t rate_stats = 0;
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ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
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TQM_STATUS_NUMBER);
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ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
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ACK_FRAME_RSSI);
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ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
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ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
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ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
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MSDU_PART_OF_AMSDU);
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ts->peer_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, SW_PEER_ID);
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ts->tid = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_7, TID);
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ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
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TRANSMIT_COUNT);
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rate_stats = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_5,
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TX_RATE_STATS);
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rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO_0,
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TX_RATE_STATS_INFO_VALID, rate_stats);
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ts->valid = rate_stats_valid;
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if (rate_stats_valid) {
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ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_BW,
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rate_stats);
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ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO_0,
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TRANSMIT_PKT_TYPE, rate_stats);
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ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO_0,
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TRANSMIT_STBC, rate_stats);
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ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_LDPC,
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rate_stats);
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ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_SGI,
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rate_stats);
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ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO_0, TRANSMIT_MCS,
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rate_stats);
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ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO_0, OFDMA_TRANSMISSION,
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rate_stats);
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ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO_0, TONES_IN_RU,
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rate_stats);
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}
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ts->release_src = hal_tx_comp_get_buffer_source(desc);
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ts->status = hal_tx_comp_get_release_reason(desc);
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ts->tsf = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_6,
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TX_RATE_STATS_INFO_TX_RATE_STATS);
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}
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#else
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static inline void hal_tx_comp_get_status(void *desc,
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struct hal_tx_completion_status *ts)
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{
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ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_3,
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TQM_STATUS_NUMBER);
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ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
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ACK_FRAME_RSSI);
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ts->first_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, FIRST_MSDU);
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ts->last_msdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4, LAST_MSDU);
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ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, WBM_RELEASE_RING_4,
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MSDU_PART_OF_AMSDU);
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ts->release_src = hal_tx_comp_get_buffer_source(desc);
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ts->status = hal_tx_comp_get_release_reason(desc);
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}
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#endif
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/**
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* hal_tx_comp_desc_sync() - collect hardware descriptor contents
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* @hal_desc: hardware descriptor pointer
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@@ -1042,4 +917,42 @@ static inline void hal_tx_desc_set_lmac_id(struct hal_soc *hal_soc,
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{
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hal_soc->ops->hal_tx_desc_set_lmac_id(desc, lmac_id);
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}
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/**
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* hal_tx_comp_get_status() - TQM Release reason
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* @hal_desc: completion ring Tx status
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*
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* This function will parse the WBM completion descriptor and populate in
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* HAL structure
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*
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* Return: none
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*/
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static inline void hal_tx_comp_get_status(void *desc, void *ts, void *hal)
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{
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struct hal_soc *hal_soc = hal;
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hal_soc->ops->hal_tx_comp_get_status(desc, ts);
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}
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/**
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* hal_tx_desc_set_buf_addr - Fill Buffer Address information in Tx Descriptor
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* @desc: Handle to Tx Descriptor
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* @paddr: Physical Address
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* @pool_id: Return Buffer Manager ID
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* @desc_id: Descriptor ID
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* @type: 0 - Address points to a MSDU buffer
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* 1 - Address points to MSDU extension descriptor
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*
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* Return: void
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*/
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static inline void hal_tx_desc_set_buf_addr(void *desc, dma_addr_t paddr,
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uint8_t pool_id, uint32_t desc_id, uint8_t type, void *hal)
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{
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struct hal_soc *hal_soc = hal;
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hal_soc->ops->hal_tx_desc_set_buf_addr(desc, paddr, pool_id,
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desc_id, type);
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}
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#endif /* HAL_TX_H */
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