qcacmn: [1/2] Support both qca8074v1 and qca8074v2 from hal
Some of the macro names defined in qca8074v1, are defined with a slightly different name in qca8074v2, and few macros have the same name in both headers but are defined with different values. Fixed the same. Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
This commit is contained in:
Balamurugan Mahalingam
committed by
nshrivas
nshrivas
parent
31c991610b
commit
5d80641550
@@ -1,31 +1,21 @@
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/*
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* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hal_hw_headers.h"
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#include "hal_api.h"
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#include "target_type.h"
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@@ -37,6 +27,9 @@ void hal_qca6290_attach(struct hal_soc *hal);
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#ifdef QCA_WIFI_QCA8074
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void hal_qca8074_attach(struct hal_soc *hal);
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#endif
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#ifdef QCA_WIFI_QCA8074V2
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void hal_qca8074v2_attach(struct hal_soc *hal);
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#endif
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#ifdef QCA_WIFI_QCA6390
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void hal_qca6390_attach(struct hal_soc *hal);
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#endif
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@@ -220,7 +213,6 @@ static void hal_target_based_configure(struct hal_soc *hal)
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switch (hal->target_type) {
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#ifdef QCA_WIFI_QCA6290
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case TARGET_TYPE_QCA6290:
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case TARGET_TYPE_QCA6390:
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hal->use_register_windowing = true;
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hal_qca6290_attach(hal);
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break;
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@@ -236,6 +228,12 @@ static void hal_target_based_configure(struct hal_soc *hal)
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hal_qca8074_attach(hal);
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break;
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#endif
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#if defined(QCA_WIFI_QCA8074V2) && defined(CONFIG_WIN)
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case TARGET_TYPE_QCA8074V2:
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hal_qca8074v2_attach(hal);
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break;
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#endif
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default:
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break;
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}
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@@ -369,121 +367,6 @@ extern void hal_detach(void *hal_soc)
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}
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qdf_export_symbol(hal_detach);
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/**
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* hal_srng_src_hw_init - Private function to initialize SRNG
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* source ring HW
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* @hal_soc: HAL SOC handle
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* @srng: SRNG ring pointer
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*/
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static inline void hal_srng_src_hw_init(struct hal_soc *hal,
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struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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uint64_t tp_addr = 0;
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HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE),
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srng->entry_size * srng->num_entries);
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SRNG_SRC_REG_WRITE(srng, BASE_MSB, reg_val);
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#if defined(WCSS_VERSION) && \
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((defined(CONFIG_WIN) && (WCSS_VERSION > 81)) || \
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(defined(CONFIG_MCL) && (WCSS_VERSION >= 72)))
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reg_val = SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
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#else
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reg_val = SRNG_SM(SRNG_SRC_FLD(ID, RING_ID), srng->ring_id) |
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SRNG_SM(SRNG_SRC_FLD(ID, ENTRY_SIZE), srng->entry_size);
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#endif
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SRNG_SRC_REG_WRITE(srng, ID, reg_val);
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/**
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* Interrupt setup:
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* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
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* if level mode is required
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*/
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reg_val = 0;
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/*
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* WAR - Hawkeye v1 has a hardware bug which requires timer value to be
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* programmed in terms of 1us resolution instead of 8us resolution as
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* given in MLD.
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*/
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if (srng->intr_timer_thres_us) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
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INTERRUPT_TIMER_THRESHOLD),
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srng->intr_timer_thres_us);
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/* For HK v2 this should be (srng->intr_timer_thres_us >> 3) */
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}
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if (srng->intr_batch_cntr_thres_entries) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX0,
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BATCH_COUNTER_THRESHOLD),
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srng->intr_batch_cntr_thres_entries *
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srng->entry_size);
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}
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX0, reg_val);
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reg_val = 0;
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if (srng->flags & HAL_SRNG_LOW_THRES_INTR_ENABLE) {
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reg_val |= SRNG_SM(SRNG_SRC_FLD(CONSUMER_INT_SETUP_IX1,
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LOW_THRESHOLD), srng->u.src_ring.low_threshold);
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}
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
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/* As per HW team, TP_ADDR and HP_ADDR for Idle link ring should
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* remain 0 to avoid some WBM stability issues. Remote head/tail
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* pointers are not required since this ring is completely managed
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* by WBM HW */
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if (srng->ring_id != HAL_SRNG_WBM_IDLE_LINK) {
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tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.src_ring.tp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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SRNG_SRC_REG_WRITE(srng, TP_ADDR_LSB, tp_addr & 0xffffffff);
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SRNG_SRC_REG_WRITE(srng, TP_ADDR_MSB, tp_addr >> 32);
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}
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/* Initilaize head and tail pointers to indicate ring is empty */
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SRNG_SRC_REG_WRITE(srng, HP, 0);
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SRNG_SRC_REG_WRITE(srng, TP, 0);
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*(srng->u.src_ring.tp_addr) = 0;
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reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_MSI_SWAP) ?
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SRNG_SM(SRNG_SRC_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
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/* Loop count is not used for SRC rings */
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reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, LOOPCNT_DISABLE), 1);
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/*
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* reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
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* todo: update fw_api and replace with above line
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* (when SRNG_ENABLE field for the MISC register is available in fw_api)
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* (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
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*/
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reg_val |= 0x40;
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SRNG_SRC_REG_WRITE(srng, MISC, reg_val);
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}
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/**
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* hal_ce_dst_setup - Initialize CE destination ring registers
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@@ -554,93 +437,6 @@ void hal_srng_dst_init_hp(struct hal_srng *srng,
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*(srng->u.dst_ring.hp_addr));
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}
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/**
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* hal_srng_dst_hw_init - Private function to initialize SRNG
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* destination ring HW
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* @hal_soc: HAL SOC handle
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* @srng: SRNG ring pointer
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*/
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static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
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struct hal_srng *srng)
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{
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uint32_t reg_val = 0;
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uint64_t hp_addr = 0;
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HIF_DBG("%s: hw_init srng %d", __func__, srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_SIZE),
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srng->entry_size * srng->num_entries);
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SRNG_DST_REG_WRITE(srng, BASE_MSB, reg_val);
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reg_val = SRNG_SM(SRNG_DST_FLD(ID, RING_ID), srng->ring_id) |
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SRNG_SM(SRNG_DST_FLD(ID, ENTRY_SIZE), srng->entry_size);
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SRNG_DST_REG_WRITE(srng, ID, reg_val);
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/**
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* Interrupt setup:
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* Default interrupt mode is 'pulse'. Need to setup SW_INTERRUPT_MODE
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* if level mode is required
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*/
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reg_val = 0;
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if (srng->intr_timer_thres_us) {
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
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INTERRUPT_TIMER_THRESHOLD),
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srng->intr_timer_thres_us >> 3);
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}
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if (srng->intr_batch_cntr_thres_entries) {
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reg_val |= SRNG_SM(SRNG_DST_FLD(PRODUCER_INT_SETUP,
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BATCH_COUNTER_THRESHOLD),
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srng->intr_batch_cntr_thres_entries *
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srng->entry_size);
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}
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
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hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.dst_ring.hp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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SRNG_DST_REG_WRITE(srng, HP_ADDR_LSB, hp_addr & 0xffffffff);
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SRNG_DST_REG_WRITE(srng, HP_ADDR_MSB, hp_addr >> 32);
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/* Initilaize head and tail pointers to indicate ring is empty */
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SRNG_DST_REG_WRITE(srng, HP, 0);
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SRNG_DST_REG_WRITE(srng, TP, 0);
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*(srng->u.dst_ring.hp_addr) = 0;
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reg_val = ((srng->flags & HAL_SRNG_DATA_TLV_SWAP) ?
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SRNG_SM(SRNG_DST_FLD(MISC, DATA_TLV_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_RING_PTR_SWAP) ?
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SRNG_SM(SRNG_DST_FLD(MISC, HOST_FW_SWAP_BIT), 1) : 0) |
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((srng->flags & HAL_SRNG_MSI_SWAP) ?
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SRNG_SM(SRNG_DST_FLD(MISC, MSI_SWAP_BIT), 1) : 0);
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/*
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* reg_val |= SRNG_SM(SRNG_SRC_FLD(MISC, SRNG_ENABLE), 1);
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* todo: update fw_api and replace with above line
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* (when SRNG_ENABLE field for the MISC register is available in fw_api)
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* (WCSS_UMAC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC)
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*/
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reg_val |= 0x40;
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SRNG_DST_REG_WRITE(srng, MISC, reg_val);
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}
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/**
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* hal_srng_hw_init - Private function to initialize SRNG HW
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* @hal_soc: HAL SOC handle
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