qcacmn: [1/2] Support both qca8074v1 and qca8074v2 from hal

Some of the macro names defined in qca8074v1, are defined with a slightly different name in qca8074v2, and few macros have the same name in both headers but are defined with different values. Fixed the same. Change-Id: I5e948baf5326d1d8fdfa2bd7ee8aa072c710d17c
2018-07-30 18:04:15 +05:30
--- a/hal/wifi3.0/hal_reo.c
+++ b/hal/wifi3.0/hal_reo.c
@@ -16,11 +16,233 @@
 * PERFORMANCE OF THIS SOFTWARE.
 */

+#include "hal_api.h"
 #include "hal_hw_headers.h"
 #include "hal_reo.h"
 #include "hal_tx.h"
+#include "hal_rx.h"
 #include "qdf_module.h"

+/* TODO: See if the following definition is available in HW headers */
+#define HAL_REO_OWNED 4
+#define HAL_REO_QUEUE_DESC 8
+#define HAL_REO_QUEUE_EXT_DESC 9
+
+/* TODO: Using associated link desc counter 1 for Rx. Check with FW on
+ * how these counters are assigned
+ */
+#define HAL_RX_LINK_DESC_CNTR 1
+/* TODO: Following definition should be from HW headers */
+#define HAL_DESC_REO_OWNED 4
+
+/**
+ * hal_uniform_desc_hdr_setup - setup reo_queue_ext descritpro
+ * @owner - owner info
+ * @buffer_type - buffer type
+ */
+static inline void hal_uniform_desc_hdr_setup(uint32_t *desc, uint32_t owner,
+	uint32_t buffer_type)
+{
+	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, OWNER,
+		owner);
+	HAL_DESC_SET_FIELD(desc, UNIFORM_DESCRIPTOR_HEADER_0, BUFFER_TYPE,
+		buffer_type);
+}
+
+#ifndef TID_TO_WME_AC
+#define WME_AC_BE 0 /* best effort */
+#define WME_AC_BK 1 /* background */
+#define WME_AC_VI 2 /* video */
+#define WME_AC_VO 3 /* voice */
+
+#define TID_TO_WME_AC(_tid) ( \
+	(((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
+	(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
+	(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
+	WME_AC_VO)
+#endif
+#define HAL_NON_QOS_TID 16
+
+/**
+ * hal_reo_qdesc_setup - Setup HW REO queue descriptor
+ *
+ * @hal_soc: Opaque HAL SOC handle
+ * @ba_window_size: BlockAck window size
+ * @start_seq: Starting sequence number
+ * @hw_qdesc_vaddr: Virtual address of REO queue descriptor memory
+ * @hw_qdesc_paddr: Physical address of REO queue descriptor memory
+ * @tid: TID
+ *
+ */
+void hal_reo_qdesc_setup(void *hal_soc, int tid, uint32_t ba_window_size,
+	uint32_t start_seq, void *hw_qdesc_vaddr, qdf_dma_addr_t hw_qdesc_paddr,
+	int pn_type)
+{
+	uint32_t *reo_queue_desc = (uint32_t *)hw_qdesc_vaddr;
+	uint32_t *reo_queue_ext_desc;
+	uint32_t reg_val;
+	uint32_t pn_enable;
+	uint32_t pn_size = 0;
+
+	qdf_mem_zero(hw_qdesc_vaddr, sizeof(struct rx_reo_queue));
+
+	hal_uniform_desc_hdr_setup(reo_queue_desc, HAL_DESC_REO_OWNED,
+		HAL_REO_QUEUE_DESC);
+	/* Fixed pattern in reserved bits for debugging */
+	HAL_DESC_SET_FIELD(reo_queue_desc, UNIFORM_DESCRIPTOR_HEADER_0,
+		RESERVED_0A, 0xDDBEEF);
+
+	/* This a just a SW meta data and will be copied to REO destination
+	 * descriptors indicated by hardware.
+	 * TODO: Setting TID in this field. See if we should set something else.
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_1,
+		RECEIVE_QUEUE_NUMBER, tid);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		VLD, 1);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		ASSOCIATED_LINK_DESCRIPTOR_COUNTER, HAL_RX_LINK_DESC_CNTR);
+
+	/*
+	 * Fields DISABLE_DUPLICATE_DETECTION and SOFT_REORDER_ENABLE will be 0
+	 */
+
+	reg_val = TID_TO_WME_AC(tid);
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, AC, reg_val);
+
+	if (ba_window_size < 1)
+		ba_window_size = 1;
+
+	/* Set RTY bit for non-BA case. Duplicate detection is currently not
+	 * done by HW in non-BA case if RTY bit is not set.
+	 * TODO: This is a temporary War and should be removed once HW fix is
+	 * made to check and discard duplicates even if RTY bit is not set.
+	 */
+	if (ba_window_size == 1)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, RTY, 1);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, BA_WINDOW_SIZE,
+		ba_window_size - 1);
+
+	switch (pn_type) {
+	case HAL_PN_WPA:
+		pn_enable = 1;
+		pn_size = PN_SIZE_48;
+		break;
+	case HAL_PN_WAPI_EVEN:
+	case HAL_PN_WAPI_UNEVEN:
+		pn_enable = 1;
+		pn_size = PN_SIZE_128;
+		break;
+	default:
+		pn_enable = 0;
+		break;
+	}
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_CHECK_NEEDED,
+		pn_enable);
+
+	if (pn_type == HAL_PN_WAPI_EVEN)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+			PN_SHALL_BE_EVEN, 1);
+	else if (pn_type == HAL_PN_WAPI_UNEVEN)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+			PN_SHALL_BE_UNEVEN, 1);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_HANDLING_ENABLE,
+		pn_enable);
+
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2, PN_SIZE,
+		pn_size);
+
+	/* TODO: Check if RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG need to be set
+	 * based on BA window size and/or AMPDU capabilities
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_2,
+		IGNORE_AMPDU_FLAG, 1);
+
+	if (start_seq <= 0xfff)
+		HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SSN,
+			start_seq);
+
+	/* TODO: SVLD should be set to 1 if a valid SSN is received in ADDBA,
+	 * but REO is not delivering packets if we set it to 1. Need to enable
+	 * this once the issue is resolved
+	 */
+	HAL_DESC_SET_FIELD(reo_queue_desc, RX_REO_QUEUE_3, SVLD, 0);
+
+	/* TODO: Check if we should set start PN for WAPI */
+
+#ifdef notyet
+	/* Setup first queue extension if BA window size is more than 1 */
+	if (ba_window_size > 1) {
+		reo_queue_ext_desc =
+			(uint32_t *)(((struct rx_reo_queue *)reo_queue_desc) +
+			1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+	/* Setup second queue extension if BA window size is more than 105 */
+	if (ba_window_size > 105) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+	/* Setup third queue extension if BA window size is more than 210 */
+	if (ba_window_size > 210) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc,
+			sizeof(struct rx_reo_queue_ext));
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+	}
+#else
+	/* TODO: HW queue descriptors are currently allocated for max BA
+	 * window size for all QOS TIDs so that same descriptor can be used
+	 * later when ADDBA request is recevied. This should be changed to
+	 * allocate HW queue descriptors based on BA window size being
+	 * negotiated (0 for non BA cases), and reallocate when BA window
+	 * size changes and also send WMI message to FW to change the REO
+	 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
+	 */
+	if (tid != HAL_NON_QOS_TID) {
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue *)reo_queue_desc) + 1);
+		qdf_mem_zero(reo_queue_ext_desc, 3 *
+			sizeof(struct rx_reo_queue_ext));
+		/* Initialize first reo queue extension descriptor */
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xADBEEF);
+		/* Initialize second reo queue extension descriptor */
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xBDBEEF);
+		/* Initialize third reo queue extension descriptor */
+		reo_queue_ext_desc = (uint32_t *)
+			(((struct rx_reo_queue_ext *)reo_queue_ext_desc) + 1);
+		hal_uniform_desc_hdr_setup(reo_queue_ext_desc,
+			HAL_DESC_REO_OWNED, HAL_REO_QUEUE_EXT_DESC);
+		/* Fixed pattern in reserved bits for debugging */
+		HAL_DESC_SET_FIELD(reo_queue_ext_desc,
+			UNIFORM_DESCRIPTOR_HEADER_0, RESERVED_0A, 0xCDBEEF);
+	}
+#endif
+}
+qdf_export_symbol(hal_reo_qdesc_setup);
+
 #define BLOCK_RES_MASK		0xF
 static inline uint8_t hal_find_one_bit(uint8_t x)
 {
@@ -560,7 +782,8 @@ inline int hal_reo_cmd_update_rx_queue(void *reo_ring, struct hal_soc *soc,
 qdf_export_symbol(hal_reo_cmd_update_rx_queue);

 inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
-			     struct hal_reo_queue_status *st)
+			     struct hal_reo_queue_status *st,
+			     struct hal_soc *hal_soc)
 {
 	uint32_t val;

@@ -569,7 +792,8 @@ inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_GET_QUEUE_STATS, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_QUEUE_STATS_STATUS_TLV,
+					&(st->header), hal_soc);

 	/* SSN */
 	val = reo_desc[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_2, SSN)];
@@ -751,7 +975,8 @@ inline void hal_reo_queue_stats_status(uint32_t *reo_desc,
 qdf_export_symbol(hal_reo_queue_stats_status);

 inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
-				    struct hal_reo_flush_queue_status *st)
+				    struct hal_reo_flush_queue_status *st,
+				    struct hal_soc *hal_soc)
 {
 	uint32_t val;

@@ -760,7 +985,8 @@ inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_QUEUE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_FLUSH_QUEUE_STATUS_TLV,
+					&(st->header), hal_soc);

 	/* error bit */
 	val = reo_desc[HAL_OFFSET(REO_FLUSH_QUEUE_STATUS_2,
@@ -771,7 +997,8 @@ inline void hal_reo_flush_queue_status(uint32_t *reo_desc,
 qdf_export_symbol(hal_reo_flush_queue_status);

 inline void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
-				    struct hal_reo_flush_cache_status *st)
+				    struct hal_reo_flush_cache_status *st,
+				    struct hal_soc *hal_soc)
 {
 	uint32_t val;

@@ -780,7 +1007,8 @@ inline void hal_reo_flush_cache_status(uint32_t *reo_desc, struct hal_soc *soc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_CACHE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_FLUSH_CACHE_STATUS_TLV,
+					&(st->header), hal_soc);

 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_2,
@@ -834,7 +1062,8 @@ inline void hal_reo_unblock_cache_status(uint32_t *reo_desc,
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_UNBLOCK_CACHE, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_UNBLK_CACHE_STATUS_TLV,
+					&(st->header), soc);

 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_2,
@@ -858,7 +1087,8 @@ qdf_export_symbol(hal_reo_unblock_cache_status);

 inline void hal_reo_flush_timeout_list_status(
 			 uint32_t *reo_desc,
-			 struct hal_reo_flush_timeout_list_status *st)
+			 struct hal_reo_flush_timeout_list_status *st,
+			 struct hal_soc *hal_soc)

 {
 	uint32_t val;
@@ -868,7 +1098,8 @@ inline void hal_reo_flush_timeout_list_status(
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc, REO_FLUSH_TIMEOUT_LIST, st->header);
+	hal_reo_status_get_header(reo_desc, HAL_REO_TIMOUT_LIST_STATUS_TLV,
+					&(st->header), hal_soc);

 	/* error bit */
 	val = reo_desc[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_2,
@@ -902,7 +1133,8 @@ qdf_export_symbol(hal_reo_flush_timeout_list_status);

 inline void hal_reo_desc_thres_reached_status(
 			 uint32_t *reo_desc,
-			 struct hal_reo_desc_thres_reached_status *st)
+			 struct hal_reo_desc_thres_reached_status *st,
+			 struct hal_soc *hal_soc)
 {
 	uint32_t val;

@@ -911,8 +1143,9 @@ inline void hal_reo_desc_thres_reached_status(
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc,
-			      REO_DESCRIPTOR_THRESHOLD_REACHED, st->header);
+	hal_reo_status_get_header(reo_desc,
+			      HAL_REO_DESC_THRES_STATUS_TLV,
+			      &(st->header), hal_soc);

 	/* threshold index */
 	val = reo_desc[HAL_OFFSET_DW(
@@ -959,15 +1192,17 @@ inline void hal_reo_desc_thres_reached_status(
 qdf_export_symbol(hal_reo_desc_thres_reached_status);

 inline void hal_reo_rx_update_queue_status(uint32_t *reo_desc,
-				      struct hal_reo_update_rx_queue_status *st)
+				      struct hal_reo_update_rx_queue_status *st,
+				      struct hal_soc *hal_soc)
 {
 	/* Offsets of descriptor fields defined in HW headers start
 	 * from the field after TLV header */
 	reo_desc += (sizeof(struct tlv_32_hdr) >> 2);

 	/* header */
-	HAL_REO_STATUS_GET_HEADER(reo_desc,
-			      REO_UPDATE_RX_REO_QUEUE, st->header);
+	hal_reo_status_get_header(reo_desc,
+			      HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV,
+			      &(st->header), hal_soc);
 }
 qdf_export_symbol(hal_reo_rx_update_queue_status);