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@@ -81,31 +81,6 @@
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#define SDE_INTR_INTF_2_VSYNC BIT(29)
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#define SDE_INTR_INTF_3_VSYNC BIT(31)
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-/**
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- * Pingpong Secondary interrupt status bit definitions
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- */
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-#define SDE_INTR_PING_PONG_S0_AUTOREFRESH_DONE BIT(0)
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-#define SDE_INTR_PING_PONG_S0_WR_PTR BIT(4)
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-#define SDE_INTR_PING_PONG_S0_RD_PTR BIT(8)
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-#define SDE_INTR_PING_PONG_S0_TEAR_DETECTED BIT(22)
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-#define SDE_INTR_PING_PONG_S0_TE_DETECTED BIT(28)
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-
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-/**
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- * Pingpong TEAR detection interrupt status bit definitions
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- */
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-#define SDE_INTR_PING_PONG_0_TEAR_DETECTED BIT(16)
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-#define SDE_INTR_PING_PONG_1_TEAR_DETECTED BIT(17)
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-#define SDE_INTR_PING_PONG_2_TEAR_DETECTED BIT(18)
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-#define SDE_INTR_PING_PONG_3_TEAR_DETECTED BIT(19)
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-
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-/**
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- * Pingpong TE detection interrupt status bit definitions
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- */
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-#define SDE_INTR_PING_PONG_0_TE_DETECTED BIT(24)
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-#define SDE_INTR_PING_PONG_1_TE_DETECTED BIT(25)
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-#define SDE_INTR_PING_PONG_2_TE_DETECTED BIT(26)
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-#define SDE_INTR_PING_PONG_3_TE_DETECTED BIT(27)
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-
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/**
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* Ctl start interrupt status bit definitions
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*/
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@@ -119,11 +94,6 @@
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/**
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* Concurrent WB overflow interrupt status bit definitions
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*/
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-#define SDE_INTR_CWB_1_OVERFLOW BIT(8)
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-#define SDE_INTR_CWB_2_OVERFLOW BIT(14)
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-#define SDE_INTR_CWB_3_OVERFLOW BIT(15)
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-#define SDE_INTR_CWB_4_OVERFLOW BIT(20)
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-#define SDE_INTR_CWB_5_OVERFLOW BIT(21)
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#define SDE_INTR_CWB_OVERFLOW BIT(29)
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/**
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@@ -300,17 +270,6 @@ static struct sde_irq_type sde_irq_intr_map[] = {
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};
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static struct sde_irq_type sde_irq_intr2_map[] = {
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-
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- { SDE_IRQ_TYPE_PING_PONG_AUTO_REF, PINGPONG_S0,
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- SDE_INTR_PING_PONG_S0_AUTOREFRESH_DONE, -1},
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- { SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,
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- SDE_INTR_PING_PONG_S0_WR_PTR, -1},
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-
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- { SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_1, SDE_INTR_CWB_1_OVERFLOW, -1},
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-
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- { SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,
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- SDE_INTR_PING_PONG_S0_RD_PTR, -1},
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-
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{ SDE_IRQ_TYPE_CTL_START, CTL_0,
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SDE_INTR_CTL_0_START, -1},
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{ SDE_IRQ_TYPE_CTL_START, CTL_1,
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@@ -324,36 +283,6 @@ static struct sde_irq_type sde_irq_intr2_map[] = {
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{ SDE_IRQ_TYPE_CTL_START, CTL_5,
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SDE_INTR_CTL_5_START, -1},
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- { SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_2, SDE_INTR_CWB_2_OVERFLOW, -1},
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- { SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_3, SDE_INTR_CWB_3_OVERFLOW, -1},
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-
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- { SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_0,
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- SDE_INTR_PING_PONG_0_TEAR_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_1,
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- SDE_INTR_PING_PONG_1_TEAR_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_2,
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- SDE_INTR_PING_PONG_2_TEAR_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_3,
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- SDE_INTR_PING_PONG_3_TEAR_DETECTED, -1},
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-
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- { SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_4, SDE_INTR_CWB_4_OVERFLOW, -1},
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- { SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_5, SDE_INTR_CWB_5_OVERFLOW, -1},
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-
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- { SDE_IRQ_TYPE_PING_PONG_TEAR_CHECK, PINGPONG_S0,
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- SDE_INTR_PING_PONG_S0_TEAR_DETECTED, -1},
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-
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- { SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_0,
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- SDE_INTR_PING_PONG_0_TE_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_1,
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- SDE_INTR_PING_PONG_1_TE_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_2,
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- SDE_INTR_PING_PONG_2_TE_DETECTED, -1},
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- { SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_3,
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- SDE_INTR_PING_PONG_3_TE_DETECTED, -1},
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-
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- { SDE_IRQ_TYPE_PING_PONG_TE_CHECK, PINGPONG_S0,
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- SDE_INTR_PING_PONG_S0_TE_DETECTED, -1},
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-
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{ SDE_IRQ_TYPE_CWB_OVERFLOW, PINGPONG_CWB_0, SDE_INTR_CWB_OVERFLOW, -1},
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{ SDE_IRQ_TYPE_PING_PONG_COMP, PINGPONG_4,
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