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qcacmn: Configure REO dest ring ctrl register to address rng mapping non UDP TCP flows

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earlier we configured only REO_R0_DESTINATION_RING_CTRL_IX_2
and REO_R0_DESTINATION_RING_CTRL_IX_3, but we now configure
REO_R0_DESTINATION_RING_CTRL_IX_0 and
REO_R0_DESTINATION_RING_CTRL_IX_1. Also added module param for
rx hash steering.

Change-Id: I690aa395bc19e49df3687be2e70eaaad4994003e
This commit is contained in:
Tallapragada Kalyan
2017-09-13 23:48:14 +05:30
committed by snandini
parent 3aa586ac29
commit 4c183b84c6
4 changed files with 40 additions and 0 deletions
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6
dp/wifi3.0/dp_main.c
View File

@@ -20,6 +20,7 @@
#include <qdf_lock.h> #include <qdf_lock.h>
#include <qdf_net_types.h> #include <qdf_net_types.h>
#include <qdf_lro.h> #include <qdf_lro.h>
#include <qdf_module.h>
#include <hal_api.h> #include <hal_api.h>
#include <hif.h> #include <hif.h>
#include <htt.h> #include <htt.h>
@@ -75,6 +76,9 @@ module_param(napi_budget, uint, 0644);
MODULE_PARM_DESC(napi_budget, MODULE_PARM_DESC(napi_budget,
"tasklet mode: more than 0xffff , napi budget if <= 0xffff"); "tasklet mode: more than 0xffff , napi budget if <= 0xffff");
bool rx_hash = 1;
qdf_declare_param(rx_hash, bool);
/** /**
* default_dscp_tid_map - Default DSCP-TID mapping * default_dscp_tid_map - Default DSCP-TID mapping
* *
@@ -5277,6 +5281,8 @@ void *dp_soc_attach_wifi3(void *osif_soc, void *hif_handle,
goto fail2; goto fail2;
} }
wlan_cfg_set_rx_hash(soc->wlan_cfg_ctx, rx_hash);
if (soc->cdp_soc.ol_ops->get_dp_cfg_param) { if (soc->cdp_soc.ol_ops->get_dp_cfg_param) {
int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc, int ret = soc->cdp_soc.ol_ops->get_dp_cfg_param(soc,
CDP_CFG_MAX_PEER_ID); CDP_CFG_MAX_PEER_ID);

22
hal/wifi3.0/hal_rx.c
View File

@@ -276,6 +276,28 @@ void hal_reo_setup(void *hal_soc,
* 7: NOT_USED. * 7: NOT_USED.
*/ */
if (reo_params->rx_hash_enabled) { if (reo_params->rx_hash_enabled) {
HAL_REG_WRITE(soc,
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET),
reo_params->remap1);
QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR 0x%x\n"),
HAL_REG_READ(soc,
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET)));
HAL_REG_WRITE(soc,
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET),
reo_params->remap2);
QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
FL("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR 0x%x\n"),
HAL_REG_READ(soc,
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET)));
HAL_REG_WRITE(soc, HAL_REG_WRITE(soc,
HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET), SEQ_WCSS_UMAC_REO_REG_OFFSET),

5
wlan_cfg/wlan_cfg.c
View File

@@ -605,6 +605,11 @@ bool wlan_cfg_is_lro_enabled(struct wlan_cfg_dp_soc_ctxt *cfg)
return cfg->lro_enabled; return cfg->lro_enabled;
} }
void wlan_cfg_set_rx_hash(struct wlan_cfg_dp_soc_ctxt *cfg, bool val)
{
cfg->rx_hash = val;
}
bool wlan_cfg_is_rx_hash_enabled(struct wlan_cfg_dp_soc_ctxt *cfg) bool wlan_cfg_is_rx_hash_enabled(struct wlan_cfg_dp_soc_ctxt *cfg)
{ {
return cfg->rx_hash; return cfg->rx_hash;

7
wlan_cfg/wlan_cfg.h
View File

@@ -503,6 +503,13 @@ bool wlan_cfg_is_lro_enabled(struct wlan_cfg_dp_soc_ctxt *cfg);
*/ */
bool wlan_cfg_is_rx_hash_enabled(struct wlan_cfg_dp_soc_ctxt *cfg); bool wlan_cfg_is_rx_hash_enabled(struct wlan_cfg_dp_soc_ctxt *cfg);
/*
* wlan_cfg_set_rx_hash - set rx hash enabled/disabled
* @wlan_cfg_soc_ctx
* @rx_hash
*/
void wlan_cfg_set_rx_hash(struct wlan_cfg_dp_soc_ctxt *cfg, bool rx_hash);
/* /*
* wlan_cfg_get_dp_pdev_nss_enabled - Return pdev nss enabled/disabled * wlan_cfg_get_dp_pdev_nss_enabled - Return pdev nss enabled/disabled
* @wlan_cfg_pdev_ctx * @wlan_cfg_pdev_ctx