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Merge "msm: camera: isp: Enable PIX & LINE count irqs by default" into camera-kernel.lnx.4.0

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This commit is contained in:
Camera Software Integration
2020-09-08 14:12:06 -07:00
committed by Gerrit - the friendly Code Review server
parent 558d74cbad 8b0144bd3a
commit 4ac0fd424d
1 changed files with 13 additions and 12 deletions
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25
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
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@@ -2154,9 +2154,8 @@ static int cam_ife_csid_enable_pxl_path(
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)
val |= CSID_PATH_INFO_INPUT_EOF; val |= CSID_PATH_INFO_INPUT_EOF;
if (path_config->measure_enabled) val |= (CSID_PATH_ERROR_PIX_COUNT |
val |= (CSID_PATH_ERROR_PIX_COUNT | CSID_PATH_ERROR_LINE_COUNT);
CSID_PATH_ERROR_LINE_COUNT);
cam_io_w_mb(val, soc_info->reg_map[0].mem_base + cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
pxl_reg->csid_pxl_irq_mask_addr); pxl_reg->csid_pxl_irq_mask_addr);
@@ -2781,9 +2780,8 @@ static int cam_ife_csid_enable_rdi_path(
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ)
val |= CSID_PATH_INFO_INPUT_EOF; val |= CSID_PATH_INFO_INPUT_EOF;
if (csid_hw->rdi_path_config[id].measure_enabled) val |= (CSID_PATH_ERROR_PIX_COUNT |
val |= (CSID_PATH_ERROR_PIX_COUNT | CSID_PATH_ERROR_LINE_COUNT);
CSID_PATH_ERROR_LINE_COUNT);
cam_io_w_mb(val, soc_info->reg_map[0].mem_base + cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr);
@@ -4843,14 +4841,15 @@ handle_fatal_error:
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
irq_status[CAM_IFE_CSID_IRQ_REG_IPP]); irq_status[CAM_IFE_CSID_IRQ_REG_IPP]);
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]",
csid_hw->ipp_path_config.height, csid_hw->ipp_path_config.height,
csid_hw->ipp_path_config.width, csid_hw->ipp_path_config.width,
((val >> ((val >>
csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_shift_val) &
csid_reg->cmn_reg->format_measure_height_mask_val), csid_reg->cmn_reg->format_measure_height_mask_val),
val & val &
csid_reg->cmn_reg->format_measure_width_mask_val); csid_reg->cmn_reg->format_measure_width_mask_val,
val);
} }
} }
@@ -4914,14 +4913,15 @@ handle_fatal_error:
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
irq_status[CAM_IFE_CSID_IRQ_REG_PPP]); irq_status[CAM_IFE_CSID_IRQ_REG_PPP]);
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]",
csid_hw->ppp_path_config.height, csid_hw->ppp_path_config.height,
csid_hw->ppp_path_config.width, csid_hw->ppp_path_config.width,
((val >> ((val >>
csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_shift_val) &
csid_reg->cmn_reg->format_measure_height_mask_val), csid_reg->cmn_reg->format_measure_height_mask_val),
val & val &
csid_reg->cmn_reg->format_measure_width_mask_val); csid_reg->cmn_reg->format_measure_width_mask_val,
val);
} }
} }
@@ -4979,7 +4979,7 @@ handle_fatal_error:
"CSID:%d irq_status_rdi[%d]:0x%x", "CSID:%d irq_status_rdi[%d]:0x%x",
csid_hw->hw_intf->hw_idx, i, irq_status[i]); csid_hw->hw_intf->hw_idx, i, irq_status[i]);
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]",
((val2 >> ((val2 >>
csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_shift_val) &
csid_reg->cmn_reg->format_measure_height_mask_val), csid_reg->cmn_reg->format_measure_height_mask_val),
@@ -4989,7 +4989,8 @@ handle_fatal_error:
csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_shift_val) &
csid_reg->cmn_reg->format_measure_height_mask_val), csid_reg->cmn_reg->format_measure_height_mask_val),
val & val &
csid_reg->cmn_reg->format_measure_width_mask_val); csid_reg->cmn_reg->format_measure_width_mask_val,
val);
} }
} }