From 8b0144bd3a112169ce80ebadb8d022f3a688cd2b Mon Sep 17 00:00:00 2001 From: Karthik Anantha Ram Date: Tue, 1 Sep 2020 11:00:33 -0700 Subject: [PATCH] msm: camera: isp: Enable PIX & LINE count irqs by default Enable these format measure error IRQs by default in CSID. CRs-Fixed: 2767775 Change-Id: Ie23d343cf2ac80d2b22096db3cbfc044a4e64fc9 Signed-off-by: Karthik Anantha Ram --- .../isp_hw/ife_csid_hw/cam_ife_csid_core.c | 25 ++++++++++--------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c index 8b9e93a47c..e84a2b5d5f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c @@ -2154,9 +2154,8 @@ static int cam_ife_csid_enable_pxl_path( if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) val |= CSID_PATH_INFO_INPUT_EOF; - if (path_config->measure_enabled) - val |= (CSID_PATH_ERROR_PIX_COUNT | - CSID_PATH_ERROR_LINE_COUNT); + val |= (CSID_PATH_ERROR_PIX_COUNT | + CSID_PATH_ERROR_LINE_COUNT); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_irq_mask_addr); @@ -2781,9 +2780,8 @@ static int cam_ife_csid_enable_rdi_path( if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ) val |= CSID_PATH_INFO_INPUT_EOF; - if (csid_hw->rdi_path_config[id].measure_enabled) - val |= (CSID_PATH_ERROR_PIX_COUNT | - CSID_PATH_ERROR_LINE_COUNT); + val |= (CSID_PATH_ERROR_PIX_COUNT | + CSID_PATH_ERROR_LINE_COUNT); cam_io_w_mb(val, soc_info->reg_map[0].mem_base + csid_reg->rdi_reg[id]->csid_rdi_irq_mask_addr); @@ -4827,14 +4825,15 @@ handle_fatal_error: csid_hw->hw_intf->hw_idx, irq_status[CAM_IFE_CSID_IRQ_REG_IPP]); CAM_ERR(CAM_ISP, - "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", + "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]", csid_hw->ipp_path_config.height, csid_hw->ipp_path_config.width, ((val >> csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_mask_val), val & - csid_reg->cmn_reg->format_measure_width_mask_val); + csid_reg->cmn_reg->format_measure_width_mask_val, + val); } } @@ -4898,14 +4897,15 @@ handle_fatal_error: csid_hw->hw_intf->hw_idx, irq_status[CAM_IFE_CSID_IRQ_REG_PPP]); CAM_ERR(CAM_ISP, - "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", + "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]", csid_hw->ppp_path_config.height, csid_hw->ppp_path_config.width, ((val >> csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_mask_val), val & - csid_reg->cmn_reg->format_measure_width_mask_val); + csid_reg->cmn_reg->format_measure_width_mask_val, + val); } } @@ -4963,7 +4963,7 @@ handle_fatal_error: "CSID:%d irq_status_rdi[%d]:0x%x", csid_hw->hw_intf->hw_idx, i, irq_status[i]); CAM_ERR(CAM_ISP, - "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x", + "Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x [format_measure0: 0x%x]", ((val2 >> csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_mask_val), @@ -4973,7 +4973,8 @@ handle_fatal_error: csid_reg->cmn_reg->format_measure_height_shift_val) & csid_reg->cmn_reg->format_measure_height_mask_val), val & - csid_reg->cmn_reg->format_measure_width_mask_val); + csid_reg->cmn_reg->format_measure_width_mask_val, + val); } }