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@@ -366,9 +366,8 @@ static u32 sde_rsc_timer_calculate(struct sde_rsc_priv *rsc,
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rsc_time_slot_0_ns = div_u64(rsc_time_slot_0_ns, cxo_period_ns);
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rsc->timer_config.rsc_time_slot_0_ns = (u32) rsc_time_slot_0_ns;
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- /* time_slot_1 for mode1 latency */
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- rsc_time_slot_1_ns = frame_time_ns;
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- rsc_time_slot_1_ns = div_u64(rsc_time_slot_1_ns, cxo_period_ns);
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+ /* time_slot_1 for mode1 latency - 1 fps */
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+ rsc_time_slot_1_ns = div_u64(TICKS_IN_NANO_SECOND, cxo_period_ns);
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rsc->timer_config.rsc_time_slot_1_ns = (u32) rsc_time_slot_1_ns;
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/* mode 2 is infinite */
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qctecmdr