Merge "msm: camera: isp: Add new ports for TFE" into camera-kernel.lnx.5.0

This commit is contained in:
Savita Patted
2021-03-29 18:42:59 -07:00
gecommit door Gerrit - the friendly Code Review server
bovenliggende 69c1bef608 dc1bf6d21b
commit 49f6c24ee9
11 gewijzigde bestanden met toevoegingen van 1482 en 91 verwijderingen

Bestand weergeven

@@ -616,6 +616,14 @@ static const char *__cam_isp_tfe_resource_handle_id_to_type(
return "STATS_BF";
case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG:
return "STATS_AWB_BG";
case CAM_ISP_TFE_OUT_RES_STATS_RS:
return "STATS_RS";
case CAM_ISP_TFE_OUT_RES_DS4:
return "DS_4";
case CAM_ISP_TFE_OUT_RES_DS16:
return "DS_16";
case CAM_ISP_TFE_OUT_RES_AI:
return "AI";
default:
return "CAM_ISP_Invalid_Resource_Type";
}

Bestand weergeven

@@ -1651,9 +1651,16 @@ static int cam_tfe_hw_mgr_preprocess_port(
uint32_t i;
struct cam_isp_tfe_out_port_info *out_port;
struct cam_tfe_hw_mgr *tfe_hw_mgr;
struct cam_hw_intf *tfe_device;
bool pdaf_rdi2_mux_en = false;
tfe_hw_mgr = tfe_ctx->hw_mgr;
tfe_device = tfe_hw_mgr->tfe_devices[0]->hw_intf;
tfe_device->hw_ops.process_cmd(tfe_device->hw_priv,
CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN,
&pdaf_rdi2_mux_en,
sizeof(pdaf_rdi2_mux_en));
for (i = 0; i < in_port->num_out_res; i++) {
out_port = &in_port->data[i];
@@ -1670,8 +1677,9 @@ static int cam_tfe_hw_mgr_preprocess_port(
}
}
if (*pdaf_enable && rdi2_enable) {
CAM_ERR(CAM_ISP, "invalid outports both RDI2 and PDAF enabled");
if (pdaf_rdi2_mux_en && *pdaf_enable && rdi2_enable) {
CAM_ERR(CAM_ISP,
"invalid outports both RDI2 and PDAF enabled");
return -EINVAL;
}

Bestand weergeven

@@ -147,6 +147,7 @@ enum cam_isp_hw_cmd_type {
CAM_ISP_HW_CMD_BUF_UPDATE,
CAM_ISP_HW_CMD_BUF_UPDATE_RM,
CAM_ISP_HW_NOTIFY_OVERFLOW,
CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN,
CAM_ISP_HW_CMD_MAX,
};

Bestand weergeven

@@ -1,10 +1,11 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include "cam_tfe530.h"
#include "cam_tfe640.h"
#include "cam_tfe_hw_intf.h"
#include "cam_tfe_core.h"
#include "cam_tfe_dev.h"
@@ -15,6 +16,10 @@ static const struct of_device_id cam_tfe_dt_match[] = {
.compatible = "qcom,tfe530",
.data = &cam_tfe530,
},
{
.compatible = "qcom,tfe640",
.data = &cam_tfe640,
},
{}
};
MODULE_DEVICE_TABLE(of, cam_tfe_dt_match);

Bestand weergeven

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
@@ -11,38 +11,46 @@
static struct cam_tfe_top_reg_offset_common tfe530_top_commong_reg = {
.hw_version = 0x00001000,
.hw_capability = 0x00001004,
.lens_feature = 0x00001008,
.stats_feature = 0x0000100C,
.zoom_feature = 0x00001010,
.global_reset_cmd = 0x00001014,
.core_cgc_ctrl = 0x00001018,
.ahb_cgc_ctrl = 0x0000101C,
.core_cfg_0 = 0x00001024,
.core_cfg_1 = 0x00001028,
.reg_update_cmd = 0x0000102C,
.diag_config = 0x00001060,
.diag_sensor_status_0 = 0x00001064,
.diag_sensor_status_1 = 0x00001068,
.diag_sensor_frame_cnt_status = 0x0000106C,
.violation_status = 0x00001070,
.stats_throttle_cnt_cfg_0 = 0x00001074,
.stats_throttle_cnt_cfg_1 = 0x00001078,
.debug_0 = 0x000010A0,
.debug_1 = 0x000010A4,
.debug_2 = 0x000010A8,
.debug_3 = 0x000010AC,
.debug_cfg = 0x000010DC,
.perf_cnt_cfg = 0x000010E0,
.perf_pixel_count = 0x000010E4,
.perf_line_count = 0x000010E8,
.perf_stall_count = 0x000010EC,
.perf_always_count = 0x000010F0,
.perf_count_status = 0x000010F4,
.diag_min_hbi_error_shift = 15,
.diag_neq_hbi_shift = 14,
.diag_sensor_hbi_mask = 0x3FFF,
.hw_version = 0x00001000,
.hw_capability = 0x00001004,
.lens_feature = 0x00001008,
.stats_feature = 0x0000100C,
.zoom_feature = 0x00001010,
.global_reset_cmd = 0x00001014,
.core_cgc_ctrl = 0x00001018,
.ahb_cgc_ctrl = 0x0000101C,
.core_cfg_0 = 0x00001024,
.core_cfg_1 = 0x00001028,
.reg_update_cmd = 0x0000102C,
.diag_config = 0x00001060,
.diag_sensor_status_0 = 0x00001064,
.diag_sensor_status_1 = 0x00001068,
.diag_sensor_frame_cnt_status = 0x0000106C,
.violation_status = 0x00001070,
.stats_throttle_cnt_cfg_0 = 0x00001074,
.stats_throttle_cnt_cfg_1 = 0x00001078,
.num_debug_reg = 4,
.debug_reg = {
0x000010A0,
0x000010A4,
0x000010A8,
0x000010AC,
},
.debug_cfg = 0x000010DC,
.num_perf_cfg = 1,
.perf_cfg = {
{
.perf_cnt_cfg = 0x000010E0,
.perf_pixel_count = 0x000010E4,
.perf_line_count = 0x000010E8,
.perf_stall_count = 0x000010EC,
.perf_always_count = 0x000010F0,
.perf_count_status = 0x000010F4,
},
},
.diag_min_hbi_error_shift = 15,
.diag_neq_hbi_shift = 14,
.diag_sensor_hbi_mask = 0x3FFF,
};
static struct cam_tfe_camif_reg tfe530_camif_reg = {
@@ -459,7 +467,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = {
.violation_shift = 30,
.image_size_violation = 31,
},
.num_client = CAM_TFE_BUS_MAX_CLIENTS,
.num_client = 10,
.bus_client_reg = {
/* BUS Client 0 BAYER */
{
@@ -742,7 +750,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = {
.client_name = "RDI2/PADF",
},
},
.num_out = CAM_TFE_BUS_TFE_OUT_MAX,
.num_out = 11,
.tfe_out_hw_info = {
{
.tfe_out_id = CAM_TFE_BUS_TFE_OUT_RDI0,
@@ -833,6 +841,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = {
.mid = 22,
},
},
.num_comp_grp = 8,
.comp_done_shift = 8,
.top_bus_wr_irq_shift = 1,
.comp_buf_done_mask = 0xFF00,
@@ -842,6 +851,7 @@ static struct cam_tfe_bus_hw_info tfe530_bus_hw_info = {
0x00000000,
},
.support_consumed_addr = true,
.pdaf_rdi2_mux_en = true,
};
struct cam_tfe_hw_info cam_tfe530 = {

Diff onderdrukt omdat het te groot bestand Laad Diff

Bestand weergeven

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/ratelimit.h>
@@ -74,6 +74,7 @@ struct cam_tfe_bus_common_data {
bool support_consumed_addr;
cam_hw_mgr_event_cb_func event_cb;
bool rup_irq_enable[CAM_TFE_BUS_RUP_GRP_MAX];
bool pdaf_rdi2_mux_en;
};
struct cam_tfe_bus_wm_resource_data {
@@ -152,6 +153,7 @@ struct cam_tfe_bus_priv {
struct cam_tfe_bus_common_data common_data;
uint32_t num_client;
uint32_t num_out;
uint32_t num_comp_grp;
uint32_t top_bus_wr_irq_shift;
struct cam_isp_resource_node bus_client[CAM_TFE_BUS_MAX_CLIENTS];
@@ -175,6 +177,9 @@ static bool cam_tfe_bus_can_be_secure(uint32_t out_id)
case CAM_TFE_BUS_TFE_OUT_RDI0:
case CAM_TFE_BUS_TFE_OUT_RDI1:
case CAM_TFE_BUS_TFE_OUT_RDI2:
case CAM_TFE_BUS_TFE_OUT_DS4:
case CAM_TFE_BUS_TFE_OUT_DS16:
case CAM_TFE_BUS_TFE_OUT_AI:
return true;
case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE:
@@ -182,6 +187,7 @@ static bool cam_tfe_bus_can_be_secure(uint32_t out_id)
case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG:
case CAM_TFE_BUS_TFE_OUT_STATS_BF:
case CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG:
case CAM_TFE_BUS_TFE_OUT_STATS_RS:
default:
return false;
}
@@ -213,6 +219,14 @@ static enum cam_tfe_bus_tfe_out_id
return CAM_TFE_BUS_TFE_OUT_STATS_BF;
case CAM_ISP_TFE_OUT_RES_STATS_AWB_BG:
return CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG;
case CAM_ISP_TFE_OUT_RES_STATS_RS:
return CAM_TFE_BUS_TFE_OUT_STATS_RS;
case CAM_ISP_TFE_OUT_RES_DS4:
return CAM_TFE_BUS_TFE_OUT_DS4;
case CAM_ISP_TFE_OUT_RES_DS16:
return CAM_TFE_BUS_TFE_OUT_DS16;
case CAM_ISP_TFE_OUT_RES_AI:
return CAM_TFE_BUS_TFE_OUT_AI;
default:
return CAM_TFE_BUS_TFE_OUT_MAX;
}
@@ -283,6 +297,32 @@ static int cam_tfe_bus_get_num_wm(
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_DS4:
switch (format) {
case CAM_FORMAT_PD10:
return 1;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_DS16:
switch (format) {
case CAM_FORMAT_PD10:
return 1;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_AI:
switch (format) {
case CAM_FORMAT_NV12:
case CAM_FORMAT_TP10:
case CAM_FORMAT_PD10:
return 2;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BE:
case CAM_TFE_BUS_TFE_OUT_STATS_HDR_BHIST:
case CAM_TFE_BUS_TFE_OUT_STATS_TL_BG:
@@ -295,6 +335,14 @@ static int cam_tfe_bus_get_num_wm(
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_STATS_RS:
switch (format) {
case CAM_FORMAT_PLAIN32:
return 1;
default:
break;
}
break;
default:
break;
}
@@ -307,7 +355,8 @@ static int cam_tfe_bus_get_num_wm(
static int cam_tfe_bus_get_wm_idx(
enum cam_tfe_bus_tfe_out_id tfe_out_res_id,
enum cam_tfe_bus_plane_type plane)
enum cam_tfe_bus_plane_type plane,
bool pdaf_rdi2_mux_en)
{
int wm_idx = -1;
@@ -342,7 +391,10 @@ static int cam_tfe_bus_get_wm_idx(
case CAM_TFE_BUS_TFE_OUT_PDAF:
switch (plane) {
case PLANE_Y:
wm_idx = 9;
if (pdaf_rdi2_mux_en)
wm_idx = 9;
else
wm_idx = 10;
break;
default:
break;
@@ -412,7 +464,44 @@ static int cam_tfe_bus_get_wm_idx(
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_STATS_RS:
switch (plane) {
case PLANE_Y:
wm_idx = 15;
break;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_DS4:
switch (plane) {
case PLANE_Y:
wm_idx = 11;
break;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_DS16:
switch (plane) {
case PLANE_Y:
wm_idx = 12;
break;
default:
break;
}
break;
case CAM_TFE_BUS_TFE_OUT_AI:
switch (plane) {
case PLANE_Y:
wm_idx = 13;
break;
case PLANE_C:
wm_idx = 14;
default:
break;
}
break;
default:
break;
}
@@ -608,7 +697,8 @@ static int cam_tfe_bus_acquire_wm(
*wm_res = NULL;
/* No need to allocate for BUS TFE OUT to WM is fixed. */
wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane);
wm_idx = cam_tfe_bus_get_wm_idx(tfe_out_res_id, plane,
bus_priv->common_data.pdaf_rdi2_mux_en);
if (wm_idx < 0 || wm_idx >= bus_priv->num_client) {
CAM_ERR(CAM_ISP, "Unsupported TFE out %d plane %d",
tfe_out_res_id, plane);
@@ -1696,7 +1786,7 @@ static int cam_tfe_bus_bufdone_bottom_half(
common_data = &bus_priv->common_data;
for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) {
for (i = 0; i < bus_priv->num_comp_grp; i++) {
if (!(evt_payload->bus_irq_val[0] &
bus_priv->comp_buf_done_mask))
break;
@@ -1773,7 +1863,7 @@ static void cam_tfe_bus_error_bottom_half(
CAM_INFO(CAM_ISP, "IMAGE_SIZE_VIOLATION val :0x%x",
evt_payload->image_size_violation_status);
for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) {
for (i = 0; i < bus_priv->num_client; i++) {
if (!(evt_payload->image_size_violation_status >> i))
break;
@@ -1801,7 +1891,7 @@ static void cam_tfe_bus_error_bottom_half(
}
if (overflow_status) {
for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) {
for (i = 0; i < bus_priv->num_client; i++) {
if (!(evt_payload->overflow_status >> i))
break;
@@ -2199,7 +2289,7 @@ static int cam_tfe_bus_dump_bus_info(
wm_data->stride);
}
for (i = 0; i < CAM_TFE_BUS_MAX_CLIENTS; i++) {
for (i = 0; i < bus_priv->num_client; i++) {
wm_data = bus_priv->bus_client[i].res_priv;
/* disable WM */
cam_io_w_mb(0, common_data->mem_base +
@@ -2271,6 +2361,7 @@ static int cam_tfe_bus_process_cmd(void *priv,
int rc = -EINVAL;
uint32_t i, val;
bool *support_consumed_addr;
bool *pdaf_rdi2_mux_en;
if (!priv || !cmd_args) {
CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid input arguments");
@@ -2314,6 +2405,11 @@ static int cam_tfe_bus_process_cmd(void *priv,
case CAM_ISP_HW_CMD_DUMP_BUS_INFO:
rc = cam_tfe_bus_dump_bus_info(priv, cmd_args, arg_size);
break;
case CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN:
bus_priv = (struct cam_tfe_bus_priv *) priv;
pdaf_rdi2_mux_en = (bool *)cmd_args;
*pdaf_rdi2_mux_en = bus_priv->common_data.pdaf_rdi2_mux_en;
break;
default:
CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d",
cmd_type);
@@ -2361,6 +2457,7 @@ int cam_tfe_bus_init(
bus_priv->num_client = hw_info->num_client;
bus_priv->num_out = hw_info->num_out;
bus_priv->num_comp_grp = hw_info->num_comp_grp;
bus_priv->top_bus_wr_irq_shift = hw_info->top_bus_wr_irq_shift;
bus_priv->common_data.comp_done_shift = hw_info->comp_done_shift;
@@ -2376,6 +2473,7 @@ int cam_tfe_bus_init(
bus_priv->comp_rup_done_mask = hw_info->comp_rup_done_mask;
bus_priv->common_data.support_consumed_addr =
hw_info->support_consumed_addr;
bus_priv->common_data.pdaf_rdi2_mux_en = hw_info->pdaf_rdi2_mux_en;
for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++)
bus_priv->bus_irq_error_mask[i] =
@@ -2404,7 +2502,7 @@ int cam_tfe_bus_init(
}
}
for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) {
for (i = 0; i < bus_priv->num_comp_grp; i++) {
rc = cam_tfe_bus_init_comp_grp(i, soc_info,
bus_priv, bus_hw_info,
&bus_priv->comp_grp[i]);
@@ -2446,7 +2544,7 @@ deinit_tfe_out:
deinit_comp_grp:
if (i < 0)
i = CAM_TFE_BUS_COMP_GRP_MAX;
i = bus_priv->num_comp_grp;
for (--i; i >= 0; i--)
cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]);
@@ -2493,7 +2591,7 @@ int cam_tfe_bus_deinit(
"Deinit WM failed rc=%d", rc);
}
for (i = 0; i < CAM_TFE_BUS_COMP_GRP_MAX; i++) {
for (i = 0; i < bus_priv->num_comp_grp; i++) {
rc = cam_tfe_bus_deinit_comp_grp(&bus_priv->comp_grp[i]);
if (rc < 0)
CAM_ERR(CAM_ISP,

Bestand weergeven

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
@@ -11,7 +11,7 @@
#include "cam_isp_hw.h"
#include "cam_tfe_hw_intf.h"
#define CAM_TFE_BUS_MAX_CLIENTS 10
#define CAM_TFE_BUS_MAX_CLIENTS 16
#define CAM_TFE_BUS_MAX_SUB_GRPS 4
#define CAM_TFE_BUS_MAX_PERF_CNT_REG 8
#define CAM_TFE_BUS_MAX_IRQ_REGISTERS 2
@@ -57,6 +57,9 @@ enum cam_tfe_bus_comp_grp_id {
CAM_TFE_BUS_COMP_GRP_5,
CAM_TFE_BUS_COMP_GRP_6,
CAM_TFE_BUS_COMP_GRP_7,
CAM_TFE_BUS_COMP_GRP_8,
CAM_TFE_BUS_COMP_GRP_9,
CAM_TFE_BUS_COMP_GRP_10,
CAM_TFE_BUS_COMP_GRP_MAX,
};
@@ -80,6 +83,10 @@ enum cam_tfe_bus_tfe_out_id {
CAM_TFE_BUS_TFE_OUT_STATS_TL_BG,
CAM_TFE_BUS_TFE_OUT_STATS_AWB_BG,
CAM_TFE_BUS_TFE_OUT_STATS_BF,
CAM_TFE_BUS_TFE_OUT_STATS_RS,
CAM_TFE_BUS_TFE_OUT_DS4,
CAM_TFE_BUS_TFE_OUT_DS16,
CAM_TFE_BUS_TFE_OUT_AI,
CAM_TFE_BUS_TFE_OUT_MAX,
};
@@ -178,12 +185,14 @@ struct cam_tfe_bus_tfe_out_hw_info {
* @num_client: Total number of write clients
* @bus_client_reg: Bus client register info
* @tfe_out_hw_info: TFE output capability
* @num_comp_grp: Number of composite group
* @comp_done_shift: Mask shift for comp done mask
* @top_bus_wr_irq_shift: Mask shift for top level BUS WR irq
* @comp_buf_done_mask: Composite buf done bits mask
* @comp_rup_done_mask: Reg update done mask
* @bus_irq_error_mask: Bus irq error mask bits
* @support_consumed_addr: Indicate if bus support consumed address
* @pdaf_rdi2_mux_en: Indicate is PDAF is muxed with RDI2
*/
struct cam_tfe_bus_hw_info {
struct cam_tfe_bus_reg_offset_common common_reg;
@@ -193,12 +202,14 @@ struct cam_tfe_bus_hw_info {
uint32_t num_out;
struct cam_tfe_bus_tfe_out_hw_info
tfe_out_hw_info[CAM_TFE_BUS_TFE_OUT_MAX];
uint32_t num_comp_grp;
uint32_t comp_done_shift;
uint32_t top_bus_wr_irq_shift;
uint32_t comp_buf_done_mask;
uint32_t comp_rup_done_mask;
uint32_t bus_irq_error_mask[CAM_TFE_BUS_IRQ_REGISTERS_MAX];
bool support_consumed_addr;
bool pdaf_rdi2_mux_en;
};
/*

Bestand weergeven

@@ -337,42 +337,37 @@ static void cam_tfe_log_error_irq_status(
top_priv->eof_ts.tv_sec,
top_priv->eof_ts.tv_nsec/1000);
val_0 = cam_io_r(mem_base +
top_priv->common_data.common_reg->debug_0);
val_1 = cam_io_r(mem_base +
top_priv->common_data.common_reg->debug_1);
val_2 = cam_io_r(mem_base +
top_priv->common_data.common_reg->debug_2);
val_3 = cam_io_r(mem_base +
top_priv->common_data.common_reg->debug_3);
CAM_INFO(CAM_ISP, "TOP IRQ[0]:0x%x IRQ[1]:0x%x IRQ[2]:0x%x",
evt_payload->irq_reg_val[0], evt_payload->irq_reg_val[1],
evt_payload->irq_reg_val[2]);
CAM_INFO(CAM_ISP, "Top debug [0]:0x%x [1]:0x%x [2]:0x%x [3]:0x%x",
val_0, val_1, val_2, val_3);
for (i = 0; i < top_priv->common_data.common_reg->num_debug_reg; i++) {
val_0 = cam_io_r(mem_base +
top_priv->common_data.common_reg->debug_reg[i]);
CAM_INFO(CAM_ISP, "Top debug [i]:0x%x", i, val_0);
}
cam_cpas_reg_read(soc_private->cpas_handle,
CAM_CPAS_REG_CAMNOC, 0x20, true, &val_0);
CAM_INFO(CAM_ISP, "tfe_niu_MaxWr_Low offset 0x20 val 0x%x",
val_0);
for (i = 0; i < top_priv->common_data.common_reg->num_perf_cfg; i++) {
val_0 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_cfg[i].perf_pixel_count);
val_0 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_pixel_count);
val_1 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_cfg[i].perf_line_count);
val_1 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_line_count);
val_2 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_cfg[i].perf_stall_count);
val_2 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_stall_count);
val_3 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_cfg[i].perf_always_count);
val_3 = cam_io_r(mem_base +
top_priv->common_data.common_reg->perf_always_count);
CAM_INFO(CAM_ISP,
"Top perf cnt pix:0x%x line:0x%x stall:0x%x always:0x%x",
val_0, val_1, val_2, val_3);
CAM_INFO(CAM_ISP,
"Top perf cnt [%d] pix:0x%x line:0x%x stall:0x%x always:0x%x",
i, val_0, val_1, val_2, val_3);
}
clc_hw_status = hw_info->clc_hw_status_info;
for (i = 0; i < hw_info->num_clc; i++) {
@@ -1973,6 +1968,8 @@ static int cam_tfe_camif_resource_start(
uint32_t epoch1_irq_mask;
uint32_t computed_epoch_line_cfg;
uint32_t camera_hw_version = 0;
struct cam_hw_intf *tfe_device;
bool pdaf_rdi2_mux_en = false;
if (!camif_res || !core_info) {
CAM_ERR(CAM_ISP, "Error Invalid input arguments");
@@ -2007,7 +2004,14 @@ static int cam_tfe_camif_resource_start(
rsrc_data->reg_data->dual_tfe_sync_sel_shift);
}
if (!rsrc_data->camif_pd_enable)
tfe_device = rsrc_data->hw_intf;
tfe_device->hw_ops.process_cmd(tfe_device->hw_priv,
CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN,
&pdaf_rdi2_mux_en,
sizeof(pdaf_rdi2_mux_en));
if (pdaf_rdi2_mux_en && !rsrc_data->camif_pd_enable)
val |= (1 << rsrc_data->reg_data->camif_pd_rdi2_src_sel_shift);
/* enables the Delay Line CLC in the pixel pipeline */
@@ -2086,7 +2090,8 @@ static int cam_tfe_camif_resource_start(
(1 << rsrc_data->reg_data->perf_window_start_shift) |
(2 << rsrc_data->reg_data->perf_window_end_shift);
cam_io_w_mb(val,
rsrc_data->mem_base + rsrc_data->common_reg->perf_cnt_cfg);
rsrc_data->mem_base +
rsrc_data->common_reg->perf_cfg[0].perf_cnt_cfg);
CAM_DBG(CAM_ISP, "TFE:%d perf_cfg val:%d", core_info->core_index,
val);
@@ -2893,6 +2898,7 @@ int cam_tfe_process_cmd(void *hw_priv, uint32_t cmd_type,
case CAM_ISP_HW_CMD_IS_CONSUMED_ADDR_SUPPORT:
case CAM_ISP_HW_CMD_GET_RES_FOR_MID:
case CAM_ISP_HW_CMD_DUMP_BUS_INFO:
case CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN:
rc = core_info->tfe_bus->hw_ops.process_cmd(
core_info->tfe_bus->bus_priv, cmd_type, cmd_args,
arg_size);

Bestand weergeven

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
@@ -25,8 +25,10 @@
#define CAM_TFE_MAX_REG_DUMP_ENTRIES 20
#define CAM_TFE_MAX_LUT_DUMP_ENTRIES 10
#define CAM_TFE_MAX_CLC 30
#define CAM_TFE_MAX_CLC 40
#define CAM_TFE_CLC_NAME_LENGTH_MAX 32
#define CAM_TFE_MAX_DEBUG_REG 10
#define CAM_TFE_MAX_PERF_CNT 2
/*we take each word as uint32_t, for dumping uint64_t count as 2 words
* soc index
@@ -67,6 +69,15 @@ struct cam_tfe_reg_dump_data {
lut_entry[CAM_TFE_MAX_LUT_DUMP_ENTRIES];
};
struct cam_tfe_top_reg_perf_cfg {
uint32_t perf_cnt_cfg;
uint32_t perf_pixel_count;
uint32_t perf_line_count;
uint32_t perf_stall_count;
uint32_t perf_always_count;
uint32_t perf_count_status;
};
struct cam_tfe_top_reg_offset_common {
uint32_t hw_version;
uint32_t hw_capability;
@@ -86,17 +97,11 @@ struct cam_tfe_top_reg_offset_common {
uint32_t violation_status;
uint32_t stats_throttle_cnt_cfg_0;
uint32_t stats_throttle_cnt_cfg_1;
uint32_t debug_0;
uint32_t debug_1;
uint32_t debug_2;
uint32_t debug_3;
uint32_t num_debug_reg;
uint32_t debug_reg[CAM_TFE_MAX_DEBUG_REG];
uint32_t debug_cfg;
uint32_t perf_cnt_cfg;
uint32_t perf_pixel_count;
uint32_t perf_line_count;
uint32_t perf_stall_count;
uint32_t perf_always_count;
uint32_t perf_count_status;
uint32_t num_perf_cfg;
struct cam_tfe_top_reg_perf_cfg perf_cfg[CAM_TFE_MAX_PERF_CNT];
/*reg data */
uint32_t diag_min_hbi_error_shift;

Bestand weergeven

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
*/
#ifndef __UAPI_CAM_ISP_TFE_H__
@@ -20,7 +20,11 @@
#define CAM_ISP_TFE_OUT_RES_STATS_TL_BG (CAM_ISP_TFE_OUT_RES_BASE + 8)
#define CAM_ISP_TFE_OUT_RES_STATS_BF (CAM_ISP_TFE_OUT_RES_BASE + 9)
#define CAM_ISP_TFE_OUT_RES_STATS_AWB_BG (CAM_ISP_TFE_OUT_RES_BASE + 10)
#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 11)
#define CAM_ISP_TFE_OUT_RES_STATS_RS (CAM_ISP_TFE_OUT_RES_BASE + 11)
#define CAM_ISP_TFE_OUT_RES_DS4 (CAM_ISP_TFE_OUT_RES_BASE + 12)
#define CAM_ISP_TFE_OUT_RES_DS16 (CAM_ISP_TFE_OUT_RES_BASE + 13)
#define CAM_ISP_TFE_OUT_RES_AI (CAM_ISP_TFE_OUT_RES_BASE + 14)
#define CAM_ISP_TFE_OUT_RES_MAX (CAM_ISP_TFE_OUT_RES_BASE + 15)
/* TFE input port resource type */