Merge "asoc: bolero: check if clock is enabled before accessing register"
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@@ -238,17 +238,20 @@ static int bolero_clk_rsc_mux1_clk_request(struct bolero_clk_rsc *priv,
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}
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priv->clk_cnt[clk_id]--;
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if (priv->clk_cnt[clk_id] == 0) {
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bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
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true);
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ret = bolero_clk_rsc_mux0_clk_request(priv,
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default_clk_id, true);
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if (!ret)
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iowrite32(0x0, clk_muxsel);
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iowrite32(0x0, clk_muxsel);
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if (priv->clk[clk_id + NPL_CLK_OFFSET])
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clk_disable_unprepare(
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priv->clk[clk_id + NPL_CLK_OFFSET]);
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clk_disable_unprepare(priv->clk[clk_id]);
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bolero_clk_rsc_mux0_clk_request(priv, default_clk_id,
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false);
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if (!ret)
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bolero_clk_rsc_mux0_clk_request(priv,
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default_clk_id, false);
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}
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}
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return ret;
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@@ -209,6 +209,7 @@ static int va_macro_event_handler(struct snd_soc_component *component,
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struct device *va_dev = NULL;
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struct va_macro_priv *va_priv = NULL;
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int retry_cnt = MAX_RETRY_ATTEMPTS;
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int ret = 0;
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if (!va_macro_get_data(component, &va_dev, &va_priv, __func__))
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return -EINVAL;
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@@ -234,6 +235,19 @@ static int va_macro_event_handler(struct snd_soc_component *component,
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"%s: va_mclk_users is non-zero still, audio SSR fail!!\n",
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__func__);
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break;
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case BOLERO_MACRO_EVT_SSR_UP:
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/* enable&disable VA_CORE_CLK to reset GFMUX reg */
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ret = bolero_clk_rsc_request_clock(va_priv->dev,
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va_priv->default_clk_id,
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VA_CORE_CLK, true);
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if (ret < 0)
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dev_err_ratelimited(va_priv->dev,
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"%s, failed to enable clk, ret:%d\n",
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__func__, ret);
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else
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bolero_clk_rsc_request_clock(va_priv->dev,
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va_priv->default_clk_id,
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VA_CORE_CLK, false);
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case BOLERO_MACRO_EVT_CLK_RESET:
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bolero_rsc_clk_reset(va_dev, VA_CORE_CLK);
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break;
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@@ -905,6 +905,7 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
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{
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struct device *wsa_dev = NULL;
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struct wsa_macro_priv *wsa_priv = NULL;
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int ret = 0;
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if (!wsa_macro_get_data(component, &wsa_dev, &wsa_priv, __func__))
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return -EINVAL;
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@@ -925,6 +926,18 @@ static int wsa_macro_event_handler(struct snd_soc_component *component,
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case BOLERO_MACRO_EVT_SSR_UP:
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/* reset swr after ssr/pdr */
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wsa_priv->reset_swr = true;
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/* enable&disable WSA_CORE_CLK to reset GFMUX reg */
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ret = bolero_clk_rsc_request_clock(wsa_priv->dev,
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wsa_priv->default_clk_id,
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WSA_CORE_CLK, true);
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if (ret < 0)
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dev_err_ratelimited(wsa_priv->dev,
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"%s, failed to enable clk, ret:%d\n",
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__func__, ret);
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else
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bolero_clk_rsc_request_clock(wsa_priv->dev,
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wsa_priv->default_clk_id,
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WSA_CORE_CLK, false);
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if (wsa_priv->swr_ctrl_data)
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swrm_wcd_notify(
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wsa_priv->swr_ctrl_data[0].wsa_swr_pdev,
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