msm: eva: Flush EVA CPU DDR transactions
Before power collapsing EVA subsystem. Change-Id: I84ea3278a3229346677cc28d2aec1e62bbe5868c Signed-off-by: George Shen <sqiao@codeaurora.org>
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@@ -3862,6 +3862,7 @@ exit:
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static int __power_off_controller(struct iris_hfi_device *device)
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{
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u32 lpi_status, reg_status = 0, count = 0, max_count = 1000;
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u32 sbm_ln0_low;
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/* HPG 6.2.2 Step 1 */
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__write_register(device, CVP_CPU_CS_X2RPMh, 0x3);
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@@ -3873,12 +3874,12 @@ static int __power_off_controller(struct iris_hfi_device *device)
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__read_register(device,
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CVP_AON_WRAPPER_MVP_NOC_LPI_STATUS);
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reg_status = lpi_status & BIT(0);
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/* Wait for noc lpi status to be set */
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/* Wait for Core noc lpi status to be set */
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usleep_range(50, 100);
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count++;
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}
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dprintk(CVP_PWR,
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"Noc: lpi_status %x noc_status %x (count %d)\n",
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"Core Noc: lpi_status %x noc_status %x (count %d)\n",
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lpi_status, reg_status, count);
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if (count == max_count) {
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u32 pc_ready, wfi_status;
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@@ -3887,12 +3888,43 @@ static int __power_off_controller(struct iris_hfi_device *device)
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pc_ready = __read_register(device, CVP_CTRL_STATUS);
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dprintk(CVP_WARN,
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"NOC not in qaccept status %x %x %x %x\n",
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"Core NOC not in qaccept status %x %x %x %x\n",
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reg_status, lpi_status, wfi_status, pc_ready);
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__print_sidebandmanager_regs(device);
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}
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/* New addition to put CPU/Tensilica to low power */
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reg_status = 0;
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count = 0;
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__write_register(device, CVP_WRAPPER_CPU_NOC_LPI_CONTROL, 0x1);
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while (!reg_status && count < max_count) {
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lpi_status =
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__read_register(device,
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CVP_WRAPPER_CPU_NOC_LPI_STATUS);
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reg_status = lpi_status & BIT(0);
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/* Wait for CPU noc lpi status to be set */
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usleep_range(50, 100);
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count++;
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}
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sbm_ln0_low = __read_register(device, CVP_NOC_SBM_SENSELN0_LOW);
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dprintk(CVP_PWR,
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"CPU Noc: lpi_status %x noc_status %x (count %d) 0x%x\n",
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lpi_status, reg_status, count, sbm_ln0_low);
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if (count == max_count) {
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u32 pc_ready, wfi_status;
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wfi_status = __read_register(device, CVP_WRAPPER_CPU_STATUS);
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pc_ready = __read_register(device, CVP_CTRL_STATUS);
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dprintk(CVP_WARN,
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"CPU NOC not in qaccept status %x %x %x %x\n",
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reg_status, lpi_status, wfi_status, pc_ready);
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__print_sidebandmanager_regs(device);
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}
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/* HPG 6.2.2 Step 3, debug bridge to low power BYPASSED */
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/* HPG 6.2.2 Step 4, debug bridge to lpi release */
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@@ -115,6 +115,8 @@
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#define CVP_WRAPPER_CPU_CLOCK_CONFIG (CVP_WRAPPER_BASE_OFFS + 0x50)
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#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (CVP_WRAPPER_BASE_OFFS + 0x54)
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#define CVP_WRAPPER_DEBUG_BRIDGE_LPI_STATUS (CVP_WRAPPER_BASE_OFFS + 0x58)
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#define CVP_WRAPPER_CPU_NOC_LPI_CONTROL (CVP_WRAPPER_BASE_OFFS + 0x5C)
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#define CVP_WRAPPER_CPU_NOC_LPI_STATUS (CVP_WRAPPER_BASE_OFFS + 0x60)
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#define CVP_WRAPPER_CORE_CLOCK_CONFIG (CVP_WRAPPER_BASE_OFFS + 0x88)
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#define CVP_CTRL_INIT CVP_CPU_CS_SCIACMD
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@@ -184,6 +186,7 @@
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#define CVP_NOC_ERR_ERRLOG3_LOW_OFFS (CVP_NOC_BASE_OFFS + 0xB8)
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#define CVP_NOC_ERR_ERRLOG3_HIGH_OFFS (CVP_NOC_BASE_OFFS + 0xBC)
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#define CVP_NOC_SBM_SENSELN0_LOW (CVP_NOC_BASE_OFFS + 0x300)
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#define CVP_NOC_CPU_PENDING_MASK 0x3F80000
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#define CVP_NOC_CORE_BASE_OFFS 0x00010000
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#define CVP_NOC_MAIN_SIDEBANDMANAGER_SENSELN0_LOW \
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