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@@ -742,6 +742,38 @@ int cam_jpeg_enc_config_cmanoc_hw_misr(struct cam_jpeg_enc_device_hw_info *hw_in
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return 0;
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}
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+int cam_jpeg_enc_dump_debug_regs(struct cam_hw_info *jpeg_enc_dev)
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+{
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+ struct cam_hw_soc_info *soc_info = NULL;
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+ struct cam_jpeg_enc_device_core_info *core_info = NULL;
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+
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+ soc_info = &jpeg_enc_dev->soc_info;
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+ core_info = (struct cam_jpeg_enc_device_core_info *)jpeg_enc_dev->core_info;
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+
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+ CAM_INFO(CAM_JPEG, "******** JPEG ENCODER REGISTER DUMP *********");
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+
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+ /* JPEG DMA TOP, Interrupt, core config, command registers & Fetch Engine Registers*/
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+ cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.top_offset,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.top_range);
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+
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+ /* Write Engine & Encoder debug registers*/
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+ cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.we_offset,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.we_range);
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+
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+ /* WE qos cfg, test bus, DMI, spare regs, bus misr, scale reg & MMU prefetch regs */
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+ cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.scale_offset,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.scale_range);
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+
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+ /* Perf Registers */
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+ cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.perf_offset,
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+ core_info->jpeg_enc_hw_info->debug_reg_offset.perf_range);
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+ return 0;
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+}
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+
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int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
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void *cmd_args, uint32_t arg_size)
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{
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@@ -868,6 +900,9 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
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}
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break;
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}
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+ case CAM_JPEG_CMD_DUMP_DEBUG_REGS:
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+ rc = cam_jpeg_enc_dump_debug_regs(jpeg_enc_dev);
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+ break;
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default:
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rc = -EINVAL;
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break;
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