msm: camera: jpeg: dump jpeg register during pagefault

This change dump jpeg dma/enc registers during pagefault
for debug purposes.

CRs-Fixed: 3503307
Change-Id: I3a9c9d76302f2cc1eb7d23193bfdd566767a6428
Signed-off-by: Shivakumar Malke <[email protected]>

drivers/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c

@@ -2003,6 +2003,17 @@ iodump:
 	cam_packet_util_dump_io_bufs(packet, hw_mgr->iommu_hdl, hw_mgr->iommu_sec_hdl,
 		pf_args, hw_pid_support);
 	cam_packet_util_put_packet_addr(pf_req_info->packet_handle);
+
+	/* Dump JPEG registers for debug purpose */
+	if (dev_type == CAM_JPEG_RES_TYPE_DMA ||
+		dev_type == CAM_JPEG_RES_TYPE_ENC) {
+		rc = hw_mgr->devices[dev_type][CAM_JPEG_MEM_BASE_INDEX]->hw_ops.process_cmd(
+			hw_mgr->devices[dev_type][CAM_JPEG_MEM_BASE_INDEX]->hw_priv,
+			CAM_JPEG_CMD_DUMP_DEBUG_REGS,
+			NULL, 0);
+	} else {
+		CAM_ERR(CAM_JPEG, "Invalid dev_type %d", dev_type);
+	}
 }
 
 static int cam_jpeg_mgr_cmd(void *hw_mgr_priv, void *cmd_args)

drivers/cam_jpeg/jpeg_hw/include/cam_jpeg_hw_intf.h

@@ -24,7 +24,7 @@
 #define CAM_JPEG_ENC_MISR_VAL_NUM    3
 #define CAM_JPEG_MISR_ID_LOW_RD      1
 #define CAM_JPEG_MISR_ID_LOW_WR      2
-
+#define CAM_JPEG_MEM_BASE_INDEX      0
 
 /**
  * struct cam_jpeg_irq_cb_data - Data that gets passed from IRQ when the cb function is called
@@ -102,6 +102,7 @@ enum cam_jpeg_cmd_type {
 	CAM_JPEG_CMD_MINI_DUMP,
 	CAM_JPEG_CMD_CONFIG_HW_MISR,
 	CAM_JPEG_CMD_DUMP_HW_MISR_VAL,
+	CAM_JPEG_CMD_DUMP_DEBUG_REGS,
 	CAM_JPEG_CMD_MAX,
 };
 

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_680_hw_info_ver_4_2_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_DMA_680_HW_INFO_VER_4_2_0_H
@@ -32,6 +33,16 @@ static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_680_hw_info = {
 		.misr_cfg0 = 0x160,
 		.misr_cfg1 = 0x164,
 	},
+	.debug_reg_offset = {
+		.top_offset = 0x0,
+		.top_range = 0x19,
+		.we_offset = 0xB8,
+		.we_range = 0x9,
+		.we_qos_offset = 0x144,
+		.we_qos_range = 0x1C,
+		.perf_offset = 0xFEC,
+		.perf_range = 0x5,
+		},
 	.reg_val = {
 		.int_clr_clearall = 0xFFFFFFFF,
 		.int_mask_disable_all = 0x00000000,

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/cam_jpeg_dma_780_hw_info_ver_4_2_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_DMA_780_HW_INFO_VER_4_2_0_H
@@ -32,6 +33,16 @@ static struct cam_jpeg_dma_device_hw_info cam_jpeg_dma_780_hw_info = {
 		.misr_cfg0 = 0x160,
 		.misr_cfg1 = 0x164,
 	},
+	.debug_reg_offset = {
+		.top_offset = 0x0,
+		.top_range = 0x19,
+		.we_offset = 0xB8,
+		.we_range = 0x9,
+		.we_qos_offset = 0x144,
+		.we_qos_range = 0x1C,
+		.perf_offset = 0xFEC,
+		.perf_range = 0x5,
+	},
 	.reg_val = {
 		.int_clr_clearall = 0xFFFFFFFF,
 		.int_mask_disable_all = 0x00000000,

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.c

@@ -647,6 +647,42 @@ int cam_jpeg_dma_config_cmanoc_hw_misr(struct cam_jpeg_dma_device_hw_info *hw_in
 	return 0;
 }
 
+int cam_jpeg_dma_dump_debug_regs(struct cam_hw_info *jpeg_dma_dev)
+{
+	struct cam_hw_soc_info *soc_info = NULL;
+	struct cam_jpeg_dma_device_core_info *core_info = NULL;
+
+	soc_info = &jpeg_dma_dev->soc_info;
+	core_info = (struct cam_jpeg_dma_device_core_info *)jpeg_dma_dev->core_info;
+
+	CAM_INFO(CAM_JPEG, "************ JPEG DMA REGISTER DUMP ************");
+
+	/* JPEG DMA TOP, Interrupt, core config, command registers & Fetch Engine Registers */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.top_offset,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.top_range);
+
+	/* Write Engine */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.we_offset,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.we_range);
+
+	/*
+	 * WE qos cfg, test bus and debug regs, spare regs, bus misr, scale reg, core status regs
+	 *	 & MMU prefetch regs
+	 */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.we_qos_offset,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.we_qos_range);
+
+	/* Perf Registers */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.perf_offset,
+		core_info->jpeg_dma_hw_info->debug_reg_offset.perf_range);
+
+	return 0;
+}
+
 int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type,
 	void *cmd_args, uint32_t arg_size)
 {
@@ -766,6 +802,9 @@ int cam_jpeg_dma_process_cmd(void *device_priv, uint32_t cmd_type,
 		}
 		break;
 	}
+	case CAM_JPEG_CMD_DUMP_DEBUG_REGS:
+		rc = cam_jpeg_dma_dump_debug_regs(jpeg_dma_dev);
+		break;
 	default:
 		rc = -EINVAL;
 		break;

drivers/cam_jpeg/jpeg_hw/jpeg_dma_hw/jpeg_dma_core.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_DMA_CORE_H
@@ -64,9 +64,21 @@ struct cam_jpeg_dma_camnoc_misr_reg_val {
 	uint32_t misc_ctl_stop;
 };
 
+struct cam_jpeg_dma_debug_regs_offset {
+	uint32_t top_offset;
+	uint32_t top_range;
+	uint32_t we_offset;
+	uint32_t we_range;
+	uint32_t we_qos_offset;
+	uint32_t we_qos_range;
+	uint32_t perf_offset;
+	uint32_t perf_range;
+};
+
 struct cam_jpeg_dma_device_hw_info {
 	struct cam_jpeg_dma_reg_offsets reg_offset;
 	struct cam_jpeg_dma_regval reg_val;
+	struct cam_jpeg_dma_debug_regs_offset debug_reg_offset;
 	struct cam_jpeg_dma_int_status int_status;
 	struct cam_jpeg_dma_camnoc_misr_reg_offset camnoc_misr_reg_offset;
 	struct cam_jpeg_dma_camnoc_misr_reg_val camnoc_misr_reg_val;

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_680_hw_info_ver_4_2_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_ENC_680_HW_INFO_TITAN170_H
@@ -58,6 +59,16 @@ static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_680_hw_info = {
 		.misr_cfg = 0x2B4,
 		.misr_rd0 = 0x2B8,
 	},
+	.debug_reg_offset = {
+		.top_offset = 0x0,
+		.top_range = 0x24,
+		.we_offset = 0xC0,
+		.we_range = 0x31,
+		.scale_offset = 0x26C,
+		.scale_range = 0x35,
+		.perf_offset = 0xFEC,
+		.perf_range = 0x5,
+	},
 	.reg_val = {
 		.int_clr_clearall = 0xFFFFFFFF,
 		.int_mask_disable_all = 0x00000000,

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/cam_jpeg_enc_780_hw_info_ver_4_2_0.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_ENC_780_HW_INFO_TITAN170_H
@@ -58,6 +59,16 @@ static struct cam_jpeg_enc_device_hw_info cam_jpeg_enc_780_hw_info = {
 		.misr_cfg = 0x2B4,
 		.misr_rd0 = 0x2B8,
 	},
+	.debug_reg_offset = {
+		.top_offset = 0x0,
+		.top_range = 0x24,
+		.we_offset = 0xC0,
+		.we_range = 0x31,
+		.scale_offset = 0x26C,
+		.scale_range = 0x35,
+		.perf_offset = 0xFEC,
+		.perf_range = 0x5,
+	},
 	.reg_val = {
 		.int_clr_clearall = 0xFFFFFFFF,
 		.int_mask_disable_all = 0x00000000,

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.c

@@ -742,6 +742,38 @@ int cam_jpeg_enc_config_cmanoc_hw_misr(struct cam_jpeg_enc_device_hw_info *hw_in
 	return 0;
 }
 
+int cam_jpeg_enc_dump_debug_regs(struct cam_hw_info *jpeg_enc_dev)
+{
+	struct cam_hw_soc_info *soc_info = NULL;
+	struct cam_jpeg_enc_device_core_info *core_info = NULL;
+
+	soc_info = &jpeg_enc_dev->soc_info;
+	core_info = (struct cam_jpeg_enc_device_core_info *)jpeg_enc_dev->core_info;
+
+	CAM_INFO(CAM_JPEG, "******** JPEG ENCODER REGISTER DUMP *********");
+
+	/* JPEG DMA TOP, Interrupt, core config, command registers & Fetch Engine Registers*/
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.top_offset,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.top_range);
+
+	/* Write Engine & Encoder debug registers*/
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.we_offset,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.we_range);
+
+	/* WE qos cfg, test bus, DMI, spare regs, bus misr, scale reg & MMU prefetch regs */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.scale_offset,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.scale_range);
+
+	/* Perf Registers */
+	cam_soc_util_reg_dump(soc_info, CAM_JPEG_MEM_BASE_INDEX,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.perf_offset,
+		core_info->jpeg_enc_hw_info->debug_reg_offset.perf_range);
+	return 0;
+}
+
 int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
 	void *cmd_args, uint32_t arg_size)
 {
@@ -868,6 +900,9 @@ int cam_jpeg_enc_process_cmd(void *device_priv, uint32_t cmd_type,
 		}
 		break;
 	}
+	case CAM_JPEG_CMD_DUMP_DEBUG_REGS:
+		rc = cam_jpeg_enc_dump_debug_regs(jpeg_enc_dev);
+		break;
 	default:
 		rc = -EINVAL;
 		break;

drivers/cam_jpeg/jpeg_hw/jpeg_enc_hw/jpeg_enc_core.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef CAM_JPEG_ENC_CORE_H
@@ -68,8 +68,20 @@ struct cam_jpeg_enc_camnoc_misr_reg_val {
 	uint32_t misc_ctl_stop;
 };
 
+struct cam_jpeg_enc_debug_regs_offset {
+	uint32_t top_offset;
+	uint32_t top_range;
+	uint32_t we_offset;
+	uint32_t we_range;
+	uint32_t scale_offset;
+	uint32_t scale_range;
+	uint32_t perf_offset;
+	uint32_t perf_range;
+};
+
 struct cam_jpeg_enc_device_hw_info {
 	struct cam_jpeg_enc_reg_offsets reg_offset;
+	struct cam_jpeg_enc_debug_regs_offset debug_reg_offset;
 	struct cam_jpeg_enc_regval reg_val;
 	struct cam_jpeg_enc_int_status int_status;
 	struct cam_jpeg_enc_reg_dump reg_dump;