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@@ -1373,8 +1373,21 @@ static void dsi_kickoff_msg_tx(struct dsi_ctrl *dsi_ctrl,
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dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
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dsi_hw_ops.reset_trig_ctrl(&dsi_ctrl->hw,
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&dsi_ctrl->host_config.common_config);
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&dsi_ctrl->host_config.common_config);
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- /* check if custom dma scheduling line needed */
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- if (flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED)
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+ /*
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+ * Always enable DMA scheduling for video mode panel.
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+ *
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+ * In video mode panel, if the DMA is triggered very close to
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+ * the beginning of the active window and the DMA transfer
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+ * happens in the last line of VBP, then the HW state will
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+ * stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
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+ * But somewhere in the middle of the active window, if SW
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+ * disables DSI command mode engine while the HW is still
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+ * waiting and re-enable after timing engine is OFF. So the
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+ * HW never ‘sees’ another vblank line and hence it gets
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+ * stuck in the ‘wait’ state.
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+ */
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+ if ((flags & DSI_CTRL_CMD_CUSTOM_DMA_SCHED) ||
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+ (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE))
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dsi_configure_command_scheduling(dsi_ctrl, cmd_mem);
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dsi_configure_command_scheduling(dsi_ctrl, cmd_mem);
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dsi_ctrl->cmd_mode = (dsi_ctrl->host_config.panel_mode ==
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dsi_ctrl->cmd_mode = (dsi_ctrl->host_config.panel_mode ==
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