|
@@ -1,7 +1,7 @@
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
|
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
/*
|
|
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
|
|
* Copyright (c) 2020-2022, The Linux Foundation. All rights reserved.
|
|
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
|
|
|
|
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
*/
|
|
|
|
|
|
#include <linux/reset.h>
|
|
#include <linux/reset.h>
|
|
@@ -134,6 +134,10 @@ typedef enum {
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33 (NOC_BASE_OFFS + 0xA038)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33 (NOC_BASE_OFFS + 0xA038)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33 (NOC_BASE_OFFS + 0xA03C)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33 (NOC_BASE_OFFS + 0xA03C)
|
|
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040)
|
|
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040)
|
|
|
|
+#define VCODEC_NOC_SidebandManager_SenseIn0_Low (NOC_BASE_OFFS + 0x7100)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH (NOC_BASE_OFFS + 0x7104)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH (NOC_BASE_OFFS + 0x710C)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW (NOC_BASE_OFFS + 0x7110)
|
|
|
|
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3508)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3508)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3518)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3518)
|
|
@@ -146,6 +150,12 @@ typedef enum {
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3538)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3538)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P (NOC_BASE_OFFS + 0x353C)
|
|
#define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P (NOC_BASE_OFFS + 0x353C)
|
|
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240)
|
|
#define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240)
|
|
|
|
+#define VCODEC_NOC_SidebandManager_SenseIn0_Low_2P (NOC_BASE_OFFS + 0x3300)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P (NOC_BASE_OFFS + 0x3304)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P (NOC_BASE_OFFS + 0x330C)
|
|
|
|
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P (NOC_BASE_OFFS + 0x3310)
|
|
|
|
+
|
|
|
|
+#define VCODEC_DMA_SPARE_3 0x87B8
|
|
|
|
|
|
static int __interrupt_init_iris33(struct msm_vidc_core *core)
|
|
static int __interrupt_init_iris33(struct msm_vidc_core *core)
|
|
{
|
|
{
|
|
@@ -282,8 +292,9 @@ static bool is_iris33_hw_power_collapsed(struct msm_vidc_core *core)
|
|
static int __power_off_iris33_hardware(struct msm_vidc_core *core)
|
|
static int __power_off_iris33_hardware(struct msm_vidc_core *core)
|
|
{
|
|
{
|
|
int rc = 0, i;
|
|
int rc = 0, i;
|
|
- u32 value = 0;
|
|
|
|
|
|
+ u32 value = 0, count = 0;
|
|
bool pwr_collapsed = false;
|
|
bool pwr_collapsed = false;
|
|
|
|
+ u32 sense0_low, sense0_high, sense1_high, sense2_low;
|
|
|
|
|
|
/*
|
|
/*
|
|
* Incase hw power control is enabled, for any error case
|
|
* Incase hw power control is enabled, for any error case
|
|
@@ -304,6 +315,10 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ rc = call_res_op(core, gdsc_sw_ctrl, core);
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* check to make sure core clock branch enabled else
|
|
* check to make sure core clock branch enabled else
|
|
* we cannot read vcodec top idle register
|
|
* we cannot read vcodec top idle register
|
|
@@ -320,6 +335,10 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ rc = __write_register_masked(core, VCODEC_DMA_SPARE_3, 0x1, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* add MNoC idle check before collapsing MVS0 per HPG update
|
|
* add MNoC idle check before collapsing MVS0 per HPG update
|
|
* poll for NoC DMA idle -> HPG 6.1.1
|
|
* poll for NoC DMA idle -> HPG 6.1.1
|
|
@@ -338,15 +357,84 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
|
|
if (rc)
|
|
if (rc)
|
|
return rc;
|
|
return rc;
|
|
|
|
|
|
- rc = __read_register_with_poll_timeout(core, AON_WRAPPER_MVP_NOC_LPI_STATUS,
|
|
|
|
- 0x1, 0x1, 200, 2000);
|
|
|
|
- if (rc)
|
|
|
|
- d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
|
|
|
|
|
|
+ rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value);
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
|
|
- rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
- 0x0, BIT(0));
|
|
|
|
- if (rc)
|
|
|
|
- return rc;
|
|
|
|
|
|
+ while ((!(value & BIT(0))) && (value & BIT(1) || value & BIT(2))) {
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x0, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x1, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+
|
|
|
|
+ rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &value);
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ ++count;
|
|
|
|
+ if (count >= 1000) {
|
|
|
|
+ d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (count < 1000) {
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x0, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ i = 0;
|
|
|
|
+ do {
|
|
|
|
+ value = 0;
|
|
|
|
+
|
|
|
|
+ if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33) {
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SidebandManager_SenseIn0_Low,
|
|
|
|
+ &sense0_low);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH,
|
|
|
|
+ &sense0_high);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH,
|
|
|
|
+ &sense1_high);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW,
|
|
|
|
+ &sense2_low);
|
|
|
|
+ } else if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33_2P) {
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SidebandManager_SenseIn0_Low_2P,
|
|
|
|
+ &sense0_low);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P,
|
|
|
|
+ &sense0_high);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P,
|
|
|
|
+ &sense1_high);
|
|
|
|
+ __read_register(core,
|
|
|
|
+ VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P,
|
|
|
|
+ &sense2_low);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ value = ((sense0_low & 0x00008000) ||
|
|
|
|
+ (sense0_high & 0x00000800) ||
|
|
|
|
+ (sense1_high & 0x00800000) ||
|
|
|
|
+ (sense2_low & 0x00002000));
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+ i++;
|
|
|
|
+ } while ((value) && (i <= 100));
|
|
|
|
+
|
|
|
|
+ d_vpr_h("%s: sideband register value = %d\n", __func__, value);
|
|
|
|
|
|
/*
|
|
/*
|
|
* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
|
|
* Reset both sides of 2 ahb2ahb_bridges (TZ and non-TZ)
|
|
@@ -370,19 +458,13 @@ disable_power:
|
|
rc = 0;
|
|
rc = 0;
|
|
}
|
|
}
|
|
|
|
|
|
- rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
|
|
|
|
- if (rc) {
|
|
|
|
- d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
|
|
|
|
- rc = 0;
|
|
|
|
- }
|
|
|
|
-
|
|
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
|
|
static int __power_off_iris33_controller(struct msm_vidc_core *core)
|
|
static int __power_off_iris33_controller(struct msm_vidc_core *core)
|
|
{
|
|
{
|
|
- int rc = 0;
|
|
|
|
- int value = 0;
|
|
|
|
|
|
+ int noc_lpi_status = 0, count = 0;
|
|
|
|
+ int rc = 0, value = 0;
|
|
|
|
|
|
/*
|
|
/*
|
|
* mask fal10_veto QLPAC error since fal10_veto can go 1
|
|
* mask fal10_veto QLPAC error since fal10_veto can go 1
|
|
@@ -434,6 +516,11 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core)
|
|
rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
|
|
rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
|
|
if (rc)
|
|
if (rc)
|
|
d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
|
|
d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, reset_control_assert, core, "video_mvs0_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: assert video_mvs0_reset failed\n", __func__);
|
|
|
|
+
|
|
/* set retain mem and peripheral before asset mvs0c reset */
|
|
/* set retain mem and peripheral before asset mvs0c reset */
|
|
rc = call_res_op(core, clk_set_flag, core,
|
|
rc = call_res_op(core, clk_set_flag, core,
|
|
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
|
|
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
|
|
@@ -447,6 +534,9 @@ static int __power_off_iris33_controller(struct msm_vidc_core *core)
|
|
if (rc)
|
|
if (rc)
|
|
d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
|
|
d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
|
|
usleep_range(400, 500);
|
|
usleep_range(400, 500);
|
|
|
|
+ rc = call_res_op(core, reset_control_deassert, core, "video_mvs0_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: de-assert video_mvs0_reset failed\n", __func__);
|
|
rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
|
|
rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
|
|
if (rc)
|
|
if (rc)
|
|
d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
|
|
d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
|
|
@@ -523,6 +613,12 @@ skip_video_xo_reset:
|
|
if (rc)
|
|
if (rc)
|
|
return rc;
|
|
return rc;
|
|
|
|
|
|
|
|
+ rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
|
|
|
|
+ if (rc) {
|
|
|
|
+ d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
|
|
|
|
+ rc = 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
/* remove retain mem and retain peripheral */
|
|
/* remove retain mem and retain peripheral */
|
|
rc = call_res_op(core, clk_set_flag, core,
|
|
rc = call_res_op(core, clk_set_flag, core,
|
|
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
|
|
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
|
|
@@ -541,6 +637,129 @@ skip_video_xo_reset:
|
|
rc = 0;
|
|
rc = 0;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ if (!is_core_state(core, MSM_VIDC_CORE_ERROR))
|
|
|
|
+ goto power_down;
|
|
|
|
+
|
|
|
|
+ /* power cycle process to recover from NoC error */
|
|
|
|
+ rc = call_res_op(core, gdsc_off, core, "iris-ctl");
|
|
|
|
+ if (rc) {
|
|
|
|
+ d_vpr_e("%s: disable regulator iris-ctl failed\n", __func__);
|
|
|
|
+ rc = 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ call_res_op(core, gdsc_on, core, "iris-ctl");
|
|
|
|
+ rc = call_res_op(core, clk_enable, core, "video_cc_mvs0c_clk");
|
|
|
|
+
|
|
|
|
+ /* assert and deassert axi and mvs0c resets */
|
|
|
|
+ rc = call_res_op(core, reset_control_assert, core, "video_axi_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: assert video_axi_reset failed\n", __func__);
|
|
|
|
+
|
|
|
|
+ /* set retain mem and peripheral before asset mvs0c reset */
|
|
|
|
+ rc = call_res_op(core, clk_set_flag, core,
|
|
|
|
+ "video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_MEM);
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: set retain mem failed\n", __func__);
|
|
|
|
+ rc = call_res_op(core, clk_set_flag, core,
|
|
|
|
+ "video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_RETAIN_PERIPH);
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: set retain peripheral failed\n", __func__);
|
|
|
|
+ rc = call_res_op(core, reset_control_assert, core, "video_mvs0c_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: assert video_mvs0c_reset failed\n", __func__);
|
|
|
|
+ usleep_range(400, 500);
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, reset_control_deassert, core, "video_axi_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: de-assert video_axi_reset failed\n", __func__);
|
|
|
|
+ rc = call_res_op(core, reset_control_deassert, core, "video_mvs0c_reset");
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: de-assert video_mvs0c_reset failed\n", __func__);
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, gdsc_on, core, "vcodec");
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, clk_enable, core, "video_cc_mvs0_clk");
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x1, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+
|
|
|
|
+ rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ while ((!(noc_lpi_status & BIT(0))) &&
|
|
|
|
+ (noc_lpi_status & BIT(1) || noc_lpi_status & BIT(2))) {
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x0, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x1, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ usleep_range(10, 20);
|
|
|
|
+
|
|
|
|
+ rc = __read_register(core, AON_WRAPPER_MVP_NOC_LPI_STATUS, &noc_lpi_status);
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+
|
|
|
|
+ ++count;
|
|
|
|
+ if (count >= 1000) {
|
|
|
|
+ d_vpr_e("%s: AON_WRAPPER_MVP_NOC_LPI_CONTROL failed\n", __func__);
|
|
|
|
+ break;
|
|
|
|
+ }
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ if (count < 1000) {
|
|
|
|
+ rc = __write_register_masked(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL,
|
|
|
|
+ 0x0, BIT(0));
|
|
|
|
+ if (rc)
|
|
|
|
+ return rc;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, clk_disable, core, "video_cc_mvs0_clk");
|
|
|
|
+ if (rc) {
|
|
|
|
+ d_vpr_e("%s: disable unprepare video_cc_mvs0_clk failed\n", __func__);
|
|
|
|
+ rc = 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, gdsc_off, core, "vcodec");
|
|
|
|
+ if (rc) {
|
|
|
|
+ d_vpr_e("%s: disable regulator vcodec failed\n", __func__);
|
|
|
|
+ rc = 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* remove retain mem and retain peripheral */
|
|
|
|
+ rc = call_res_op(core, clk_set_flag, core,
|
|
|
|
+ "video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: set noretain peripheral failed\n", __func__);
|
|
|
|
+
|
|
|
|
+ rc = call_res_op(core, clk_set_flag, core,
|
|
|
|
+ "video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_MEM);
|
|
|
|
+ if (rc)
|
|
|
|
+ d_vpr_e("%s: set noretain mem failed\n", __func__);
|
|
|
|
+
|
|
|
|
+ /* Turn off MVP MVS0C core clock */
|
|
|
|
+ rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk");
|
|
|
|
+ if (rc) {
|
|
|
|
+ d_vpr_e("%s: disable unprepare video_cc_mvs0c_clk failed\n", __func__);
|
|
|
|
+ rc = 0;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+power_down:
|
|
/* power down process */
|
|
/* power down process */
|
|
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
|
|
rc = call_res_op(core, gdsc_off, core, "iris-ctl");
|
|
if (rc) {
|
|
if (rc) {
|
|
@@ -1067,7 +1286,6 @@ static int __noc_error_info_iris33(struct msm_vidc_core *core)
|
|
|
|
|
|
fail_deassert_xo_reset:
|
|
fail_deassert_xo_reset:
|
|
fail_assert_xo_reset:
|
|
fail_assert_xo_reset:
|
|
- MSM_VIDC_FATAL(true);
|
|
|
|
return rc;
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
|