video: driver: Add mvs0 clock reset and update sideBand Register

For Cliffs target, Add mvs0 reset clock and update sideBand NoC
registers.

Change-Id: I6e48e0cab842f3ee12b1e3cb68495afe5f4e67de
Signed-off-by: Vedang Nagar <[email protected]>

driver/platform/cliffs/src/msm_vidc_cliffs.c

@@ -4909,6 +4909,7 @@ static const struct clk_rst_table cliffs_clk_reset_table[] = {
 	{ "video_axi_reset",        0  },
 	{ "video_xo_reset",         1  },
 	{ "video_mvs0c_reset",      0  },
+	{ "video_mvs0_reset",       0  },
 };
 
 /* name, llcc_id */
@@ -5071,7 +5072,9 @@ static const u32 cliffs_vdec_output_properties_av1[] = {
 
 static const u32 cliffs_msm_vidc_ssr_type[] = {
 	HFI_SSR_TYPE_SW_ERR_FATAL,
+	HFI_SSR_TYPE_SW_DIV_BY_ZERO,
 	HFI_SSR_TYPE_CPU_WDOG_IRQ,
+	HFI_SSR_TYPE_NOC_ERROR,
 };
 
 static struct msm_vidc_efuse_data efuse_data_cliffs[] = {

driver/variant/iris33/src/msm_vidc_iris33.c

@@ -134,10 +134,10 @@ typedef enum {
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33   (NOC_BASE_OFFS + 0xA038)
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33  (NOC_BASE_OFFS + 0xA03C)
 #define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33 (NOC_BASE_OFFS + 0x7040)
-#define VCODEC_NOC_SidebandManager_main_SidebandManager_SenseIn0_Low  (NOC_BASE_OFFS + 0x7100)
-#define VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN0_HIGH (NOC_BASE_OFFS + 0x7104)
-#define VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN1_HIGH (NOC_BASE_OFFS + 0x710C)
-#define VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN2_LOW  (NOC_BASE_OFFS + 0x7110)
+#define VCODEC_NOC_SidebandManager_SenseIn0_Low  (NOC_BASE_OFFS + 0x7100)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH (NOC_BASE_OFFS + 0x7104)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH (NOC_BASE_OFFS + 0x710C)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW  (NOC_BASE_OFFS + 0x7110)
 
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_MAINCTL_LOW_IRIS33_2P   (NOC_BASE_OFFS + 0x3508)
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRCLR_LOW_IRIS33_2P    (NOC_BASE_OFFS + 0x3518)
@@ -150,6 +150,10 @@ typedef enum {
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_LOW_IRIS33_2P   (NOC_BASE_OFFS + 0x3538)
 #define NOC_ERL_ERRORLOGGER_MAIN_ERRORLOGGER_ERRLOG3_HIGH_IRIS33_2P  (NOC_BASE_OFFS + 0x353C)
 #define NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_FAULTINEN0_LOW_IRIS33_2P (NOC_BASE_OFFS + 0x3240)
+#define VCODEC_NOC_SidebandManager_SenseIn0_Low_2P  (NOC_BASE_OFFS + 0x3300)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P (NOC_BASE_OFFS + 0x3304)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P (NOC_BASE_OFFS + 0x330C)
+#define VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P  (NOC_BASE_OFFS + 0x3310)
 
 #define VCODEC_DMA_SPARE_3 0x87B8
 
@@ -394,18 +398,33 @@ static int __power_off_iris33_hardware(struct msm_vidc_core *core)
 	do {
 		value = 0;
 
-		__read_register(core,
-				VCODEC_NOC_SidebandManager_main_SidebandManager_SenseIn0_Low,
-				&sense0_low);
-		__read_register(core,
-				VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN0_HIGH,
-				&sense0_high);
-		__read_register(core,
-				VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN1_HIGH,
-				&sense1_high);
-		__read_register(core,
-				VCODEC_NOC_SIDEBANDMANAGER_MAIN_SIDEBANDMANAGER_SENSEIN2_LOW,
-				&sense2_low);
+		if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33) {
+			__read_register(core,
+					VCODEC_NOC_SidebandManager_SenseIn0_Low,
+					&sense0_low);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH,
+					&sense0_high);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH,
+					&sense1_high);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW,
+					&sense2_low);
+		} else if (core->platform->data.vpu_ver == VPU_VERSION_IRIS33_2P) {
+			__read_register(core,
+					VCODEC_NOC_SidebandManager_SenseIn0_Low_2P,
+					&sense0_low);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN0_HIGH_2P,
+					&sense0_high);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN1_HIGH_2P,
+					&sense1_high);
+			__read_register(core,
+					VCODEC_NOC_SIDEBANDMANAGER_SENSEIN2_LOW_2P,
+					&sense2_low);
+		}
 
 		value = ((sense0_low & 0x00008000) ||
 			 (sense0_high & 0x00000800) ||