qcacmn: HAL internal API changes for beryllium
Add HAL internal symbol changes for WCN7850. Change-Id: Ibf04113f58b76976b2233ace24d7f9e7ca284245 CRs-Fixed: 2891049
このコミットが含まれているのは:
Rakesh Pillai
@@ -64,6 +64,39 @@ extern bool is_hal_verbose_debug_enabled;
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params)
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#endif
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/*
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* Given the offset of a field in bytes, returns uint8_t *
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*/
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#define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
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(((uint8_t *)(_ptr)) + (_off_in_bytes))
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/*
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* Given the offset of a field in bytes, returns uint32_t *
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*/
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#define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
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(((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
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/*
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* Given the offset of a field in bytes, returns uint64_t *
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*/
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#define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \
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(((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3))
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#define _HAL_MS(_word, _mask, _shift) \
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(((_word) & (_mask)) >> (_shift))
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/*
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* Get number of QWORDS possible for num.
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* Its the caller's duty to make sure num is a multiple of QWORD (8)
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*/
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#define HAL_GET_NUM_QWORDS(num) ((num) >> 3)
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/*
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* Get number of DWORDS possible for num.
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* Its the caller's duty to make sure num is a multiple of DWORD (8)
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*/
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#define HAL_GET_NUM_DWORDS(num) ((num) >> 2)
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/*
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* dp_hal_soc - opaque handle for DP HAL soc
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*/
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@@ -100,23 +133,35 @@ typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t;
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struct hal_rx_mon_desc_info;
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typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t;
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struct hal_buf_info;
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typedef struct hal_buf_info *hal_buf_info_t;
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struct rx_msdu_desc_info;
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typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t;
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/* TBD: This should be movded to shared HW header file */
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enum hal_srng_ring_id {
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/* UMAC rings */
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HAL_SRNG_REO2SW1 = 0,
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HAL_SRNG_REO2SW2 = 1,
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HAL_SRNG_REO2SW3 = 2,
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HAL_SRNG_REO2SW4 = 3,
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HAL_SRNG_REO2TCL = 4,
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HAL_SRNG_SW2REO = 5,
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/* 6-7 unused */
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HAL_SRNG_REO_CMD = 8,
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HAL_SRNG_REO_STATUS = 9,
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/* 10-15 unused */
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HAL_SRNG_REO2SW0 = 0,
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HAL_SRNG_REO2SW1 = 1,
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HAL_SRNG_REO2SW2 = 2,
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HAL_SRNG_REO2SW3 = 3,
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HAL_SRNG_REO2SW4 = 4,
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HAL_SRNG_REO2SW5 = 5,
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HAL_SRNG_REO2SW6 = 6,
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HAL_SRNG_REO2SW7 = 7,
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HAL_SRNG_REO2SW8 = 8,
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HAL_SRNG_REO2TCL = 9,
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HAL_SRNG_SW2REO = 10,
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HAL_SRNG_SW2REO1 = 11,
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HAL_SRNG_REO_CMD = 12,
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HAL_SRNG_REO_STATUS = 13,
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/* 14-15 unused */
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HAL_SRNG_SW2TCL1 = 16,
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HAL_SRNG_SW2TCL2 = 17,
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HAL_SRNG_SW2TCL3 = 18,
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HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */
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HAL_SRNG_SW2TCL5 = 20,
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/* 20-23 unused */
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HAL_SRNG_SW2TCL_CMD = 24,
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HAL_SRNG_TCL_STATUS = 25,
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@@ -166,7 +211,10 @@ enum hal_srng_ring_id {
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HAL_SRNG_WBM2SW1_RELEASE = 107,
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HAL_SRNG_WBM2SW2_RELEASE = 108,
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HAL_SRNG_WBM2SW3_RELEASE = 109,
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/* 110-127 unused */
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HAL_SRNG_WBM2SW4_RELEASE = 110,
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HAL_SRNG_WBM2SW5_RELEASE = 111,
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HAL_SRNG_WBM2SW6_RELEASE = 112,
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/* 113-127 unused */
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HAL_SRNG_UMAC_ID_END = 127,
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/* LMAC rings - The following set will be replicated for each LMAC */
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HAL_SRNG_LMAC1_ID_START = 128,
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@@ -236,6 +284,20 @@ enum hal_srng_dir {
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HAL_SRNG_DST_RING
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};
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/**
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* enum hal_reo_remap_reg - REO remap registers
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* @HAL_REO_REMAP_REG_IX0: reo remap reg IX0
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* @HAL_REO_REMAP_REG_IX1: reo remap reg IX1
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* @HAL_REO_REMAP_REG_IX2: reo remap reg IX2
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* @HAL_REO_REMAP_REG_IX3: reo remap reg IX3
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*/
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enum hal_reo_remap_reg {
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HAL_REO_REMAP_REG_IX0,
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HAL_REO_REMAP_REG_IX1,
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HAL_REO_REMAP_REG_IX2,
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HAL_REO_REMAP_REG_IX3
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};
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/* Lock wrappers for SRNG */
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#define hal_srng_lock_t qdf_spinlock_t
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#define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock)
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@@ -352,6 +414,19 @@ struct hal_reg_write_tcl_stats {
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#endif
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#endif
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struct hal_offload_info {
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uint8_t lro_eligible;
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uint8_t tcp_proto;
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uint8_t tcp_pure_ack;
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uint8_t ipv6_proto;
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uint8_t tcp_offset;
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uint16_t tcp_csum;
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uint16_t tcp_win;
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uint32_t tcp_seq_num;
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uint32_t tcp_ack_num;
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uint32_t flow_id;
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};
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/* Common SRNG ring structure for source and destination rings */
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struct hal_srng {
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/* Unique SRNG ring ID */
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@@ -491,7 +566,7 @@ struct hal_hw_srng_config {
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uint32_t max_size;
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};
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#define MAX_SHADOW_REGISTERS 36
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#define MAX_SHADOW_REGISTERS 40
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#define MAX_GENERIC_SHADOW_REG 5
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/**
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@@ -529,8 +604,26 @@ struct hal_reo_params {
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uint8_t padding[2];
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};
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struct hal_hw_txrx_ops {
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/**
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* enum hal_reo_cmd_type: Enum for REO command type
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* @CMD_GET_QUEUE_STATS: Get REO queue status/stats
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* @CMD_FLUSH_QUEUE: Flush all frames in REO queue
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* @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
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* @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked
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* earlier with a ‘REO_FLUSH_CACHE’ command
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* @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
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* @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
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*/
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enum hal_reo_cmd_type {
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CMD_GET_QUEUE_STATS = 0,
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CMD_FLUSH_QUEUE = 1,
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CMD_FLUSH_CACHE = 2,
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CMD_UNBLOCK_CACHE = 3,
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CMD_FLUSH_TIMEOUT_LIST = 4,
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CMD_UPDATE_RX_REO_QUEUE = 5
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};
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struct hal_hw_txrx_ops {
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/* init and setup */
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void (*hal_srng_dst_hw_init)(struct hal_soc *hal,
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struct hal_srng *srng);
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@@ -552,6 +645,13 @@ struct hal_hw_txrx_ops {
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qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc,
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qdf_iomem_t addr);
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void (*hal_reo_set_err_dst_remap)(void *hal_soc);
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void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid,
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uint32_t ba_window_size,
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uint32_t start_seq, void *hw_qdesc_vaddr,
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qdf_dma_addr_t hw_qdesc_paddr,
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int pn_type);
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uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg,
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uint8_t *ix0_map);
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/* tx */
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void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id);
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@@ -561,8 +661,9 @@ struct hal_hw_txrx_ops {
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uint8_t id,
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uint8_t dscp);
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void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id);
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void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
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uint8_t pool_id, uint32_t desc_id, uint8_t type);
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void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr,
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uint8_t pool_id, uint32_t desc_id,
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uint8_t type);
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void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type);
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void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index);
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void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index);
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@@ -573,6 +674,7 @@ struct hal_hw_txrx_ops {
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void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en);
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void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl);
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uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc);
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/* rx */
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uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *);
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@@ -590,7 +692,8 @@ struct hal_hw_txrx_ops {
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uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf);
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void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr);
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void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr);
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void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h);
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void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b,
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void *h);
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uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr,
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void *ppdu_info,
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hal_soc_handle_t hal_soc_hdl,
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@@ -604,6 +707,8 @@ struct hal_hw_txrx_ops {
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void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp,
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uint8_t id);
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void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio);
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/* rx */
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uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf);
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uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf);
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@@ -697,6 +802,98 @@ struct hal_hw_txrx_ops {
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uint32_t *fse, qdf_size_t len);
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void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf,
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uint32_t *reo_destination_indication);
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uint8_t (*hal_tx_get_num_tcl_banks)(void);
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void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie,
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qdf_dma_addr_t link_desc_paddr);
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void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl);
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void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr);
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void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
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uint8_t ac, uint32_t *value);
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void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl,
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uint8_t ac, uint32_t value);
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uint32_t (*hal_get_reo_reg_base_offset)(void);
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void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size,
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uint16_t *rx_mon_pkt_tlv_size);
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uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf);
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uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr);
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void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl,
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uint8_t *buf, uint8_t dbg_level);
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int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv,
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struct hal_offload_info *offload_info);
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uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf);
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uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf);
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int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params);
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int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset,
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uint32_t *l4_hdr_offset);
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uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf);
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void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num);
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uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf);
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uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc);
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uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc);
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void (*hal_rx_buf_cookie_rbm_get)(hal_buff_addrinfo_t buf_addr_info_hdl,
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hal_buf_info_t buf_info_hdl);
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void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry,
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qdf_dma_addr_t paddr,
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uint32_t cookie, uint8_t manager);
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uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl);
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uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc);
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void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr,
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uint32_t *ip_csum_err,
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uint32_t *tcp_udp_csum_err);
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void (*hal_rx_mpdu_desc_info_get)(void *desc_addr,
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void *mpdu_desc_info_hdl);
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uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc);
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uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc);
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bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf);
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uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr);
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uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr);
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void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr,
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struct hal_rx_pkt_capture_flags *flags);
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uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr);
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uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr);
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void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf,
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uint8_t *priv_data,
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uint32_t len);
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void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf,
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uint8_t *priv_data,
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uint32_t len);
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void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len);
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/* REO CMD and STATUS */
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int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl,
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hal_ring_handle_t hal_ring_hdl,
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enum hal_reo_cmd_type cmd,
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void *params);
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void (*hal_reo_queue_stats_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void (*hal_reo_flush_queue_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void (*hal_reo_flush_cache_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void (*hal_reo_unblock_cache_status)(hal_ring_desc_t ring_desc,
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hal_soc_handle_t hal_soc_hdl,
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void *st_handle);
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void (*hal_reo_flush_timeout_list_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void (*hal_reo_desc_thres_reached_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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void (*hal_reo_rx_update_queue_status)(hal_ring_desc_t ring_desc,
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void *st_handle,
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hal_soc_handle_t hal_soc_hdl);
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};
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/**
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@@ -871,6 +1068,7 @@ void hal_qca6490_attach(struct hal_soc *hal_soc);
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void hal_qca6390_attach(struct hal_soc *hal_soc);
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void hal_qca6290_attach(struct hal_soc *hal_soc);
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void hal_qca8074_attach(struct hal_soc *hal_soc);
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void hal_wcn7850_attach(struct hal_soc *hal_soc);
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/*
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* hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque
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