diff --git a/hal/wifi3.0/hal_internal.h b/hal/wifi3.0/hal_internal.h index 9990316758..7465aaf42e 100644 --- a/hal/wifi3.0/hal_internal.h +++ b/hal/wifi3.0/hal_internal.h @@ -64,6 +64,39 @@ extern bool is_hal_verbose_debug_enabled; params) #endif +/* + * Given the offset of a field in bytes, returns uint8_t * + */ +#define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \ + (((uint8_t *)(_ptr)) + (_off_in_bytes)) + +/* + * Given the offset of a field in bytes, returns uint32_t * + */ +#define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \ + (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2)) + +/* + * Given the offset of a field in bytes, returns uint64_t * + */ +#define _OFFSET_TO_QWORD_PTR(_ptr, _off_in_bytes) \ + (((uint64_t *)(_ptr)) + ((_off_in_bytes) >> 3)) + +#define _HAL_MS(_word, _mask, _shift) \ + (((_word) & (_mask)) >> (_shift)) + +/* + * Get number of QWORDS possible for num. + * Its the caller's duty to make sure num is a multiple of QWORD (8) + */ +#define HAL_GET_NUM_QWORDS(num) ((num) >> 3) + +/* + * Get number of DWORDS possible for num. + * Its the caller's duty to make sure num is a multiple of DWORD (8) + */ +#define HAL_GET_NUM_DWORDS(num) ((num) >> 2) + /* * dp_hal_soc - opaque handle for DP HAL soc */ @@ -100,23 +133,35 @@ typedef struct hal_buff_addrinfo *hal_buff_addrinfo_t; struct hal_rx_mon_desc_info; typedef struct hal_rx_mon_desc_info *hal_rx_mon_desc_info_t; +struct hal_buf_info; +typedef struct hal_buf_info *hal_buf_info_t; + +struct rx_msdu_desc_info; +typedef struct rx_msdu_desc_info *rx_msdu_desc_info_t; + /* TBD: This should be movded to shared HW header file */ enum hal_srng_ring_id { /* UMAC rings */ - HAL_SRNG_REO2SW1 = 0, - HAL_SRNG_REO2SW2 = 1, - HAL_SRNG_REO2SW3 = 2, - HAL_SRNG_REO2SW4 = 3, - HAL_SRNG_REO2TCL = 4, - HAL_SRNG_SW2REO = 5, - /* 6-7 unused */ - HAL_SRNG_REO_CMD = 8, - HAL_SRNG_REO_STATUS = 9, - /* 10-15 unused */ + HAL_SRNG_REO2SW0 = 0, + HAL_SRNG_REO2SW1 = 1, + HAL_SRNG_REO2SW2 = 2, + HAL_SRNG_REO2SW3 = 3, + HAL_SRNG_REO2SW4 = 4, + HAL_SRNG_REO2SW5 = 5, + HAL_SRNG_REO2SW6 = 6, + HAL_SRNG_REO2SW7 = 7, + HAL_SRNG_REO2SW8 = 8, + HAL_SRNG_REO2TCL = 9, + HAL_SRNG_SW2REO = 10, + HAL_SRNG_SW2REO1 = 11, + HAL_SRNG_REO_CMD = 12, + HAL_SRNG_REO_STATUS = 13, + /* 14-15 unused */ HAL_SRNG_SW2TCL1 = 16, HAL_SRNG_SW2TCL2 = 17, HAL_SRNG_SW2TCL3 = 18, HAL_SRNG_SW2TCL4 = 19, /* FW2TCL ring */ + HAL_SRNG_SW2TCL5 = 20, /* 20-23 unused */ HAL_SRNG_SW2TCL_CMD = 24, HAL_SRNG_TCL_STATUS = 25, @@ -166,7 +211,10 @@ enum hal_srng_ring_id { HAL_SRNG_WBM2SW1_RELEASE = 107, HAL_SRNG_WBM2SW2_RELEASE = 108, HAL_SRNG_WBM2SW3_RELEASE = 109, - /* 110-127 unused */ + HAL_SRNG_WBM2SW4_RELEASE = 110, + HAL_SRNG_WBM2SW5_RELEASE = 111, + HAL_SRNG_WBM2SW6_RELEASE = 112, + /* 113-127 unused */ HAL_SRNG_UMAC_ID_END = 127, /* LMAC rings - The following set will be replicated for each LMAC */ HAL_SRNG_LMAC1_ID_START = 128, @@ -236,6 +284,20 @@ enum hal_srng_dir { HAL_SRNG_DST_RING }; +/** + * enum hal_reo_remap_reg - REO remap registers + * @HAL_REO_REMAP_REG_IX0: reo remap reg IX0 + * @HAL_REO_REMAP_REG_IX1: reo remap reg IX1 + * @HAL_REO_REMAP_REG_IX2: reo remap reg IX2 + * @HAL_REO_REMAP_REG_IX3: reo remap reg IX3 + */ +enum hal_reo_remap_reg { + HAL_REO_REMAP_REG_IX0, + HAL_REO_REMAP_REG_IX1, + HAL_REO_REMAP_REG_IX2, + HAL_REO_REMAP_REG_IX3 +}; + /* Lock wrappers for SRNG */ #define hal_srng_lock_t qdf_spinlock_t #define SRNG_LOCK_INIT(_lock) qdf_spinlock_create(_lock) @@ -352,6 +414,19 @@ struct hal_reg_write_tcl_stats { #endif #endif +struct hal_offload_info { + uint8_t lro_eligible; + uint8_t tcp_proto; + uint8_t tcp_pure_ack; + uint8_t ipv6_proto; + uint8_t tcp_offset; + uint16_t tcp_csum; + uint16_t tcp_win; + uint32_t tcp_seq_num; + uint32_t tcp_ack_num; + uint32_t flow_id; +}; + /* Common SRNG ring structure for source and destination rings */ struct hal_srng { /* Unique SRNG ring ID */ @@ -491,7 +566,7 @@ struct hal_hw_srng_config { uint32_t max_size; }; -#define MAX_SHADOW_REGISTERS 36 +#define MAX_SHADOW_REGISTERS 40 #define MAX_GENERIC_SHADOW_REG 5 /** @@ -529,8 +604,26 @@ struct hal_reo_params { uint8_t padding[2]; }; -struct hal_hw_txrx_ops { +/** + * enum hal_reo_cmd_type: Enum for REO command type + * @CMD_GET_QUEUE_STATS: Get REO queue status/stats + * @CMD_FLUSH_QUEUE: Flush all frames in REO queue + * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache + * @CMD_UNBLOCK_CACHE: Unblock a descriptor’s address that was blocked + * earlier with a ‘REO_FLUSH_CACHE’ command + * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list + * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings + */ +enum hal_reo_cmd_type { + CMD_GET_QUEUE_STATS = 0, + CMD_FLUSH_QUEUE = 1, + CMD_FLUSH_CACHE = 2, + CMD_UNBLOCK_CACHE = 3, + CMD_FLUSH_TIMEOUT_LIST = 4, + CMD_UPDATE_RX_REO_QUEUE = 5 +}; +struct hal_hw_txrx_ops { /* init and setup */ void (*hal_srng_dst_hw_init)(struct hal_soc *hal, struct hal_srng *srng); @@ -552,6 +645,13 @@ struct hal_hw_txrx_ops { qdf_iomem_t (*hal_get_window_address)(struct hal_soc *hal_soc, qdf_iomem_t addr); void (*hal_reo_set_err_dst_remap)(void *hal_soc); + void (*hal_reo_qdesc_setup)(hal_soc_handle_t hal_soc_hdl, int tid, + uint32_t ba_window_size, + uint32_t start_seq, void *hw_qdesc_vaddr, + qdf_dma_addr_t hw_qdesc_paddr, + int pn_type); + uint32_t (*hal_gen_reo_remap_val)(enum hal_reo_remap_reg, + uint8_t *ix0_map); /* tx */ void (*hal_tx_desc_set_dscp_tid_table_id)(void *desc, uint8_t id); @@ -561,8 +661,9 @@ struct hal_hw_txrx_ops { uint8_t id, uint8_t dscp); void (*hal_tx_desc_set_lmac_id)(void *desc, uint8_t lmac_id); - void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, - uint8_t pool_id, uint32_t desc_id, uint8_t type); + void (*hal_tx_desc_set_buf_addr)(void *desc, dma_addr_t paddr, + uint8_t pool_id, uint32_t desc_id, + uint8_t type); void (*hal_tx_desc_set_search_type)(void *desc, uint8_t search_type); void (*hal_tx_desc_set_search_index)(void *desc, uint32_t search_index); void (*hal_tx_desc_set_cache_set_num)(void *desc, uint8_t search_index); @@ -573,6 +674,7 @@ struct hal_hw_txrx_ops { void (*hal_tx_desc_set_mesh_en)(void *desc, uint8_t en); void (*hal_tx_init_cmd_credit_ring)(hal_soc_handle_t hal_soc_hdl, hal_ring_handle_t hal_ring_hdl); + uint32_t (*hal_tx_comp_get_buffer_source)(void *hal_desc); /* rx */ uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); @@ -590,7 +692,8 @@ struct hal_hw_txrx_ops { uint16_t (*hal_rx_msdu_end_da_idx_get)(uint8_t *buf); void* (*hal_rx_msdu_desc_info_get_ptr)(void *msdu_details_ptr); void* (*hal_rx_link_desc_msdu0_ptr)(void *msdu_link_ptr); - void (*hal_reo_status_get_header)(uint32_t *d, int b, void *h); + void (*hal_reo_status_get_header)(hal_ring_desc_t ring_desc, int b, + void *h); uint32_t (*hal_rx_status_get_tlv_info)(void *rx_tlv_hdr, void *ppdu_info, hal_soc_handle_t hal_soc_hdl, @@ -604,6 +707,8 @@ struct hal_hw_txrx_ops { void (*hal_tx_update_pcp_tid_map)(struct hal_soc *hal_soc, uint8_t pcp, uint8_t id); void (*hal_tx_set_tidmap_prty)(struct hal_soc *hal_soc, uint8_t prio); + + /* rx */ uint8_t (*hal_rx_get_rx_fragment_number)(uint8_t *buf); uint8_t (*hal_rx_msdu_end_da_is_mcbc_get)(uint8_t *buf); uint8_t (*hal_rx_msdu_end_sa_is_valid_get)(uint8_t *buf); @@ -697,6 +802,98 @@ struct hal_hw_txrx_ops { uint32_t *fse, qdf_size_t len); void (*hal_rx_msdu_get_reo_destination_indication)(uint8_t *buf, uint32_t *reo_destination_indication); + uint8_t (*hal_tx_get_num_tcl_banks)(void); + void (*hal_set_link_desc_addr)(void *desc, uint32_t cookie, + qdf_dma_addr_t link_desc_paddr); + void (*hal_tx_init_data_ring)(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl); + void* (*hal_rx_msdu_ext_desc_info_get_ptr)(void *msdu_details_ptr); + void (*hal_get_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t *value); + void (*hal_set_ba_aging_timeout)(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t value); + uint32_t (*hal_get_reo_reg_base_offset)(void); + void (*hal_rx_get_tlv_size)(uint16_t *rx_pkt_tlv_size, + uint16_t *rx_mon_pkt_tlv_size); + uint32_t (*hal_rx_msdu_is_wlan_mcast)(qdf_nbuf_t nbuf); + uint32_t (*hal_rx_tlv_decap_format_get)(void *hw_desc_addr); + void (*hal_rx_dump_pkt_tlvs)(hal_soc_handle_t hal_soc_hdl, + uint8_t *buf, uint8_t dbg_level); + int (*hal_rx_tlv_get_offload_info)(uint8_t *rx_tlv, + struct hal_offload_info *offload_info); + uint16_t (*hal_rx_tlv_phy_ppdu_id_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_msdu_done_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_msdu_len_get)(uint8_t *buf); + uint16_t (*hal_rx_get_frame_ctrl_field)(uint8_t *buf); + int (*hal_rx_get_proto_params)(uint8_t *buf, void *fisa_params); + int (*hal_rx_get_l3_l4_offsets)(uint8_t *buf, uint32_t *l3_hdr_offset, + uint32_t *l4_hdr_offset); + uint32_t (*hal_rx_tlv_mic_err_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_get_pkt_type)(uint8_t *buf); + void (*hal_rx_tlv_get_pn_num)(uint8_t *buf, uint64_t *pn_num); + uint8_t * (*hal_rx_pkt_hdr_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_sgi_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_rate_mcs_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_decrypt_err_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_first_mpdu_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_bw_get)(uint8_t *buf); + uint32_t (*hal_rx_wbm_err_src_get)(hal_ring_desc_t ring_desc); + uint8_t (*hal_rx_ret_buf_manager_get)(hal_ring_desc_t ring_desc); + void (*hal_rx_buf_cookie_rbm_get)(hal_buff_addrinfo_t buf_addr_info_hdl, + hal_buf_info_t buf_info_hdl); + void (*hal_rxdma_buff_addr_info_set)(void *rxdma_entry, + qdf_dma_addr_t paddr, + uint32_t cookie, uint8_t manager); + uint32_t (*hal_rx_msdu_flags_get)(rx_msdu_desc_info_t msdu_desc_info_hdl); + uint32_t (*hal_rx_get_reo_error_code)(hal_ring_desc_t rx_desc); + void (*hal_rx_tlv_csum_err_get)(uint8_t *rx_tlv_hdr, + uint32_t *ip_csum_err, + uint32_t *tcp_udp_csum_err); + void (*hal_rx_mpdu_desc_info_get)(void *desc_addr, + void *mpdu_desc_info_hdl); + uint8_t (*hal_rx_err_status_get)(hal_ring_desc_t rx_desc); + uint8_t (*hal_rx_reo_buf_type_get)(hal_ring_desc_t rx_desc); + bool (*hal_rx_mpdu_info_ampdu_flag_get)(uint8_t *buf); + uint32_t (*hal_rx_tlv_mpdu_len_err_get)(void *hw_desc_addr); + uint32_t (*hal_rx_tlv_mpdu_fcs_err_get)(void *hw_desc_addr); + void (*hal_rx_tlv_get_pkt_capture_flags)(uint8_t *rx_tlv_hdr, + struct hal_rx_pkt_capture_flags *flags); + uint8_t *(*hal_rx_desc_get_80211_hdr)(void *hw_desc_addr); + uint32_t (*hal_rx_hw_desc_mpdu_user_id)(void *hw_desc_addr); + void (*hal_rx_priv_info_set_in_tlv)(uint8_t *buf, + uint8_t *priv_data, + uint32_t len); + void (*hal_rx_priv_info_get_from_tlv)(uint8_t *buf, + uint8_t *priv_data, + uint32_t len); + void (*hal_rx_tlv_msdu_len_set)(uint8_t *buf, uint32_t len); + + /* REO CMD and STATUS */ + int (*hal_reo_send_cmd)(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + enum hal_reo_cmd_type cmd, + void *params); + void (*hal_reo_queue_stats_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); + void (*hal_reo_flush_queue_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); + void (*hal_reo_flush_cache_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); + void (*hal_reo_unblock_cache_status)(hal_ring_desc_t ring_desc, + hal_soc_handle_t hal_soc_hdl, + void *st_handle); + void (*hal_reo_flush_timeout_list_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); + void (*hal_reo_desc_thres_reached_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); + void (*hal_reo_rx_update_queue_status)(hal_ring_desc_t ring_desc, + void *st_handle, + hal_soc_handle_t hal_soc_hdl); }; /** @@ -871,6 +1068,7 @@ void hal_qca6490_attach(struct hal_soc *hal_soc); void hal_qca6390_attach(struct hal_soc *hal_soc); void hal_qca6290_attach(struct hal_soc *hal_soc); void hal_qca8074_attach(struct hal_soc *hal_soc); +void hal_wcn7850_attach(struct hal_soc *hal_soc); /* * hal_soc_to_dp_hal_roc - API to convert hal_soc to opaque