Merge "asoc: codecs: Add WSA init reg writes"

asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c

@@ -72,6 +72,9 @@ enum {
 	LPASS_CDC_WSA_MACRO_RX_MIX1,
 	LPASS_CDC_WSA_MACRO_RX4,
 	LPASS_CDC_WSA_MACRO_RX5,
+	LPASS_CDC_WSA_MACRO_RX6,
+	LPASS_CDC_WSA_MACRO_RX7,
+	LPASS_CDC_WSA_MACRO_RX8,
 	LPASS_CDC_WSA_MACRO_RX_MAX,
 };
 
@@ -342,11 +345,12 @@ static struct snd_soc_dai_driver lpass_cdc_wsa_macro_dai[];
 static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0);
 
 static const char *const rx_text[] = {
-	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "DEC0", "DEC1"
+	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4",
+	"RX5", "RX6", "RX7", "RX8", "DEC0", "DEC1"
 };
 
 static const char *const rx_mix_text[] = {
-	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5",
+	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "RX4", "RX5", "RX6", "RX7", "RX8"
 };
 
 static const char *const rx_mix_ec_text[] = {
@@ -397,19 +401,19 @@ static SOC_ENUM_SINGLE_EXT_DECL(idle_detect_enum, idle_detect_text);
 /* RX INT0 */
 static const struct soc_enum rx0_prim_inp0_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
-		0, 9, rx_text);
+		0, 12, rx_text);
 
 static const struct soc_enum rx0_prim_inp1_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
-		3, 9, rx_text);
+		3, 12, rx_text);
 
 static const struct soc_enum rx0_prim_inp2_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
-		3, 9, rx_text);
+		3, 12, rx_text);
 
 static const struct soc_enum rx0_mix_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
-		0, 7, rx_mix_text);
+		0, 10, rx_mix_text);
 
 static const struct soc_enum rx0_sidetone_mix_enum =
 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
@@ -432,19 +436,19 @@ static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
 /* RX INT1 */
 static const struct soc_enum rx1_prim_inp0_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
-		0, 9, rx_text);
+		0, 12, rx_text);
 
 static const struct soc_enum rx1_prim_inp1_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
-		3, 9, rx_text);
+		3, 12, rx_text);
 
 static const struct soc_enum rx1_prim_inp2_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
-		3, 9, rx_text);
+		3, 12, rx_text);
 
 static const struct soc_enum rx1_mix_chain_enum =
 	SOC_ENUM_SINGLE(LPASS_CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
-		0, 7, rx_mix_text);
+		0, 10, rx_mix_text);
 
 static const struct snd_kcontrol_new rx1_prim_inp0_mux =
 	SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);

asoc/codecs/wsa884x/wsa884x-reg-masks.h

@@ -214,4 +214,23 @@
 #define WSA884X_CKWD_CTL_1_SPARE_BITS_7_6_MASK                           0xc0
 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_MASK                               0x20
 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_MASK                      0x1f
+/* WSA884X_VBAT_CAL_CTL Fields: */
+#define WSA884X_VBAT_CAL_CTL_RESERVE_MASK                                0x0e
+#define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_MASK                            0x01
+/* WSA884X_REF_CTRL Fields: */
+#define WSA884X_REF_CTRL_DC_STARTUP_EN_MASK                              0x80
+#define WSA884X_REF_CTRL_DC_STARTUP_HOLD_MASK                            0x40
+#define WSA884X_REF_CTRL_TRAN_STARTUP_EN_CORE_MASK                       0x20
+#define WSA884X_REF_CTRL_TRAN_STARTUP_EN_PTAT_MASK                       0x10
+#define WSA884X_REF_CTRL_BG_EN_MASK                                      0x08
+#define WSA884X_REF_CTRL_BG_READY_FORCE_MASK                             0x04
+#define WSA884X_REF_CTRL_BG_RDY_SEL_MASK                                 0x03
+/* WSA884X_ZX_CTRL1 Fields: */
+#define WSA884X_ZX_CTRL1_ZX_DET_EN_MASK                                  0x80
+#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_MASK                               0x40
+#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_MASK                       0x20
+#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_MASK                              0x18
+#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_MASK                         0x04
+#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_MASK                            0x02
+#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_MASK                        0x01
 #endif /* WSA884X_REG_MASKS_H */

asoc/codecs/wsa884x/wsa884x-reg-shifts.h

@@ -204,4 +204,23 @@
 #define WSA884X_CKWD_CTL_1_SPARE_BITS_7_6_SHIFT                           0x06
 #define WSA884X_CKWD_CTL_1_VPP_SW_CTL_SHIFT                               0x05
 #define WSA884X_CKWD_CTL_1_CKWD_VCOMP_VREF_SEL_SHIFT                      0x00
+/* WSA884X_VBAT_CAL_CTL Fields: */
+#define WSA884X_VBAT_CAL_CTL_RESERVE_SHIFT                                0x01
+#define WSA884X_VBAT_CAL_CTL_VBAT_CAL_EN_SHIFT                            0x00
+/* WSA884X_REF_CTRL Fields: */
+#define WSA884X_REF_CTRL_DC_STARTUP_EN_SHIFT                              0x07
+#define WSA884X_REF_CTRL_DC_STARTUP_HOLD_SHIFT                            0x06
+#define WSA884X_REF_CTRL_TRAN_STARTUP_EN_CORE_SHIFT                       0x05
+#define WSA884X_REF_CTRL_TRAN_STARTUP_EN_PTAT_SHIFT                       0x04
+#define WSA884X_REF_CTRL_BG_EN_SHIFT                                      0x03
+#define WSA884X_REF_CTRL_BG_READY_FORCE_SHIFT                             0x02
+#define WSA884X_REF_CTRL_BG_RDY_SEL_SHIFT                                 0x00
+/* WSA884X_ZX_CTRL1 Fields: */
+#define WSA884X_ZX_CTRL1_ZX_DET_EN_SHIFT                                  0x07
+#define WSA884X_ZX_CTRL1_ZX_DET_SW_EN_SHIFT                               0x06
+#define WSA884X_ZX_CTRL1_ZX_DET_STAGE_DEFAULT_SHIFT                       0x05
+#define WSA884X_ZX_CTRL1_ZX_DET_SW_SEL_SHIFT                              0x03
+#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_IGNORE_SHIFT                         0x02
+#define WSA884X_ZX_CTRL1_ZX_BYP_MASK_DEL_SHIFT                            0x01
+#define WSA884X_ZX_CTRL1_BOOTCAP_REFRESH_DIS_SHIFT                        0x00
 #endif /* WSA884X_REG_SHIFTS_H */

asoc/codecs/wsa884x/wsa884x.c

@@ -125,6 +125,9 @@ static const struct wsa_reg_mask_val reg_init[] = {
 	{REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
 	{REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
 	{REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
+	{REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
+	{REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
+	{REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
 };
 
 static int wsa884x_handle_post_irq(void *data);
@@ -620,7 +623,7 @@ static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
 		snd_soc_component_update_bits(component,
 			REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
 	} else {
-		wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->system_gain];
+		wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
 		snd_soc_component_update_bits(component,
 			REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
 		snd_soc_component_update_bits(component,