wsa884x.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #include <linux/module.h>
  7. #include <linux/init.h>
  8. #include <linux/slab.h>
  9. #include <linux/platform_device.h>
  10. #include <linux/device.h>
  11. #include <linux/printk.h>
  12. #include <linux/bitops.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/pm_runtime.h>
  15. #include <linux/delay.h>
  16. #include <linux/kernel.h>
  17. #include <linux/gpio.h>
  18. #include <linux/of_gpio.h>
  19. #include <linux/of_platform.h>
  20. #include <linux/regmap.h>
  21. #include <linux/debugfs.h>
  22. #include <soc/soundwire.h>
  23. #include <sound/pcm.h>
  24. #include <sound/pcm_params.h>
  25. #include <sound/soc.h>
  26. #include <sound/soc-dapm.h>
  27. #include <sound/tlv.h>
  28. #include <asoc/msm-cdc-pinctrl.h>
  29. #include <asoc/msm-cdc-supply.h>
  30. #include "wsa884x.h"
  31. #include "internal.h"
  32. #include "asoc/bolero-slave-internal.h"
  33. #include <linux/qti-regmap-debugfs.h>
  34. #define T1_TEMP -10
  35. #define T2_TEMP 150
  36. #define LOW_TEMP_THRESHOLD 5
  37. #define HIGH_TEMP_THRESHOLD 45
  38. #define TEMP_INVALID 0xFFFF
  39. #define WSA884X_TEMP_RETRY 3
  40. #define PBR_MAX_VOLTAGE 20
  41. #define PBR_MAX_CODE 255
  42. #define WSA884X_IDLE_DETECT_NG_BLOCK_MASK 0x38
  43. #define MAX_NAME_LEN 40
  44. #define WSA884X_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  45. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  46. SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  47. SNDRV_PCM_RATE_384000)
  48. /* Fractional Rates */
  49. #define WSA884X_FRAC_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  50. SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  51. #define WSA884X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  52. SNDRV_PCM_FMTBIT_S24_LE |\
  53. SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
  54. #define REG_FIELD_VALUE(register_name, field_name, value) \
  55. WSA884X_##register_name, FIELD_MASK(register_name, field_name), \
  56. value << FIELD_SHIFT(register_name, field_name)
  57. enum {
  58. IDLE_DETECT,
  59. NG1,
  60. NG2,
  61. NG3,
  62. };
  63. struct wsa_temp_register {
  64. u8 d1_msb;
  65. u8 d1_lsb;
  66. u8 d2_msb;
  67. u8 d2_lsb;
  68. u8 dmeas_msb;
  69. u8 dmeas_lsb;
  70. };
  71. enum {
  72. COMP_OFFSET0,
  73. COMP_OFFSET1,
  74. COMP_OFFSET2,
  75. COMP_OFFSET3,
  76. COMP_OFFSET4,
  77. };
  78. #define WSA884X_VTH_TO_REG(vth) \
  79. ((vth) != 0 ? (((vth) - 150 / PBR_MAX_VOLTAGE) * PBR_MAX_CODE / 100) : 0)
  80. struct wsa_reg_mask_val {
  81. u16 reg;
  82. u8 mask;
  83. u8 val;
  84. };
  85. static const struct wsa_reg_mask_val reg_init[] = {
  86. {REG_FIELD_VALUE(CKWD_CTL_1, VPP_SW_CTL, 0x00)},
  87. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_0, COEF_A2, 0x0A)},
  88. {REG_FIELD_VALUE(CDC_SPK_DSM_A2_1, COEF_A2, 0x08)},
  89. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_0, COEF_A3, 0xF3)},
  90. {REG_FIELD_VALUE(CDC_SPK_DSM_A3_1, COEF_A3, 0x07)},
  91. {REG_FIELD_VALUE(CDC_SPK_DSM_A4_0, COEF_A4, 0x79)},
  92. {REG_FIELD_VALUE(CDC_SPK_DSM_A5_0, COEF_A5, 0x0B)},
  93. {REG_FIELD_VALUE(CDC_SPK_DSM_A6_0, COEF_A6, 0x8A)},
  94. {REG_FIELD_VALUE(CDC_SPK_DSM_A7_0, COEF_A7, 0x9B)},
  95. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C3, 0x06)},
  96. {REG_FIELD_VALUE(CDC_SPK_DSM_C_0, COEF_C2, 0x08)},
  97. {REG_FIELD_VALUE(CDC_SPK_DSM_C_2, COEF_C7, 0x0F)},
  98. {REG_FIELD_VALUE(CDC_SPK_DSM_C_3, COEF_C7, 0x20)},
  99. {REG_FIELD_VALUE(CDC_SPK_DSM_R1, SAT_LIMIT_R1, 0x83)},
  100. {REG_FIELD_VALUE(CDC_SPK_DSM_R2, SAT_LIMIT_R2, 0x7F)},
  101. {REG_FIELD_VALUE(CDC_SPK_DSM_R3, SAT_LIMIT_R3, 0x9D)},
  102. {REG_FIELD_VALUE(CDC_SPK_DSM_R4, SAT_LIMIT_R4, 0x82)},
  103. {REG_FIELD_VALUE(CDC_SPK_DSM_R5, SAT_LIMIT_R5, 0x8B)},
  104. {REG_FIELD_VALUE(CDC_SPK_DSM_R6, SAT_LIMIT_R6, 0x9B)},
  105. {REG_FIELD_VALUE(CDC_SPK_DSM_R7, SAT_LIMIT_R7, 0x3F)},
  106. {REG_FIELD_VALUE(BOP_DEGLITCH_CTL, BOP_DEGLITCH_SETTING, 0x08)},
  107. {REG_FIELD_VALUE(VBAT_THRM_FLT_CTL, VBAT_COEF_SEL, 0x04)},
  108. {REG_FIELD_VALUE(CLSH_CTL_0, DLY_CODE, 0x06)},
  109. {REG_FIELD_VALUE(CLSH_SOFT_MAX, SOFT_MAX, 0xFF)},
  110. {REG_FIELD_VALUE(OTP_REG_38, BOOST_ILIM_TUNE, 0x00)},
  111. {REG_FIELD_VALUE(OTP_REG_40, ISENSE_RESCAL, 0x08)},
  112. {REG_FIELD_VALUE(STB_CTRL1, SLOPE_COMP_CURRENT, 0x0D)},
  113. {REG_FIELD_VALUE(ILIM_CTRL1, ILIM_OFFSET_PB, 0x03)},
  114. {REG_FIELD_VALUE(CURRENT_LIMIT, CURRENT_LIMIT, 0x09)},
  115. {REG_FIELD_VALUE(CKWD_CTL_1, CKWD_VCOMP_VREF_SEL, 0x13)},
  116. {REG_FIELD_VALUE(BOP2_PROG, BOP2_VTH, 0x06)},
  117. {REG_FIELD_VALUE(BOP2_PROG, BOP2_HYST, 0x06)},
  118. {REG_FIELD_VALUE(VBAT_CAL_CTL, RESERVE, 0x02)},
  119. {REG_FIELD_VALUE(REF_CTRL, BG_RDY_SEL, 0x01)},
  120. {REG_FIELD_VALUE(ZX_CTRL1, ZX_DET_SW_SEL, 0x03)},
  121. };
  122. static int wsa884x_handle_post_irq(void *data);
  123. static int wsa884x_get_temperature(struct snd_soc_component *component,
  124. int *temp);
  125. enum {
  126. WSA8840 = 0,
  127. WSA8845 = 5,
  128. WSA8845H = 0xC,
  129. };
  130. enum {
  131. SPKR_STATUS = 0,
  132. WSA_SUPPLIES_LPM_MODE,
  133. SPKR_ADIE_LB,
  134. };
  135. enum {
  136. WSA884X_IRQ_INT_SAF2WAR = 0,
  137. WSA884X_IRQ_INT_WAR2SAF,
  138. WSA884X_IRQ_INT_DISABLE,
  139. WSA884X_IRQ_INT_OCP,
  140. WSA884X_IRQ_INT_CLIP,
  141. WSA884X_IRQ_INT_PDM_WD,
  142. WSA884X_IRQ_INT_CLK_WD,
  143. WSA884X_IRQ_INT_INTR_PIN,
  144. WSA884X_IRQ_INT_UVLO,
  145. WSA884X_IRQ_INT_PA_ON_ERR,
  146. WSA884X_NUM_IRQS,
  147. };
  148. static const struct regmap_irq wsa884x_irqs[WSA884X_NUM_IRQS] = {
  149. REGMAP_IRQ_REG(WSA884X_IRQ_INT_SAF2WAR, 0, 0x01),
  150. REGMAP_IRQ_REG(WSA884X_IRQ_INT_WAR2SAF, 0, 0x02),
  151. REGMAP_IRQ_REG(WSA884X_IRQ_INT_DISABLE, 0, 0x04),
  152. REGMAP_IRQ_REG(WSA884X_IRQ_INT_OCP, 0, 0x08),
  153. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLIP, 0, 0x10),
  154. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PDM_WD, 0, 0x20),
  155. REGMAP_IRQ_REG(WSA884X_IRQ_INT_CLK_WD, 0, 0x40),
  156. REGMAP_IRQ_REG(WSA884X_IRQ_INT_INTR_PIN, 0, 0x80),
  157. REGMAP_IRQ_REG(WSA884X_IRQ_INT_UVLO, 1, 0x01),
  158. REGMAP_IRQ_REG(WSA884X_IRQ_INT_PA_ON_ERR, 1, 0x02),
  159. };
  160. static struct regmap_irq_chip wsa884x_regmap_irq_chip = {
  161. .name = "wsa884x",
  162. .irqs = wsa884x_irqs,
  163. .num_irqs = ARRAY_SIZE(wsa884x_irqs),
  164. .num_regs = 2,
  165. .status_base = WSA884X_INTR_STATUS0,
  166. .mask_base = WSA884X_INTR_MASK0,
  167. .type_base = WSA884X_INTR_LEVEL0,
  168. .ack_base = WSA884X_INTR_CLEAR0,
  169. .use_ack = 1,
  170. .runtime_pm = false,
  171. .handle_post_irq = wsa884x_handle_post_irq,
  172. .irq_drv_data = NULL,
  173. };
  174. static int wsa884x_handle_post_irq(void *data)
  175. {
  176. struct wsa884x_priv *wsa884x = data;
  177. u32 sts1 = 0, sts2 = 0;
  178. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS0, &sts1);
  179. regmap_read(wsa884x->regmap, WSA884X_INTR_STATUS1, &sts2);
  180. wsa884x->swr_slave->slave_irq_pending =
  181. ((sts1 || sts2) ? true : false);
  182. return IRQ_HANDLED;
  183. }
  184. #ifdef CONFIG_DEBUG_FS
  185. static int codec_debug_open(struct inode *inode, struct file *file)
  186. {
  187. file->private_data = inode->i_private;
  188. return 0;
  189. }
  190. static int get_parameters(char *buf, u32 *param1, int num_of_par)
  191. {
  192. char *token;
  193. int base, cnt;
  194. token = strsep(&buf, " ");
  195. for (cnt = 0; cnt < num_of_par; cnt++) {
  196. if (token) {
  197. if ((token[1] == 'x') || (token[1] == 'X'))
  198. base = 16;
  199. else
  200. base = 10;
  201. if (kstrtou32(token, base, &param1[cnt]) != 0)
  202. return -EINVAL;
  203. token = strsep(&buf, " ");
  204. } else {
  205. return -EINVAL;
  206. }
  207. }
  208. return 0;
  209. }
  210. static bool is_swr_slave_reg_readable(int reg)
  211. {
  212. int ret = true;
  213. if (((reg > 0x46) && (reg < 0x4A)) ||
  214. ((reg > 0x4A) && (reg < 0x50)) ||
  215. ((reg > 0x55) && (reg < 0xD0)) ||
  216. ((reg > 0xD0) && (reg < 0xE0)) ||
  217. ((reg > 0xE0) && (reg < 0xF0)) ||
  218. ((reg > 0xF0) && (reg < 0x100)) ||
  219. ((reg > 0x105) && (reg < 0x120)) ||
  220. ((reg > 0x205) && (reg < 0x220)) ||
  221. ((reg > 0x305) && (reg < 0x320)) ||
  222. ((reg > 0x405) && (reg < 0x420)) ||
  223. ((reg > 0x505) && (reg < 0x520)) ||
  224. ((reg > 0x605) && (reg < 0x620)) ||
  225. ((reg > 0x127) && (reg < 0x130)) ||
  226. ((reg > 0x227) && (reg < 0x230)) ||
  227. ((reg > 0x327) && (reg < 0x330)) ||
  228. ((reg > 0x427) && (reg < 0x430)) ||
  229. ((reg > 0x527) && (reg < 0x530)) ||
  230. ((reg > 0x627) && (reg < 0x630)) ||
  231. ((reg > 0x137) && (reg < 0x200)) ||
  232. ((reg > 0x237) && (reg < 0x300)) ||
  233. ((reg > 0x337) && (reg < 0x400)) ||
  234. ((reg > 0x437) && (reg < 0x500)) ||
  235. ((reg > 0x537) && (reg < 0x600)) ||
  236. ((reg > 0x637) && (reg < 0xF00)) ||
  237. ((reg > 0xF05) && (reg < 0xF20)) ||
  238. ((reg > 0xF25) && (reg < 0xF30)) ||
  239. ((reg > 0xF35) && (reg < 0x2000)))
  240. ret = false;
  241. return ret;
  242. }
  243. static ssize_t swr_slave_reg_show(struct swr_device *pdev, char __user *ubuf,
  244. size_t count, loff_t *ppos)
  245. {
  246. int i, reg_val, len;
  247. ssize_t total = 0;
  248. char tmp_buf[SWR_SLV_MAX_BUF_LEN];
  249. if (!ubuf || !ppos)
  250. return 0;
  251. for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
  252. i <= SWR_SLV_MAX_REG_ADDR; i++) {
  253. if (!is_swr_slave_reg_readable(i))
  254. continue;
  255. swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
  256. len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
  257. (reg_val & 0xFF));
  258. if (len < 0) {
  259. pr_err("%s: fail to fill the buffer\n", __func__);
  260. total = -EFAULT;
  261. goto copy_err;
  262. }
  263. if ((total + len) >= count - 1)
  264. break;
  265. if (copy_to_user((ubuf + total), tmp_buf, len)) {
  266. pr_err("%s: fail to copy reg dump\n", __func__);
  267. total = -EFAULT;
  268. goto copy_err;
  269. }
  270. total += len;
  271. *ppos += len;
  272. }
  273. copy_err:
  274. *ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
  275. return total;
  276. }
  277. static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
  278. size_t count, loff_t *ppos)
  279. {
  280. struct swr_device *pdev;
  281. if (!count || !file || !ppos || !ubuf)
  282. return -EINVAL;
  283. pdev = file->private_data;
  284. if (!pdev)
  285. return -EINVAL;
  286. if (*ppos < 0)
  287. return -EINVAL;
  288. return swr_slave_reg_show(pdev, ubuf, count, ppos);
  289. }
  290. static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
  291. size_t count, loff_t *ppos)
  292. {
  293. char lbuf[SWR_SLV_RD_BUF_LEN];
  294. struct swr_device *pdev = NULL;
  295. struct wsa884x_priv *wsa884x = NULL;
  296. if (!count || !file || !ppos || !ubuf)
  297. return -EINVAL;
  298. pdev = file->private_data;
  299. if (!pdev)
  300. return -EINVAL;
  301. wsa884x = swr_get_dev_data(pdev);
  302. if (!wsa884x)
  303. return -EINVAL;
  304. if (*ppos < 0)
  305. return -EINVAL;
  306. snprintf(lbuf, sizeof(lbuf), "0x%x\n",
  307. (wsa884x->read_data & 0xFF));
  308. return simple_read_from_buffer(ubuf, count, ppos, lbuf,
  309. strnlen(lbuf, 7));
  310. }
  311. static ssize_t codec_debug_peek_write(struct file *file,
  312. const char __user *ubuf, size_t cnt, loff_t *ppos)
  313. {
  314. char lbuf[SWR_SLV_WR_BUF_LEN];
  315. int rc = 0;
  316. u32 param[5];
  317. struct swr_device *pdev = NULL;
  318. struct wsa884x_priv *wsa884x = NULL;
  319. if (!cnt || !file || !ppos || !ubuf)
  320. return -EINVAL;
  321. pdev = file->private_data;
  322. if (!pdev)
  323. return -EINVAL;
  324. wsa884x = swr_get_dev_data(pdev);
  325. if (!wsa884x)
  326. return -EINVAL;
  327. if (*ppos < 0)
  328. return -EINVAL;
  329. if (cnt > sizeof(lbuf) - 1)
  330. return -EINVAL;
  331. rc = copy_from_user(lbuf, ubuf, cnt);
  332. if (rc)
  333. return -EFAULT;
  334. lbuf[cnt] = '\0';
  335. rc = get_parameters(lbuf, param, 1);
  336. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
  337. return -EINVAL;
  338. swr_read(pdev, pdev->dev_num, param[0], &wsa884x->read_data, 1);
  339. if (rc == 0)
  340. rc = cnt;
  341. else
  342. pr_err("%s: rc = %d\n", __func__, rc);
  343. return rc;
  344. }
  345. static ssize_t codec_debug_write(struct file *file,
  346. const char __user *ubuf, size_t cnt, loff_t *ppos)
  347. {
  348. char lbuf[SWR_SLV_WR_BUF_LEN];
  349. int rc = 0;
  350. u32 param[5];
  351. struct swr_device *pdev;
  352. if (!file || !ppos || !ubuf)
  353. return -EINVAL;
  354. pdev = file->private_data;
  355. if (!pdev)
  356. return -EINVAL;
  357. if (cnt > sizeof(lbuf) - 1)
  358. return -EINVAL;
  359. rc = copy_from_user(lbuf, ubuf, cnt);
  360. if (rc)
  361. return -EFAULT;
  362. lbuf[cnt] = '\0';
  363. rc = get_parameters(lbuf, param, 2);
  364. if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
  365. (param[1] <= 0xFF) && (rc == 0)))
  366. return -EINVAL;
  367. swr_write(pdev, pdev->dev_num, param[0], &param[1]);
  368. if (rc == 0)
  369. rc = cnt;
  370. else
  371. pr_err("%s: rc = %d\n", __func__, rc);
  372. return rc;
  373. }
  374. static const struct file_operations codec_debug_write_ops = {
  375. .open = codec_debug_open,
  376. .write = codec_debug_write,
  377. };
  378. static const struct file_operations codec_debug_read_ops = {
  379. .open = codec_debug_open,
  380. .read = codec_debug_read,
  381. .write = codec_debug_peek_write,
  382. };
  383. static const struct file_operations codec_debug_dump_ops = {
  384. .open = codec_debug_open,
  385. .read = codec_debug_dump,
  386. };
  387. #endif
  388. static void wsa884x_regcache_sync(struct wsa884x_priv *wsa884x)
  389. {
  390. mutex_lock(&wsa884x->res_lock);
  391. regcache_mark_dirty(wsa884x->regmap);
  392. regcache_sync(wsa884x->regmap);
  393. mutex_unlock(&wsa884x->res_lock);
  394. }
  395. static irqreturn_t wsa884x_saf2war_handle_irq(int irq, void *data)
  396. {
  397. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  398. __func__, irq);
  399. return IRQ_HANDLED;
  400. }
  401. static irqreturn_t wsa884x_war2saf_handle_irq(int irq, void *data)
  402. {
  403. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  404. __func__, irq);
  405. return IRQ_HANDLED;
  406. }
  407. static irqreturn_t wsa884x_otp_handle_irq(int irq, void *data)
  408. {
  409. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  410. __func__, irq);
  411. return IRQ_HANDLED;
  412. }
  413. static irqreturn_t wsa884x_ocp_handle_irq(int irq, void *data)
  414. {
  415. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  416. __func__, irq);
  417. return IRQ_HANDLED;
  418. }
  419. static irqreturn_t wsa884x_clip_handle_irq(int irq, void *data)
  420. {
  421. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  422. __func__, irq);
  423. return IRQ_HANDLED;
  424. }
  425. static irqreturn_t wsa884x_pdm_wd_handle_irq(int irq, void *data)
  426. {
  427. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  428. __func__, irq);
  429. return IRQ_HANDLED;
  430. }
  431. static irqreturn_t wsa884x_clk_wd_handle_irq(int irq, void *data)
  432. {
  433. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  434. __func__, irq);
  435. return IRQ_HANDLED;
  436. }
  437. static irqreturn_t wsa884x_ext_int_handle_irq(int irq, void *data)
  438. {
  439. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  440. __func__, irq);
  441. return IRQ_HANDLED;
  442. }
  443. static irqreturn_t wsa884x_uvlo_handle_irq(int irq, void *data)
  444. {
  445. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  446. __func__, irq);
  447. return IRQ_HANDLED;
  448. }
  449. static irqreturn_t wsa884x_pa_on_err_handle_irq(int irq, void *data)
  450. {
  451. u8 pa_fsm_sta = 0, pa_fsm_err = 0;
  452. struct wsa884x_priv *wsa884x = data;
  453. struct snd_soc_component *component = NULL;
  454. if (!wsa884x)
  455. return IRQ_NONE;
  456. component = wsa884x->component;
  457. if (!component)
  458. return IRQ_NONE;
  459. pa_fsm_sta = (snd_soc_component_read(component, WSA884X_PA_FSM_STA1)
  460. & 0x1F);
  461. if (pa_fsm_sta)
  462. pa_fsm_err = snd_soc_component_read(component,
  463. WSA884X_PA_FSM_ERR_COND0);
  464. pr_err_ratelimited("%s: interrupt for irq =%d triggered\n",
  465. __func__, irq);
  466. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  467. 0x10, 0x00);
  468. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  469. 0x10, 0x10);
  470. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL0,
  471. 0x10, 0x00);
  472. return IRQ_HANDLED;
  473. }
  474. static int wsa884x_set_gain_parameters(struct snd_soc_component *component)
  475. {
  476. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  477. u8 igain;
  478. u8 vgain;
  479. switch (wsa884x->bat_cfg) {
  480. case CONFIG_1S:
  481. case EXT_1S:
  482. switch (wsa884x->system_gain) {
  483. case G_21_DB:
  484. wsa884x->comp_offset = COMP_OFFSET0;
  485. wsa884x->min_gain = G_0_DB;
  486. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  487. break;
  488. case G_19P5_DB:
  489. wsa884x->comp_offset = COMP_OFFSET1;
  490. wsa884x->min_gain = G_M1P5_DB;
  491. wsa884x->pa_aux_gain = PA_AUX_M1P5_DB;
  492. break;
  493. case G_18_DB:
  494. wsa884x->comp_offset = COMP_OFFSET2;
  495. wsa884x->min_gain = G_M3_DB;
  496. wsa884x->pa_aux_gain = PA_AUX_M3_DB;
  497. break;
  498. case G_16P5_DB:
  499. wsa884x->comp_offset = COMP_OFFSET3;
  500. wsa884x->min_gain = G_M4P5_DB;
  501. wsa884x->pa_aux_gain = PA_AUX_M4P5_DB;
  502. break;
  503. default:
  504. wsa884x->comp_offset = COMP_OFFSET4;
  505. wsa884x->min_gain = G_M6_DB;
  506. wsa884x->pa_aux_gain = PA_AUX_M6_DB;
  507. break;
  508. }
  509. break;
  510. case CONFIG_3S:
  511. case EXT_3S:
  512. wsa884x->comp_offset = COMP_OFFSET0;
  513. wsa884x->min_gain = G_7P5_DB;
  514. wsa884x->pa_aux_gain = PA_AUX_7P5_DB;
  515. break;
  516. case EXT_ABOVE_3S:
  517. wsa884x->comp_offset = COMP_OFFSET0;
  518. wsa884x->min_gain = G_12_DB;
  519. wsa884x->pa_aux_gain = PA_AUX_12_DB;
  520. break;
  521. default:
  522. wsa884x->comp_offset = COMP_OFFSET0;
  523. wsa884x->min_gain = G_0_DB;
  524. wsa884x->pa_aux_gain = PA_AUX_0_DB;
  525. break;
  526. }
  527. igain = isense_gain_data[wsa884x->system_gain][wsa884x->rload];
  528. vgain = vsense_gain_data[wsa884x->system_gain];
  529. snd_soc_component_update_bits(component,
  530. REG_FIELD_VALUE(ISENSE2, ISENSE_GAIN_CTL, igain));
  531. snd_soc_component_update_bits(component,
  532. REG_FIELD_VALUE(VSENSE1, GAIN_VSENSE_FE, vgain));
  533. snd_soc_component_update_bits(component,
  534. REG_FIELD_VALUE(GAIN_RAMPING_MIN, MIN_GAIN, wsa884x->min_gain));
  535. if (wsa884x->comp_enable) {
  536. snd_soc_component_update_bits(component,
  537. REG_FIELD_VALUE(DRE_CTL_0, OFFSET,
  538. wsa884x->comp_offset));
  539. snd_soc_component_update_bits(component,
  540. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x00));
  541. } else {
  542. wsa884x->pa_aux_gain = pa_aux_no_comp[wsa884x->pa_gain];
  543. snd_soc_component_update_bits(component,
  544. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  545. snd_soc_component_update_bits(component,
  546. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN, wsa884x->pa_gain));
  547. }
  548. return 0;
  549. }
  550. static int wsa884x_set_pbr_parameters(struct snd_soc_component *component)
  551. {
  552. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  553. int vth1_reg_val;
  554. int vth2_reg_val;
  555. int vth3_reg_val;
  556. int vth4_reg_val;
  557. int vth5_reg_val;
  558. int vth6_reg_val;
  559. int vth7_reg_val;
  560. int vth8_reg_val;
  561. int vth9_reg_val;
  562. int vth10_reg_val;
  563. int vth11_reg_val;
  564. int vth12_reg_val;
  565. int vth13_reg_val;
  566. int vth14_reg_val;
  567. int vth15_reg_val;
  568. int vth1_val = pbr_vth1_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  569. int vth2_val = pbr_vth2_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  570. int vth3_val = pbr_vth3_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  571. int vth4_val = pbr_vth4_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  572. int vth5_val = pbr_vth5_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  573. int vth6_val = pbr_vth6_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  574. int vth7_val = pbr_vth7_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  575. int vth8_val = pbr_vth8_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  576. int vth9_val = pbr_vth9_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  577. int vth10_val = pbr_vth10_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  578. int vth11_val = pbr_vth11_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  579. int vth12_val = pbr_vth12_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  580. int vth13_val = pbr_vth13_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  581. int vth14_val = pbr_vth14_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  582. int vth15_val = pbr_vth15_data[wsa884x->system_gain][wsa884x->bat_cfg][wsa884x->rload];
  583. vth1_reg_val = WSA884X_VTH_TO_REG(vth1_val);
  584. vth2_reg_val = WSA884X_VTH_TO_REG(vth2_val);
  585. vth3_reg_val = WSA884X_VTH_TO_REG(vth3_val);
  586. vth4_reg_val = WSA884X_VTH_TO_REG(vth4_val);
  587. vth5_reg_val = WSA884X_VTH_TO_REG(vth5_val);
  588. vth6_reg_val = WSA884X_VTH_TO_REG(vth6_val);
  589. vth7_reg_val = WSA884X_VTH_TO_REG(vth7_val);
  590. vth8_reg_val = WSA884X_VTH_TO_REG(vth8_val);
  591. vth9_reg_val = WSA884X_VTH_TO_REG(vth9_val);
  592. vth10_reg_val = WSA884X_VTH_TO_REG(vth10_val);
  593. vth11_reg_val = WSA884X_VTH_TO_REG(vth11_val);
  594. vth12_reg_val = WSA884X_VTH_TO_REG(vth12_val);
  595. vth13_reg_val = WSA884X_VTH_TO_REG(vth13_val);
  596. vth14_reg_val = WSA884X_VTH_TO_REG(vth14_val);
  597. vth15_reg_val = WSA884X_VTH_TO_REG(vth15_val);
  598. snd_soc_component_write(component, WSA884X_CLSH_VTH1, vth1_reg_val);
  599. snd_soc_component_write(component, WSA884X_CLSH_VTH2, vth2_reg_val);
  600. snd_soc_component_write(component, WSA884X_CLSH_VTH3, vth3_reg_val);
  601. snd_soc_component_write(component, WSA884X_CLSH_VTH4, vth4_reg_val);
  602. snd_soc_component_write(component, WSA884X_CLSH_VTH5, vth5_reg_val);
  603. snd_soc_component_write(component, WSA884X_CLSH_VTH6, vth6_reg_val);
  604. snd_soc_component_write(component, WSA884X_CLSH_VTH7, vth7_reg_val);
  605. snd_soc_component_write(component, WSA884X_CLSH_VTH8, vth8_reg_val);
  606. snd_soc_component_write(component, WSA884X_CLSH_VTH9, vth9_reg_val);
  607. snd_soc_component_write(component, WSA884X_CLSH_VTH10, vth10_reg_val);
  608. snd_soc_component_write(component, WSA884X_CLSH_VTH11, vth11_reg_val);
  609. snd_soc_component_write(component, WSA884X_CLSH_VTH12, vth12_reg_val);
  610. snd_soc_component_write(component, WSA884X_CLSH_VTH13, vth13_reg_val);
  611. snd_soc_component_write(component, WSA884X_CLSH_VTH14, vth14_reg_val);
  612. snd_soc_component_write(component, WSA884X_CLSH_VTH15, vth15_reg_val);
  613. return 0;
  614. }
  615. static void wsa_noise_gate_write(struct snd_soc_component *component,
  616. int imode)
  617. {
  618. switch (imode) {
  619. case NG1:
  620. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  621. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x30);
  622. break;
  623. case NG2:
  624. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  625. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x28);
  626. break;
  627. case NG3:
  628. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  629. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x18);
  630. break;
  631. default:
  632. snd_soc_component_update_bits(component, WSA884X_PA_FSM_CTL1,
  633. WSA884X_IDLE_DETECT_NG_BLOCK_MASK, 0x8);
  634. break;
  635. }
  636. }
  637. static const char * const wsa_dev_mode_text[] = {
  638. "speaker", "receiver"
  639. };
  640. static const struct soc_enum wsa_dev_mode_enum =
  641. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_dev_mode_text), wsa_dev_mode_text);
  642. static int wsa_dev_mode_get(struct snd_kcontrol *kcontrol,
  643. struct snd_ctl_elem_value *ucontrol)
  644. {
  645. struct snd_soc_component *component =
  646. snd_soc_kcontrol_component(kcontrol);
  647. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  648. ucontrol->value.integer.value[0] = wsa884x->dev_mode;
  649. dev_dbg(component->dev, "%s: mode = 0x%x\n", __func__,
  650. wsa884x->dev_mode);
  651. return 0;
  652. }
  653. static int wsa_dev_mode_put(struct snd_kcontrol *kcontrol,
  654. struct snd_ctl_elem_value *ucontrol)
  655. {
  656. struct snd_soc_component *component =
  657. snd_soc_kcontrol_component(kcontrol);
  658. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  659. int dev_mode;
  660. dev_mode = ucontrol->value.integer.value[0];
  661. dev_dbg(component->dev, "%s: Dev Mode current: %d, new: %d = %ld\n",
  662. __func__, wsa884x->dev_mode, dev_mode);
  663. /* Check if input parameter is in range */
  664. if ((wsa884x->dev_mode + (wsa884x->dev_index - 1) * 2) <
  665. (MAX_DEV_MODE * 2)) {
  666. wsa884x->dev_mode = dev_mode;
  667. wsa884x->system_gain = wsa884x->sys_gains[
  668. wsa884x->dev_mode + (wsa884x->dev_index - 1) * 2];
  669. } else {
  670. return -EINVAL;
  671. }
  672. return 0;
  673. }
  674. static const char * const wsa_pa_gain_text[] = {
  675. "G_21_DB", "G_19P5_DB" "G_18_DB", "G_16P5_DB", "G_15_DB", "G_13P5_DB",
  676. "G_12_DB", "G_10P5_DB", "G_9_DB", "G_7P5_DB", "G_6_DB", "G_4P5_DB",
  677. "G_3_DB", "G_1P5_DB", "G_0_DB", "G_M1P5_DB", "G_M3_DB", "G_M4P5_DB"
  678. "G_M6_DB", "G_M7P5_DB", "G_M9_DB"
  679. };
  680. static const struct soc_enum wsa_pa_gain_enum =
  681. SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(wsa_pa_gain_text), wsa_pa_gain_text);
  682. static int wsa_pa_gain_get(struct snd_kcontrol *kcontrol,
  683. struct snd_ctl_elem_value *ucontrol)
  684. {
  685. struct snd_soc_component *component =
  686. snd_soc_kcontrol_component(kcontrol);
  687. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  688. ucontrol->value.integer.value[0] = wsa884x->pa_gain;
  689. dev_dbg(component->dev, "%s: PA gain = 0x%x\n", __func__,
  690. wsa884x->pa_gain);
  691. return 0;
  692. }
  693. static int wsa_pa_gain_put(struct snd_kcontrol *kcontrol,
  694. struct snd_ctl_elem_value *ucontrol)
  695. {
  696. struct snd_soc_component *component =
  697. snd_soc_kcontrol_component(kcontrol);
  698. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  699. dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
  700. __func__, ucontrol->value.integer.value[0]);
  701. wsa884x->pa_gain = ucontrol->value.integer.value[0];
  702. return 0;
  703. }
  704. static int wsa_get_temp(struct snd_kcontrol *kcontrol,
  705. struct snd_ctl_elem_value *ucontrol)
  706. {
  707. struct snd_soc_component *component =
  708. snd_soc_kcontrol_component(kcontrol);
  709. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  710. int temp = 0;
  711. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  712. temp = wsa884x->curr_temp;
  713. else
  714. wsa884x_get_temperature(component, &temp);
  715. ucontrol->value.integer.value[0] = temp;
  716. return 0;
  717. }
  718. static ssize_t wsa884x_codec_version_read(struct snd_info_entry *entry,
  719. void *file_private_data, struct file *file,
  720. char __user *buf, size_t count, loff_t pos)
  721. {
  722. struct wsa884x_priv *wsa884x;
  723. char buffer[WSA884X_VERSION_ENTRY_SIZE];
  724. int len = 0;
  725. wsa884x = (struct wsa884x_priv *) entry->private_data;
  726. if (!wsa884x) {
  727. pr_err("%s: wsa884x priv is null\n", __func__);
  728. return -EINVAL;
  729. }
  730. switch (wsa884x->version) {
  731. case WSA884X_VERSION_1_0:
  732. len = snprintf(buffer, sizeof(buffer), "WSA884X_1_0\n");
  733. break;
  734. default:
  735. len = snprintf(buffer, sizeof(buffer), "VER_UNDEFINED\n");
  736. break;
  737. }
  738. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  739. }
  740. static struct snd_info_entry_ops wsa884x_codec_info_ops = {
  741. .read = wsa884x_codec_version_read,
  742. };
  743. static ssize_t wsa884x_variant_read(struct snd_info_entry *entry,
  744. void *file_private_data,
  745. struct file *file,
  746. char __user *buf, size_t count,
  747. loff_t pos)
  748. {
  749. struct wsa884x_priv *wsa884x;
  750. char buffer[WSA884X_VARIANT_ENTRY_SIZE];
  751. int len = 0;
  752. wsa884x = (struct wsa884x_priv *) entry->private_data;
  753. if (!wsa884x) {
  754. pr_err("%s: wsa884x priv is null\n", __func__);
  755. return -EINVAL;
  756. }
  757. switch (wsa884x->variant) {
  758. case WSA8840:
  759. len = snprintf(buffer, sizeof(buffer), "WSA8840\n");
  760. break;
  761. case WSA8845:
  762. len = snprintf(buffer, sizeof(buffer), "WSA8845\n");
  763. break;
  764. case WSA8845H:
  765. len = snprintf(buffer, sizeof(buffer), "WSA8845H\n");
  766. break;
  767. default:
  768. len = snprintf(buffer, sizeof(buffer), "UNDEFINED\n");
  769. break;
  770. }
  771. return simple_read_from_buffer(buf, count, &pos, buffer, len);
  772. }
  773. static struct snd_info_entry_ops wsa884x_variant_ops = {
  774. .read = wsa884x_variant_read,
  775. };
  776. /*
  777. * wsa884x_codec_info_create_codec_entry - creates wsa884x module
  778. * @codec_root: The parent directory
  779. * @component: Codec instance
  780. *
  781. * Creates wsa884x module and version entry under the given
  782. * parent directory.
  783. *
  784. * Return: 0 on success or negative error code on failure.
  785. */
  786. int wsa884x_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
  787. struct snd_soc_component *component)
  788. {
  789. struct snd_info_entry *version_entry;
  790. struct snd_info_entry *variant_entry;
  791. struct wsa884x_priv *wsa884x;
  792. struct snd_soc_card *card;
  793. char name[80];
  794. if (!codec_root || !component)
  795. return -EINVAL;
  796. wsa884x = snd_soc_component_get_drvdata(component);
  797. if (wsa884x->entry) {
  798. dev_dbg(wsa884x->dev,
  799. "%s:wsa884x module already created\n", __func__);
  800. return 0;
  801. }
  802. card = component->card;
  803. snprintf(name, sizeof(name), "%s.%llx", "wsa884x",
  804. wsa884x->swr_slave->addr);
  805. wsa884x->entry = snd_info_create_module_entry(codec_root->module,
  806. (const char *)name,
  807. codec_root);
  808. if (!wsa884x->entry) {
  809. dev_dbg(component->dev, "%s: failed to create wsa884x entry\n",
  810. __func__);
  811. return -ENOMEM;
  812. }
  813. wsa884x->entry->mode = S_IFDIR | 0555;
  814. if (snd_info_register(wsa884x->entry) < 0) {
  815. snd_info_free_entry(wsa884x->entry);
  816. return -ENOMEM;
  817. }
  818. version_entry = snd_info_create_card_entry(card->snd_card,
  819. "version",
  820. wsa884x->entry);
  821. if (!version_entry) {
  822. dev_dbg(component->dev, "%s: failed to create wsa884x version entry\n",
  823. __func__);
  824. snd_info_free_entry(wsa884x->entry);
  825. return -ENOMEM;
  826. }
  827. version_entry->private_data = wsa884x;
  828. version_entry->size = WSA884X_VERSION_ENTRY_SIZE;
  829. version_entry->content = SNDRV_INFO_CONTENT_DATA;
  830. version_entry->c.ops = &wsa884x_codec_info_ops;
  831. if (snd_info_register(version_entry) < 0) {
  832. snd_info_free_entry(version_entry);
  833. snd_info_free_entry(wsa884x->entry);
  834. return -ENOMEM;
  835. }
  836. wsa884x->version_entry = version_entry;
  837. variant_entry = snd_info_create_card_entry(card->snd_card,
  838. "variant",
  839. wsa884x->entry);
  840. if (!variant_entry) {
  841. dev_dbg(component->dev,
  842. "%s: failed to create wsa884x variant entry\n",
  843. __func__);
  844. snd_info_free_entry(version_entry);
  845. snd_info_free_entry(wsa884x->entry);
  846. return -ENOMEM;
  847. }
  848. variant_entry->private_data = wsa884x;
  849. variant_entry->size = WSA884X_VARIANT_ENTRY_SIZE;
  850. variant_entry->content = SNDRV_INFO_CONTENT_DATA;
  851. variant_entry->c.ops = &wsa884x_variant_ops;
  852. if (snd_info_register(variant_entry) < 0) {
  853. snd_info_free_entry(variant_entry);
  854. snd_info_free_entry(version_entry);
  855. snd_info_free_entry(wsa884x->entry);
  856. return -ENOMEM;
  857. }
  858. wsa884x->variant_entry = variant_entry;
  859. return 0;
  860. }
  861. EXPORT_SYMBOL(wsa884x_codec_info_create_codec_entry);
  862. /*
  863. * wsa884x_codec_get_dev_num - returns swr device number
  864. * @component: Codec instance
  865. *
  866. * Return: swr device number on success or negative error
  867. * code on failure.
  868. */
  869. int wsa884x_codec_get_dev_num(struct snd_soc_component *component)
  870. {
  871. struct wsa884x_priv *wsa884x;
  872. if (!component)
  873. return -EINVAL;
  874. wsa884x = snd_soc_component_get_drvdata(component);
  875. if (!wsa884x) {
  876. pr_err("%s: wsa884x component is NULL\n", __func__);
  877. return -EINVAL;
  878. }
  879. return wsa884x->swr_slave->dev_num;
  880. }
  881. EXPORT_SYMBOL(wsa884x_codec_get_dev_num);
  882. static int wsa884x_get_dev_num(struct snd_kcontrol *kcontrol,
  883. struct snd_ctl_elem_value *ucontrol)
  884. {
  885. struct snd_soc_component *component =
  886. snd_soc_kcontrol_component(kcontrol);
  887. struct wsa884x_priv *wsa884x;
  888. if (!component)
  889. return -EINVAL;
  890. wsa884x = snd_soc_component_get_drvdata(component);
  891. if (!wsa884x) {
  892. pr_err("%s: wsa884x component is NULL\n", __func__);
  893. return -EINVAL;
  894. }
  895. ucontrol->value.integer.value[0] = wsa884x->swr_slave->dev_num;
  896. return 0;
  897. }
  898. static int wsa884x_get_compander(struct snd_kcontrol *kcontrol,
  899. struct snd_ctl_elem_value *ucontrol)
  900. {
  901. struct snd_soc_component *component =
  902. snd_soc_kcontrol_component(kcontrol);
  903. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  904. ucontrol->value.integer.value[0] = wsa884x->comp_enable;
  905. return 0;
  906. }
  907. /*
  908. * wsa884x_validate_dt_configuration_params - returns 1 or 0
  909. * Return: 0 Valid configuration, 1 Invalid configuration
  910. */
  911. static bool wsa884x_validate_dt_configuration_params(u8 irload, u8 ibat_cfg,
  912. u8 isystem_gain)
  913. {
  914. bool is_invalid_flag = true;
  915. if ((WSA_4_OHMS <= irload && irload < WSA_MAX_OHMS) &&
  916. (G_21_DB <= isystem_gain && isystem_gain < G_MAX_DB) &&
  917. (EXT_ABOVE_3S <= ibat_cfg && ibat_cfg < CONFIG_MAX))
  918. is_invalid_flag = false;
  919. return is_invalid_flag;
  920. }
  921. static int wsa884x_set_compander(struct snd_kcontrol *kcontrol,
  922. struct snd_ctl_elem_value *ucontrol)
  923. {
  924. struct snd_soc_component *component =
  925. snd_soc_kcontrol_component(kcontrol);
  926. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  927. int value = ucontrol->value.integer.value[0];
  928. dev_dbg(component->dev, "%s: Compander enable current %d, new %d\n",
  929. __func__, wsa884x->comp_enable, value);
  930. wsa884x->comp_enable = value;
  931. return 0;
  932. }
  933. static int wsa884x_get_visense(struct snd_kcontrol *kcontrol,
  934. struct snd_ctl_elem_value *ucontrol)
  935. {
  936. struct snd_soc_component *component =
  937. snd_soc_kcontrol_component(kcontrol);
  938. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  939. ucontrol->value.integer.value[0] = wsa884x->visense_enable;
  940. return 0;
  941. }
  942. static int wsa884x_set_visense(struct snd_kcontrol *kcontrol,
  943. struct snd_ctl_elem_value *ucontrol)
  944. {
  945. struct snd_soc_component *component =
  946. snd_soc_kcontrol_component(kcontrol);
  947. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  948. int value = ucontrol->value.integer.value[0];
  949. dev_dbg(component->dev, "%s: VIsense enable current %d, new %d\n",
  950. __func__, wsa884x->visense_enable, value);
  951. wsa884x->visense_enable = value;
  952. return 0;
  953. }
  954. static int wsa884x_get_pbr(struct snd_kcontrol *kcontrol,
  955. struct snd_ctl_elem_value *ucontrol)
  956. {
  957. struct snd_soc_component *component =
  958. snd_soc_kcontrol_component(kcontrol);
  959. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  960. ucontrol->value.integer.value[0] = wsa884x->pbr_enable;
  961. return 0;
  962. }
  963. static int wsa884x_set_pbr(struct snd_kcontrol *kcontrol,
  964. struct snd_ctl_elem_value *ucontrol)
  965. {
  966. struct snd_soc_component *component =
  967. snd_soc_kcontrol_component(kcontrol);
  968. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  969. int value = ucontrol->value.integer.value[0];
  970. dev_dbg(component->dev, "%s: PBR enable current %d, new %d\n",
  971. __func__, wsa884x->pbr_enable, value);
  972. wsa884x->pbr_enable = value;
  973. return 0;
  974. }
  975. static int wsa884x_get_cps(struct snd_kcontrol *kcontrol,
  976. struct snd_ctl_elem_value *ucontrol)
  977. {
  978. struct snd_soc_component *component =
  979. snd_soc_kcontrol_component(kcontrol);
  980. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  981. ucontrol->value.integer.value[0] = wsa884x->cps_enable;
  982. return 0;
  983. }
  984. static int wsa884x_set_cps(struct snd_kcontrol *kcontrol,
  985. struct snd_ctl_elem_value *ucontrol)
  986. {
  987. struct snd_soc_component *component =
  988. snd_soc_kcontrol_component(kcontrol);
  989. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  990. int value = ucontrol->value.integer.value[0];
  991. dev_dbg(component->dev, "%s: CPS enable current %d, new %d\n",
  992. __func__, wsa884x->cps_enable, value);
  993. wsa884x->cps_enable = value;
  994. return 0;
  995. }
  996. static const struct snd_kcontrol_new wsa884x_snd_controls[] = {
  997. SOC_ENUM_EXT("WSA PA Gain", wsa_pa_gain_enum,
  998. wsa_pa_gain_get, wsa_pa_gain_put),
  999. SOC_SINGLE_EXT("WSA Temp", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1000. wsa_get_temp, NULL),
  1001. SOC_SINGLE_EXT("WSA Get DevNum", SND_SOC_NOPM, 0, UINT_MAX, 0,
  1002. wsa884x_get_dev_num, NULL),
  1003. SOC_ENUM_EXT("WSA MODE", wsa_dev_mode_enum,
  1004. wsa_dev_mode_get, wsa_dev_mode_put),
  1005. SOC_SINGLE_EXT("COMP Switch", SND_SOC_NOPM, 0, 1, 0,
  1006. wsa884x_get_compander, wsa884x_set_compander),
  1007. SOC_SINGLE_EXT("VISENSE Switch", SND_SOC_NOPM, 0, 1, 0,
  1008. wsa884x_get_visense, wsa884x_set_visense),
  1009. SOC_SINGLE_EXT("PBR Switch", SND_SOC_NOPM, 0, 1, 0,
  1010. wsa884x_get_pbr, wsa884x_set_pbr),
  1011. SOC_SINGLE_EXT("CPS Switch", SND_SOC_NOPM, 0, 1, 0,
  1012. wsa884x_get_cps, wsa884x_set_cps),
  1013. };
  1014. static const struct snd_kcontrol_new swr_dac_port[] = {
  1015. SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
  1016. };
  1017. static int wsa884x_set_port(struct snd_soc_component *component, int port_idx,
  1018. u8 *port_id, u8 *num_ch, u8 *ch_mask, u32 *ch_rate,
  1019. u8 *port_type)
  1020. {
  1021. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1022. *port_id = wsa884x->port[port_idx].port_id;
  1023. *num_ch = wsa884x->port[port_idx].num_ch;
  1024. *ch_mask = wsa884x->port[port_idx].ch_mask;
  1025. *ch_rate = wsa884x->port[port_idx].ch_rate;
  1026. *port_type = wsa884x->port[port_idx].port_type;
  1027. return 0;
  1028. }
  1029. static int wsa884x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
  1030. struct snd_kcontrol *kcontrol, int event)
  1031. {
  1032. struct snd_soc_component *component =
  1033. snd_soc_dapm_to_component(w->dapm);
  1034. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1035. u8 port_id[WSA884X_MAX_SWR_PORTS];
  1036. u8 num_ch[WSA884X_MAX_SWR_PORTS];
  1037. u8 ch_mask[WSA884X_MAX_SWR_PORTS];
  1038. u32 ch_rate[WSA884X_MAX_SWR_PORTS];
  1039. u8 port_type[WSA884X_MAX_SWR_PORTS];
  1040. u8 num_port = 0;
  1041. dev_dbg(component->dev, "%s: event %d name %s\n", __func__,
  1042. event, w->name);
  1043. if (wsa884x == NULL)
  1044. return -EINVAL;
  1045. switch (event) {
  1046. case SND_SOC_DAPM_PRE_PMU:
  1047. wsa884x_set_port(component, SWR_DAC_PORT,
  1048. &port_id[num_port], &num_ch[num_port],
  1049. &ch_mask[num_port], &ch_rate[num_port],
  1050. &port_type[num_port]);
  1051. if (wsa884x->dev_mode == RECEIVER)
  1052. ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
  1053. ++num_port;
  1054. if (wsa884x->comp_enable) {
  1055. wsa884x_set_port(component, SWR_COMP_PORT,
  1056. &port_id[num_port], &num_ch[num_port],
  1057. &ch_mask[num_port], &ch_rate[num_port],
  1058. &port_type[num_port]);
  1059. ++num_port;
  1060. }
  1061. if (wsa884x->pbr_enable) {
  1062. wsa884x_set_port(component, SWR_PBR_PORT,
  1063. &port_id[num_port], &num_ch[num_port],
  1064. &ch_mask[num_port], &ch_rate[num_port],
  1065. &port_type[num_port]);
  1066. ++num_port;
  1067. }
  1068. if (wsa884x->visense_enable) {
  1069. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1070. &port_id[num_port], &num_ch[num_port],
  1071. &ch_mask[num_port], &ch_rate[num_port],
  1072. &port_type[num_port]);
  1073. ++num_port;
  1074. }
  1075. if (wsa884x->cps_enable) {
  1076. wsa884x_set_port(component, SWR_CPS_PORT,
  1077. &port_id[num_port], &num_ch[num_port],
  1078. &ch_mask[num_port], &ch_rate[num_port],
  1079. &port_type[num_port]);
  1080. ++num_port;
  1081. }
  1082. swr_connect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1083. &ch_mask[0], &ch_rate[0], &num_ch[0],
  1084. &port_type[0]);
  1085. break;
  1086. case SND_SOC_DAPM_POST_PMU:
  1087. set_bit(SPKR_STATUS, &wsa884x->status_mask);
  1088. break;
  1089. case SND_SOC_DAPM_PRE_PMD:
  1090. wsa884x_set_port(component, SWR_DAC_PORT,
  1091. &port_id[num_port], &num_ch[num_port],
  1092. &ch_mask[num_port], &ch_rate[num_port],
  1093. &port_type[num_port]);
  1094. ++num_port;
  1095. if (wsa884x->comp_enable) {
  1096. wsa884x_set_port(component, SWR_COMP_PORT,
  1097. &port_id[num_port], &num_ch[num_port],
  1098. &ch_mask[num_port], &ch_rate[num_port],
  1099. &port_type[num_port]);
  1100. ++num_port;
  1101. }
  1102. if (wsa884x->pbr_enable) {
  1103. wsa884x_set_port(component, SWR_PBR_PORT,
  1104. &port_id[num_port], &num_ch[num_port],
  1105. &ch_mask[num_port], &ch_rate[num_port],
  1106. &port_type[num_port]);
  1107. ++num_port;
  1108. }
  1109. if (wsa884x->visense_enable) {
  1110. wsa884x_set_port(component, SWR_VISENSE_PORT,
  1111. &port_id[num_port], &num_ch[num_port],
  1112. &ch_mask[num_port], &ch_rate[num_port],
  1113. &port_type[num_port]);
  1114. ++num_port;
  1115. }
  1116. if (wsa884x->cps_enable) {
  1117. wsa884x_set_port(component, SWR_CPS_PORT,
  1118. &port_id[num_port], &num_ch[num_port],
  1119. &ch_mask[num_port], &ch_rate[num_port],
  1120. &port_type[num_port]);
  1121. ++num_port;
  1122. }
  1123. swr_disconnect_port(wsa884x->swr_slave, &port_id[0], num_port,
  1124. &ch_mask[0], &port_type[0]);
  1125. break;
  1126. case SND_SOC_DAPM_POST_PMD:
  1127. if (swr_set_device_group(wsa884x->swr_slave, SWR_GROUP_NONE))
  1128. dev_err(component->dev,
  1129. "%s: set num ch failed\n", __func__);
  1130. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1131. wsa884x->swr_slave->dev_num,
  1132. false);
  1133. break;
  1134. default:
  1135. break;
  1136. }
  1137. return 0;
  1138. }
  1139. static int wsa884x_spkr_event(struct snd_soc_dapm_widget *w,
  1140. struct snd_kcontrol *kcontrol, int event)
  1141. {
  1142. struct snd_soc_component *component =
  1143. snd_soc_dapm_to_component(w->dapm);
  1144. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1145. dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
  1146. switch (event) {
  1147. case SND_SOC_DAPM_POST_PMU:
  1148. swr_slvdev_datapath_control(wsa884x->swr_slave,
  1149. wsa884x->swr_slave->dev_num,
  1150. true);
  1151. wsa884x_set_gain_parameters(component);
  1152. if (wsa884x->dev_mode == SPEAKER) {
  1153. snd_soc_component_update_bits(component,
  1154. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1155. } else {
  1156. snd_soc_component_update_bits(component,
  1157. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1158. snd_soc_component_update_bits(component,
  1159. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1160. snd_soc_component_update_bits(component,
  1161. REG_FIELD_VALUE(PWM_CLK_CTL,
  1162. PWM_CLK_FREQ_SEL, 0x01));
  1163. }
  1164. if (wsa884x->pbr_enable) {
  1165. snd_soc_component_update_bits(component,
  1166. REG_FIELD_VALUE(CURRENT_LIMIT,
  1167. CURRENT_LIMIT_OVRD_EN, 0x00));
  1168. switch (wsa884x->bat_cfg) {
  1169. case CONFIG_1S:
  1170. snd_soc_component_update_bits(component,
  1171. REG_FIELD_VALUE(CURRENT_LIMIT,
  1172. CURRENT_LIMIT, 0x15));
  1173. break;
  1174. case CONFIG_2S:
  1175. snd_soc_component_update_bits(component,
  1176. REG_FIELD_VALUE(CURRENT_LIMIT,
  1177. CURRENT_LIMIT, 0x11));
  1178. break;
  1179. case CONFIG_3S:
  1180. snd_soc_component_update_bits(component,
  1181. REG_FIELD_VALUE(CURRENT_LIMIT,
  1182. CURRENT_LIMIT, 0x0D));
  1183. break;
  1184. }
  1185. } else {
  1186. snd_soc_component_update_bits(component,
  1187. REG_FIELD_VALUE(CURRENT_LIMIT,
  1188. CURRENT_LIMIT_OVRD_EN, 0x01));
  1189. if (wsa884x->system_gain >= G_12_DB)
  1190. snd_soc_component_update_bits(component,
  1191. REG_FIELD_VALUE(CURRENT_LIMIT,
  1192. CURRENT_LIMIT, 0x15));
  1193. else
  1194. snd_soc_component_update_bits(component,
  1195. REG_FIELD_VALUE(CURRENT_LIMIT,
  1196. CURRENT_LIMIT, 0x09));
  1197. }
  1198. /* Force remove group */
  1199. swr_remove_from_group(wsa884x->swr_slave,
  1200. wsa884x->swr_slave->dev_num);
  1201. if (test_bit(SPKR_ADIE_LB, &wsa884x->status_mask))
  1202. snd_soc_component_update_bits(component,
  1203. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1204. break;
  1205. case SND_SOC_DAPM_PRE_PMD:
  1206. snd_soc_component_update_bits(component,
  1207. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1208. snd_soc_component_update_bits(component,
  1209. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x00));
  1210. clear_bit(SPKR_STATUS, &wsa884x->status_mask);
  1211. clear_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1212. break;
  1213. }
  1214. return 0;
  1215. }
  1216. static const struct snd_soc_dapm_widget wsa884x_dapm_widgets[] = {
  1217. SND_SOC_DAPM_INPUT("IN"),
  1218. SND_SOC_DAPM_MIXER_E("SWR DAC_Port", SND_SOC_NOPM, 0, 0, swr_dac_port,
  1219. ARRAY_SIZE(swr_dac_port), wsa884x_enable_swr_dac_port,
  1220. SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
  1221. SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
  1222. SND_SOC_DAPM_SPK("SPKR", wsa884x_spkr_event),
  1223. };
  1224. static const struct snd_soc_dapm_route wsa884x_audio_map[] = {
  1225. {"SWR DAC_Port", "Switch", "IN"},
  1226. {"SPKR", NULL, "SWR DAC_Port"},
  1227. };
  1228. int wsa884x_set_channel_map(struct snd_soc_component *component, u8 *port,
  1229. u8 num_port, unsigned int *ch_mask,
  1230. unsigned int *ch_rate, u8 *port_type)
  1231. {
  1232. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1233. int i;
  1234. if (!port || !ch_mask || !ch_rate ||
  1235. (num_port > WSA884X_MAX_SWR_PORTS)) {
  1236. dev_err(component->dev,
  1237. "%s: Invalid port=%pK, ch_mask=%pK, ch_rate=%pK\n",
  1238. __func__, port, ch_mask, ch_rate);
  1239. return -EINVAL;
  1240. }
  1241. for (i = 0; i < num_port; i++) {
  1242. wsa884x->port[i].port_id = port[i];
  1243. wsa884x->port[i].ch_mask = ch_mask[i];
  1244. wsa884x->port[i].ch_rate = ch_rate[i];
  1245. wsa884x->port[i].num_ch = __sw_hweight8(ch_mask[i]);
  1246. if (port_type)
  1247. wsa884x->port[i].port_type = port_type[i];
  1248. }
  1249. return 0;
  1250. }
  1251. EXPORT_SYMBOL(wsa884x_set_channel_map);
  1252. static void wsa884x_codec_init(struct snd_soc_component *component)
  1253. {
  1254. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1255. int i;
  1256. if (!wsa884x)
  1257. return;
  1258. for (i = 0; i < ARRAY_SIZE(reg_init); i++)
  1259. snd_soc_component_update_bits(component, reg_init[i].reg,
  1260. reg_init[i].mask, reg_init[i].val);
  1261. if (wsa884x->variant == WSA8845H)
  1262. snd_soc_component_update_bits(wsa884x->component,
  1263. REG_FIELD_VALUE(DRE_CTL_1, CSR_GAIN_EN, 0x01));
  1264. wsa_noise_gate_write(component, wsa884x->noise_gate_mode);
  1265. }
  1266. static int32_t wsa884x_temp_reg_read(struct snd_soc_component *component,
  1267. struct wsa_temp_register *wsa_temp_reg)
  1268. {
  1269. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1270. if (!wsa884x) {
  1271. dev_err(component->dev, "%s: wsa884x is NULL\n", __func__);
  1272. return -EINVAL;
  1273. }
  1274. mutex_lock(&wsa884x->res_lock);
  1275. snd_soc_component_update_bits(component,
  1276. REG_FIELD_VALUE(PA_FSM_BYP0, DC_CAL_EN, 0x01));
  1277. snd_soc_component_update_bits(component,
  1278. REG_FIELD_VALUE(PA_FSM_BYP0, BG_EN, 0x01));
  1279. snd_soc_component_update_bits(component,
  1280. REG_FIELD_VALUE(PA_FSM_BYP0, CLK_WD_EN, 0x01));
  1281. snd_soc_component_update_bits(component,
  1282. REG_FIELD_VALUE(PA_FSM_BYP0, TSADC_EN, 0x01));
  1283. snd_soc_component_update_bits(component,
  1284. REG_FIELD_VALUE(PA_FSM_BYP0, D_UNMUTE, 0x01));
  1285. snd_soc_component_update_bits(component,
  1286. REG_FIELD_VALUE(PA_FSM_BYP0, SPKR_PROT_EN, 0x01));
  1287. snd_soc_component_update_bits(component,
  1288. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x00));
  1289. wsa_temp_reg->dmeas_msb = snd_soc_component_read(component,
  1290. WSA884X_TEMP_DIN_MSB);
  1291. wsa_temp_reg->dmeas_lsb = snd_soc_component_read(component,
  1292. WSA884X_TEMP_DIN_LSB);
  1293. snd_soc_component_update_bits(component,
  1294. REG_FIELD_VALUE(TADC_VALUE_CTL, TEMP_VALUE_RD_EN, 0x01));
  1295. wsa_temp_reg->d1_msb = snd_soc_component_read(component,
  1296. WSA884X_OTP_REG_1);
  1297. wsa_temp_reg->d1_lsb = snd_soc_component_read(component,
  1298. WSA884X_OTP_REG_2);
  1299. wsa_temp_reg->d2_msb = snd_soc_component_read(component,
  1300. WSA884X_OTP_REG_3);
  1301. wsa_temp_reg->d2_lsb = snd_soc_component_read(component,
  1302. WSA884X_OTP_REG_4);
  1303. snd_soc_component_update_bits(component,
  1304. WSA884X_PA_FSM_BYP0, 0xE7, 0x00);
  1305. mutex_unlock(&wsa884x->res_lock);
  1306. return 0;
  1307. }
  1308. static int wsa884x_get_temperature(struct snd_soc_component *component,
  1309. int *temp)
  1310. {
  1311. struct wsa_temp_register reg;
  1312. int dmeas, d1, d2;
  1313. int ret = 0;
  1314. int temp_val = 0;
  1315. int t1 = T1_TEMP;
  1316. int t2 = T2_TEMP;
  1317. u8 retry = WSA884X_TEMP_RETRY;
  1318. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1319. if (!wsa884x)
  1320. return -EINVAL;
  1321. do {
  1322. ret = wsa884x_temp_reg_read(component, &reg);
  1323. if (ret) {
  1324. pr_err("%s: temp read failed: %d, current temp: %d\n",
  1325. __func__, ret, wsa884x->curr_temp);
  1326. if (temp)
  1327. *temp = wsa884x->curr_temp;
  1328. return 0;
  1329. }
  1330. /*
  1331. * Temperature register values are expected to be in the
  1332. * following range.
  1333. * d1_msb = 68 - 92 and d1_lsb = 0, 64, 128, 192
  1334. * d2_msb = 185 -218 and d2_lsb = 0, 64, 128, 192
  1335. */
  1336. if ((reg.d1_msb < 68 || reg.d1_msb > 92) ||
  1337. (!(reg.d1_lsb == 0 || reg.d1_lsb == 64 || reg.d1_lsb == 128 ||
  1338. reg.d1_lsb == 192)) ||
  1339. (reg.d2_msb < 185 || reg.d2_msb > 218) ||
  1340. (!(reg.d2_lsb == 0 || reg.d2_lsb == 64 || reg.d2_lsb == 128 ||
  1341. reg.d2_lsb == 192))) {
  1342. printk_ratelimited("%s: Temperature registers[%d %d %d %d] are out of range\n",
  1343. __func__, reg.d1_msb, reg.d1_lsb, reg.d2_msb,
  1344. reg.d2_lsb);
  1345. }
  1346. dmeas = ((reg.dmeas_msb << 0x8) | reg.dmeas_lsb) >> 0x6;
  1347. d1 = ((reg.d1_msb << 0x8) | reg.d1_lsb) >> 0x6;
  1348. d2 = ((reg.d2_msb << 0x8) | reg.d2_lsb) >> 0x6;
  1349. if (d1 == d2)
  1350. temp_val = TEMP_INVALID;
  1351. else
  1352. temp_val = t1 + (((dmeas - d1) * (t2 - t1))/(d2 - d1));
  1353. if (temp_val <= LOW_TEMP_THRESHOLD ||
  1354. temp_val >= HIGH_TEMP_THRESHOLD) {
  1355. pr_debug("%s: T0: %d is out of range[%d, %d]\n", __func__,
  1356. temp_val, LOW_TEMP_THRESHOLD, HIGH_TEMP_THRESHOLD);
  1357. if (retry--)
  1358. msleep(10);
  1359. } else {
  1360. break;
  1361. }
  1362. } while (retry);
  1363. wsa884x->curr_temp = temp_val;
  1364. if (temp)
  1365. *temp = temp_val;
  1366. pr_debug("%s: t0 measured: %d dmeas = %d, d1 = %d, d2 = %d\n",
  1367. __func__, temp_val, dmeas, d1, d2);
  1368. return ret;
  1369. }
  1370. static int wsa884x_codec_probe(struct snd_soc_component *component)
  1371. {
  1372. char w_name[MAX_NAME_LEN];
  1373. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1374. struct swr_device *dev;
  1375. int variant = 0, version = 0;
  1376. struct snd_soc_dapm_context *dapm =
  1377. snd_soc_component_get_dapm(component);
  1378. if (!wsa884x)
  1379. return -EINVAL;
  1380. if (!component->name_prefix)
  1381. return -EINVAL;
  1382. snd_soc_component_init_regmap(component, wsa884x->regmap);
  1383. dev = wsa884x->swr_slave;
  1384. wsa884x->component = component;
  1385. variant = (snd_soc_component_read(component, WSA884X_OTP_REG_0)
  1386. & FIELD_MASK(OTP_REG_0, WSA884X_ID));
  1387. wsa884x->variant = variant;
  1388. version = (snd_soc_component_read(component, WSA884X_CHIP_ID0)
  1389. & FIELD_MASK(CHIP_ID0, BYTE_0));
  1390. wsa884x->version = version;
  1391. wsa884x->comp_offset = COMP_OFFSET2;
  1392. wsa884x_codec_init(component);
  1393. wsa884x->global_pa_cnt = 0;
  1394. memset(w_name, 0, sizeof(w_name));
  1395. strlcpy(w_name, wsa884x->dai_driver->playback.stream_name,
  1396. sizeof(w_name));
  1397. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1398. memset(w_name, 0, sizeof(w_name));
  1399. strlcpy(w_name, "IN", sizeof(w_name));
  1400. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1401. memset(w_name, 0, sizeof(w_name));
  1402. strlcpy(w_name, "SWR DAC_Port", sizeof(w_name));
  1403. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1404. memset(w_name, 0, sizeof(w_name));
  1405. strlcpy(w_name, "SPKR", sizeof(w_name));
  1406. snd_soc_dapm_ignore_suspend(dapm, w_name);
  1407. snd_soc_dapm_sync(dapm);
  1408. return 0;
  1409. }
  1410. static void wsa884x_codec_remove(struct snd_soc_component *component)
  1411. {
  1412. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1413. if (!wsa884x)
  1414. return;
  1415. snd_soc_component_exit_regmap(component);
  1416. return;
  1417. }
  1418. static int wsa884x_soc_codec_suspend(struct snd_soc_component *component)
  1419. {
  1420. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1421. if (!wsa884x)
  1422. return 0;
  1423. wsa884x->dapm_bias_off = true;
  1424. return 0;
  1425. }
  1426. static int wsa884x_soc_codec_resume(struct snd_soc_component *component)
  1427. {
  1428. struct wsa884x_priv *wsa884x = snd_soc_component_get_drvdata(component);
  1429. if (!wsa884x)
  1430. return 0;
  1431. wsa884x->dapm_bias_off = false;
  1432. return 0;
  1433. }
  1434. static const struct snd_soc_component_driver soc_codec_dev_wsa884x_wsa = {
  1435. .name = "",
  1436. .probe = wsa884x_codec_probe,
  1437. .remove = wsa884x_codec_remove,
  1438. .controls = wsa884x_snd_controls,
  1439. .num_controls = ARRAY_SIZE(wsa884x_snd_controls),
  1440. .dapm_widgets = wsa884x_dapm_widgets,
  1441. .num_dapm_widgets = ARRAY_SIZE(wsa884x_dapm_widgets),
  1442. .dapm_routes = wsa884x_audio_map,
  1443. .num_dapm_routes = ARRAY_SIZE(wsa884x_audio_map),
  1444. .suspend = wsa884x_soc_codec_suspend,
  1445. .resume = wsa884x_soc_codec_resume,
  1446. };
  1447. static int wsa884x_gpio_ctrl(struct wsa884x_priv *wsa884x, bool enable)
  1448. {
  1449. int ret = 0;
  1450. if (enable)
  1451. ret = msm_cdc_pinctrl_select_active_state(
  1452. wsa884x->wsa_rst_np);
  1453. else
  1454. ret = msm_cdc_pinctrl_select_sleep_state(
  1455. wsa884x->wsa_rst_np);
  1456. if (ret != 0)
  1457. dev_err(wsa884x->dev,
  1458. "%s: Failed to turn state %d; ret=%d\n",
  1459. __func__, enable, ret);
  1460. return ret;
  1461. }
  1462. static int wsa884x_swr_up(struct wsa884x_priv *wsa884x)
  1463. {
  1464. int ret;
  1465. ret = wsa884x_gpio_ctrl(wsa884x, true);
  1466. if (ret)
  1467. dev_err(wsa884x->dev, "%s: Failed to enable gpio\n", __func__);
  1468. return ret;
  1469. }
  1470. static int wsa884x_swr_down(struct wsa884x_priv *wsa884x)
  1471. {
  1472. int ret;
  1473. ret = wsa884x_gpio_ctrl(wsa884x, false);
  1474. if (ret)
  1475. dev_err(wsa884x->dev, "%s: Failed to disable gpio\n", __func__);
  1476. return ret;
  1477. }
  1478. static int wsa884x_swr_reset(struct wsa884x_priv *wsa884x)
  1479. {
  1480. u8 retry = WSA884X_NUM_RETRY;
  1481. u8 devnum = 0;
  1482. struct swr_device *pdev;
  1483. pdev = wsa884x->swr_slave;
  1484. while (swr_get_logical_dev_num(pdev, pdev->addr, &devnum) && retry--) {
  1485. /* Retry after 1 msec delay */
  1486. usleep_range(1000, 1100);
  1487. }
  1488. pdev->dev_num = devnum;
  1489. wsa884x_regcache_sync(wsa884x);
  1490. return 0;
  1491. }
  1492. static int wsa884x_event_notify(struct notifier_block *nb,
  1493. unsigned long val, void *ptr)
  1494. {
  1495. u16 event = (val & 0xffff);
  1496. struct wsa884x_priv *wsa884x = container_of(nb, struct wsa884x_priv,
  1497. parent_nblock);
  1498. if (!wsa884x)
  1499. return -EINVAL;
  1500. switch (event) {
  1501. case BOLERO_SLV_EVT_PA_OFF_PRE_SSR:
  1502. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1503. snd_soc_component_update_bits(wsa884x->component,
  1504. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x00));
  1505. wsa884x_swr_down(wsa884x);
  1506. break;
  1507. case BOLERO_SLV_EVT_SSR_UP:
  1508. wsa884x_swr_up(wsa884x);
  1509. /* Add delay to allow enumerate */
  1510. usleep_range(20000, 20010);
  1511. wsa884x_swr_reset(wsa884x);
  1512. break;
  1513. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK:
  1514. if (test_bit(SPKR_STATUS, &wsa884x->status_mask)) {
  1515. snd_soc_component_update_bits(wsa884x->component,
  1516. REG_FIELD_VALUE(PDM_WD_CTL, PDM_WD_EN, 0x01));
  1517. snd_soc_component_update_bits(wsa884x->component,
  1518. REG_FIELD_VALUE(PA_FSM_EN, GLOBAL_PA_EN, 0x01));
  1519. }
  1520. break;
  1521. case BOLERO_SLV_EVT_PA_ON_POST_FSCLK_ADIE_LB:
  1522. if (test_bit(SPKR_STATUS, &wsa884x->status_mask))
  1523. set_bit(SPKR_ADIE_LB, &wsa884x->status_mask);
  1524. break;
  1525. default:
  1526. dev_dbg(wsa884x->dev, "%s: unknown event %d\n",
  1527. __func__, event);
  1528. break;
  1529. }
  1530. return 0;
  1531. }
  1532. static int wsa884x_parse_port_params(struct device *dev, char *prop)
  1533. {
  1534. u32 *dt_array, map_size, max_uc;
  1535. int ret = 0;
  1536. u32 cnt = 0;
  1537. u32 i, j;
  1538. struct swr_port_params (*map)[SWR_UC_MAX][WSA884X_MAX_SWR_PORTS];
  1539. struct swr_dev_frame_config (*map_uc)[SWR_UC_MAX];
  1540. struct wsa884x_priv *wsa884x = dev_get_drvdata(dev);
  1541. map = &wsa884x->wsa_port_params;
  1542. map_uc = &wsa884x->swr_wsa_port_params;
  1543. if (!of_find_property(dev->of_node, prop,
  1544. &map_size)) {
  1545. dev_err(dev, "missing port mapping prop %s\n", prop);
  1546. ret = -EINVAL;
  1547. goto err_port_map;
  1548. }
  1549. max_uc = map_size / (WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * sizeof(u32));
  1550. if (max_uc != SWR_UC_MAX) {
  1551. dev_err(dev, "%s: port params not provided for all usecases\n",
  1552. __func__);
  1553. ret = -EINVAL;
  1554. goto err_port_map;
  1555. }
  1556. dt_array = kzalloc(map_size, GFP_KERNEL);
  1557. if (!dt_array) {
  1558. ret = -ENOMEM;
  1559. goto err_port_map;
  1560. }
  1561. ret = of_property_read_u32_array(dev->of_node, prop, dt_array,
  1562. WSA884X_MAX_SWR_PORTS * SWR_PORT_PARAMS * max_uc);
  1563. if (ret) {
  1564. dev_err(dev, "%s: Failed to read port mapping from prop %s\n",
  1565. __func__, prop);
  1566. goto err_pdata_fail;
  1567. }
  1568. for (i = 0; i < max_uc; i++) {
  1569. for (j = 0; j < WSA884X_MAX_SWR_PORTS; j++) {
  1570. cnt = (i * WSA884X_MAX_SWR_PORTS + j) * SWR_PORT_PARAMS;
  1571. (*map)[i][j].offset1 = dt_array[cnt];
  1572. (*map)[i][j].lane_ctrl = dt_array[cnt + 1];
  1573. }
  1574. (*map_uc)[i].pp = &(*map)[i][0];
  1575. }
  1576. kfree(dt_array);
  1577. return 0;
  1578. err_pdata_fail:
  1579. kfree(dt_array);
  1580. err_port_map:
  1581. return ret;
  1582. }
  1583. static int wsa884x_enable_supplies(struct device *dev,
  1584. struct wsa884x_priv *priv)
  1585. {
  1586. int ret = 0;
  1587. /* Parse power supplies */
  1588. msm_cdc_get_power_supplies(dev, &priv->regulator,
  1589. &priv->num_supplies);
  1590. if (!priv->regulator || (priv->num_supplies <= 0)) {
  1591. dev_err(dev, "%s: no power supplies defined\n", __func__);
  1592. return -EINVAL;
  1593. }
  1594. ret = msm_cdc_init_supplies(dev, &priv->supplies,
  1595. priv->regulator, priv->num_supplies);
  1596. if (!priv->supplies) {
  1597. dev_err(dev, "%s: Cannot init wsa supplies\n",
  1598. __func__);
  1599. return ret;
  1600. }
  1601. ret = msm_cdc_enable_static_supplies(dev, priv->supplies,
  1602. priv->regulator,
  1603. priv->num_supplies);
  1604. if (ret)
  1605. dev_err(dev, "%s: wsa static supply enable failed!\n",
  1606. __func__);
  1607. return ret;
  1608. }
  1609. static struct snd_soc_dai_driver wsa_dai[] = {
  1610. {
  1611. .name = "",
  1612. .playback = {
  1613. .stream_name = "",
  1614. .rates = WSA884X_RATES | WSA884X_FRAC_RATES,
  1615. .formats = WSA884X_FORMATS,
  1616. .rate_max = 192000,
  1617. .rate_min = 8000,
  1618. .channels_min = 1,
  1619. .channels_max = 2,
  1620. },
  1621. },
  1622. };
  1623. static int wsa884x_swr_probe(struct swr_device *pdev)
  1624. {
  1625. int ret = 0;
  1626. struct wsa884x_priv *wsa884x;
  1627. u8 devnum = 0;
  1628. bool pin_state_current = false;
  1629. struct wsa_ctrl_platform_data *plat_data = NULL;
  1630. struct snd_soc_component *component;
  1631. u32 noise_gate_mode;
  1632. char buffer[MAX_NAME_LEN];
  1633. int dev_index = 0;
  1634. struct regmap_irq_chip *wsa884x_sub_regmap_irq_chip = NULL;
  1635. u8 wo0_val;
  1636. int sys_gain_size, sys_gain_length;
  1637. wsa884x = devm_kzalloc(&pdev->dev, sizeof(struct wsa884x_priv),
  1638. GFP_KERNEL);
  1639. if (!wsa884x)
  1640. return -ENOMEM;
  1641. wsa884x_sub_regmap_irq_chip = devm_kzalloc(&pdev->dev, sizeof(struct regmap_irq_chip),
  1642. GFP_KERNEL);
  1643. if (!wsa884x_sub_regmap_irq_chip)
  1644. return -ENOMEM;
  1645. memcpy(wsa884x_sub_regmap_irq_chip, &wsa884x_regmap_irq_chip,
  1646. sizeof(struct regmap_irq_chip));
  1647. ret = wsa884x_enable_supplies(&pdev->dev, wsa884x);
  1648. if (ret) {
  1649. ret = -EPROBE_DEFER;
  1650. goto err;
  1651. }
  1652. wsa884x->wsa_rst_np = of_parse_phandle(pdev->dev.of_node,
  1653. "qcom,spkr-sd-n-node", 0);
  1654. if (!wsa884x->wsa_rst_np) {
  1655. dev_dbg(&pdev->dev, "%s: pinctrl not defined\n", __func__);
  1656. goto err_supply;
  1657. }
  1658. swr_set_dev_data(pdev, wsa884x);
  1659. wsa884x->swr_slave = pdev;
  1660. wsa884x->dev = &pdev->dev;
  1661. pin_state_current = msm_cdc_pinctrl_get_state(wsa884x->wsa_rst_np);
  1662. wsa884x_gpio_ctrl(wsa884x, true);
  1663. /*
  1664. * Add 5msec delay to provide sufficient time for
  1665. * soundwire auto enumeration of slave devices as
  1666. * per HW requirement.
  1667. */
  1668. usleep_range(5000, 5010);
  1669. ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
  1670. if (ret) {
  1671. dev_dbg(&pdev->dev,
  1672. "%s get devnum %d for dev addr %lx failed\n",
  1673. __func__, devnum, pdev->addr);
  1674. ret = -EPROBE_DEFER;
  1675. goto err_supply;
  1676. }
  1677. pdev->dev_num = devnum;
  1678. wsa884x->regmap = devm_regmap_init_swr(pdev,
  1679. &wsa884x_regmap_config);
  1680. if (IS_ERR(wsa884x->regmap)) {
  1681. ret = PTR_ERR(wsa884x->regmap);
  1682. dev_err(&pdev->dev, "%s: regmap_init failed %d\n",
  1683. __func__, ret);
  1684. goto dev_err;
  1685. }
  1686. devm_regmap_qti_debugfs_register(&pdev->dev, wsa884x->regmap);
  1687. wsa884x_sub_regmap_irq_chip->irq_drv_data = wsa884x;
  1688. wsa884x->irq_info.wcd_regmap_irq_chip = wsa884x_sub_regmap_irq_chip;
  1689. wsa884x->irq_info.codec_name = "WSA884X";
  1690. wsa884x->irq_info.regmap = wsa884x->regmap;
  1691. wsa884x->irq_info.dev = &pdev->dev;
  1692. ret = wcd_irq_init(&wsa884x->irq_info, &wsa884x->virq);
  1693. if (ret) {
  1694. dev_err(wsa884x->dev, "%s: IRQ init failed: %d\n",
  1695. __func__, ret);
  1696. goto dev_err;
  1697. }
  1698. wsa884x->swr_slave->slave_irq = wsa884x->virq;
  1699. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR,
  1700. "WSA SAF2WAR", wsa884x_saf2war_handle_irq, wsa884x);
  1701. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF,
  1702. "WSA WAR2SAF", wsa884x_war2saf_handle_irq, wsa884x);
  1703. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE,
  1704. "WSA OTP", wsa884x_otp_handle_irq, wsa884x);
  1705. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP,
  1706. "WSA OCP", wsa884x_ocp_handle_irq, wsa884x);
  1707. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP,
  1708. "WSA CLIP", wsa884x_clip_handle_irq, wsa884x);
  1709. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP);
  1710. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD,
  1711. "WSA PDM WD", wsa884x_pdm_wd_handle_irq, wsa884x);
  1712. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD,
  1713. "WSA CLK WD", wsa884x_clk_wd_handle_irq, wsa884x);
  1714. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN,
  1715. "WSA EXT INT", wsa884x_ext_int_handle_irq, wsa884x);
  1716. wcd_disable_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN);
  1717. /* Under Voltage Lock out (UVLO) interrupt handle */
  1718. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO,
  1719. "WSA UVLO", wsa884x_uvlo_handle_irq, wsa884x);
  1720. wcd_request_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR,
  1721. "WSA PA ERR", wsa884x_pa_on_err_handle_irq, wsa884x);
  1722. wsa884x->driver = devm_kzalloc(&pdev->dev,
  1723. sizeof(struct snd_soc_component_driver), GFP_KERNEL);
  1724. if (!wsa884x->driver) {
  1725. ret = -ENOMEM;
  1726. goto err_irq;
  1727. }
  1728. memcpy(wsa884x->driver, &soc_codec_dev_wsa884x_wsa,
  1729. sizeof(struct snd_soc_component_driver));
  1730. wsa884x->dai_driver = devm_kzalloc(&pdev->dev,
  1731. sizeof(struct snd_soc_dai_driver), GFP_KERNEL);
  1732. if (!wsa884x->dai_driver) {
  1733. ret = -ENOMEM;
  1734. goto err_mem;
  1735. }
  1736. memcpy(wsa884x->dai_driver, wsa_dai, sizeof(struct snd_soc_dai_driver));
  1737. /* Get last digit from HEX format */
  1738. dev_index = (int)((char)(pdev->addr & 0xF));
  1739. dev_index += 1;
  1740. if (of_device_is_compatible(pdev->dev.of_node, "qcom,wsa884x_2"))
  1741. dev_index += 2;
  1742. snprintf(buffer, sizeof(buffer), "wsa-codec.%d", dev_index);
  1743. wsa884x->driver->name = kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1744. snprintf(buffer, sizeof(buffer), "wsa_rx%d", dev_index);
  1745. wsa884x->dai_driver->name =
  1746. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1747. snprintf(buffer, sizeof(buffer), "WSA884X_AIF%d Playback", dev_index);
  1748. wsa884x->dai_driver->playback.stream_name =
  1749. kstrndup(buffer, strlen(buffer), GFP_KERNEL);
  1750. /* Number of DAI's used is 1 */
  1751. ret = snd_soc_register_component(&pdev->dev,
  1752. wsa884x->driver, wsa884x->dai_driver, 1);
  1753. component = snd_soc_lookup_component(&pdev->dev, wsa884x->driver->name);
  1754. if (!component) {
  1755. dev_err(&pdev->dev, "%s: component is NULL\n", __func__);
  1756. ret = -EINVAL;
  1757. goto err_mem;
  1758. }
  1759. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1760. "qcom,bolero-handle", 0);
  1761. if (!wsa884x->parent_np)
  1762. wsa884x->parent_np = of_parse_phandle(pdev->dev.of_node,
  1763. "qcom,lpass-cdc-handle", 0);
  1764. if (wsa884x->parent_np) {
  1765. wsa884x->parent_dev =
  1766. of_find_device_by_node(wsa884x->parent_np);
  1767. if (wsa884x->parent_dev) {
  1768. plat_data = dev_get_platdata(&wsa884x->parent_dev->dev);
  1769. if (plat_data) {
  1770. wsa884x->parent_nblock.notifier_call =
  1771. wsa884x_event_notify;
  1772. if (plat_data->register_notifier)
  1773. plat_data->register_notifier(
  1774. plat_data->handle,
  1775. &wsa884x->parent_nblock,
  1776. true);
  1777. wsa884x->register_notifier =
  1778. plat_data->register_notifier;
  1779. wsa884x->handle = plat_data->handle;
  1780. } else {
  1781. dev_err(&pdev->dev, "%s: plat data not found\n",
  1782. __func__);
  1783. }
  1784. } else {
  1785. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1786. __func__);
  1787. }
  1788. } else {
  1789. dev_info(&pdev->dev, "%s: parent node not found\n", __func__);
  1790. }
  1791. /* Start in speaker mode by default */
  1792. wsa884x->dev_mode = SPEAKER;
  1793. wsa884x->dev_index = dev_index;
  1794. wsa884x->macro_np = of_parse_phandle(pdev->dev.of_node,
  1795. "qcom,wsa-macro-handle", 0);
  1796. if (wsa884x->macro_np) {
  1797. wsa884x->macro_dev =
  1798. of_find_device_by_node(wsa884x->macro_np);
  1799. if (wsa884x->macro_dev) {
  1800. ret = of_property_read_u32_index(
  1801. wsa884x->macro_dev->dev.of_node,
  1802. "qcom,wsa-rloads",
  1803. dev_index - 1,
  1804. &wsa884x->rload);
  1805. if (ret) {
  1806. dev_err(&pdev->dev,
  1807. "%s: Failed to read wsa rloads\n",
  1808. __func__);
  1809. goto err_mem;
  1810. }
  1811. ret = of_property_read_u32(wsa884x->macro_dev->dev.of_node,
  1812. "qcom,noise-gate-mode", &noise_gate_mode);
  1813. if (ret) {
  1814. dev_info(&pdev->dev,
  1815. "%s: Failed to read wsa noise gate mode\n",
  1816. __func__);
  1817. wsa884x->noise_gate_mode = IDLE_DETECT;
  1818. } else {
  1819. if (IDLE_DETECT <= noise_gate_mode && noise_gate_mode <= NG3)
  1820. wsa884x->noise_gate_mode = noise_gate_mode;
  1821. else
  1822. wsa884x->noise_gate_mode = IDLE_DETECT;
  1823. }
  1824. if (!of_find_property(wsa884x->macro_dev->dev.of_node,
  1825. "qcom,wsa-system-gains", &sys_gain_size)) {
  1826. dev_err(&pdev->dev,
  1827. "%s: missing wsa-system-gains\n",
  1828. __func__);
  1829. goto err_mem;
  1830. }
  1831. sys_gain_length = sys_gain_size / (2 * sizeof(u32));
  1832. ret = of_property_read_u32_array(
  1833. wsa884x->macro_dev->dev.of_node,
  1834. "qcom,wsa-system-gains", wsa884x->sys_gains,
  1835. sys_gain_length);
  1836. if (ret) {
  1837. dev_err(&pdev->dev,
  1838. "%s: Failed to read wsa system gains\n",
  1839. __func__);
  1840. goto err_mem;
  1841. }
  1842. wsa884x->system_gain = wsa884x->sys_gains[
  1843. wsa884x->dev_mode + (dev_index - 1) * 2];
  1844. } else {
  1845. dev_err(&pdev->dev, "%s: parent dev not found\n",
  1846. __func__);
  1847. goto err_mem;
  1848. }
  1849. } else {
  1850. dev_err(&pdev->dev, "%s: parent node not found\n", __func__);
  1851. goto err_mem;
  1852. }
  1853. wsa884x->bat_cfg = snd_soc_component_read(component,
  1854. WSA884X_VPHX_SYS_EN_STATUS);
  1855. dev_dbg(component->dev,
  1856. "%s: Bat_cfg: 0x%x, Rload: 0x%x, Sys_gain: 0x%x\n", __func__,
  1857. wsa884x->bat_cfg, wsa884x->rload, wsa884x->system_gain);
  1858. ret = wsa884x_validate_dt_configuration_params(wsa884x->rload,
  1859. wsa884x->bat_cfg, wsa884x->system_gain);
  1860. if (ret) {
  1861. dev_err(&pdev->dev, "%s: invalid dt parameter\n", __func__);
  1862. ret = -EINVAL;
  1863. goto err_mem;
  1864. }
  1865. wsa884x_set_gain_parameters(component);
  1866. wsa884x_set_pbr_parameters(component);
  1867. /* Must write WO registers in a single write */
  1868. wo0_val = (0xC | (wsa884x->pa_aux_gain << 0x02) | !wsa884x->dev_mode);
  1869. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_0, wo0_val);
  1870. snd_soc_component_write(component, WSA884X_ANA_WO_CTL_1, 0x0);
  1871. if (wsa884x->rload == WSA_4_OHMS || wsa884x->rload == WSA_6_OHMS)
  1872. snd_soc_component_update_bits(component,
  1873. REG_FIELD_VALUE(OCP_CTL, OCP_CURR_LIMIT, 0x07));
  1874. if (wsa884x->dev_mode == SPEAKER) {
  1875. snd_soc_component_update_bits(component,
  1876. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x0F));
  1877. } else {
  1878. snd_soc_component_update_bits(component,
  1879. REG_FIELD_VALUE(DRE_CTL_0, PROG_DELAY, 0x03));
  1880. snd_soc_component_update_bits(component,
  1881. REG_FIELD_VALUE(CDC_PATH_MODE, RXD_MODE, 0x01));
  1882. snd_soc_component_update_bits(component,
  1883. REG_FIELD_VALUE(PWM_CLK_CTL,
  1884. PWM_CLK_FREQ_SEL, 0x01));
  1885. }
  1886. if (wsa884x->bat_cfg != CONFIG_1S && wsa884x->bat_cfg != EXT_1S)
  1887. snd_soc_component_update_bits(component,
  1888. REG_FIELD_VALUE(TOP_CTRL1,
  1889. OCP_LOWVBAT_ITH_SEL_EN, 0x00));
  1890. ret = wsa884x_parse_port_params(&pdev->dev, "qcom,swr-wsa-port-params");
  1891. if (ret) {
  1892. dev_err(&pdev->dev, "Failed to read port params\n");
  1893. goto err;
  1894. }
  1895. swr_init_port_params(wsa884x->swr_slave, WSA884X_MAX_SWR_PORTS,
  1896. wsa884x->swr_wsa_port_params);
  1897. mutex_init(&wsa884x->res_lock);
  1898. #ifdef CONFIG_DEBUG_FS
  1899. if (!wsa884x->debugfs_dent) {
  1900. wsa884x->debugfs_dent = debugfs_create_dir(
  1901. dev_name(&pdev->dev), 0);
  1902. if (!IS_ERR(wsa884x->debugfs_dent)) {
  1903. wsa884x->debugfs_peek =
  1904. debugfs_create_file("swrslave_peek",
  1905. S_IFREG | 0444,
  1906. wsa884x->debugfs_dent,
  1907. (void *) pdev,
  1908. &codec_debug_read_ops);
  1909. wsa884x->debugfs_poke =
  1910. debugfs_create_file("swrslave_poke",
  1911. S_IFREG | 0444,
  1912. wsa884x->debugfs_dent,
  1913. (void *) pdev,
  1914. &codec_debug_write_ops);
  1915. wsa884x->debugfs_reg_dump =
  1916. debugfs_create_file(
  1917. "swrslave_reg_dump",
  1918. S_IFREG | 0444,
  1919. wsa884x->debugfs_dent,
  1920. (void *) pdev,
  1921. &codec_debug_dump_ops);
  1922. }
  1923. }
  1924. #endif
  1925. return 0;
  1926. err_mem:
  1927. if (wsa884x->dai_driver) {
  1928. kfree(wsa884x->dai_driver->name);
  1929. kfree(wsa884x->dai_driver->playback.stream_name);
  1930. kfree(wsa884x->dai_driver);
  1931. }
  1932. if (wsa884x->driver) {
  1933. kfree(wsa884x->driver->name);
  1934. kfree(wsa884x->driver);
  1935. }
  1936. err_irq:
  1937. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1938. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1939. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1940. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1941. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1942. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1943. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1944. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1945. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1946. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1947. wcd_irq_exit(&wsa884x->irq_info, wsa884x->virq);
  1948. dev_err:
  1949. if (pin_state_current == false)
  1950. wsa884x_gpio_ctrl(wsa884x, false);
  1951. swr_remove_device(pdev);
  1952. err_supply:
  1953. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1954. wsa884x->regulator,
  1955. wsa884x->num_supplies);
  1956. err:
  1957. swr_set_dev_data(pdev, NULL);
  1958. return ret;
  1959. }
  1960. static int wsa884x_swr_remove(struct swr_device *pdev)
  1961. {
  1962. struct wsa884x_priv *wsa884x;
  1963. wsa884x = swr_get_dev_data(pdev);
  1964. if (!wsa884x) {
  1965. dev_err(&pdev->dev, "%s: wsa884x is NULL\n", __func__);
  1966. return -EINVAL;
  1967. }
  1968. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_SAF2WAR, NULL);
  1969. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_WAR2SAF, NULL);
  1970. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_DISABLE, NULL);
  1971. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_OCP, NULL);
  1972. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLIP, NULL);
  1973. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PDM_WD, NULL);
  1974. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_CLK_WD, NULL);
  1975. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_INTR_PIN, NULL);
  1976. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_UVLO, NULL);
  1977. wcd_free_irq(&wsa884x->irq_info, WSA884X_IRQ_INT_PA_ON_ERR, NULL);
  1978. if (wsa884x->register_notifier)
  1979. wsa884x->register_notifier(wsa884x->handle,
  1980. &wsa884x->parent_nblock, false);
  1981. #ifdef CONFIG_DEBUG_FS
  1982. debugfs_remove_recursive(wsa884x->debugfs_dent);
  1983. wsa884x->debugfs_dent = NULL;
  1984. #endif
  1985. mutex_destroy(&wsa884x->res_lock);
  1986. snd_soc_unregister_component(&pdev->dev);
  1987. if (wsa884x->dai_driver) {
  1988. kfree(wsa884x->dai_driver->name);
  1989. kfree(wsa884x->dai_driver->playback.stream_name);
  1990. kfree(wsa884x->dai_driver);
  1991. }
  1992. if (wsa884x->driver) {
  1993. kfree(wsa884x->driver->name);
  1994. kfree(wsa884x->driver);
  1995. }
  1996. msm_cdc_release_supplies(&pdev->dev, wsa884x->supplies,
  1997. wsa884x->regulator,
  1998. wsa884x->num_supplies);
  1999. swr_set_dev_data(pdev, NULL);
  2000. return 0;
  2001. }
  2002. #ifdef CONFIG_PM_SLEEP
  2003. static int wsa884x_swr_suspend(struct device *dev)
  2004. {
  2005. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2006. if (!wsa884x) {
  2007. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2008. return -EINVAL;
  2009. }
  2010. dev_dbg(dev, "%s: system suspend\n", __func__);
  2011. if (wsa884x->dapm_bias_off) {
  2012. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2013. wsa884x->regulator,
  2014. wsa884x->num_supplies,
  2015. true);
  2016. set_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2017. }
  2018. return 0;
  2019. }
  2020. static int wsa884x_swr_resume(struct device *dev)
  2021. {
  2022. struct wsa884x_priv *wsa884x = swr_get_dev_data(to_swr_device(dev));
  2023. if (!wsa884x) {
  2024. dev_err(dev, "%s: wsa884x private data is NULL\n", __func__);
  2025. return -EINVAL;
  2026. }
  2027. if (test_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask)) {
  2028. msm_cdc_set_supplies_lpm_mode(dev, wsa884x->supplies,
  2029. wsa884x->regulator,
  2030. wsa884x->num_supplies,
  2031. false);
  2032. clear_bit(WSA_SUPPLIES_LPM_MODE, &wsa884x->status_mask);
  2033. }
  2034. dev_dbg(dev, "%s: system resume\n", __func__);
  2035. return 0;
  2036. }
  2037. #endif /* CONFIG_PM_SLEEP */
  2038. static const struct dev_pm_ops wsa884x_swr_pm_ops = {
  2039. .suspend_late = wsa884x_swr_suspend,
  2040. .resume_early = wsa884x_swr_resume,
  2041. };
  2042. static const struct swr_device_id wsa884x_swr_id[] = {
  2043. {"wsa884x", 0},
  2044. {"wsa884x_2", 0},
  2045. {}
  2046. };
  2047. static const struct of_device_id wsa884x_swr_dt_match[] = {
  2048. {
  2049. .compatible = "qcom,wsa884x",
  2050. },
  2051. {
  2052. .compatible = "qcom,wsa884x_2",
  2053. },
  2054. {}
  2055. };
  2056. static struct swr_driver wsa884x_swr_driver = {
  2057. .driver = {
  2058. .name = "wsa884x",
  2059. .owner = THIS_MODULE,
  2060. .pm = &wsa884x_swr_pm_ops,
  2061. .of_match_table = wsa884x_swr_dt_match,
  2062. },
  2063. .probe = wsa884x_swr_probe,
  2064. .remove = wsa884x_swr_remove,
  2065. .id_table = wsa884x_swr_id,
  2066. };
  2067. static int __init wsa884x_swr_init(void)
  2068. {
  2069. return swr_driver_register(&wsa884x_swr_driver);
  2070. }
  2071. static void __exit wsa884x_swr_exit(void)
  2072. {
  2073. swr_driver_unregister(&wsa884x_swr_driver);
  2074. }
  2075. module_init(wsa884x_swr_init);
  2076. module_exit(wsa884x_swr_exit);
  2077. MODULE_DESCRIPTION("WSA884x codec driver");
  2078. MODULE_LICENSE("GPL v2");